1 /* 2 * Component description for PAC 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_PAC_COMPONENT_H_ 22 #define _PIC32CXSG61_PAC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR PAC */ 26 /* ************************************************************************** */ 27 28 /* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */ 29 #define PAC_WRCTRL_RESETVALUE _UINT32_(0x00) /* (PAC_WRCTRL) Write control Reset Value */ 30 31 #define PAC_WRCTRL_PERID_Pos _UINT32_(0) /* (PAC_WRCTRL) Peripheral identifier Position */ 32 #define PAC_WRCTRL_PERID_Msk (_UINT32_(0xFFFF) << PAC_WRCTRL_PERID_Pos) /* (PAC_WRCTRL) Peripheral identifier Mask */ 33 #define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & (_UINT32_(value) << PAC_WRCTRL_PERID_Pos)) /* Assigment of value for PERID in the PAC_WRCTRL register */ 34 #define PAC_WRCTRL_KEY_Pos _UINT32_(16) /* (PAC_WRCTRL) Peripheral access control key Position */ 35 #define PAC_WRCTRL_KEY_Msk (_UINT32_(0xFF) << PAC_WRCTRL_KEY_Pos) /* (PAC_WRCTRL) Peripheral access control key Mask */ 36 #define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & (_UINT32_(value) << PAC_WRCTRL_KEY_Pos)) /* Assigment of value for KEY in the PAC_WRCTRL register */ 37 #define PAC_WRCTRL_KEY_OFF_Val _UINT32_(0x0) /* (PAC_WRCTRL) No action */ 38 #define PAC_WRCTRL_KEY_CLR_Val _UINT32_(0x1) /* (PAC_WRCTRL) Clear protection */ 39 #define PAC_WRCTRL_KEY_SET_Val _UINT32_(0x2) /* (PAC_WRCTRL) Set protection */ 40 #define PAC_WRCTRL_KEY_SETLCK_Val _UINT32_(0x3) /* (PAC_WRCTRL) Set and lock protection */ 41 #define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos) /* (PAC_WRCTRL) No action Position */ 42 #define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos) /* (PAC_WRCTRL) Clear protection Position */ 43 #define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos) /* (PAC_WRCTRL) Set protection Position */ 44 #define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos) /* (PAC_WRCTRL) Set and lock protection Position */ 45 #define PAC_WRCTRL_Msk _UINT32_(0x00FFFFFF) /* (PAC_WRCTRL) Register Mask */ 46 47 48 /* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */ 49 #define PAC_EVCTRL_RESETVALUE _UINT8_(0x00) /* (PAC_EVCTRL) Event control Reset Value */ 50 51 #define PAC_EVCTRL_ERREO_Pos _UINT8_(0) /* (PAC_EVCTRL) Peripheral acess error event output Position */ 52 #define PAC_EVCTRL_ERREO_Msk (_UINT8_(0x1) << PAC_EVCTRL_ERREO_Pos) /* (PAC_EVCTRL) Peripheral acess error event output Mask */ 53 #define PAC_EVCTRL_ERREO(value) (PAC_EVCTRL_ERREO_Msk & (_UINT8_(value) << PAC_EVCTRL_ERREO_Pos)) /* Assigment of value for ERREO in the PAC_EVCTRL register */ 54 #define PAC_EVCTRL_Msk _UINT8_(0x01) /* (PAC_EVCTRL) Register Mask */ 55 56 57 /* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */ 58 #define PAC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (PAC_INTENCLR) Interrupt enable clear Reset Value */ 59 60 #define PAC_INTENCLR_ERR_Pos _UINT8_(0) /* (PAC_INTENCLR) Peripheral access error interrupt disable Position */ 61 #define PAC_INTENCLR_ERR_Msk (_UINT8_(0x1) << PAC_INTENCLR_ERR_Pos) /* (PAC_INTENCLR) Peripheral access error interrupt disable Mask */ 62 #define PAC_INTENCLR_ERR(value) (PAC_INTENCLR_ERR_Msk & (_UINT8_(value) << PAC_INTENCLR_ERR_Pos)) /* Assigment of value for ERR in the PAC_INTENCLR register */ 63 #define PAC_INTENCLR_Msk _UINT8_(0x01) /* (PAC_INTENCLR) Register Mask */ 64 65 66 /* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */ 67 #define PAC_INTENSET_RESETVALUE _UINT8_(0x00) /* (PAC_INTENSET) Interrupt enable set Reset Value */ 68 69 #define PAC_INTENSET_ERR_Pos _UINT8_(0) /* (PAC_INTENSET) Peripheral access error interrupt enable Position */ 70 #define PAC_INTENSET_ERR_Msk (_UINT8_(0x1) << PAC_INTENSET_ERR_Pos) /* (PAC_INTENSET) Peripheral access error interrupt enable Mask */ 71 #define PAC_INTENSET_ERR(value) (PAC_INTENSET_ERR_Msk & (_UINT8_(value) << PAC_INTENSET_ERR_Pos)) /* Assigment of value for ERR in the PAC_INTENSET register */ 72 #define PAC_INTENSET_Msk _UINT8_(0x01) /* (PAC_INTENSET) Register Mask */ 73 74 75 /* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */ 76 #define PAC_INTFLAGAHB_RESETVALUE _UINT32_(0x00) /* (PAC_INTFLAGAHB) Bridge interrupt flag status Reset Value */ 77 78 #define PAC_INTFLAGAHB_FLASH_Pos _UINT32_(0) /* (PAC_INTFLAGAHB) FLASH Position */ 79 #define PAC_INTFLAGAHB_FLASH_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_FLASH_Pos) /* (PAC_INTFLAGAHB) FLASH Mask */ 80 #define PAC_INTFLAGAHB_FLASH(value) (PAC_INTFLAGAHB_FLASH_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_FLASH_Pos)) /* Assigment of value for FLASH in the PAC_INTFLAGAHB register */ 81 #define PAC_INTFLAGAHB_FLASH_ALT_Pos _UINT32_(1) /* (PAC_INTFLAGAHB) FLASH_ALT Position */ 82 #define PAC_INTFLAGAHB_FLASH_ALT_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos) /* (PAC_INTFLAGAHB) FLASH_ALT Mask */ 83 #define PAC_INTFLAGAHB_FLASH_ALT(value) (PAC_INTFLAGAHB_FLASH_ALT_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_FLASH_ALT_Pos)) /* Assigment of value for FLASH_ALT in the PAC_INTFLAGAHB register */ 84 #define PAC_INTFLAGAHB_SEEPROM_Pos _UINT32_(2) /* (PAC_INTFLAGAHB) SEEPROM Position */ 85 #define PAC_INTFLAGAHB_SEEPROM_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos) /* (PAC_INTFLAGAHB) SEEPROM Mask */ 86 #define PAC_INTFLAGAHB_SEEPROM(value) (PAC_INTFLAGAHB_SEEPROM_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_SEEPROM_Pos)) /* Assigment of value for SEEPROM in the PAC_INTFLAGAHB register */ 87 #define PAC_INTFLAGAHB_RAMCM4S_Pos _UINT32_(3) /* (PAC_INTFLAGAHB) RAMCM4S Position */ 88 #define PAC_INTFLAGAHB_RAMCM4S_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos) /* (PAC_INTFLAGAHB) RAMCM4S Mask */ 89 #define PAC_INTFLAGAHB_RAMCM4S(value) (PAC_INTFLAGAHB_RAMCM4S_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_RAMCM4S_Pos)) /* Assigment of value for RAMCM4S in the PAC_INTFLAGAHB register */ 90 #define PAC_INTFLAGAHB_RAMPPPDSU_Pos _UINT32_(4) /* (PAC_INTFLAGAHB) RAMPPPDSU Position */ 91 #define PAC_INTFLAGAHB_RAMPPPDSU_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos) /* (PAC_INTFLAGAHB) RAMPPPDSU Mask */ 92 #define PAC_INTFLAGAHB_RAMPPPDSU(value) (PAC_INTFLAGAHB_RAMPPPDSU_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_RAMPPPDSU_Pos)) /* Assigment of value for RAMPPPDSU in the PAC_INTFLAGAHB register */ 93 #define PAC_INTFLAGAHB_RAMDMAWR_Pos _UINT32_(5) /* (PAC_INTFLAGAHB) RAMDMAWR Position */ 94 #define PAC_INTFLAGAHB_RAMDMAWR_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos) /* (PAC_INTFLAGAHB) RAMDMAWR Mask */ 95 #define PAC_INTFLAGAHB_RAMDMAWR(value) (PAC_INTFLAGAHB_RAMDMAWR_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_RAMDMAWR_Pos)) /* Assigment of value for RAMDMAWR in the PAC_INTFLAGAHB register */ 96 #define PAC_INTFLAGAHB_RAMDMACICM_Pos _UINT32_(6) /* (PAC_INTFLAGAHB) RAMDMACICM Position */ 97 #define PAC_INTFLAGAHB_RAMDMACICM_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos) /* (PAC_INTFLAGAHB) RAMDMACICM Mask */ 98 #define PAC_INTFLAGAHB_RAMDMACICM(value) (PAC_INTFLAGAHB_RAMDMACICM_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_RAMDMACICM_Pos)) /* Assigment of value for RAMDMACICM in the PAC_INTFLAGAHB register */ 99 #define PAC_INTFLAGAHB_HPB0_Pos _UINT32_(7) /* (PAC_INTFLAGAHB) HPB0 Position */ 100 #define PAC_INTFLAGAHB_HPB0_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_HPB0_Pos) /* (PAC_INTFLAGAHB) HPB0 Mask */ 101 #define PAC_INTFLAGAHB_HPB0(value) (PAC_INTFLAGAHB_HPB0_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_HPB0_Pos)) /* Assigment of value for HPB0 in the PAC_INTFLAGAHB register */ 102 #define PAC_INTFLAGAHB_HPB1_Pos _UINT32_(8) /* (PAC_INTFLAGAHB) HPB1 Position */ 103 #define PAC_INTFLAGAHB_HPB1_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_HPB1_Pos) /* (PAC_INTFLAGAHB) HPB1 Mask */ 104 #define PAC_INTFLAGAHB_HPB1(value) (PAC_INTFLAGAHB_HPB1_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_HPB1_Pos)) /* Assigment of value for HPB1 in the PAC_INTFLAGAHB register */ 105 #define PAC_INTFLAGAHB_HPB2_Pos _UINT32_(9) /* (PAC_INTFLAGAHB) HPB2 Position */ 106 #define PAC_INTFLAGAHB_HPB2_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_HPB2_Pos) /* (PAC_INTFLAGAHB) HPB2 Mask */ 107 #define PAC_INTFLAGAHB_HPB2(value) (PAC_INTFLAGAHB_HPB2_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_HPB2_Pos)) /* Assigment of value for HPB2 in the PAC_INTFLAGAHB register */ 108 #define PAC_INTFLAGAHB_HPB3_Pos _UINT32_(10) /* (PAC_INTFLAGAHB) HPB3 Position */ 109 #define PAC_INTFLAGAHB_HPB3_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_HPB3_Pos) /* (PAC_INTFLAGAHB) HPB3 Mask */ 110 #define PAC_INTFLAGAHB_HPB3(value) (PAC_INTFLAGAHB_HPB3_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_HPB3_Pos)) /* Assigment of value for HPB3 in the PAC_INTFLAGAHB register */ 111 #define PAC_INTFLAGAHB_PUKCC_Pos _UINT32_(11) /* (PAC_INTFLAGAHB) PUKCC Position */ 112 #define PAC_INTFLAGAHB_PUKCC_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos) /* (PAC_INTFLAGAHB) PUKCC Mask */ 113 #define PAC_INTFLAGAHB_PUKCC(value) (PAC_INTFLAGAHB_PUKCC_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_PUKCC_Pos)) /* Assigment of value for PUKCC in the PAC_INTFLAGAHB register */ 114 #define PAC_INTFLAGAHB_SDHC0_Pos _UINT32_(12) /* (PAC_INTFLAGAHB) SDHC0 Position */ 115 #define PAC_INTFLAGAHB_SDHC0_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos) /* (PAC_INTFLAGAHB) SDHC0 Mask */ 116 #define PAC_INTFLAGAHB_SDHC0(value) (PAC_INTFLAGAHB_SDHC0_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_SDHC0_Pos)) /* Assigment of value for SDHC0 in the PAC_INTFLAGAHB register */ 117 #define PAC_INTFLAGAHB_SDHC1_Pos _UINT32_(13) /* (PAC_INTFLAGAHB) SDHC1 Position */ 118 #define PAC_INTFLAGAHB_SDHC1_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos) /* (PAC_INTFLAGAHB) SDHC1 Mask */ 119 #define PAC_INTFLAGAHB_SDHC1(value) (PAC_INTFLAGAHB_SDHC1_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_SDHC1_Pos)) /* Assigment of value for SDHC1 in the PAC_INTFLAGAHB register */ 120 #define PAC_INTFLAGAHB_QSPI_Pos _UINT32_(14) /* (PAC_INTFLAGAHB) QSPI Position */ 121 #define PAC_INTFLAGAHB_QSPI_Msk (_UINT32_(0x1) << PAC_INTFLAGAHB_QSPI_Pos) /* (PAC_INTFLAGAHB) QSPI Mask */ 122 #define PAC_INTFLAGAHB_QSPI(value) (PAC_INTFLAGAHB_QSPI_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_QSPI_Pos)) /* Assigment of value for QSPI in the PAC_INTFLAGAHB register */ 123 #define PAC_INTFLAGAHB_Msk _UINT32_(0x00007FFF) /* (PAC_INTFLAGAHB) Register Mask */ 124 125 #define PAC_INTFLAGAHB_HPB_Pos _UINT32_(7) /* (PAC_INTFLAGAHB Position) HPBx */ 126 #define PAC_INTFLAGAHB_HPB_Msk (_UINT32_(0xF) << PAC_INTFLAGAHB_HPB_Pos) /* (PAC_INTFLAGAHB Mask) HPB */ 127 #define PAC_INTFLAGAHB_HPB(value) (PAC_INTFLAGAHB_HPB_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_HPB_Pos)) 128 #define PAC_INTFLAGAHB_SDHC_Pos _UINT32_(12) /* (PAC_INTFLAGAHB Position) SDHCx */ 129 #define PAC_INTFLAGAHB_SDHC_Msk (_UINT32_(0x3) << PAC_INTFLAGAHB_SDHC_Pos) /* (PAC_INTFLAGAHB Mask) SDHC */ 130 #define PAC_INTFLAGAHB_SDHC(value) (PAC_INTFLAGAHB_SDHC_Msk & (_UINT32_(value) << PAC_INTFLAGAHB_SDHC_Pos)) 131 132 /* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */ 133 #define PAC_INTFLAGA_RESETVALUE _UINT32_(0x00) /* (PAC_INTFLAGA) Peripheral interrupt flag status - Bridge A Reset Value */ 134 135 #define PAC_INTFLAGA_PAC_Pos _UINT32_(0) /* (PAC_INTFLAGA) PAC Position */ 136 #define PAC_INTFLAGA_PAC_Msk (_UINT32_(0x1) << PAC_INTFLAGA_PAC_Pos) /* (PAC_INTFLAGA) PAC Mask */ 137 #define PAC_INTFLAGA_PAC(value) (PAC_INTFLAGA_PAC_Msk & (_UINT32_(value) << PAC_INTFLAGA_PAC_Pos)) /* Assigment of value for PAC in the PAC_INTFLAGA register */ 138 #define PAC_INTFLAGA_PM_Pos _UINT32_(1) /* (PAC_INTFLAGA) PM Position */ 139 #define PAC_INTFLAGA_PM_Msk (_UINT32_(0x1) << PAC_INTFLAGA_PM_Pos) /* (PAC_INTFLAGA) PM Mask */ 140 #define PAC_INTFLAGA_PM(value) (PAC_INTFLAGA_PM_Msk & (_UINT32_(value) << PAC_INTFLAGA_PM_Pos)) /* Assigment of value for PM in the PAC_INTFLAGA register */ 141 #define PAC_INTFLAGA_MCLK_Pos _UINT32_(2) /* (PAC_INTFLAGA) MCLK Position */ 142 #define PAC_INTFLAGA_MCLK_Msk (_UINT32_(0x1) << PAC_INTFLAGA_MCLK_Pos) /* (PAC_INTFLAGA) MCLK Mask */ 143 #define PAC_INTFLAGA_MCLK(value) (PAC_INTFLAGA_MCLK_Msk & (_UINT32_(value) << PAC_INTFLAGA_MCLK_Pos)) /* Assigment of value for MCLK in the PAC_INTFLAGA register */ 144 #define PAC_INTFLAGA_RSTC_Pos _UINT32_(3) /* (PAC_INTFLAGA) RSTC Position */ 145 #define PAC_INTFLAGA_RSTC_Msk (_UINT32_(0x1) << PAC_INTFLAGA_RSTC_Pos) /* (PAC_INTFLAGA) RSTC Mask */ 146 #define PAC_INTFLAGA_RSTC(value) (PAC_INTFLAGA_RSTC_Msk & (_UINT32_(value) << PAC_INTFLAGA_RSTC_Pos)) /* Assigment of value for RSTC in the PAC_INTFLAGA register */ 147 #define PAC_INTFLAGA_OSCCTRL_Pos _UINT32_(4) /* (PAC_INTFLAGA) OSCCTRL Position */ 148 #define PAC_INTFLAGA_OSCCTRL_Msk (_UINT32_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos) /* (PAC_INTFLAGA) OSCCTRL Mask */ 149 #define PAC_INTFLAGA_OSCCTRL(value) (PAC_INTFLAGA_OSCCTRL_Msk & (_UINT32_(value) << PAC_INTFLAGA_OSCCTRL_Pos)) /* Assigment of value for OSCCTRL in the PAC_INTFLAGA register */ 150 #define PAC_INTFLAGA_OSC32KCTRL_Pos _UINT32_(5) /* (PAC_INTFLAGA) OSC32KCTRL Position */ 151 #define PAC_INTFLAGA_OSC32KCTRL_Msk (_UINT32_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos) /* (PAC_INTFLAGA) OSC32KCTRL Mask */ 152 #define PAC_INTFLAGA_OSC32KCTRL(value) (PAC_INTFLAGA_OSC32KCTRL_Msk & (_UINT32_(value) << PAC_INTFLAGA_OSC32KCTRL_Pos)) /* Assigment of value for OSC32KCTRL in the PAC_INTFLAGA register */ 153 #define PAC_INTFLAGA_SUPC_Pos _UINT32_(6) /* (PAC_INTFLAGA) SUPC Position */ 154 #define PAC_INTFLAGA_SUPC_Msk (_UINT32_(0x1) << PAC_INTFLAGA_SUPC_Pos) /* (PAC_INTFLAGA) SUPC Mask */ 155 #define PAC_INTFLAGA_SUPC(value) (PAC_INTFLAGA_SUPC_Msk & (_UINT32_(value) << PAC_INTFLAGA_SUPC_Pos)) /* Assigment of value for SUPC in the PAC_INTFLAGA register */ 156 #define PAC_INTFLAGA_GCLK_Pos _UINT32_(7) /* (PAC_INTFLAGA) GCLK Position */ 157 #define PAC_INTFLAGA_GCLK_Msk (_UINT32_(0x1) << PAC_INTFLAGA_GCLK_Pos) /* (PAC_INTFLAGA) GCLK Mask */ 158 #define PAC_INTFLAGA_GCLK(value) (PAC_INTFLAGA_GCLK_Msk & (_UINT32_(value) << PAC_INTFLAGA_GCLK_Pos)) /* Assigment of value for GCLK in the PAC_INTFLAGA register */ 159 #define PAC_INTFLAGA_WDT_Pos _UINT32_(8) /* (PAC_INTFLAGA) WDT Position */ 160 #define PAC_INTFLAGA_WDT_Msk (_UINT32_(0x1) << PAC_INTFLAGA_WDT_Pos) /* (PAC_INTFLAGA) WDT Mask */ 161 #define PAC_INTFLAGA_WDT(value) (PAC_INTFLAGA_WDT_Msk & (_UINT32_(value) << PAC_INTFLAGA_WDT_Pos)) /* Assigment of value for WDT in the PAC_INTFLAGA register */ 162 #define PAC_INTFLAGA_RTC_Pos _UINT32_(9) /* (PAC_INTFLAGA) RTC Position */ 163 #define PAC_INTFLAGA_RTC_Msk (_UINT32_(0x1) << PAC_INTFLAGA_RTC_Pos) /* (PAC_INTFLAGA) RTC Mask */ 164 #define PAC_INTFLAGA_RTC(value) (PAC_INTFLAGA_RTC_Msk & (_UINT32_(value) << PAC_INTFLAGA_RTC_Pos)) /* Assigment of value for RTC in the PAC_INTFLAGA register */ 165 #define PAC_INTFLAGA_EIC_Pos _UINT32_(10) /* (PAC_INTFLAGA) EIC Position */ 166 #define PAC_INTFLAGA_EIC_Msk (_UINT32_(0x1) << PAC_INTFLAGA_EIC_Pos) /* (PAC_INTFLAGA) EIC Mask */ 167 #define PAC_INTFLAGA_EIC(value) (PAC_INTFLAGA_EIC_Msk & (_UINT32_(value) << PAC_INTFLAGA_EIC_Pos)) /* Assigment of value for EIC in the PAC_INTFLAGA register */ 168 #define PAC_INTFLAGA_FREQM_Pos _UINT32_(11) /* (PAC_INTFLAGA) FREQM Position */ 169 #define PAC_INTFLAGA_FREQM_Msk (_UINT32_(0x1) << PAC_INTFLAGA_FREQM_Pos) /* (PAC_INTFLAGA) FREQM Mask */ 170 #define PAC_INTFLAGA_FREQM(value) (PAC_INTFLAGA_FREQM_Msk & (_UINT32_(value) << PAC_INTFLAGA_FREQM_Pos)) /* Assigment of value for FREQM in the PAC_INTFLAGA register */ 171 #define PAC_INTFLAGA_SERCOM0_Pos _UINT32_(12) /* (PAC_INTFLAGA) SERCOM0 Position */ 172 #define PAC_INTFLAGA_SERCOM0_Msk (_UINT32_(0x1) << PAC_INTFLAGA_SERCOM0_Pos) /* (PAC_INTFLAGA) SERCOM0 Mask */ 173 #define PAC_INTFLAGA_SERCOM0(value) (PAC_INTFLAGA_SERCOM0_Msk & (_UINT32_(value) << PAC_INTFLAGA_SERCOM0_Pos)) /* Assigment of value for SERCOM0 in the PAC_INTFLAGA register */ 174 #define PAC_INTFLAGA_SERCOM1_Pos _UINT32_(13) /* (PAC_INTFLAGA) SERCOM1 Position */ 175 #define PAC_INTFLAGA_SERCOM1_Msk (_UINT32_(0x1) << PAC_INTFLAGA_SERCOM1_Pos) /* (PAC_INTFLAGA) SERCOM1 Mask */ 176 #define PAC_INTFLAGA_SERCOM1(value) (PAC_INTFLAGA_SERCOM1_Msk & (_UINT32_(value) << PAC_INTFLAGA_SERCOM1_Pos)) /* Assigment of value for SERCOM1 in the PAC_INTFLAGA register */ 177 #define PAC_INTFLAGA_TC0_Pos _UINT32_(14) /* (PAC_INTFLAGA) TC0 Position */ 178 #define PAC_INTFLAGA_TC0_Msk (_UINT32_(0x1) << PAC_INTFLAGA_TC0_Pos) /* (PAC_INTFLAGA) TC0 Mask */ 179 #define PAC_INTFLAGA_TC0(value) (PAC_INTFLAGA_TC0_Msk & (_UINT32_(value) << PAC_INTFLAGA_TC0_Pos)) /* Assigment of value for TC0 in the PAC_INTFLAGA register */ 180 #define PAC_INTFLAGA_TC1_Pos _UINT32_(15) /* (PAC_INTFLAGA) TC1 Position */ 181 #define PAC_INTFLAGA_TC1_Msk (_UINT32_(0x1) << PAC_INTFLAGA_TC1_Pos) /* (PAC_INTFLAGA) TC1 Mask */ 182 #define PAC_INTFLAGA_TC1(value) (PAC_INTFLAGA_TC1_Msk & (_UINT32_(value) << PAC_INTFLAGA_TC1_Pos)) /* Assigment of value for TC1 in the PAC_INTFLAGA register */ 183 #define PAC_INTFLAGA_Msk _UINT32_(0x0000FFFF) /* (PAC_INTFLAGA) Register Mask */ 184 185 #define PAC_INTFLAGA_SERCOM_Pos _UINT32_(12) /* (PAC_INTFLAGA Position) SERCOMx */ 186 #define PAC_INTFLAGA_SERCOM_Msk (_UINT32_(0x3) << PAC_INTFLAGA_SERCOM_Pos) /* (PAC_INTFLAGA Mask) SERCOM */ 187 #define PAC_INTFLAGA_SERCOM(value) (PAC_INTFLAGA_SERCOM_Msk & (_UINT32_(value) << PAC_INTFLAGA_SERCOM_Pos)) 188 #define PAC_INTFLAGA_TC_Pos _UINT32_(14) /* (PAC_INTFLAGA Position) TCx */ 189 #define PAC_INTFLAGA_TC_Msk (_UINT32_(0x3) << PAC_INTFLAGA_TC_Pos) /* (PAC_INTFLAGA Mask) TC */ 190 #define PAC_INTFLAGA_TC(value) (PAC_INTFLAGA_TC_Msk & (_UINT32_(value) << PAC_INTFLAGA_TC_Pos)) 191 192 /* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */ 193 #define PAC_INTFLAGB_RESETVALUE _UINT32_(0x00) /* (PAC_INTFLAGB) Peripheral interrupt flag status - Bridge B Reset Value */ 194 195 #define PAC_INTFLAGB_USB_Pos _UINT32_(0) /* (PAC_INTFLAGB) USB Position */ 196 #define PAC_INTFLAGB_USB_Msk (_UINT32_(0x1) << PAC_INTFLAGB_USB_Pos) /* (PAC_INTFLAGB) USB Mask */ 197 #define PAC_INTFLAGB_USB(value) (PAC_INTFLAGB_USB_Msk & (_UINT32_(value) << PAC_INTFLAGB_USB_Pos)) /* Assigment of value for USB in the PAC_INTFLAGB register */ 198 #define PAC_INTFLAGB_DSU_Pos _UINT32_(1) /* (PAC_INTFLAGB) DSU Position */ 199 #define PAC_INTFLAGB_DSU_Msk (_UINT32_(0x1) << PAC_INTFLAGB_DSU_Pos) /* (PAC_INTFLAGB) DSU Mask */ 200 #define PAC_INTFLAGB_DSU(value) (PAC_INTFLAGB_DSU_Msk & (_UINT32_(value) << PAC_INTFLAGB_DSU_Pos)) /* Assigment of value for DSU in the PAC_INTFLAGB register */ 201 #define PAC_INTFLAGB_NVMCTRL_Pos _UINT32_(2) /* (PAC_INTFLAGB) NVMCTRL Position */ 202 #define PAC_INTFLAGB_NVMCTRL_Msk (_UINT32_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos) /* (PAC_INTFLAGB) NVMCTRL Mask */ 203 #define PAC_INTFLAGB_NVMCTRL(value) (PAC_INTFLAGB_NVMCTRL_Msk & (_UINT32_(value) << PAC_INTFLAGB_NVMCTRL_Pos)) /* Assigment of value for NVMCTRL in the PAC_INTFLAGB register */ 204 #define PAC_INTFLAGB_CMCC_Pos _UINT32_(3) /* (PAC_INTFLAGB) CMCC Position */ 205 #define PAC_INTFLAGB_CMCC_Msk (_UINT32_(0x1) << PAC_INTFLAGB_CMCC_Pos) /* (PAC_INTFLAGB) CMCC Mask */ 206 #define PAC_INTFLAGB_CMCC(value) (PAC_INTFLAGB_CMCC_Msk & (_UINT32_(value) << PAC_INTFLAGB_CMCC_Pos)) /* Assigment of value for CMCC in the PAC_INTFLAGB register */ 207 #define PAC_INTFLAGB_PORT_Pos _UINT32_(4) /* (PAC_INTFLAGB) PORT Position */ 208 #define PAC_INTFLAGB_PORT_Msk (_UINT32_(0x1) << PAC_INTFLAGB_PORT_Pos) /* (PAC_INTFLAGB) PORT Mask */ 209 #define PAC_INTFLAGB_PORT(value) (PAC_INTFLAGB_PORT_Msk & (_UINT32_(value) << PAC_INTFLAGB_PORT_Pos)) /* Assigment of value for PORT in the PAC_INTFLAGB register */ 210 #define PAC_INTFLAGB_DMAC_Pos _UINT32_(5) /* (PAC_INTFLAGB) DMAC Position */ 211 #define PAC_INTFLAGB_DMAC_Msk (_UINT32_(0x1) << PAC_INTFLAGB_DMAC_Pos) /* (PAC_INTFLAGB) DMAC Mask */ 212 #define PAC_INTFLAGB_DMAC(value) (PAC_INTFLAGB_DMAC_Msk & (_UINT32_(value) << PAC_INTFLAGB_DMAC_Pos)) /* Assigment of value for DMAC in the PAC_INTFLAGB register */ 213 #define PAC_INTFLAGB_EVSYS_Pos _UINT32_(7) /* (PAC_INTFLAGB) EVSYS Position */ 214 #define PAC_INTFLAGB_EVSYS_Msk (_UINT32_(0x1) << PAC_INTFLAGB_EVSYS_Pos) /* (PAC_INTFLAGB) EVSYS Mask */ 215 #define PAC_INTFLAGB_EVSYS(value) (PAC_INTFLAGB_EVSYS_Msk & (_UINT32_(value) << PAC_INTFLAGB_EVSYS_Pos)) /* Assigment of value for EVSYS in the PAC_INTFLAGB register */ 216 #define PAC_INTFLAGB_SERCOM2_Pos _UINT32_(9) /* (PAC_INTFLAGB) SERCOM2 Position */ 217 #define PAC_INTFLAGB_SERCOM2_Msk (_UINT32_(0x1) << PAC_INTFLAGB_SERCOM2_Pos) /* (PAC_INTFLAGB) SERCOM2 Mask */ 218 #define PAC_INTFLAGB_SERCOM2(value) (PAC_INTFLAGB_SERCOM2_Msk & (_UINT32_(value) << PAC_INTFLAGB_SERCOM2_Pos)) /* Assigment of value for SERCOM2 in the PAC_INTFLAGB register */ 219 #define PAC_INTFLAGB_SERCOM3_Pos _UINT32_(10) /* (PAC_INTFLAGB) SERCOM3 Position */ 220 #define PAC_INTFLAGB_SERCOM3_Msk (_UINT32_(0x1) << PAC_INTFLAGB_SERCOM3_Pos) /* (PAC_INTFLAGB) SERCOM3 Mask */ 221 #define PAC_INTFLAGB_SERCOM3(value) (PAC_INTFLAGB_SERCOM3_Msk & (_UINT32_(value) << PAC_INTFLAGB_SERCOM3_Pos)) /* Assigment of value for SERCOM3 in the PAC_INTFLAGB register */ 222 #define PAC_INTFLAGB_TCC0_Pos _UINT32_(11) /* (PAC_INTFLAGB) TCC0 Position */ 223 #define PAC_INTFLAGB_TCC0_Msk (_UINT32_(0x1) << PAC_INTFLAGB_TCC0_Pos) /* (PAC_INTFLAGB) TCC0 Mask */ 224 #define PAC_INTFLAGB_TCC0(value) (PAC_INTFLAGB_TCC0_Msk & (_UINT32_(value) << PAC_INTFLAGB_TCC0_Pos)) /* Assigment of value for TCC0 in the PAC_INTFLAGB register */ 225 #define PAC_INTFLAGB_TCC1_Pos _UINT32_(12) /* (PAC_INTFLAGB) TCC1 Position */ 226 #define PAC_INTFLAGB_TCC1_Msk (_UINT32_(0x1) << PAC_INTFLAGB_TCC1_Pos) /* (PAC_INTFLAGB) TCC1 Mask */ 227 #define PAC_INTFLAGB_TCC1(value) (PAC_INTFLAGB_TCC1_Msk & (_UINT32_(value) << PAC_INTFLAGB_TCC1_Pos)) /* Assigment of value for TCC1 in the PAC_INTFLAGB register */ 228 #define PAC_INTFLAGB_TC2_Pos _UINT32_(13) /* (PAC_INTFLAGB) TC2 Position */ 229 #define PAC_INTFLAGB_TC2_Msk (_UINT32_(0x1) << PAC_INTFLAGB_TC2_Pos) /* (PAC_INTFLAGB) TC2 Mask */ 230 #define PAC_INTFLAGB_TC2(value) (PAC_INTFLAGB_TC2_Msk & (_UINT32_(value) << PAC_INTFLAGB_TC2_Pos)) /* Assigment of value for TC2 in the PAC_INTFLAGB register */ 231 #define PAC_INTFLAGB_TC3_Pos _UINT32_(14) /* (PAC_INTFLAGB) TC3 Position */ 232 #define PAC_INTFLAGB_TC3_Msk (_UINT32_(0x1) << PAC_INTFLAGB_TC3_Pos) /* (PAC_INTFLAGB) TC3 Mask */ 233 #define PAC_INTFLAGB_TC3(value) (PAC_INTFLAGB_TC3_Msk & (_UINT32_(value) << PAC_INTFLAGB_TC3_Pos)) /* Assigment of value for TC3 in the PAC_INTFLAGB register */ 234 #define PAC_INTFLAGB_RAMECC_Pos _UINT32_(16) /* (PAC_INTFLAGB) RAMECC Position */ 235 #define PAC_INTFLAGB_RAMECC_Msk (_UINT32_(0x1) << PAC_INTFLAGB_RAMECC_Pos) /* (PAC_INTFLAGB) RAMECC Mask */ 236 #define PAC_INTFLAGB_RAMECC(value) (PAC_INTFLAGB_RAMECC_Msk & (_UINT32_(value) << PAC_INTFLAGB_RAMECC_Pos)) /* Assigment of value for RAMECC in the PAC_INTFLAGB register */ 237 #define PAC_INTFLAGB_Msk _UINT32_(0x00017EBF) /* (PAC_INTFLAGB) Register Mask */ 238 239 #define PAC_INTFLAGB_SERCOM_Pos _UINT32_(9) /* (PAC_INTFLAGB Position) SERCOM2 */ 240 #define PAC_INTFLAGB_SERCOM_Msk (_UINT32_(0x3) << PAC_INTFLAGB_SERCOM_Pos) /* (PAC_INTFLAGB Mask) SERCOM */ 241 #define PAC_INTFLAGB_SERCOM(value) (PAC_INTFLAGB_SERCOM_Msk & (_UINT32_(value) << PAC_INTFLAGB_SERCOM_Pos)) 242 #define PAC_INTFLAGB_TCC_Pos _UINT32_(11) /* (PAC_INTFLAGB Position) TCCx */ 243 #define PAC_INTFLAGB_TCC_Msk (_UINT32_(0x3) << PAC_INTFLAGB_TCC_Pos) /* (PAC_INTFLAGB Mask) TCC */ 244 #define PAC_INTFLAGB_TCC(value) (PAC_INTFLAGB_TCC_Msk & (_UINT32_(value) << PAC_INTFLAGB_TCC_Pos)) 245 #define PAC_INTFLAGB_TC_Pos _UINT32_(13) /* (PAC_INTFLAGB Position) TC2 */ 246 #define PAC_INTFLAGB_TC_Msk (_UINT32_(0x3) << PAC_INTFLAGB_TC_Pos) /* (PAC_INTFLAGB Mask) TC */ 247 #define PAC_INTFLAGB_TC(value) (PAC_INTFLAGB_TC_Msk & (_UINT32_(value) << PAC_INTFLAGB_TC_Pos)) 248 249 /* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */ 250 #define PAC_INTFLAGC_RESETVALUE _UINT32_(0x00) /* (PAC_INTFLAGC) Peripheral interrupt flag status - Bridge C Reset Value */ 251 252 #define PAC_INTFLAGC_CAN0_Pos _UINT32_(0) /* (PAC_INTFLAGC) CAN0 Position */ 253 #define PAC_INTFLAGC_CAN0_Msk (_UINT32_(0x1) << PAC_INTFLAGC_CAN0_Pos) /* (PAC_INTFLAGC) CAN0 Mask */ 254 #define PAC_INTFLAGC_CAN0(value) (PAC_INTFLAGC_CAN0_Msk & (_UINT32_(value) << PAC_INTFLAGC_CAN0_Pos)) /* Assigment of value for CAN0 in the PAC_INTFLAGC register */ 255 #define PAC_INTFLAGC_CAN1_Pos _UINT32_(1) /* (PAC_INTFLAGC) CAN1 Position */ 256 #define PAC_INTFLAGC_CAN1_Msk (_UINT32_(0x1) << PAC_INTFLAGC_CAN1_Pos) /* (PAC_INTFLAGC) CAN1 Mask */ 257 #define PAC_INTFLAGC_CAN1(value) (PAC_INTFLAGC_CAN1_Msk & (_UINT32_(value) << PAC_INTFLAGC_CAN1_Pos)) /* Assigment of value for CAN1 in the PAC_INTFLAGC register */ 258 #define PAC_INTFLAGC_GMAC_Pos _UINT32_(2) /* (PAC_INTFLAGC) GMAC Position */ 259 #define PAC_INTFLAGC_GMAC_Msk (_UINT32_(0x1) << PAC_INTFLAGC_GMAC_Pos) /* (PAC_INTFLAGC) GMAC Mask */ 260 #define PAC_INTFLAGC_GMAC(value) (PAC_INTFLAGC_GMAC_Msk & (_UINT32_(value) << PAC_INTFLAGC_GMAC_Pos)) /* Assigment of value for GMAC in the PAC_INTFLAGC register */ 261 #define PAC_INTFLAGC_TCC2_Pos _UINT32_(3) /* (PAC_INTFLAGC) TCC2 Position */ 262 #define PAC_INTFLAGC_TCC2_Msk (_UINT32_(0x1) << PAC_INTFLAGC_TCC2_Pos) /* (PAC_INTFLAGC) TCC2 Mask */ 263 #define PAC_INTFLAGC_TCC2(value) (PAC_INTFLAGC_TCC2_Msk & (_UINT32_(value) << PAC_INTFLAGC_TCC2_Pos)) /* Assigment of value for TCC2 in the PAC_INTFLAGC register */ 264 #define PAC_INTFLAGC_TCC3_Pos _UINT32_(4) /* (PAC_INTFLAGC) TCC3 Position */ 265 #define PAC_INTFLAGC_TCC3_Msk (_UINT32_(0x1) << PAC_INTFLAGC_TCC3_Pos) /* (PAC_INTFLAGC) TCC3 Mask */ 266 #define PAC_INTFLAGC_TCC3(value) (PAC_INTFLAGC_TCC3_Msk & (_UINT32_(value) << PAC_INTFLAGC_TCC3_Pos)) /* Assigment of value for TCC3 in the PAC_INTFLAGC register */ 267 #define PAC_INTFLAGC_TC4_Pos _UINT32_(5) /* (PAC_INTFLAGC) TC4 Position */ 268 #define PAC_INTFLAGC_TC4_Msk (_UINT32_(0x1) << PAC_INTFLAGC_TC4_Pos) /* (PAC_INTFLAGC) TC4 Mask */ 269 #define PAC_INTFLAGC_TC4(value) (PAC_INTFLAGC_TC4_Msk & (_UINT32_(value) << PAC_INTFLAGC_TC4_Pos)) /* Assigment of value for TC4 in the PAC_INTFLAGC register */ 270 #define PAC_INTFLAGC_TC5_Pos _UINT32_(6) /* (PAC_INTFLAGC) TC5 Position */ 271 #define PAC_INTFLAGC_TC5_Msk (_UINT32_(0x1) << PAC_INTFLAGC_TC5_Pos) /* (PAC_INTFLAGC) TC5 Mask */ 272 #define PAC_INTFLAGC_TC5(value) (PAC_INTFLAGC_TC5_Msk & (_UINT32_(value) << PAC_INTFLAGC_TC5_Pos)) /* Assigment of value for TC5 in the PAC_INTFLAGC register */ 273 #define PAC_INTFLAGC_PDEC_Pos _UINT32_(7) /* (PAC_INTFLAGC) PDEC Position */ 274 #define PAC_INTFLAGC_PDEC_Msk (_UINT32_(0x1) << PAC_INTFLAGC_PDEC_Pos) /* (PAC_INTFLAGC) PDEC Mask */ 275 #define PAC_INTFLAGC_PDEC(value) (PAC_INTFLAGC_PDEC_Msk & (_UINT32_(value) << PAC_INTFLAGC_PDEC_Pos)) /* Assigment of value for PDEC in the PAC_INTFLAGC register */ 276 #define PAC_INTFLAGC_AC_Pos _UINT32_(8) /* (PAC_INTFLAGC) AC Position */ 277 #define PAC_INTFLAGC_AC_Msk (_UINT32_(0x1) << PAC_INTFLAGC_AC_Pos) /* (PAC_INTFLAGC) AC Mask */ 278 #define PAC_INTFLAGC_AC(value) (PAC_INTFLAGC_AC_Msk & (_UINT32_(value) << PAC_INTFLAGC_AC_Pos)) /* Assigment of value for AC in the PAC_INTFLAGC register */ 279 #define PAC_INTFLAGC_AES_Pos _UINT32_(9) /* (PAC_INTFLAGC) AES Position */ 280 #define PAC_INTFLAGC_AES_Msk (_UINT32_(0x1) << PAC_INTFLAGC_AES_Pos) /* (PAC_INTFLAGC) AES Mask */ 281 #define PAC_INTFLAGC_AES(value) (PAC_INTFLAGC_AES_Msk & (_UINT32_(value) << PAC_INTFLAGC_AES_Pos)) /* Assigment of value for AES in the PAC_INTFLAGC register */ 282 #define PAC_INTFLAGC_TRNG_Pos _UINT32_(10) /* (PAC_INTFLAGC) TRNG Position */ 283 #define PAC_INTFLAGC_TRNG_Msk (_UINT32_(0x1) << PAC_INTFLAGC_TRNG_Pos) /* (PAC_INTFLAGC) TRNG Mask */ 284 #define PAC_INTFLAGC_TRNG(value) (PAC_INTFLAGC_TRNG_Msk & (_UINT32_(value) << PAC_INTFLAGC_TRNG_Pos)) /* Assigment of value for TRNG in the PAC_INTFLAGC register */ 285 #define PAC_INTFLAGC_ICM_Pos _UINT32_(11) /* (PAC_INTFLAGC) ICM Position */ 286 #define PAC_INTFLAGC_ICM_Msk (_UINT32_(0x1) << PAC_INTFLAGC_ICM_Pos) /* (PAC_INTFLAGC) ICM Mask */ 287 #define PAC_INTFLAGC_ICM(value) (PAC_INTFLAGC_ICM_Msk & (_UINT32_(value) << PAC_INTFLAGC_ICM_Pos)) /* Assigment of value for ICM in the PAC_INTFLAGC register */ 288 #define PAC_INTFLAGC_PUKCC_Pos _UINT32_(12) /* (PAC_INTFLAGC) PUKCC Position */ 289 #define PAC_INTFLAGC_PUKCC_Msk (_UINT32_(0x1) << PAC_INTFLAGC_PUKCC_Pos) /* (PAC_INTFLAGC) PUKCC Mask */ 290 #define PAC_INTFLAGC_PUKCC(value) (PAC_INTFLAGC_PUKCC_Msk & (_UINT32_(value) << PAC_INTFLAGC_PUKCC_Pos)) /* Assigment of value for PUKCC in the PAC_INTFLAGC register */ 291 #define PAC_INTFLAGC_QSPI_Pos _UINT32_(13) /* (PAC_INTFLAGC) QSPI Position */ 292 #define PAC_INTFLAGC_QSPI_Msk (_UINT32_(0x1) << PAC_INTFLAGC_QSPI_Pos) /* (PAC_INTFLAGC) QSPI Mask */ 293 #define PAC_INTFLAGC_QSPI(value) (PAC_INTFLAGC_QSPI_Msk & (_UINT32_(value) << PAC_INTFLAGC_QSPI_Pos)) /* Assigment of value for QSPI in the PAC_INTFLAGC register */ 294 #define PAC_INTFLAGC_CCL_Pos _UINT32_(14) /* (PAC_INTFLAGC) CCL Position */ 295 #define PAC_INTFLAGC_CCL_Msk (_UINT32_(0x1) << PAC_INTFLAGC_CCL_Pos) /* (PAC_INTFLAGC) CCL Mask */ 296 #define PAC_INTFLAGC_CCL(value) (PAC_INTFLAGC_CCL_Msk & (_UINT32_(value) << PAC_INTFLAGC_CCL_Pos)) /* Assigment of value for CCL in the PAC_INTFLAGC register */ 297 #define PAC_INTFLAGC_Msk _UINT32_(0x00007FFF) /* (PAC_INTFLAGC) Register Mask */ 298 299 #define PAC_INTFLAGC_CAN_Pos _UINT32_(0) /* (PAC_INTFLAGC Position) CANx */ 300 #define PAC_INTFLAGC_CAN_Msk (_UINT32_(0x3) << PAC_INTFLAGC_CAN_Pos) /* (PAC_INTFLAGC Mask) CAN */ 301 #define PAC_INTFLAGC_CAN(value) (PAC_INTFLAGC_CAN_Msk & (_UINT32_(value) << PAC_INTFLAGC_CAN_Pos)) 302 #define PAC_INTFLAGC_TCC_Pos _UINT32_(3) /* (PAC_INTFLAGC Position) TCC2 */ 303 #define PAC_INTFLAGC_TCC_Msk (_UINT32_(0x3) << PAC_INTFLAGC_TCC_Pos) /* (PAC_INTFLAGC Mask) TCC */ 304 #define PAC_INTFLAGC_TCC(value) (PAC_INTFLAGC_TCC_Msk & (_UINT32_(value) << PAC_INTFLAGC_TCC_Pos)) 305 #define PAC_INTFLAGC_TC_Pos _UINT32_(5) /* (PAC_INTFLAGC Position) TC4 */ 306 #define PAC_INTFLAGC_TC_Msk (_UINT32_(0x3) << PAC_INTFLAGC_TC_Pos) /* (PAC_INTFLAGC Mask) TC */ 307 #define PAC_INTFLAGC_TC(value) (PAC_INTFLAGC_TC_Msk & (_UINT32_(value) << PAC_INTFLAGC_TC_Pos)) 308 309 /* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */ 310 #define PAC_INTFLAGD_RESETVALUE _UINT32_(0x00) /* (PAC_INTFLAGD) Peripheral interrupt flag status - Bridge D Reset Value */ 311 312 #define PAC_INTFLAGD_SERCOM4_Pos _UINT32_(0) /* (PAC_INTFLAGD) SERCOM4 Position */ 313 #define PAC_INTFLAGD_SERCOM4_Msk (_UINT32_(0x1) << PAC_INTFLAGD_SERCOM4_Pos) /* (PAC_INTFLAGD) SERCOM4 Mask */ 314 #define PAC_INTFLAGD_SERCOM4(value) (PAC_INTFLAGD_SERCOM4_Msk & (_UINT32_(value) << PAC_INTFLAGD_SERCOM4_Pos)) /* Assigment of value for SERCOM4 in the PAC_INTFLAGD register */ 315 #define PAC_INTFLAGD_SERCOM5_Pos _UINT32_(1) /* (PAC_INTFLAGD) SERCOM5 Position */ 316 #define PAC_INTFLAGD_SERCOM5_Msk (_UINT32_(0x1) << PAC_INTFLAGD_SERCOM5_Pos) /* (PAC_INTFLAGD) SERCOM5 Mask */ 317 #define PAC_INTFLAGD_SERCOM5(value) (PAC_INTFLAGD_SERCOM5_Msk & (_UINT32_(value) << PAC_INTFLAGD_SERCOM5_Pos)) /* Assigment of value for SERCOM5 in the PAC_INTFLAGD register */ 318 #define PAC_INTFLAGD_SERCOM6_Pos _UINT32_(2) /* (PAC_INTFLAGD) SERCOM6 Position */ 319 #define PAC_INTFLAGD_SERCOM6_Msk (_UINT32_(0x1) << PAC_INTFLAGD_SERCOM6_Pos) /* (PAC_INTFLAGD) SERCOM6 Mask */ 320 #define PAC_INTFLAGD_SERCOM6(value) (PAC_INTFLAGD_SERCOM6_Msk & (_UINT32_(value) << PAC_INTFLAGD_SERCOM6_Pos)) /* Assigment of value for SERCOM6 in the PAC_INTFLAGD register */ 321 #define PAC_INTFLAGD_SERCOM7_Pos _UINT32_(3) /* (PAC_INTFLAGD) SERCOM7 Position */ 322 #define PAC_INTFLAGD_SERCOM7_Msk (_UINT32_(0x1) << PAC_INTFLAGD_SERCOM7_Pos) /* (PAC_INTFLAGD) SERCOM7 Mask */ 323 #define PAC_INTFLAGD_SERCOM7(value) (PAC_INTFLAGD_SERCOM7_Msk & (_UINT32_(value) << PAC_INTFLAGD_SERCOM7_Pos)) /* Assigment of value for SERCOM7 in the PAC_INTFLAGD register */ 324 #define PAC_INTFLAGD_TCC4_Pos _UINT32_(4) /* (PAC_INTFLAGD) TCC4 Position */ 325 #define PAC_INTFLAGD_TCC4_Msk (_UINT32_(0x1) << PAC_INTFLAGD_TCC4_Pos) /* (PAC_INTFLAGD) TCC4 Mask */ 326 #define PAC_INTFLAGD_TCC4(value) (PAC_INTFLAGD_TCC4_Msk & (_UINT32_(value) << PAC_INTFLAGD_TCC4_Pos)) /* Assigment of value for TCC4 in the PAC_INTFLAGD register */ 327 #define PAC_INTFLAGD_TC6_Pos _UINT32_(5) /* (PAC_INTFLAGD) TC6 Position */ 328 #define PAC_INTFLAGD_TC6_Msk (_UINT32_(0x1) << PAC_INTFLAGD_TC6_Pos) /* (PAC_INTFLAGD) TC6 Mask */ 329 #define PAC_INTFLAGD_TC6(value) (PAC_INTFLAGD_TC6_Msk & (_UINT32_(value) << PAC_INTFLAGD_TC6_Pos)) /* Assigment of value for TC6 in the PAC_INTFLAGD register */ 330 #define PAC_INTFLAGD_TC7_Pos _UINT32_(6) /* (PAC_INTFLAGD) TC7 Position */ 331 #define PAC_INTFLAGD_TC7_Msk (_UINT32_(0x1) << PAC_INTFLAGD_TC7_Pos) /* (PAC_INTFLAGD) TC7 Mask */ 332 #define PAC_INTFLAGD_TC7(value) (PAC_INTFLAGD_TC7_Msk & (_UINT32_(value) << PAC_INTFLAGD_TC7_Pos)) /* Assigment of value for TC7 in the PAC_INTFLAGD register */ 333 #define PAC_INTFLAGD_ADC0_Pos _UINT32_(7) /* (PAC_INTFLAGD) ADC0 Position */ 334 #define PAC_INTFLAGD_ADC0_Msk (_UINT32_(0x1) << PAC_INTFLAGD_ADC0_Pos) /* (PAC_INTFLAGD) ADC0 Mask */ 335 #define PAC_INTFLAGD_ADC0(value) (PAC_INTFLAGD_ADC0_Msk & (_UINT32_(value) << PAC_INTFLAGD_ADC0_Pos)) /* Assigment of value for ADC0 in the PAC_INTFLAGD register */ 336 #define PAC_INTFLAGD_ADC1_Pos _UINT32_(8) /* (PAC_INTFLAGD) ADC1 Position */ 337 #define PAC_INTFLAGD_ADC1_Msk (_UINT32_(0x1) << PAC_INTFLAGD_ADC1_Pos) /* (PAC_INTFLAGD) ADC1 Mask */ 338 #define PAC_INTFLAGD_ADC1(value) (PAC_INTFLAGD_ADC1_Msk & (_UINT32_(value) << PAC_INTFLAGD_ADC1_Pos)) /* Assigment of value for ADC1 in the PAC_INTFLAGD register */ 339 #define PAC_INTFLAGD_DAC_Pos _UINT32_(9) /* (PAC_INTFLAGD) DAC Position */ 340 #define PAC_INTFLAGD_DAC_Msk (_UINT32_(0x1) << PAC_INTFLAGD_DAC_Pos) /* (PAC_INTFLAGD) DAC Mask */ 341 #define PAC_INTFLAGD_DAC(value) (PAC_INTFLAGD_DAC_Msk & (_UINT32_(value) << PAC_INTFLAGD_DAC_Pos)) /* Assigment of value for DAC in the PAC_INTFLAGD register */ 342 #define PAC_INTFLAGD_I2S_Pos _UINT32_(10) /* (PAC_INTFLAGD) I2S Position */ 343 #define PAC_INTFLAGD_I2S_Msk (_UINT32_(0x1) << PAC_INTFLAGD_I2S_Pos) /* (PAC_INTFLAGD) I2S Mask */ 344 #define PAC_INTFLAGD_I2S(value) (PAC_INTFLAGD_I2S_Msk & (_UINT32_(value) << PAC_INTFLAGD_I2S_Pos)) /* Assigment of value for I2S in the PAC_INTFLAGD register */ 345 #define PAC_INTFLAGD_PCC_Pos _UINT32_(11) /* (PAC_INTFLAGD) PCC Position */ 346 #define PAC_INTFLAGD_PCC_Msk (_UINT32_(0x1) << PAC_INTFLAGD_PCC_Pos) /* (PAC_INTFLAGD) PCC Mask */ 347 #define PAC_INTFLAGD_PCC(value) (PAC_INTFLAGD_PCC_Msk & (_UINT32_(value) << PAC_INTFLAGD_PCC_Pos)) /* Assigment of value for PCC in the PAC_INTFLAGD register */ 348 #define PAC_INTFLAGD_Msk _UINT32_(0x00000FFF) /* (PAC_INTFLAGD) Register Mask */ 349 350 #define PAC_INTFLAGD_SERCOM_Pos _UINT32_(0) /* (PAC_INTFLAGD Position) SERCOM4 */ 351 #define PAC_INTFLAGD_SERCOM_Msk (_UINT32_(0xF) << PAC_INTFLAGD_SERCOM_Pos) /* (PAC_INTFLAGD Mask) SERCOM */ 352 #define PAC_INTFLAGD_SERCOM(value) (PAC_INTFLAGD_SERCOM_Msk & (_UINT32_(value) << PAC_INTFLAGD_SERCOM_Pos)) 353 #define PAC_INTFLAGD_TCC_Pos _UINT32_(4) /* (PAC_INTFLAGD Position) TCC4 */ 354 #define PAC_INTFLAGD_TCC_Msk (_UINT32_(0x1) << PAC_INTFLAGD_TCC_Pos) /* (PAC_INTFLAGD Mask) TCC */ 355 #define PAC_INTFLAGD_TCC(value) (PAC_INTFLAGD_TCC_Msk & (_UINT32_(value) << PAC_INTFLAGD_TCC_Pos)) 356 #define PAC_INTFLAGD_TC_Pos _UINT32_(5) /* (PAC_INTFLAGD Position) TC6 */ 357 #define PAC_INTFLAGD_TC_Msk (_UINT32_(0x3) << PAC_INTFLAGD_TC_Pos) /* (PAC_INTFLAGD Mask) TC */ 358 #define PAC_INTFLAGD_TC(value) (PAC_INTFLAGD_TC_Msk & (_UINT32_(value) << PAC_INTFLAGD_TC_Pos)) 359 #define PAC_INTFLAGD_ADC_Pos _UINT32_(7) /* (PAC_INTFLAGD Position) ADCx */ 360 #define PAC_INTFLAGD_ADC_Msk (_UINT32_(0x3) << PAC_INTFLAGD_ADC_Pos) /* (PAC_INTFLAGD Mask) ADC */ 361 #define PAC_INTFLAGD_ADC(value) (PAC_INTFLAGD_ADC_Msk & (_UINT32_(value) << PAC_INTFLAGD_ADC_Pos)) 362 363 /* -------- PAC_STATUSA : (PAC Offset: 0x34) ( R/ 32) Peripheral write protection status - Bridge A -------- */ 364 #define PAC_STATUSA_RESETVALUE _UINT32_(0x10000) /* (PAC_STATUSA) Peripheral write protection status - Bridge A Reset Value */ 365 366 #define PAC_STATUSA_PAC_Pos _UINT32_(0) /* (PAC_STATUSA) PAC APB Protect Enable Position */ 367 #define PAC_STATUSA_PAC_Msk (_UINT32_(0x1) << PAC_STATUSA_PAC_Pos) /* (PAC_STATUSA) PAC APB Protect Enable Mask */ 368 #define PAC_STATUSA_PAC(value) (PAC_STATUSA_PAC_Msk & (_UINT32_(value) << PAC_STATUSA_PAC_Pos)) /* Assigment of value for PAC in the PAC_STATUSA register */ 369 #define PAC_STATUSA_PM_Pos _UINT32_(1) /* (PAC_STATUSA) PM APB Protect Enable Position */ 370 #define PAC_STATUSA_PM_Msk (_UINT32_(0x1) << PAC_STATUSA_PM_Pos) /* (PAC_STATUSA) PM APB Protect Enable Mask */ 371 #define PAC_STATUSA_PM(value) (PAC_STATUSA_PM_Msk & (_UINT32_(value) << PAC_STATUSA_PM_Pos)) /* Assigment of value for PM in the PAC_STATUSA register */ 372 #define PAC_STATUSA_MCLK_Pos _UINT32_(2) /* (PAC_STATUSA) MCLK APB Protect Enable Position */ 373 #define PAC_STATUSA_MCLK_Msk (_UINT32_(0x1) << PAC_STATUSA_MCLK_Pos) /* (PAC_STATUSA) MCLK APB Protect Enable Mask */ 374 #define PAC_STATUSA_MCLK(value) (PAC_STATUSA_MCLK_Msk & (_UINT32_(value) << PAC_STATUSA_MCLK_Pos)) /* Assigment of value for MCLK in the PAC_STATUSA register */ 375 #define PAC_STATUSA_RSTC_Pos _UINT32_(3) /* (PAC_STATUSA) RSTC APB Protect Enable Position */ 376 #define PAC_STATUSA_RSTC_Msk (_UINT32_(0x1) << PAC_STATUSA_RSTC_Pos) /* (PAC_STATUSA) RSTC APB Protect Enable Mask */ 377 #define PAC_STATUSA_RSTC(value) (PAC_STATUSA_RSTC_Msk & (_UINT32_(value) << PAC_STATUSA_RSTC_Pos)) /* Assigment of value for RSTC in the PAC_STATUSA register */ 378 #define PAC_STATUSA_OSCCTRL_Pos _UINT32_(4) /* (PAC_STATUSA) OSCCTRL APB Protect Enable Position */ 379 #define PAC_STATUSA_OSCCTRL_Msk (_UINT32_(0x1) << PAC_STATUSA_OSCCTRL_Pos) /* (PAC_STATUSA) OSCCTRL APB Protect Enable Mask */ 380 #define PAC_STATUSA_OSCCTRL(value) (PAC_STATUSA_OSCCTRL_Msk & (_UINT32_(value) << PAC_STATUSA_OSCCTRL_Pos)) /* Assigment of value for OSCCTRL in the PAC_STATUSA register */ 381 #define PAC_STATUSA_OSC32KCTRL_Pos _UINT32_(5) /* (PAC_STATUSA) OSC32KCTRL APB Protect Enable Position */ 382 #define PAC_STATUSA_OSC32KCTRL_Msk (_UINT32_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos) /* (PAC_STATUSA) OSC32KCTRL APB Protect Enable Mask */ 383 #define PAC_STATUSA_OSC32KCTRL(value) (PAC_STATUSA_OSC32KCTRL_Msk & (_UINT32_(value) << PAC_STATUSA_OSC32KCTRL_Pos)) /* Assigment of value for OSC32KCTRL in the PAC_STATUSA register */ 384 #define PAC_STATUSA_SUPC_Pos _UINT32_(6) /* (PAC_STATUSA) SUPC APB Protect Enable Position */ 385 #define PAC_STATUSA_SUPC_Msk (_UINT32_(0x1) << PAC_STATUSA_SUPC_Pos) /* (PAC_STATUSA) SUPC APB Protect Enable Mask */ 386 #define PAC_STATUSA_SUPC(value) (PAC_STATUSA_SUPC_Msk & (_UINT32_(value) << PAC_STATUSA_SUPC_Pos)) /* Assigment of value for SUPC in the PAC_STATUSA register */ 387 #define PAC_STATUSA_GCLK_Pos _UINT32_(7) /* (PAC_STATUSA) GCLK APB Protect Enable Position */ 388 #define PAC_STATUSA_GCLK_Msk (_UINT32_(0x1) << PAC_STATUSA_GCLK_Pos) /* (PAC_STATUSA) GCLK APB Protect Enable Mask */ 389 #define PAC_STATUSA_GCLK(value) (PAC_STATUSA_GCLK_Msk & (_UINT32_(value) << PAC_STATUSA_GCLK_Pos)) /* Assigment of value for GCLK in the PAC_STATUSA register */ 390 #define PAC_STATUSA_WDT_Pos _UINT32_(8) /* (PAC_STATUSA) WDT APB Protect Enable Position */ 391 #define PAC_STATUSA_WDT_Msk (_UINT32_(0x1) << PAC_STATUSA_WDT_Pos) /* (PAC_STATUSA) WDT APB Protect Enable Mask */ 392 #define PAC_STATUSA_WDT(value) (PAC_STATUSA_WDT_Msk & (_UINT32_(value) << PAC_STATUSA_WDT_Pos)) /* Assigment of value for WDT in the PAC_STATUSA register */ 393 #define PAC_STATUSA_RTC_Pos _UINT32_(9) /* (PAC_STATUSA) RTC APB Protect Enable Position */ 394 #define PAC_STATUSA_RTC_Msk (_UINT32_(0x1) << PAC_STATUSA_RTC_Pos) /* (PAC_STATUSA) RTC APB Protect Enable Mask */ 395 #define PAC_STATUSA_RTC(value) (PAC_STATUSA_RTC_Msk & (_UINT32_(value) << PAC_STATUSA_RTC_Pos)) /* Assigment of value for RTC in the PAC_STATUSA register */ 396 #define PAC_STATUSA_EIC_Pos _UINT32_(10) /* (PAC_STATUSA) EIC APB Protect Enable Position */ 397 #define PAC_STATUSA_EIC_Msk (_UINT32_(0x1) << PAC_STATUSA_EIC_Pos) /* (PAC_STATUSA) EIC APB Protect Enable Mask */ 398 #define PAC_STATUSA_EIC(value) (PAC_STATUSA_EIC_Msk & (_UINT32_(value) << PAC_STATUSA_EIC_Pos)) /* Assigment of value for EIC in the PAC_STATUSA register */ 399 #define PAC_STATUSA_FREQM_Pos _UINT32_(11) /* (PAC_STATUSA) FREQM APB Protect Enable Position */ 400 #define PAC_STATUSA_FREQM_Msk (_UINT32_(0x1) << PAC_STATUSA_FREQM_Pos) /* (PAC_STATUSA) FREQM APB Protect Enable Mask */ 401 #define PAC_STATUSA_FREQM(value) (PAC_STATUSA_FREQM_Msk & (_UINT32_(value) << PAC_STATUSA_FREQM_Pos)) /* Assigment of value for FREQM in the PAC_STATUSA register */ 402 #define PAC_STATUSA_SERCOM0_Pos _UINT32_(12) /* (PAC_STATUSA) SERCOM0 APB Protect Enable Position */ 403 #define PAC_STATUSA_SERCOM0_Msk (_UINT32_(0x1) << PAC_STATUSA_SERCOM0_Pos) /* (PAC_STATUSA) SERCOM0 APB Protect Enable Mask */ 404 #define PAC_STATUSA_SERCOM0(value) (PAC_STATUSA_SERCOM0_Msk & (_UINT32_(value) << PAC_STATUSA_SERCOM0_Pos)) /* Assigment of value for SERCOM0 in the PAC_STATUSA register */ 405 #define PAC_STATUSA_SERCOM1_Pos _UINT32_(13) /* (PAC_STATUSA) SERCOM1 APB Protect Enable Position */ 406 #define PAC_STATUSA_SERCOM1_Msk (_UINT32_(0x1) << PAC_STATUSA_SERCOM1_Pos) /* (PAC_STATUSA) SERCOM1 APB Protect Enable Mask */ 407 #define PAC_STATUSA_SERCOM1(value) (PAC_STATUSA_SERCOM1_Msk & (_UINT32_(value) << PAC_STATUSA_SERCOM1_Pos)) /* Assigment of value for SERCOM1 in the PAC_STATUSA register */ 408 #define PAC_STATUSA_TC0_Pos _UINT32_(14) /* (PAC_STATUSA) TC0 APB Protect Enable Position */ 409 #define PAC_STATUSA_TC0_Msk (_UINT32_(0x1) << PAC_STATUSA_TC0_Pos) /* (PAC_STATUSA) TC0 APB Protect Enable Mask */ 410 #define PAC_STATUSA_TC0(value) (PAC_STATUSA_TC0_Msk & (_UINT32_(value) << PAC_STATUSA_TC0_Pos)) /* Assigment of value for TC0 in the PAC_STATUSA register */ 411 #define PAC_STATUSA_TC1_Pos _UINT32_(15) /* (PAC_STATUSA) TC1 APB Protect Enable Position */ 412 #define PAC_STATUSA_TC1_Msk (_UINT32_(0x1) << PAC_STATUSA_TC1_Pos) /* (PAC_STATUSA) TC1 APB Protect Enable Mask */ 413 #define PAC_STATUSA_TC1(value) (PAC_STATUSA_TC1_Msk & (_UINT32_(value) << PAC_STATUSA_TC1_Pos)) /* Assigment of value for TC1 in the PAC_STATUSA register */ 414 #define PAC_STATUSA_Msk _UINT32_(0x0000FFFF) /* (PAC_STATUSA) Register Mask */ 415 416 #define PAC_STATUSA_SERCOM_Pos _UINT32_(12) /* (PAC_STATUSA Position) SERCOMx APB Protect Enable */ 417 #define PAC_STATUSA_SERCOM_Msk (_UINT32_(0x3) << PAC_STATUSA_SERCOM_Pos) /* (PAC_STATUSA Mask) SERCOM */ 418 #define PAC_STATUSA_SERCOM(value) (PAC_STATUSA_SERCOM_Msk & (_UINT32_(value) << PAC_STATUSA_SERCOM_Pos)) 419 #define PAC_STATUSA_TC_Pos _UINT32_(14) /* (PAC_STATUSA Position) TCx APB Protect Enable */ 420 #define PAC_STATUSA_TC_Msk (_UINT32_(0x3) << PAC_STATUSA_TC_Pos) /* (PAC_STATUSA Mask) TC */ 421 #define PAC_STATUSA_TC(value) (PAC_STATUSA_TC_Msk & (_UINT32_(value) << PAC_STATUSA_TC_Pos)) 422 423 /* -------- PAC_STATUSB : (PAC Offset: 0x38) ( R/ 32) Peripheral write protection status - Bridge B -------- */ 424 #define PAC_STATUSB_RESETVALUE _UINT32_(0x02) /* (PAC_STATUSB) Peripheral write protection status - Bridge B Reset Value */ 425 426 #define PAC_STATUSB_USB_Pos _UINT32_(0) /* (PAC_STATUSB) USB APB Protect Enable Position */ 427 #define PAC_STATUSB_USB_Msk (_UINT32_(0x1) << PAC_STATUSB_USB_Pos) /* (PAC_STATUSB) USB APB Protect Enable Mask */ 428 #define PAC_STATUSB_USB(value) (PAC_STATUSB_USB_Msk & (_UINT32_(value) << PAC_STATUSB_USB_Pos)) /* Assigment of value for USB in the PAC_STATUSB register */ 429 #define PAC_STATUSB_DSU_Pos _UINT32_(1) /* (PAC_STATUSB) DSU APB Protect Enable Position */ 430 #define PAC_STATUSB_DSU_Msk (_UINT32_(0x1) << PAC_STATUSB_DSU_Pos) /* (PAC_STATUSB) DSU APB Protect Enable Mask */ 431 #define PAC_STATUSB_DSU(value) (PAC_STATUSB_DSU_Msk & (_UINT32_(value) << PAC_STATUSB_DSU_Pos)) /* Assigment of value for DSU in the PAC_STATUSB register */ 432 #define PAC_STATUSB_NVMCTRL_Pos _UINT32_(2) /* (PAC_STATUSB) NVMCTRL APB Protect Enable Position */ 433 #define PAC_STATUSB_NVMCTRL_Msk (_UINT32_(0x1) << PAC_STATUSB_NVMCTRL_Pos) /* (PAC_STATUSB) NVMCTRL APB Protect Enable Mask */ 434 #define PAC_STATUSB_NVMCTRL(value) (PAC_STATUSB_NVMCTRL_Msk & (_UINT32_(value) << PAC_STATUSB_NVMCTRL_Pos)) /* Assigment of value for NVMCTRL in the PAC_STATUSB register */ 435 #define PAC_STATUSB_CMCC_Pos _UINT32_(3) /* (PAC_STATUSB) CMCC APB Protect Enable Position */ 436 #define PAC_STATUSB_CMCC_Msk (_UINT32_(0x1) << PAC_STATUSB_CMCC_Pos) /* (PAC_STATUSB) CMCC APB Protect Enable Mask */ 437 #define PAC_STATUSB_CMCC(value) (PAC_STATUSB_CMCC_Msk & (_UINT32_(value) << PAC_STATUSB_CMCC_Pos)) /* Assigment of value for CMCC in the PAC_STATUSB register */ 438 #define PAC_STATUSB_PORT_Pos _UINT32_(4) /* (PAC_STATUSB) PORT APB Protect Enable Position */ 439 #define PAC_STATUSB_PORT_Msk (_UINT32_(0x1) << PAC_STATUSB_PORT_Pos) /* (PAC_STATUSB) PORT APB Protect Enable Mask */ 440 #define PAC_STATUSB_PORT(value) (PAC_STATUSB_PORT_Msk & (_UINT32_(value) << PAC_STATUSB_PORT_Pos)) /* Assigment of value for PORT in the PAC_STATUSB register */ 441 #define PAC_STATUSB_DMAC_Pos _UINT32_(5) /* (PAC_STATUSB) DMAC APB Protect Enable Position */ 442 #define PAC_STATUSB_DMAC_Msk (_UINT32_(0x1) << PAC_STATUSB_DMAC_Pos) /* (PAC_STATUSB) DMAC APB Protect Enable Mask */ 443 #define PAC_STATUSB_DMAC(value) (PAC_STATUSB_DMAC_Msk & (_UINT32_(value) << PAC_STATUSB_DMAC_Pos)) /* Assigment of value for DMAC in the PAC_STATUSB register */ 444 #define PAC_STATUSB_EVSYS_Pos _UINT32_(7) /* (PAC_STATUSB) EVSYS APB Protect Enable Position */ 445 #define PAC_STATUSB_EVSYS_Msk (_UINT32_(0x1) << PAC_STATUSB_EVSYS_Pos) /* (PAC_STATUSB) EVSYS APB Protect Enable Mask */ 446 #define PAC_STATUSB_EVSYS(value) (PAC_STATUSB_EVSYS_Msk & (_UINT32_(value) << PAC_STATUSB_EVSYS_Pos)) /* Assigment of value for EVSYS in the PAC_STATUSB register */ 447 #define PAC_STATUSB_SERCOM2_Pos _UINT32_(9) /* (PAC_STATUSB) SERCOM2 APB Protect Enable Position */ 448 #define PAC_STATUSB_SERCOM2_Msk (_UINT32_(0x1) << PAC_STATUSB_SERCOM2_Pos) /* (PAC_STATUSB) SERCOM2 APB Protect Enable Mask */ 449 #define PAC_STATUSB_SERCOM2(value) (PAC_STATUSB_SERCOM2_Msk & (_UINT32_(value) << PAC_STATUSB_SERCOM2_Pos)) /* Assigment of value for SERCOM2 in the PAC_STATUSB register */ 450 #define PAC_STATUSB_SERCOM3_Pos _UINT32_(10) /* (PAC_STATUSB) SERCOM3 APB Protect Enable Position */ 451 #define PAC_STATUSB_SERCOM3_Msk (_UINT32_(0x1) << PAC_STATUSB_SERCOM3_Pos) /* (PAC_STATUSB) SERCOM3 APB Protect Enable Mask */ 452 #define PAC_STATUSB_SERCOM3(value) (PAC_STATUSB_SERCOM3_Msk & (_UINT32_(value) << PAC_STATUSB_SERCOM3_Pos)) /* Assigment of value for SERCOM3 in the PAC_STATUSB register */ 453 #define PAC_STATUSB_TCC0_Pos _UINT32_(11) /* (PAC_STATUSB) TCC0 APB Protect Enable Position */ 454 #define PAC_STATUSB_TCC0_Msk (_UINT32_(0x1) << PAC_STATUSB_TCC0_Pos) /* (PAC_STATUSB) TCC0 APB Protect Enable Mask */ 455 #define PAC_STATUSB_TCC0(value) (PAC_STATUSB_TCC0_Msk & (_UINT32_(value) << PAC_STATUSB_TCC0_Pos)) /* Assigment of value for TCC0 in the PAC_STATUSB register */ 456 #define PAC_STATUSB_TCC1_Pos _UINT32_(12) /* (PAC_STATUSB) TCC1 APB Protect Enable Position */ 457 #define PAC_STATUSB_TCC1_Msk (_UINT32_(0x1) << PAC_STATUSB_TCC1_Pos) /* (PAC_STATUSB) TCC1 APB Protect Enable Mask */ 458 #define PAC_STATUSB_TCC1(value) (PAC_STATUSB_TCC1_Msk & (_UINT32_(value) << PAC_STATUSB_TCC1_Pos)) /* Assigment of value for TCC1 in the PAC_STATUSB register */ 459 #define PAC_STATUSB_TC2_Pos _UINT32_(13) /* (PAC_STATUSB) TC2 APB Protect Enable Position */ 460 #define PAC_STATUSB_TC2_Msk (_UINT32_(0x1) << PAC_STATUSB_TC2_Pos) /* (PAC_STATUSB) TC2 APB Protect Enable Mask */ 461 #define PAC_STATUSB_TC2(value) (PAC_STATUSB_TC2_Msk & (_UINT32_(value) << PAC_STATUSB_TC2_Pos)) /* Assigment of value for TC2 in the PAC_STATUSB register */ 462 #define PAC_STATUSB_TC3_Pos _UINT32_(14) /* (PAC_STATUSB) TC3 APB Protect Enable Position */ 463 #define PAC_STATUSB_TC3_Msk (_UINT32_(0x1) << PAC_STATUSB_TC3_Pos) /* (PAC_STATUSB) TC3 APB Protect Enable Mask */ 464 #define PAC_STATUSB_TC3(value) (PAC_STATUSB_TC3_Msk & (_UINT32_(value) << PAC_STATUSB_TC3_Pos)) /* Assigment of value for TC3 in the PAC_STATUSB register */ 465 #define PAC_STATUSB_RAMECC_Pos _UINT32_(16) /* (PAC_STATUSB) RAMECC APB Protect Enable Position */ 466 #define PAC_STATUSB_RAMECC_Msk (_UINT32_(0x1) << PAC_STATUSB_RAMECC_Pos) /* (PAC_STATUSB) RAMECC APB Protect Enable Mask */ 467 #define PAC_STATUSB_RAMECC(value) (PAC_STATUSB_RAMECC_Msk & (_UINT32_(value) << PAC_STATUSB_RAMECC_Pos)) /* Assigment of value for RAMECC in the PAC_STATUSB register */ 468 #define PAC_STATUSB_Msk _UINT32_(0x00017EBF) /* (PAC_STATUSB) Register Mask */ 469 470 #define PAC_STATUSB_SERCOM_Pos _UINT32_(9) /* (PAC_STATUSB Position) SERCOM2 APB Protect Enable */ 471 #define PAC_STATUSB_SERCOM_Msk (_UINT32_(0x3) << PAC_STATUSB_SERCOM_Pos) /* (PAC_STATUSB Mask) SERCOM */ 472 #define PAC_STATUSB_SERCOM(value) (PAC_STATUSB_SERCOM_Msk & (_UINT32_(value) << PAC_STATUSB_SERCOM_Pos)) 473 #define PAC_STATUSB_TCC_Pos _UINT32_(11) /* (PAC_STATUSB Position) TCCx APB Protect Enable */ 474 #define PAC_STATUSB_TCC_Msk (_UINT32_(0x3) << PAC_STATUSB_TCC_Pos) /* (PAC_STATUSB Mask) TCC */ 475 #define PAC_STATUSB_TCC(value) (PAC_STATUSB_TCC_Msk & (_UINT32_(value) << PAC_STATUSB_TCC_Pos)) 476 #define PAC_STATUSB_TC_Pos _UINT32_(13) /* (PAC_STATUSB Position) TC2 APB Protect Enable */ 477 #define PAC_STATUSB_TC_Msk (_UINT32_(0x3) << PAC_STATUSB_TC_Pos) /* (PAC_STATUSB Mask) TC */ 478 #define PAC_STATUSB_TC(value) (PAC_STATUSB_TC_Msk & (_UINT32_(value) << PAC_STATUSB_TC_Pos)) 479 480 /* -------- PAC_STATUSC : (PAC Offset: 0x3C) ( R/ 32) Peripheral write protection status - Bridge C -------- */ 481 #define PAC_STATUSC_RESETVALUE _UINT32_(0x00) /* (PAC_STATUSC) Peripheral write protection status - Bridge C Reset Value */ 482 483 #define PAC_STATUSC_CAN0_Pos _UINT32_(0) /* (PAC_STATUSC) CAN0 APB Protect Enable Position */ 484 #define PAC_STATUSC_CAN0_Msk (_UINT32_(0x1) << PAC_STATUSC_CAN0_Pos) /* (PAC_STATUSC) CAN0 APB Protect Enable Mask */ 485 #define PAC_STATUSC_CAN0(value) (PAC_STATUSC_CAN0_Msk & (_UINT32_(value) << PAC_STATUSC_CAN0_Pos)) /* Assigment of value for CAN0 in the PAC_STATUSC register */ 486 #define PAC_STATUSC_CAN1_Pos _UINT32_(1) /* (PAC_STATUSC) CAN1 APB Protect Enable Position */ 487 #define PAC_STATUSC_CAN1_Msk (_UINT32_(0x1) << PAC_STATUSC_CAN1_Pos) /* (PAC_STATUSC) CAN1 APB Protect Enable Mask */ 488 #define PAC_STATUSC_CAN1(value) (PAC_STATUSC_CAN1_Msk & (_UINT32_(value) << PAC_STATUSC_CAN1_Pos)) /* Assigment of value for CAN1 in the PAC_STATUSC register */ 489 #define PAC_STATUSC_GMAC_Pos _UINT32_(2) /* (PAC_STATUSC) GMAC APB Protect Enable Position */ 490 #define PAC_STATUSC_GMAC_Msk (_UINT32_(0x1) << PAC_STATUSC_GMAC_Pos) /* (PAC_STATUSC) GMAC APB Protect Enable Mask */ 491 #define PAC_STATUSC_GMAC(value) (PAC_STATUSC_GMAC_Msk & (_UINT32_(value) << PAC_STATUSC_GMAC_Pos)) /* Assigment of value for GMAC in the PAC_STATUSC register */ 492 #define PAC_STATUSC_TCC2_Pos _UINT32_(3) /* (PAC_STATUSC) TCC2 APB Protect Enable Position */ 493 #define PAC_STATUSC_TCC2_Msk (_UINT32_(0x1) << PAC_STATUSC_TCC2_Pos) /* (PAC_STATUSC) TCC2 APB Protect Enable Mask */ 494 #define PAC_STATUSC_TCC2(value) (PAC_STATUSC_TCC2_Msk & (_UINT32_(value) << PAC_STATUSC_TCC2_Pos)) /* Assigment of value for TCC2 in the PAC_STATUSC register */ 495 #define PAC_STATUSC_TCC3_Pos _UINT32_(4) /* (PAC_STATUSC) TCC3 APB Protect Enable Position */ 496 #define PAC_STATUSC_TCC3_Msk (_UINT32_(0x1) << PAC_STATUSC_TCC3_Pos) /* (PAC_STATUSC) TCC3 APB Protect Enable Mask */ 497 #define PAC_STATUSC_TCC3(value) (PAC_STATUSC_TCC3_Msk & (_UINT32_(value) << PAC_STATUSC_TCC3_Pos)) /* Assigment of value for TCC3 in the PAC_STATUSC register */ 498 #define PAC_STATUSC_TC4_Pos _UINT32_(5) /* (PAC_STATUSC) TC4 APB Protect Enable Position */ 499 #define PAC_STATUSC_TC4_Msk (_UINT32_(0x1) << PAC_STATUSC_TC4_Pos) /* (PAC_STATUSC) TC4 APB Protect Enable Mask */ 500 #define PAC_STATUSC_TC4(value) (PAC_STATUSC_TC4_Msk & (_UINT32_(value) << PAC_STATUSC_TC4_Pos)) /* Assigment of value for TC4 in the PAC_STATUSC register */ 501 #define PAC_STATUSC_TC5_Pos _UINT32_(6) /* (PAC_STATUSC) TC5 APB Protect Enable Position */ 502 #define PAC_STATUSC_TC5_Msk (_UINT32_(0x1) << PAC_STATUSC_TC5_Pos) /* (PAC_STATUSC) TC5 APB Protect Enable Mask */ 503 #define PAC_STATUSC_TC5(value) (PAC_STATUSC_TC5_Msk & (_UINT32_(value) << PAC_STATUSC_TC5_Pos)) /* Assigment of value for TC5 in the PAC_STATUSC register */ 504 #define PAC_STATUSC_PDEC_Pos _UINT32_(7) /* (PAC_STATUSC) PDEC APB Protect Enable Position */ 505 #define PAC_STATUSC_PDEC_Msk (_UINT32_(0x1) << PAC_STATUSC_PDEC_Pos) /* (PAC_STATUSC) PDEC APB Protect Enable Mask */ 506 #define PAC_STATUSC_PDEC(value) (PAC_STATUSC_PDEC_Msk & (_UINT32_(value) << PAC_STATUSC_PDEC_Pos)) /* Assigment of value for PDEC in the PAC_STATUSC register */ 507 #define PAC_STATUSC_AC_Pos _UINT32_(8) /* (PAC_STATUSC) AC APB Protect Enable Position */ 508 #define PAC_STATUSC_AC_Msk (_UINT32_(0x1) << PAC_STATUSC_AC_Pos) /* (PAC_STATUSC) AC APB Protect Enable Mask */ 509 #define PAC_STATUSC_AC(value) (PAC_STATUSC_AC_Msk & (_UINT32_(value) << PAC_STATUSC_AC_Pos)) /* Assigment of value for AC in the PAC_STATUSC register */ 510 #define PAC_STATUSC_AES_Pos _UINT32_(9) /* (PAC_STATUSC) AES APB Protect Enable Position */ 511 #define PAC_STATUSC_AES_Msk (_UINT32_(0x1) << PAC_STATUSC_AES_Pos) /* (PAC_STATUSC) AES APB Protect Enable Mask */ 512 #define PAC_STATUSC_AES(value) (PAC_STATUSC_AES_Msk & (_UINT32_(value) << PAC_STATUSC_AES_Pos)) /* Assigment of value for AES in the PAC_STATUSC register */ 513 #define PAC_STATUSC_TRNG_Pos _UINT32_(10) /* (PAC_STATUSC) TRNG APB Protect Enable Position */ 514 #define PAC_STATUSC_TRNG_Msk (_UINT32_(0x1) << PAC_STATUSC_TRNG_Pos) /* (PAC_STATUSC) TRNG APB Protect Enable Mask */ 515 #define PAC_STATUSC_TRNG(value) (PAC_STATUSC_TRNG_Msk & (_UINT32_(value) << PAC_STATUSC_TRNG_Pos)) /* Assigment of value for TRNG in the PAC_STATUSC register */ 516 #define PAC_STATUSC_ICM_Pos _UINT32_(11) /* (PAC_STATUSC) ICM APB Protect Enable Position */ 517 #define PAC_STATUSC_ICM_Msk (_UINT32_(0x1) << PAC_STATUSC_ICM_Pos) /* (PAC_STATUSC) ICM APB Protect Enable Mask */ 518 #define PAC_STATUSC_ICM(value) (PAC_STATUSC_ICM_Msk & (_UINT32_(value) << PAC_STATUSC_ICM_Pos)) /* Assigment of value for ICM in the PAC_STATUSC register */ 519 #define PAC_STATUSC_PUKCC_Pos _UINT32_(12) /* (PAC_STATUSC) PUKCC APB Protect Enable Position */ 520 #define PAC_STATUSC_PUKCC_Msk (_UINT32_(0x1) << PAC_STATUSC_PUKCC_Pos) /* (PAC_STATUSC) PUKCC APB Protect Enable Mask */ 521 #define PAC_STATUSC_PUKCC(value) (PAC_STATUSC_PUKCC_Msk & (_UINT32_(value) << PAC_STATUSC_PUKCC_Pos)) /* Assigment of value for PUKCC in the PAC_STATUSC register */ 522 #define PAC_STATUSC_QSPI_Pos _UINT32_(13) /* (PAC_STATUSC) QSPI APB Protect Enable Position */ 523 #define PAC_STATUSC_QSPI_Msk (_UINT32_(0x1) << PAC_STATUSC_QSPI_Pos) /* (PAC_STATUSC) QSPI APB Protect Enable Mask */ 524 #define PAC_STATUSC_QSPI(value) (PAC_STATUSC_QSPI_Msk & (_UINT32_(value) << PAC_STATUSC_QSPI_Pos)) /* Assigment of value for QSPI in the PAC_STATUSC register */ 525 #define PAC_STATUSC_CCL_Pos _UINT32_(14) /* (PAC_STATUSC) CCL APB Protect Enable Position */ 526 #define PAC_STATUSC_CCL_Msk (_UINT32_(0x1) << PAC_STATUSC_CCL_Pos) /* (PAC_STATUSC) CCL APB Protect Enable Mask */ 527 #define PAC_STATUSC_CCL(value) (PAC_STATUSC_CCL_Msk & (_UINT32_(value) << PAC_STATUSC_CCL_Pos)) /* Assigment of value for CCL in the PAC_STATUSC register */ 528 #define PAC_STATUSC_Msk _UINT32_(0x00007FFF) /* (PAC_STATUSC) Register Mask */ 529 530 #define PAC_STATUSC_CAN_Pos _UINT32_(0) /* (PAC_STATUSC Position) CANx APB Protect Enable */ 531 #define PAC_STATUSC_CAN_Msk (_UINT32_(0x3) << PAC_STATUSC_CAN_Pos) /* (PAC_STATUSC Mask) CAN */ 532 #define PAC_STATUSC_CAN(value) (PAC_STATUSC_CAN_Msk & (_UINT32_(value) << PAC_STATUSC_CAN_Pos)) 533 #define PAC_STATUSC_TCC_Pos _UINT32_(3) /* (PAC_STATUSC Position) TCC2 APB Protect Enable */ 534 #define PAC_STATUSC_TCC_Msk (_UINT32_(0x3) << PAC_STATUSC_TCC_Pos) /* (PAC_STATUSC Mask) TCC */ 535 #define PAC_STATUSC_TCC(value) (PAC_STATUSC_TCC_Msk & (_UINT32_(value) << PAC_STATUSC_TCC_Pos)) 536 #define PAC_STATUSC_TC_Pos _UINT32_(5) /* (PAC_STATUSC Position) TC4 APB Protect Enable */ 537 #define PAC_STATUSC_TC_Msk (_UINT32_(0x3) << PAC_STATUSC_TC_Pos) /* (PAC_STATUSC Mask) TC */ 538 #define PAC_STATUSC_TC(value) (PAC_STATUSC_TC_Msk & (_UINT32_(value) << PAC_STATUSC_TC_Pos)) 539 540 /* -------- PAC_STATUSD : (PAC Offset: 0x40) ( R/ 32) Peripheral write protection status - Bridge D -------- */ 541 #define PAC_STATUSD_RESETVALUE _UINT32_(0x00) /* (PAC_STATUSD) Peripheral write protection status - Bridge D Reset Value */ 542 543 #define PAC_STATUSD_SERCOM4_Pos _UINT32_(0) /* (PAC_STATUSD) SERCOM4 APB Protect Enable Position */ 544 #define PAC_STATUSD_SERCOM4_Msk (_UINT32_(0x1) << PAC_STATUSD_SERCOM4_Pos) /* (PAC_STATUSD) SERCOM4 APB Protect Enable Mask */ 545 #define PAC_STATUSD_SERCOM4(value) (PAC_STATUSD_SERCOM4_Msk & (_UINT32_(value) << PAC_STATUSD_SERCOM4_Pos)) /* Assigment of value for SERCOM4 in the PAC_STATUSD register */ 546 #define PAC_STATUSD_SERCOM5_Pos _UINT32_(1) /* (PAC_STATUSD) SERCOM5 APB Protect Enable Position */ 547 #define PAC_STATUSD_SERCOM5_Msk (_UINT32_(0x1) << PAC_STATUSD_SERCOM5_Pos) /* (PAC_STATUSD) SERCOM5 APB Protect Enable Mask */ 548 #define PAC_STATUSD_SERCOM5(value) (PAC_STATUSD_SERCOM5_Msk & (_UINT32_(value) << PAC_STATUSD_SERCOM5_Pos)) /* Assigment of value for SERCOM5 in the PAC_STATUSD register */ 549 #define PAC_STATUSD_SERCOM6_Pos _UINT32_(2) /* (PAC_STATUSD) SERCOM6 APB Protect Enable Position */ 550 #define PAC_STATUSD_SERCOM6_Msk (_UINT32_(0x1) << PAC_STATUSD_SERCOM6_Pos) /* (PAC_STATUSD) SERCOM6 APB Protect Enable Mask */ 551 #define PAC_STATUSD_SERCOM6(value) (PAC_STATUSD_SERCOM6_Msk & (_UINT32_(value) << PAC_STATUSD_SERCOM6_Pos)) /* Assigment of value for SERCOM6 in the PAC_STATUSD register */ 552 #define PAC_STATUSD_SERCOM7_Pos _UINT32_(3) /* (PAC_STATUSD) SERCOM7 APB Protect Enable Position */ 553 #define PAC_STATUSD_SERCOM7_Msk (_UINT32_(0x1) << PAC_STATUSD_SERCOM7_Pos) /* (PAC_STATUSD) SERCOM7 APB Protect Enable Mask */ 554 #define PAC_STATUSD_SERCOM7(value) (PAC_STATUSD_SERCOM7_Msk & (_UINT32_(value) << PAC_STATUSD_SERCOM7_Pos)) /* Assigment of value for SERCOM7 in the PAC_STATUSD register */ 555 #define PAC_STATUSD_TCC4_Pos _UINT32_(4) /* (PAC_STATUSD) TCC4 APB Protect Enable Position */ 556 #define PAC_STATUSD_TCC4_Msk (_UINT32_(0x1) << PAC_STATUSD_TCC4_Pos) /* (PAC_STATUSD) TCC4 APB Protect Enable Mask */ 557 #define PAC_STATUSD_TCC4(value) (PAC_STATUSD_TCC4_Msk & (_UINT32_(value) << PAC_STATUSD_TCC4_Pos)) /* Assigment of value for TCC4 in the PAC_STATUSD register */ 558 #define PAC_STATUSD_TC6_Pos _UINT32_(5) /* (PAC_STATUSD) TC6 APB Protect Enable Position */ 559 #define PAC_STATUSD_TC6_Msk (_UINT32_(0x1) << PAC_STATUSD_TC6_Pos) /* (PAC_STATUSD) TC6 APB Protect Enable Mask */ 560 #define PAC_STATUSD_TC6(value) (PAC_STATUSD_TC6_Msk & (_UINT32_(value) << PAC_STATUSD_TC6_Pos)) /* Assigment of value for TC6 in the PAC_STATUSD register */ 561 #define PAC_STATUSD_TC7_Pos _UINT32_(6) /* (PAC_STATUSD) TC7 APB Protect Enable Position */ 562 #define PAC_STATUSD_TC7_Msk (_UINT32_(0x1) << PAC_STATUSD_TC7_Pos) /* (PAC_STATUSD) TC7 APB Protect Enable Mask */ 563 #define PAC_STATUSD_TC7(value) (PAC_STATUSD_TC7_Msk & (_UINT32_(value) << PAC_STATUSD_TC7_Pos)) /* Assigment of value for TC7 in the PAC_STATUSD register */ 564 #define PAC_STATUSD_ADC0_Pos _UINT32_(7) /* (PAC_STATUSD) ADC0 APB Protect Enable Position */ 565 #define PAC_STATUSD_ADC0_Msk (_UINT32_(0x1) << PAC_STATUSD_ADC0_Pos) /* (PAC_STATUSD) ADC0 APB Protect Enable Mask */ 566 #define PAC_STATUSD_ADC0(value) (PAC_STATUSD_ADC0_Msk & (_UINT32_(value) << PAC_STATUSD_ADC0_Pos)) /* Assigment of value for ADC0 in the PAC_STATUSD register */ 567 #define PAC_STATUSD_ADC1_Pos _UINT32_(8) /* (PAC_STATUSD) ADC1 APB Protect Enable Position */ 568 #define PAC_STATUSD_ADC1_Msk (_UINT32_(0x1) << PAC_STATUSD_ADC1_Pos) /* (PAC_STATUSD) ADC1 APB Protect Enable Mask */ 569 #define PAC_STATUSD_ADC1(value) (PAC_STATUSD_ADC1_Msk & (_UINT32_(value) << PAC_STATUSD_ADC1_Pos)) /* Assigment of value for ADC1 in the PAC_STATUSD register */ 570 #define PAC_STATUSD_DAC_Pos _UINT32_(9) /* (PAC_STATUSD) DAC APB Protect Enable Position */ 571 #define PAC_STATUSD_DAC_Msk (_UINT32_(0x1) << PAC_STATUSD_DAC_Pos) /* (PAC_STATUSD) DAC APB Protect Enable Mask */ 572 #define PAC_STATUSD_DAC(value) (PAC_STATUSD_DAC_Msk & (_UINT32_(value) << PAC_STATUSD_DAC_Pos)) /* Assigment of value for DAC in the PAC_STATUSD register */ 573 #define PAC_STATUSD_I2S_Pos _UINT32_(10) /* (PAC_STATUSD) I2S APB Protect Enable Position */ 574 #define PAC_STATUSD_I2S_Msk (_UINT32_(0x1) << PAC_STATUSD_I2S_Pos) /* (PAC_STATUSD) I2S APB Protect Enable Mask */ 575 #define PAC_STATUSD_I2S(value) (PAC_STATUSD_I2S_Msk & (_UINT32_(value) << PAC_STATUSD_I2S_Pos)) /* Assigment of value for I2S in the PAC_STATUSD register */ 576 #define PAC_STATUSD_PCC_Pos _UINT32_(11) /* (PAC_STATUSD) PCC APB Protect Enable Position */ 577 #define PAC_STATUSD_PCC_Msk (_UINT32_(0x1) << PAC_STATUSD_PCC_Pos) /* (PAC_STATUSD) PCC APB Protect Enable Mask */ 578 #define PAC_STATUSD_PCC(value) (PAC_STATUSD_PCC_Msk & (_UINT32_(value) << PAC_STATUSD_PCC_Pos)) /* Assigment of value for PCC in the PAC_STATUSD register */ 579 #define PAC_STATUSD_Msk _UINT32_(0x00000FFF) /* (PAC_STATUSD) Register Mask */ 580 581 #define PAC_STATUSD_SERCOM_Pos _UINT32_(0) /* (PAC_STATUSD Position) SERCOM4 APB Protect Enable */ 582 #define PAC_STATUSD_SERCOM_Msk (_UINT32_(0xF) << PAC_STATUSD_SERCOM_Pos) /* (PAC_STATUSD Mask) SERCOM */ 583 #define PAC_STATUSD_SERCOM(value) (PAC_STATUSD_SERCOM_Msk & (_UINT32_(value) << PAC_STATUSD_SERCOM_Pos)) 584 #define PAC_STATUSD_TCC_Pos _UINT32_(4) /* (PAC_STATUSD Position) TCC4 APB Protect Enable */ 585 #define PAC_STATUSD_TCC_Msk (_UINT32_(0x1) << PAC_STATUSD_TCC_Pos) /* (PAC_STATUSD Mask) TCC */ 586 #define PAC_STATUSD_TCC(value) (PAC_STATUSD_TCC_Msk & (_UINT32_(value) << PAC_STATUSD_TCC_Pos)) 587 #define PAC_STATUSD_TC_Pos _UINT32_(5) /* (PAC_STATUSD Position) TC6 APB Protect Enable */ 588 #define PAC_STATUSD_TC_Msk (_UINT32_(0x3) << PAC_STATUSD_TC_Pos) /* (PAC_STATUSD Mask) TC */ 589 #define PAC_STATUSD_TC(value) (PAC_STATUSD_TC_Msk & (_UINT32_(value) << PAC_STATUSD_TC_Pos)) 590 #define PAC_STATUSD_ADC_Pos _UINT32_(7) /* (PAC_STATUSD Position) ADCx APB Protect Enable */ 591 #define PAC_STATUSD_ADC_Msk (_UINT32_(0x3) << PAC_STATUSD_ADC_Pos) /* (PAC_STATUSD Mask) ADC */ 592 #define PAC_STATUSD_ADC(value) (PAC_STATUSD_ADC_Msk & (_UINT32_(value) << PAC_STATUSD_ADC_Pos)) 593 594 /** \brief PAC register offsets definitions */ 595 #define PAC_WRCTRL_REG_OFST _UINT32_(0x00) /* (PAC_WRCTRL) Write control Offset */ 596 #define PAC_EVCTRL_REG_OFST _UINT32_(0x04) /* (PAC_EVCTRL) Event control Offset */ 597 #define PAC_INTENCLR_REG_OFST _UINT32_(0x08) /* (PAC_INTENCLR) Interrupt enable clear Offset */ 598 #define PAC_INTENSET_REG_OFST _UINT32_(0x09) /* (PAC_INTENSET) Interrupt enable set Offset */ 599 #define PAC_INTFLAGAHB_REG_OFST _UINT32_(0x10) /* (PAC_INTFLAGAHB) Bridge interrupt flag status Offset */ 600 #define PAC_INTFLAGA_REG_OFST _UINT32_(0x14) /* (PAC_INTFLAGA) Peripheral interrupt flag status - Bridge A Offset */ 601 #define PAC_INTFLAGB_REG_OFST _UINT32_(0x18) /* (PAC_INTFLAGB) Peripheral interrupt flag status - Bridge B Offset */ 602 #define PAC_INTFLAGC_REG_OFST _UINT32_(0x1C) /* (PAC_INTFLAGC) Peripheral interrupt flag status - Bridge C Offset */ 603 #define PAC_INTFLAGD_REG_OFST _UINT32_(0x20) /* (PAC_INTFLAGD) Peripheral interrupt flag status - Bridge D Offset */ 604 #define PAC_STATUSA_REG_OFST _UINT32_(0x34) /* (PAC_STATUSA) Peripheral write protection status - Bridge A Offset */ 605 #define PAC_STATUSB_REG_OFST _UINT32_(0x38) /* (PAC_STATUSB) Peripheral write protection status - Bridge B Offset */ 606 #define PAC_STATUSC_REG_OFST _UINT32_(0x3C) /* (PAC_STATUSC) Peripheral write protection status - Bridge C Offset */ 607 #define PAC_STATUSD_REG_OFST _UINT32_(0x40) /* (PAC_STATUSD) Peripheral write protection status - Bridge D Offset */ 608 609 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 610 /** \brief PAC register API structure */ 611 typedef struct 612 { /* Peripheral Access Controller */ 613 __IO uint32_t PAC_WRCTRL; /**< Offset: 0x00 (R/W 32) Write control */ 614 __IO uint8_t PAC_EVCTRL; /**< Offset: 0x04 (R/W 8) Event control */ 615 __I uint8_t Reserved1[0x03]; 616 __IO uint8_t PAC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt enable clear */ 617 __IO uint8_t PAC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt enable set */ 618 __I uint8_t Reserved2[0x06]; 619 __IO uint32_t PAC_INTFLAGAHB; /**< Offset: 0x10 (R/W 32) Bridge interrupt flag status */ 620 __IO uint32_t PAC_INTFLAGA; /**< Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */ 621 __IO uint32_t PAC_INTFLAGB; /**< Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */ 622 __IO uint32_t PAC_INTFLAGC; /**< Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */ 623 __IO uint32_t PAC_INTFLAGD; /**< Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */ 624 __I uint8_t Reserved3[0x10]; 625 __I uint32_t PAC_STATUSA; /**< Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */ 626 __I uint32_t PAC_STATUSB; /**< Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */ 627 __I uint32_t PAC_STATUSC; /**< Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */ 628 __I uint32_t PAC_STATUSD; /**< Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */ 629 } pac_registers_t; 630 631 632 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 633 #endif /* _PIC32CXSG61_PAC_COMPONENT_H_ */ 634
