1 /* 2 * Peripheral I/O description for PIC32CX1025SG41064 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:50:01Z */ 21 #ifndef _PIC32CX1025SG41064_GPIO_H_ 22 #define _PIC32CX1025SG41064_GPIO_H_ 23 24 /* ======================= Peripheral I/O pin numbers ======================= */ 25 #define PIN_PA00 ( 0) /* Pin Number for PA00 */ 26 #define PIN_PA01 ( 1) /* Pin Number for PA01 */ 27 #define PIN_PA02 ( 2) /* Pin Number for PA02 */ 28 #define PIN_PA03 ( 3) /* Pin Number for PA03 */ 29 #define PIN_PA04 ( 4) /* Pin Number for PA04 */ 30 #define PIN_PA05 ( 5) /* Pin Number for PA05 */ 31 #define PIN_PA06 ( 6) /* Pin Number for PA06 */ 32 #define PIN_PA07 ( 7) /* Pin Number for PA07 */ 33 #define PIN_PA08 ( 8) /* Pin Number for PA08 */ 34 #define PIN_PA09 ( 9) /* Pin Number for PA09 */ 35 #define PIN_PA10 ( 10) /* Pin Number for PA10 */ 36 #define PIN_PA11 ( 11) /* Pin Number for PA11 */ 37 #define PIN_PA12 ( 12) /* Pin Number for PA12 */ 38 #define PIN_PA13 ( 13) /* Pin Number for PA13 */ 39 #define PIN_PA14 ( 14) /* Pin Number for PA14 */ 40 #define PIN_PA15 ( 15) /* Pin Number for PA15 */ 41 #define PIN_PA16 ( 16) /* Pin Number for PA16 */ 42 #define PIN_PA17 ( 17) /* Pin Number for PA17 */ 43 #define PIN_PA18 ( 18) /* Pin Number for PA18 */ 44 #define PIN_PA19 ( 19) /* Pin Number for PA19 */ 45 #define PIN_PA20 ( 20) /* Pin Number for PA20 */ 46 #define PIN_PA21 ( 21) /* Pin Number for PA21 */ 47 #define PIN_PA22 ( 22) /* Pin Number for PA22 */ 48 #define PIN_PA23 ( 23) /* Pin Number for PA23 */ 49 #define PIN_PA24 ( 24) /* Pin Number for PA24 */ 50 #define PIN_PA25 ( 25) /* Pin Number for PA25 */ 51 #define PIN_PA27 ( 27) /* Pin Number for PA27 */ 52 #define PIN_PA30 ( 30) /* Pin Number for PA30 */ 53 #define PIN_PA31 ( 31) /* Pin Number for PA31 */ 54 #define PIN_PB00 ( 32) /* Pin Number for PB00 */ 55 #define PIN_PB01 ( 33) /* Pin Number for PB01 */ 56 #define PIN_PB02 ( 34) /* Pin Number for PB02 */ 57 #define PIN_PB03 ( 35) /* Pin Number for PB03 */ 58 #define PIN_PB04 ( 36) /* Pin Number for PB04 */ 59 #define PIN_PB05 ( 37) /* Pin Number for PB05 */ 60 #define PIN_PB06 ( 38) /* Pin Number for PB06 */ 61 #define PIN_PB07 ( 39) /* Pin Number for PB07 */ 62 #define PIN_PB08 ( 40) /* Pin Number for PB08 */ 63 #define PIN_PB09 ( 41) /* Pin Number for PB09 */ 64 #define PIN_PB10 ( 42) /* Pin Number for PB10 */ 65 #define PIN_PB11 ( 43) /* Pin Number for PB11 */ 66 #define PIN_PB12 ( 44) /* Pin Number for PB12 */ 67 #define PIN_PB13 ( 45) /* Pin Number for PB13 */ 68 #define PIN_PB14 ( 46) /* Pin Number for PB14 */ 69 #define PIN_PB15 ( 47) /* Pin Number for PB15 */ 70 #define PIN_PB16 ( 48) /* Pin Number for PB16 */ 71 #define PIN_PB17 ( 49) /* Pin Number for PB17 */ 72 #define PIN_PB22 ( 54) /* Pin Number for PB22 */ 73 #define PIN_PB23 ( 55) /* Pin Number for PB23 */ 74 #define PIN_PB30 ( 62) /* Pin Number for PB30 */ 75 #define PIN_PB31 ( 63) /* Pin Number for PB31 */ 76 77 /* ========================== Peripheral I/O masks ========================== */ 78 #define PORT_PA00 (_UINT32_(1) << 0) /* PORT mask for PA00 */ 79 #define PORT_PA01 (_UINT32_(1) << 1) /* PORT mask for PA01 */ 80 #define PORT_PA02 (_UINT32_(1) << 2) /* PORT mask for PA02 */ 81 #define PORT_PA03 (_UINT32_(1) << 3) /* PORT mask for PA03 */ 82 #define PORT_PA04 (_UINT32_(1) << 4) /* PORT mask for PA04 */ 83 #define PORT_PA05 (_UINT32_(1) << 5) /* PORT mask for PA05 */ 84 #define PORT_PA06 (_UINT32_(1) << 6) /* PORT mask for PA06 */ 85 #define PORT_PA07 (_UINT32_(1) << 7) /* PORT mask for PA07 */ 86 #define PORT_PA08 (_UINT32_(1) << 8) /* PORT mask for PA08 */ 87 #define PORT_PA09 (_UINT32_(1) << 9) /* PORT mask for PA09 */ 88 #define PORT_PA10 (_UINT32_(1) << 10) /* PORT mask for PA10 */ 89 #define PORT_PA11 (_UINT32_(1) << 11) /* PORT mask for PA11 */ 90 #define PORT_PA12 (_UINT32_(1) << 12) /* PORT mask for PA12 */ 91 #define PORT_PA13 (_UINT32_(1) << 13) /* PORT mask for PA13 */ 92 #define PORT_PA14 (_UINT32_(1) << 14) /* PORT mask for PA14 */ 93 #define PORT_PA15 (_UINT32_(1) << 15) /* PORT mask for PA15 */ 94 #define PORT_PA16 (_UINT32_(1) << 16) /* PORT mask for PA16 */ 95 #define PORT_PA17 (_UINT32_(1) << 17) /* PORT mask for PA17 */ 96 #define PORT_PA18 (_UINT32_(1) << 18) /* PORT mask for PA18 */ 97 #define PORT_PA19 (_UINT32_(1) << 19) /* PORT mask for PA19 */ 98 #define PORT_PA20 (_UINT32_(1) << 20) /* PORT mask for PA20 */ 99 #define PORT_PA21 (_UINT32_(1) << 21) /* PORT mask for PA21 */ 100 #define PORT_PA22 (_UINT32_(1) << 22) /* PORT mask for PA22 */ 101 #define PORT_PA23 (_UINT32_(1) << 23) /* PORT mask for PA23 */ 102 #define PORT_PA24 (_UINT32_(1) << 24) /* PORT mask for PA24 */ 103 #define PORT_PA25 (_UINT32_(1) << 25) /* PORT mask for PA25 */ 104 #define PORT_PA27 (_UINT32_(1) << 27) /* PORT mask for PA27 */ 105 #define PORT_PA30 (_UINT32_(1) << 30) /* PORT mask for PA30 */ 106 #define PORT_PA31 (_UINT32_(1) << 31) /* PORT mask for PA31 */ 107 #define PORT_PB00 (_UINT32_(1) << 0) /* PORT mask for PB00 */ 108 #define PORT_PB01 (_UINT32_(1) << 1) /* PORT mask for PB01 */ 109 #define PORT_PB02 (_UINT32_(1) << 2) /* PORT mask for PB02 */ 110 #define PORT_PB03 (_UINT32_(1) << 3) /* PORT mask for PB03 */ 111 #define PORT_PB04 (_UINT32_(1) << 4) /* PORT mask for PB04 */ 112 #define PORT_PB05 (_UINT32_(1) << 5) /* PORT mask for PB05 */ 113 #define PORT_PB06 (_UINT32_(1) << 6) /* PORT mask for PB06 */ 114 #define PORT_PB07 (_UINT32_(1) << 7) /* PORT mask for PB07 */ 115 #define PORT_PB08 (_UINT32_(1) << 8) /* PORT mask for PB08 */ 116 #define PORT_PB09 (_UINT32_(1) << 9) /* PORT mask for PB09 */ 117 #define PORT_PB10 (_UINT32_(1) << 10) /* PORT mask for PB10 */ 118 #define PORT_PB11 (_UINT32_(1) << 11) /* PORT mask for PB11 */ 119 #define PORT_PB12 (_UINT32_(1) << 12) /* PORT mask for PB12 */ 120 #define PORT_PB13 (_UINT32_(1) << 13) /* PORT mask for PB13 */ 121 #define PORT_PB14 (_UINT32_(1) << 14) /* PORT mask for PB14 */ 122 #define PORT_PB15 (_UINT32_(1) << 15) /* PORT mask for PB15 */ 123 #define PORT_PB16 (_UINT32_(1) << 16) /* PORT mask for PB16 */ 124 #define PORT_PB17 (_UINT32_(1) << 17) /* PORT mask for PB17 */ 125 #define PORT_PB22 (_UINT32_(1) << 22) /* PORT mask for PB22 */ 126 #define PORT_PB23 (_UINT32_(1) << 23) /* PORT mask for PB23 */ 127 #define PORT_PB30 (_UINT32_(1) << 30) /* PORT mask for PB30 */ 128 #define PORT_PB31 (_UINT32_(1) << 31) /* PORT mask for PB31 */ 129 130 /* =================== PORT definition for AC peripheral ==================== */ 131 #define PIN_PA04B_AC_AIN0 _UINT32_(4) 132 #define MUX_PA04B_AC_AIN0 _UINT32_(1) 133 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 134 #define PORT_PA04B_AC_AIN0 (_UINT32_(1) << 4) 135 136 #define PIN_PA05B_AC_AIN1 _UINT32_(5) 137 #define MUX_PA05B_AC_AIN1 _UINT32_(1) 138 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 139 #define PORT_PA05B_AC_AIN1 (_UINT32_(1) << 5) 140 141 #define PIN_PA06B_AC_AIN2 _UINT32_(6) 142 #define MUX_PA06B_AC_AIN2 _UINT32_(1) 143 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 144 #define PORT_PA06B_AC_AIN2 (_UINT32_(1) << 6) 145 146 #define PIN_PA07B_AC_AIN3 _UINT32_(7) 147 #define MUX_PA07B_AC_AIN3 _UINT32_(1) 148 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 149 #define PORT_PA07B_AC_AIN3 (_UINT32_(1) << 7) 150 151 #define PIN_PA12M_AC_CMP0 _UINT32_(12) 152 #define MUX_PA12M_AC_CMP0 _UINT32_(12) 153 #define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) 154 #define PORT_PA12M_AC_CMP0 (_UINT32_(1) << 12) 155 156 #define PIN_PA18M_AC_CMP0 _UINT32_(18) 157 #define MUX_PA18M_AC_CMP0 _UINT32_(12) 158 #define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) 159 #define PORT_PA18M_AC_CMP0 (_UINT32_(1) << 18) 160 161 #define PIN_PA13M_AC_CMP1 _UINT32_(13) 162 #define MUX_PA13M_AC_CMP1 _UINT32_(12) 163 #define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) 164 #define PORT_PA13M_AC_CMP1 (_UINT32_(1) << 13) 165 166 #define PIN_PA19M_AC_CMP1 _UINT32_(19) 167 #define MUX_PA19M_AC_CMP1 _UINT32_(12) 168 #define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) 169 #define PORT_PA19M_AC_CMP1 (_UINT32_(1) << 19) 170 171 /* ================== PORT definition for ADC0 peripheral =================== */ 172 #define PIN_PA02B_ADC0_AIN0 _UINT32_(2) 173 #define MUX_PA02B_ADC0_AIN0 _UINT32_(1) 174 #define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) 175 #define PORT_PA02B_ADC0_AIN0 (_UINT32_(1) << 2) 176 177 #define PIN_PA03B_ADC0_AIN1 _UINT32_(3) 178 #define MUX_PA03B_ADC0_AIN1 _UINT32_(1) 179 #define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) 180 #define PORT_PA03B_ADC0_AIN1 (_UINT32_(1) << 3) 181 182 #define PIN_PB08B_ADC0_AIN2 _UINT32_(40) 183 #define MUX_PB08B_ADC0_AIN2 _UINT32_(1) 184 #define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) 185 #define PORT_PB08B_ADC0_AIN2 (_UINT32_(1) << 8) 186 187 #define PIN_PB09B_ADC0_AIN3 _UINT32_(41) 188 #define MUX_PB09B_ADC0_AIN3 _UINT32_(1) 189 #define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) 190 #define PORT_PB09B_ADC0_AIN3 (_UINT32_(1) << 9) 191 192 #define PIN_PA04B_ADC0_AIN4 _UINT32_(4) 193 #define MUX_PA04B_ADC0_AIN4 _UINT32_(1) 194 #define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) 195 #define PORT_PA04B_ADC0_AIN4 (_UINT32_(1) << 4) 196 197 #define PIN_PA05B_ADC0_AIN5 _UINT32_(5) 198 #define MUX_PA05B_ADC0_AIN5 _UINT32_(1) 199 #define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) 200 #define PORT_PA05B_ADC0_AIN5 (_UINT32_(1) << 5) 201 202 #define PIN_PA06B_ADC0_AIN6 _UINT32_(6) 203 #define MUX_PA06B_ADC0_AIN6 _UINT32_(1) 204 #define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) 205 #define PORT_PA06B_ADC0_AIN6 (_UINT32_(1) << 6) 206 207 #define PIN_PA07B_ADC0_AIN7 _UINT32_(7) 208 #define MUX_PA07B_ADC0_AIN7 _UINT32_(1) 209 #define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) 210 #define PORT_PA07B_ADC0_AIN7 (_UINT32_(1) << 7) 211 212 #define PIN_PA08B_ADC0_AIN8 _UINT32_(8) 213 #define MUX_PA08B_ADC0_AIN8 _UINT32_(1) 214 #define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) 215 #define PORT_PA08B_ADC0_AIN8 (_UINT32_(1) << 8) 216 217 #define PIN_PA09B_ADC0_AIN9 _UINT32_(9) 218 #define MUX_PA09B_ADC0_AIN9 _UINT32_(1) 219 #define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) 220 #define PORT_PA09B_ADC0_AIN9 (_UINT32_(1) << 9) 221 222 #define PIN_PA10B_ADC0_AIN10 _UINT32_(10) 223 #define MUX_PA10B_ADC0_AIN10 _UINT32_(1) 224 #define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) 225 #define PORT_PA10B_ADC0_AIN10 (_UINT32_(1) << 10) 226 227 #define PIN_PA11B_ADC0_AIN11 _UINT32_(11) 228 #define MUX_PA11B_ADC0_AIN11 _UINT32_(1) 229 #define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) 230 #define PORT_PA11B_ADC0_AIN11 (_UINT32_(1) << 11) 231 232 #define PIN_PB00B_ADC0_AIN12 _UINT32_(32) 233 #define MUX_PB00B_ADC0_AIN12 _UINT32_(1) 234 #define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) 235 #define PORT_PB00B_ADC0_AIN12 (_UINT32_(1) << 0) 236 237 #define PIN_PB01B_ADC0_AIN13 _UINT32_(33) 238 #define MUX_PB01B_ADC0_AIN13 _UINT32_(1) 239 #define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) 240 #define PORT_PB01B_ADC0_AIN13 (_UINT32_(1) << 1) 241 242 #define PIN_PB02B_ADC0_AIN14 _UINT32_(34) 243 #define MUX_PB02B_ADC0_AIN14 _UINT32_(1) 244 #define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) 245 #define PORT_PB02B_ADC0_AIN14 (_UINT32_(1) << 2) 246 247 #define PIN_PB03B_ADC0_AIN15 _UINT32_(35) 248 #define MUX_PB03B_ADC0_AIN15 _UINT32_(1) 249 #define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) 250 #define PORT_PB03B_ADC0_AIN15 (_UINT32_(1) << 3) 251 252 #define PIN_PA03B_ADC0_VREFA _UINT32_(3) 253 #define MUX_PA03B_ADC0_VREFA _UINT32_(1) 254 #define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) 255 #define PORT_PA03B_ADC0_VREFA (_UINT32_(1) << 3) 256 257 #define PIN_PA04B_ADC0_VREFB _UINT32_(4) 258 #define MUX_PA04B_ADC0_VREFB _UINT32_(1) 259 #define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) 260 #define PORT_PA04B_ADC0_VREFB (_UINT32_(1) << 4) 261 262 #define PIN_PA06B_ADC0_VREFC _UINT32_(6) 263 #define MUX_PA06B_ADC0_VREFC _UINT32_(1) 264 #define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) 265 #define PORT_PA06B_ADC0_VREFC (_UINT32_(1) << 6) 266 267 #define PIN_PA03B_ADC0_X0 _UINT32_(3) 268 #define MUX_PA03B_ADC0_X0 _UINT32_(1) 269 #define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) 270 #define PORT_PA03B_ADC0_X0 (_UINT32_(1) << 3) 271 272 #define PIN_PB08B_ADC0_X1 _UINT32_(40) 273 #define MUX_PB08B_ADC0_X1 _UINT32_(1) 274 #define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) 275 #define PORT_PB08B_ADC0_X1 (_UINT32_(1) << 8) 276 277 #define PIN_PB09B_ADC0_X2 _UINT32_(41) 278 #define MUX_PB09B_ADC0_X2 _UINT32_(1) 279 #define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) 280 #define PORT_PB09B_ADC0_X2 (_UINT32_(1) << 9) 281 282 #define PIN_PA04B_ADC0_X3 _UINT32_(4) 283 #define MUX_PA04B_ADC0_X3 _UINT32_(1) 284 #define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) 285 #define PORT_PA04B_ADC0_X3 (_UINT32_(1) << 4) 286 287 #define PIN_PA06B_ADC0_X4 _UINT32_(6) 288 #define MUX_PA06B_ADC0_X4 _UINT32_(1) 289 #define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) 290 #define PORT_PA06B_ADC0_X4 (_UINT32_(1) << 6) 291 292 #define PIN_PA07B_ADC0_X5 _UINT32_(7) 293 #define MUX_PA07B_ADC0_X5 _UINT32_(1) 294 #define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) 295 #define PORT_PA07B_ADC0_X5 (_UINT32_(1) << 7) 296 297 #define PIN_PA08B_ADC0_X6 _UINT32_(8) 298 #define MUX_PA08B_ADC0_X6 _UINT32_(1) 299 #define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) 300 #define PORT_PA08B_ADC0_X6 (_UINT32_(1) << 8) 301 302 #define PIN_PA09B_ADC0_X7 _UINT32_(9) 303 #define MUX_PA09B_ADC0_X7 _UINT32_(1) 304 #define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) 305 #define PORT_PA09B_ADC0_X7 (_UINT32_(1) << 9) 306 307 #define PIN_PA10B_ADC0_X8 _UINT32_(10) 308 #define MUX_PA10B_ADC0_X8 _UINT32_(1) 309 #define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) 310 #define PORT_PA10B_ADC0_X8 (_UINT32_(1) << 10) 311 312 #define PIN_PA11B_ADC0_X9 _UINT32_(11) 313 #define MUX_PA11B_ADC0_X9 _UINT32_(1) 314 #define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) 315 #define PORT_PA11B_ADC0_X9 (_UINT32_(1) << 11) 316 317 #define PIN_PA16B_ADC0_X10 _UINT32_(16) 318 #define MUX_PA16B_ADC0_X10 _UINT32_(1) 319 #define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) 320 #define PORT_PA16B_ADC0_X10 (_UINT32_(1) << 16) 321 322 #define PIN_PA17B_ADC0_X11 _UINT32_(17) 323 #define MUX_PA17B_ADC0_X11 _UINT32_(1) 324 #define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) 325 #define PORT_PA17B_ADC0_X11 (_UINT32_(1) << 17) 326 327 #define PIN_PA18B_ADC0_X12 _UINT32_(18) 328 #define MUX_PA18B_ADC0_X12 _UINT32_(1) 329 #define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) 330 #define PORT_PA18B_ADC0_X12 (_UINT32_(1) << 18) 331 332 #define PIN_PA19B_ADC0_X13 _UINT32_(19) 333 #define MUX_PA19B_ADC0_X13 _UINT32_(1) 334 #define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) 335 #define PORT_PA19B_ADC0_X13 (_UINT32_(1) << 19) 336 337 #define PIN_PA20B_ADC0_X14 _UINT32_(20) 338 #define MUX_PA20B_ADC0_X14 _UINT32_(1) 339 #define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) 340 #define PORT_PA20B_ADC0_X14 (_UINT32_(1) << 20) 341 342 #define PIN_PA21B_ADC0_X15 _UINT32_(21) 343 #define MUX_PA21B_ADC0_X15 _UINT32_(1) 344 #define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) 345 #define PORT_PA21B_ADC0_X15 (_UINT32_(1) << 21) 346 347 #define PIN_PA22B_ADC0_X16 _UINT32_(22) 348 #define MUX_PA22B_ADC0_X16 _UINT32_(1) 349 #define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) 350 #define PORT_PA22B_ADC0_X16 (_UINT32_(1) << 22) 351 352 #define PIN_PA23B_ADC0_X17 _UINT32_(23) 353 #define MUX_PA23B_ADC0_X17 _UINT32_(1) 354 #define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) 355 #define PORT_PA23B_ADC0_X17 (_UINT32_(1) << 23) 356 357 #define PIN_PA27B_ADC0_X18 _UINT32_(27) 358 #define MUX_PA27B_ADC0_X18 _UINT32_(1) 359 #define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) 360 #define PORT_PA27B_ADC0_X18 (_UINT32_(1) << 27) 361 362 #define PIN_PA30B_ADC0_X19 _UINT32_(30) 363 #define MUX_PA30B_ADC0_X19 _UINT32_(1) 364 #define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) 365 #define PORT_PA30B_ADC0_X19 (_UINT32_(1) << 30) 366 367 #define PIN_PB02B_ADC0_X20 _UINT32_(34) 368 #define MUX_PB02B_ADC0_X20 _UINT32_(1) 369 #define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) 370 #define PORT_PB02B_ADC0_X20 (_UINT32_(1) << 2) 371 372 #define PIN_PB03B_ADC0_X21 _UINT32_(35) 373 #define MUX_PB03B_ADC0_X21 _UINT32_(1) 374 #define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) 375 #define PORT_PB03B_ADC0_X21 (_UINT32_(1) << 3) 376 377 #define PIN_PB04B_ADC0_X22 _UINT32_(36) 378 #define MUX_PB04B_ADC0_X22 _UINT32_(1) 379 #define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) 380 #define PORT_PB04B_ADC0_X22 (_UINT32_(1) << 4) 381 382 #define PIN_PB05B_ADC0_X23 _UINT32_(37) 383 #define MUX_PB05B_ADC0_X23 _UINT32_(1) 384 #define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) 385 #define PORT_PB05B_ADC0_X23 (_UINT32_(1) << 5) 386 387 #define PIN_PB06B_ADC0_X24 _UINT32_(38) 388 #define MUX_PB06B_ADC0_X24 _UINT32_(1) 389 #define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) 390 #define PORT_PB06B_ADC0_X24 (_UINT32_(1) << 6) 391 392 #define PIN_PB07B_ADC0_X25 _UINT32_(39) 393 #define MUX_PB07B_ADC0_X25 _UINT32_(1) 394 #define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) 395 #define PORT_PB07B_ADC0_X25 (_UINT32_(1) << 7) 396 397 #define PIN_PB12B_ADC0_X26 _UINT32_(44) 398 #define MUX_PB12B_ADC0_X26 _UINT32_(1) 399 #define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) 400 #define PORT_PB12B_ADC0_X26 (_UINT32_(1) << 12) 401 402 #define PIN_PB13B_ADC0_X27 _UINT32_(45) 403 #define MUX_PB13B_ADC0_X27 _UINT32_(1) 404 #define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) 405 #define PORT_PB13B_ADC0_X27 (_UINT32_(1) << 13) 406 407 #define PIN_PB14B_ADC0_X28 _UINT32_(46) 408 #define MUX_PB14B_ADC0_X28 _UINT32_(1) 409 #define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) 410 #define PORT_PB14B_ADC0_X28 (_UINT32_(1) << 14) 411 412 #define PIN_PB15B_ADC0_X29 _UINT32_(47) 413 #define MUX_PB15B_ADC0_X29 _UINT32_(1) 414 #define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) 415 #define PORT_PB15B_ADC0_X29 (_UINT32_(1) << 15) 416 417 #define PIN_PB00B_ADC0_X30 _UINT32_(32) 418 #define MUX_PB00B_ADC0_X30 _UINT32_(1) 419 #define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) 420 #define PORT_PB00B_ADC0_X30 (_UINT32_(1) << 0) 421 422 #define PIN_PB01B_ADC0_X31 _UINT32_(33) 423 #define MUX_PB01B_ADC0_X31 _UINT32_(1) 424 #define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) 425 #define PORT_PB01B_ADC0_X31 (_UINT32_(1) << 1) 426 427 #define PIN_PA03B_ADC0_Y0 _UINT32_(3) 428 #define MUX_PA03B_ADC0_Y0 _UINT32_(1) 429 #define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) 430 #define PORT_PA03B_ADC0_Y0 (_UINT32_(1) << 3) 431 432 #define PIN_PB08B_ADC0_Y1 _UINT32_(40) 433 #define MUX_PB08B_ADC0_Y1 _UINT32_(1) 434 #define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) 435 #define PORT_PB08B_ADC0_Y1 (_UINT32_(1) << 8) 436 437 #define PIN_PB09B_ADC0_Y2 _UINT32_(41) 438 #define MUX_PB09B_ADC0_Y2 _UINT32_(1) 439 #define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) 440 #define PORT_PB09B_ADC0_Y2 (_UINT32_(1) << 9) 441 442 #define PIN_PA04B_ADC0_Y3 _UINT32_(4) 443 #define MUX_PA04B_ADC0_Y3 _UINT32_(1) 444 #define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) 445 #define PORT_PA04B_ADC0_Y3 (_UINT32_(1) << 4) 446 447 #define PIN_PA06B_ADC0_Y4 _UINT32_(6) 448 #define MUX_PA06B_ADC0_Y4 _UINT32_(1) 449 #define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) 450 #define PORT_PA06B_ADC0_Y4 (_UINT32_(1) << 6) 451 452 #define PIN_PA07B_ADC0_Y5 _UINT32_(7) 453 #define MUX_PA07B_ADC0_Y5 _UINT32_(1) 454 #define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) 455 #define PORT_PA07B_ADC0_Y5 (_UINT32_(1) << 7) 456 457 #define PIN_PA08B_ADC0_Y6 _UINT32_(8) 458 #define MUX_PA08B_ADC0_Y6 _UINT32_(1) 459 #define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) 460 #define PORT_PA08B_ADC0_Y6 (_UINT32_(1) << 8) 461 462 #define PIN_PA09B_ADC0_Y7 _UINT32_(9) 463 #define MUX_PA09B_ADC0_Y7 _UINT32_(1) 464 #define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) 465 #define PORT_PA09B_ADC0_Y7 (_UINT32_(1) << 9) 466 467 #define PIN_PA10B_ADC0_Y8 _UINT32_(10) 468 #define MUX_PA10B_ADC0_Y8 _UINT32_(1) 469 #define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) 470 #define PORT_PA10B_ADC0_Y8 (_UINT32_(1) << 10) 471 472 #define PIN_PA11B_ADC0_Y9 _UINT32_(11) 473 #define MUX_PA11B_ADC0_Y9 _UINT32_(1) 474 #define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) 475 #define PORT_PA11B_ADC0_Y9 (_UINT32_(1) << 11) 476 477 #define PIN_PA16B_ADC0_Y10 _UINT32_(16) 478 #define MUX_PA16B_ADC0_Y10 _UINT32_(1) 479 #define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) 480 #define PORT_PA16B_ADC0_Y10 (_UINT32_(1) << 16) 481 482 #define PIN_PA17B_ADC0_Y11 _UINT32_(17) 483 #define MUX_PA17B_ADC0_Y11 _UINT32_(1) 484 #define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) 485 #define PORT_PA17B_ADC0_Y11 (_UINT32_(1) << 17) 486 487 #define PIN_PA18B_ADC0_Y12 _UINT32_(18) 488 #define MUX_PA18B_ADC0_Y12 _UINT32_(1) 489 #define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) 490 #define PORT_PA18B_ADC0_Y12 (_UINT32_(1) << 18) 491 492 #define PIN_PA19B_ADC0_Y13 _UINT32_(19) 493 #define MUX_PA19B_ADC0_Y13 _UINT32_(1) 494 #define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) 495 #define PORT_PA19B_ADC0_Y13 (_UINT32_(1) << 19) 496 497 #define PIN_PA20B_ADC0_Y14 _UINT32_(20) 498 #define MUX_PA20B_ADC0_Y14 _UINT32_(1) 499 #define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) 500 #define PORT_PA20B_ADC0_Y14 (_UINT32_(1) << 20) 501 502 #define PIN_PA21B_ADC0_Y15 _UINT32_(21) 503 #define MUX_PA21B_ADC0_Y15 _UINT32_(1) 504 #define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) 505 #define PORT_PA21B_ADC0_Y15 (_UINT32_(1) << 21) 506 507 #define PIN_PA22B_ADC0_Y16 _UINT32_(22) 508 #define MUX_PA22B_ADC0_Y16 _UINT32_(1) 509 #define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) 510 #define PORT_PA22B_ADC0_Y16 (_UINT32_(1) << 22) 511 512 #define PIN_PA23B_ADC0_Y17 _UINT32_(23) 513 #define MUX_PA23B_ADC0_Y17 _UINT32_(1) 514 #define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) 515 #define PORT_PA23B_ADC0_Y17 (_UINT32_(1) << 23) 516 517 #define PIN_PA27B_ADC0_Y18 _UINT32_(27) 518 #define MUX_PA27B_ADC0_Y18 _UINT32_(1) 519 #define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) 520 #define PORT_PA27B_ADC0_Y18 (_UINT32_(1) << 27) 521 522 #define PIN_PA30B_ADC0_Y19 _UINT32_(30) 523 #define MUX_PA30B_ADC0_Y19 _UINT32_(1) 524 #define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) 525 #define PORT_PA30B_ADC0_Y19 (_UINT32_(1) << 30) 526 527 #define PIN_PB02B_ADC0_Y20 _UINT32_(34) 528 #define MUX_PB02B_ADC0_Y20 _UINT32_(1) 529 #define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) 530 #define PORT_PB02B_ADC0_Y20 (_UINT32_(1) << 2) 531 532 #define PIN_PB03B_ADC0_Y21 _UINT32_(35) 533 #define MUX_PB03B_ADC0_Y21 _UINT32_(1) 534 #define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) 535 #define PORT_PB03B_ADC0_Y21 (_UINT32_(1) << 3) 536 537 #define PIN_PB04B_ADC0_Y22 _UINT32_(36) 538 #define MUX_PB04B_ADC0_Y22 _UINT32_(1) 539 #define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) 540 #define PORT_PB04B_ADC0_Y22 (_UINT32_(1) << 4) 541 542 #define PIN_PB05B_ADC0_Y23 _UINT32_(37) 543 #define MUX_PB05B_ADC0_Y23 _UINT32_(1) 544 #define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) 545 #define PORT_PB05B_ADC0_Y23 (_UINT32_(1) << 5) 546 547 #define PIN_PB06B_ADC0_Y24 _UINT32_(38) 548 #define MUX_PB06B_ADC0_Y24 _UINT32_(1) 549 #define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) 550 #define PORT_PB06B_ADC0_Y24 (_UINT32_(1) << 6) 551 552 #define PIN_PB07B_ADC0_Y25 _UINT32_(39) 553 #define MUX_PB07B_ADC0_Y25 _UINT32_(1) 554 #define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) 555 #define PORT_PB07B_ADC0_Y25 (_UINT32_(1) << 7) 556 557 #define PIN_PB12B_ADC0_Y26 _UINT32_(44) 558 #define MUX_PB12B_ADC0_Y26 _UINT32_(1) 559 #define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) 560 #define PORT_PB12B_ADC0_Y26 (_UINT32_(1) << 12) 561 562 #define PIN_PB13B_ADC0_Y27 _UINT32_(45) 563 #define MUX_PB13B_ADC0_Y27 _UINT32_(1) 564 #define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) 565 #define PORT_PB13B_ADC0_Y27 (_UINT32_(1) << 13) 566 567 #define PIN_PB14B_ADC0_Y28 _UINT32_(46) 568 #define MUX_PB14B_ADC0_Y28 _UINT32_(1) 569 #define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) 570 #define PORT_PB14B_ADC0_Y28 (_UINT32_(1) << 14) 571 572 #define PIN_PB15B_ADC0_Y29 _UINT32_(47) 573 #define MUX_PB15B_ADC0_Y29 _UINT32_(1) 574 #define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) 575 #define PORT_PB15B_ADC0_Y29 (_UINT32_(1) << 15) 576 577 #define PIN_PB00B_ADC0_Y30 _UINT32_(32) 578 #define MUX_PB00B_ADC0_Y30 _UINT32_(1) 579 #define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) 580 #define PORT_PB00B_ADC0_Y30 (_UINT32_(1) << 0) 581 582 #define PIN_PB01B_ADC0_Y31 _UINT32_(33) 583 #define MUX_PB01B_ADC0_Y31 _UINT32_(1) 584 #define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) 585 #define PORT_PB01B_ADC0_Y31 (_UINT32_(1) << 1) 586 587 /* ================== PORT definition for ADC1 peripheral =================== */ 588 #define PIN_PB08B_ADC1_AIN0 _UINT32_(40) 589 #define MUX_PB08B_ADC1_AIN0 _UINT32_(1) 590 #define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) 591 #define PORT_PB08B_ADC1_AIN0 (_UINT32_(1) << 8) 592 593 #define PIN_PB09B_ADC1_AIN1 _UINT32_(41) 594 #define MUX_PB09B_ADC1_AIN1 _UINT32_(1) 595 #define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) 596 #define PORT_PB09B_ADC1_AIN1 (_UINT32_(1) << 9) 597 598 #define PIN_PA08B_ADC1_AIN2 _UINT32_(8) 599 #define MUX_PA08B_ADC1_AIN2 _UINT32_(1) 600 #define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) 601 #define PORT_PA08B_ADC1_AIN2 (_UINT32_(1) << 8) 602 603 #define PIN_PA09B_ADC1_AIN3 _UINT32_(9) 604 #define MUX_PA09B_ADC1_AIN3 _UINT32_(1) 605 #define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) 606 #define PORT_PA09B_ADC1_AIN3 (_UINT32_(1) << 9) 607 608 #define PIN_PB04B_ADC1_AIN6 _UINT32_(36) 609 #define MUX_PB04B_ADC1_AIN6 _UINT32_(1) 610 #define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) 611 #define PORT_PB04B_ADC1_AIN6 (_UINT32_(1) << 4) 612 613 #define PIN_PB05B_ADC1_AIN7 _UINT32_(37) 614 #define MUX_PB05B_ADC1_AIN7 _UINT32_(1) 615 #define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) 616 #define PORT_PB05B_ADC1_AIN7 (_UINT32_(1) << 5) 617 618 #define PIN_PB06B_ADC1_AIN8 _UINT32_(38) 619 #define MUX_PB06B_ADC1_AIN8 _UINT32_(1) 620 #define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) 621 #define PORT_PB06B_ADC1_AIN8 (_UINT32_(1) << 6) 622 623 #define PIN_PB07B_ADC1_AIN9 _UINT32_(39) 624 #define MUX_PB07B_ADC1_AIN9 _UINT32_(1) 625 #define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) 626 #define PORT_PB07B_ADC1_AIN9 (_UINT32_(1) << 7) 627 628 /* =================== PORT definition for CCL peripheral =================== */ 629 #define PIN_PA04N_CCL_IN0 _UINT32_(4) 630 #define MUX_PA04N_CCL_IN0 _UINT32_(13) 631 #define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) 632 #define PORT_PA04N_CCL_IN0 (_UINT32_(1) << 4) 633 634 #define PIN_PA16N_CCL_IN0 _UINT32_(16) 635 #define MUX_PA16N_CCL_IN0 _UINT32_(13) 636 #define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) 637 #define PORT_PA16N_CCL_IN0 (_UINT32_(1) << 16) 638 639 #define PIN_PB22N_CCL_IN0 _UINT32_(54) 640 #define MUX_PB22N_CCL_IN0 _UINT32_(13) 641 #define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) 642 #define PORT_PB22N_CCL_IN0 (_UINT32_(1) << 22) 643 644 #define PIN_PA05N_CCL_IN1 _UINT32_(5) 645 #define MUX_PA05N_CCL_IN1 _UINT32_(13) 646 #define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) 647 #define PORT_PA05N_CCL_IN1 (_UINT32_(1) << 5) 648 649 #define PIN_PA17N_CCL_IN1 _UINT32_(17) 650 #define MUX_PA17N_CCL_IN1 _UINT32_(13) 651 #define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) 652 #define PORT_PA17N_CCL_IN1 (_UINT32_(1) << 17) 653 654 #define PIN_PB00N_CCL_IN1 _UINT32_(32) 655 #define MUX_PB00N_CCL_IN1 _UINT32_(13) 656 #define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) 657 #define PORT_PB00N_CCL_IN1 (_UINT32_(1) << 0) 658 659 #define PIN_PA06N_CCL_IN2 _UINT32_(6) 660 #define MUX_PA06N_CCL_IN2 _UINT32_(13) 661 #define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) 662 #define PORT_PA06N_CCL_IN2 (_UINT32_(1) << 6) 663 664 #define PIN_PA18N_CCL_IN2 _UINT32_(18) 665 #define MUX_PA18N_CCL_IN2 _UINT32_(13) 666 #define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) 667 #define PORT_PA18N_CCL_IN2 (_UINT32_(1) << 18) 668 669 #define PIN_PB01N_CCL_IN2 _UINT32_(33) 670 #define MUX_PB01N_CCL_IN2 _UINT32_(13) 671 #define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) 672 #define PORT_PB01N_CCL_IN2 (_UINT32_(1) << 1) 673 674 #define PIN_PA08N_CCL_IN3 _UINT32_(8) 675 #define MUX_PA08N_CCL_IN3 _UINT32_(13) 676 #define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) 677 #define PORT_PA08N_CCL_IN3 (_UINT32_(1) << 8) 678 679 #define PIN_PA30N_CCL_IN3 _UINT32_(30) 680 #define MUX_PA30N_CCL_IN3 _UINT32_(13) 681 #define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) 682 #define PORT_PA30N_CCL_IN3 (_UINT32_(1) << 30) 683 684 #define PIN_PA09N_CCL_IN4 _UINT32_(9) 685 #define MUX_PA09N_CCL_IN4 _UINT32_(13) 686 #define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) 687 #define PORT_PA09N_CCL_IN4 (_UINT32_(1) << 9) 688 689 #define PIN_PA10N_CCL_IN5 _UINT32_(10) 690 #define MUX_PA10N_CCL_IN5 _UINT32_(13) 691 #define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) 692 #define PORT_PA10N_CCL_IN5 (_UINT32_(1) << 10) 693 694 #define PIN_PA22N_CCL_IN6 _UINT32_(22) 695 #define MUX_PA22N_CCL_IN6 _UINT32_(13) 696 #define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) 697 #define PORT_PA22N_CCL_IN6 (_UINT32_(1) << 22) 698 699 #define PIN_PB06N_CCL_IN6 _UINT32_(38) 700 #define MUX_PB06N_CCL_IN6 _UINT32_(13) 701 #define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) 702 #define PORT_PB06N_CCL_IN6 (_UINT32_(1) << 6) 703 704 #define PIN_PA23N_CCL_IN7 _UINT32_(23) 705 #define MUX_PA23N_CCL_IN7 _UINT32_(13) 706 #define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) 707 #define PORT_PA23N_CCL_IN7 (_UINT32_(1) << 23) 708 709 #define PIN_PB07N_CCL_IN7 _UINT32_(39) 710 #define MUX_PB07N_CCL_IN7 _UINT32_(13) 711 #define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) 712 #define PORT_PB07N_CCL_IN7 (_UINT32_(1) << 7) 713 714 #define PIN_PA24N_CCL_IN8 _UINT32_(24) 715 #define MUX_PA24N_CCL_IN8 _UINT32_(13) 716 #define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) 717 #define PORT_PA24N_CCL_IN8 (_UINT32_(1) << 24) 718 719 #define PIN_PB08N_CCL_IN8 _UINT32_(40) 720 #define MUX_PB08N_CCL_IN8 _UINT32_(13) 721 #define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) 722 #define PORT_PB08N_CCL_IN8 (_UINT32_(1) << 8) 723 724 #define PIN_PB14N_CCL_IN9 _UINT32_(46) 725 #define MUX_PB14N_CCL_IN9 _UINT32_(13) 726 #define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) 727 #define PORT_PB14N_CCL_IN9 (_UINT32_(1) << 14) 728 729 #define PIN_PB15N_CCL_IN10 _UINT32_(47) 730 #define MUX_PB15N_CCL_IN10 _UINT32_(13) 731 #define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) 732 #define PORT_PB15N_CCL_IN10 (_UINT32_(1) << 15) 733 734 #define PIN_PB10N_CCL_IN11 _UINT32_(42) 735 #define MUX_PB10N_CCL_IN11 _UINT32_(13) 736 #define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) 737 #define PORT_PB10N_CCL_IN11 (_UINT32_(1) << 10) 738 739 #define PIN_PB16N_CCL_IN11 _UINT32_(48) 740 #define MUX_PB16N_CCL_IN11 _UINT32_(13) 741 #define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) 742 #define PORT_PB16N_CCL_IN11 (_UINT32_(1) << 16) 743 744 #define PIN_PA07N_CCL_OUT0 _UINT32_(7) 745 #define MUX_PA07N_CCL_OUT0 _UINT32_(13) 746 #define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) 747 #define PORT_PA07N_CCL_OUT0 (_UINT32_(1) << 7) 748 749 #define PIN_PA19N_CCL_OUT0 _UINT32_(19) 750 #define MUX_PA19N_CCL_OUT0 _UINT32_(13) 751 #define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) 752 #define PORT_PA19N_CCL_OUT0 (_UINT32_(1) << 19) 753 754 #define PIN_PB02N_CCL_OUT0 _UINT32_(34) 755 #define MUX_PB02N_CCL_OUT0 _UINT32_(13) 756 #define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) 757 #define PORT_PB02N_CCL_OUT0 (_UINT32_(1) << 2) 758 759 #define PIN_PB23N_CCL_OUT0 _UINT32_(55) 760 #define MUX_PB23N_CCL_OUT0 _UINT32_(13) 761 #define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) 762 #define PORT_PB23N_CCL_OUT0 (_UINT32_(1) << 23) 763 764 #define PIN_PA11N_CCL_OUT1 _UINT32_(11) 765 #define MUX_PA11N_CCL_OUT1 _UINT32_(13) 766 #define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) 767 #define PORT_PA11N_CCL_OUT1 (_UINT32_(1) << 11) 768 769 #define PIN_PA31N_CCL_OUT1 _UINT32_(31) 770 #define MUX_PA31N_CCL_OUT1 _UINT32_(13) 771 #define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) 772 #define PORT_PA31N_CCL_OUT1 (_UINT32_(1) << 31) 773 774 #define PIN_PB11N_CCL_OUT1 _UINT32_(43) 775 #define MUX_PB11N_CCL_OUT1 _UINT32_(13) 776 #define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) 777 #define PORT_PB11N_CCL_OUT1 (_UINT32_(1) << 11) 778 779 #define PIN_PA25N_CCL_OUT2 _UINT32_(25) 780 #define MUX_PA25N_CCL_OUT2 _UINT32_(13) 781 #define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) 782 #define PORT_PA25N_CCL_OUT2 (_UINT32_(1) << 25) 783 784 #define PIN_PB09N_CCL_OUT2 _UINT32_(41) 785 #define MUX_PB09N_CCL_OUT2 _UINT32_(13) 786 #define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) 787 #define PORT_PB09N_CCL_OUT2 (_UINT32_(1) << 9) 788 789 #define PIN_PB17N_CCL_OUT3 _UINT32_(49) 790 #define MUX_PB17N_CCL_OUT3 _UINT32_(13) 791 #define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) 792 #define PORT_PB17N_CCL_OUT3 (_UINT32_(1) << 17) 793 794 /* =================== PORT definition for DAC peripheral =================== */ 795 #define PIN_PA02B_DAC_VOUT0 _UINT32_(2) 796 #define MUX_PA02B_DAC_VOUT0 _UINT32_(1) 797 #define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) 798 #define PORT_PA02B_DAC_VOUT0 (_UINT32_(1) << 2) 799 800 #define PIN_PA05B_DAC_VOUT1 _UINT32_(5) 801 #define MUX_PA05B_DAC_VOUT1 _UINT32_(1) 802 #define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) 803 #define PORT_PA05B_DAC_VOUT1 (_UINT32_(1) << 5) 804 805 /* =================== PORT definition for EIC peripheral =================== */ 806 #define PIN_PA00A_EIC_EXTINT0 _UINT32_(0) 807 #define MUX_PA00A_EIC_EXTINT0 _UINT32_(0) 808 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 809 #define PORT_PA00A_EIC_EXTINT0 (_UINT32_(1) << 0) 810 #define PIN_PA00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA00 External Interrupt Line */ 811 812 #define PIN_PA16A_EIC_EXTINT0 _UINT32_(16) 813 #define MUX_PA16A_EIC_EXTINT0 _UINT32_(0) 814 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 815 #define PORT_PA16A_EIC_EXTINT0 (_UINT32_(1) << 16) 816 #define PIN_PA16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA16 External Interrupt Line */ 817 818 #define PIN_PB00A_EIC_EXTINT0 _UINT32_(32) 819 #define MUX_PB00A_EIC_EXTINT0 _UINT32_(0) 820 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) 821 #define PORT_PB00A_EIC_EXTINT0 (_UINT32_(1) << 0) 822 #define PIN_PB00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB00 External Interrupt Line */ 823 824 #define PIN_PB16A_EIC_EXTINT0 _UINT32_(48) 825 #define MUX_PB16A_EIC_EXTINT0 _UINT32_(0) 826 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) 827 #define PORT_PB16A_EIC_EXTINT0 (_UINT32_(1) << 16) 828 #define PIN_PB16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB16 External Interrupt Line */ 829 830 #define PIN_PA01A_EIC_EXTINT1 _UINT32_(1) 831 #define MUX_PA01A_EIC_EXTINT1 _UINT32_(0) 832 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 833 #define PORT_PA01A_EIC_EXTINT1 (_UINT32_(1) << 1) 834 #define PIN_PA01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA01 External Interrupt Line */ 835 836 #define PIN_PA17A_EIC_EXTINT1 _UINT32_(17) 837 #define MUX_PA17A_EIC_EXTINT1 _UINT32_(0) 838 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 839 #define PORT_PA17A_EIC_EXTINT1 (_UINT32_(1) << 17) 840 #define PIN_PA17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA17 External Interrupt Line */ 841 842 #define PIN_PB01A_EIC_EXTINT1 _UINT32_(33) 843 #define MUX_PB01A_EIC_EXTINT1 _UINT32_(0) 844 #define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) 845 #define PORT_PB01A_EIC_EXTINT1 (_UINT32_(1) << 1) 846 #define PIN_PB01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB01 External Interrupt Line */ 847 848 #define PIN_PB17A_EIC_EXTINT1 _UINT32_(49) 849 #define MUX_PB17A_EIC_EXTINT1 _UINT32_(0) 850 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) 851 #define PORT_PB17A_EIC_EXTINT1 (_UINT32_(1) << 17) 852 #define PIN_PB17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB17 External Interrupt Line */ 853 854 #define PIN_PA02A_EIC_EXTINT2 _UINT32_(2) 855 #define MUX_PA02A_EIC_EXTINT2 _UINT32_(0) 856 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 857 #define PORT_PA02A_EIC_EXTINT2 (_UINT32_(1) << 2) 858 #define PIN_PA02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA02 External Interrupt Line */ 859 860 #define PIN_PA18A_EIC_EXTINT2 _UINT32_(18) 861 #define MUX_PA18A_EIC_EXTINT2 _UINT32_(0) 862 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 863 #define PORT_PA18A_EIC_EXTINT2 (_UINT32_(1) << 18) 864 #define PIN_PA18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA18 External Interrupt Line */ 865 866 #define PIN_PB02A_EIC_EXTINT2 _UINT32_(34) 867 #define MUX_PB02A_EIC_EXTINT2 _UINT32_(0) 868 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 869 #define PORT_PB02A_EIC_EXTINT2 (_UINT32_(1) << 2) 870 #define PIN_PB02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB02 External Interrupt Line */ 871 872 #define PIN_PA03A_EIC_EXTINT3 _UINT32_(3) 873 #define MUX_PA03A_EIC_EXTINT3 _UINT32_(0) 874 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 875 #define PORT_PA03A_EIC_EXTINT3 (_UINT32_(1) << 3) 876 #define PIN_PA03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA03 External Interrupt Line */ 877 878 #define PIN_PA19A_EIC_EXTINT3 _UINT32_(19) 879 #define MUX_PA19A_EIC_EXTINT3 _UINT32_(0) 880 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 881 #define PORT_PA19A_EIC_EXTINT3 (_UINT32_(1) << 19) 882 #define PIN_PA19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA19 External Interrupt Line */ 883 884 #define PIN_PB03A_EIC_EXTINT3 _UINT32_(35) 885 #define MUX_PB03A_EIC_EXTINT3 _UINT32_(0) 886 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 887 #define PORT_PB03A_EIC_EXTINT3 (_UINT32_(1) << 3) 888 #define PIN_PB03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB03 External Interrupt Line */ 889 890 #define PIN_PA04A_EIC_EXTINT4 _UINT32_(4) 891 #define MUX_PA04A_EIC_EXTINT4 _UINT32_(0) 892 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 893 #define PORT_PA04A_EIC_EXTINT4 (_UINT32_(1) << 4) 894 #define PIN_PA04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA04 External Interrupt Line */ 895 896 #define PIN_PA20A_EIC_EXTINT4 _UINT32_(20) 897 #define MUX_PA20A_EIC_EXTINT4 _UINT32_(0) 898 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 899 #define PORT_PA20A_EIC_EXTINT4 (_UINT32_(1) << 20) 900 #define PIN_PA20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA20 External Interrupt Line */ 901 902 #define PIN_PB04A_EIC_EXTINT4 _UINT32_(36) 903 #define MUX_PB04A_EIC_EXTINT4 _UINT32_(0) 904 #define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) 905 #define PORT_PB04A_EIC_EXTINT4 (_UINT32_(1) << 4) 906 #define PIN_PB04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB04 External Interrupt Line */ 907 908 #define PIN_PA05A_EIC_EXTINT5 _UINT32_(5) 909 #define MUX_PA05A_EIC_EXTINT5 _UINT32_(0) 910 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 911 #define PORT_PA05A_EIC_EXTINT5 (_UINT32_(1) << 5) 912 #define PIN_PA05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA05 External Interrupt Line */ 913 914 #define PIN_PA21A_EIC_EXTINT5 _UINT32_(21) 915 #define MUX_PA21A_EIC_EXTINT5 _UINT32_(0) 916 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 917 #define PORT_PA21A_EIC_EXTINT5 (_UINT32_(1) << 21) 918 #define PIN_PA21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA21 External Interrupt Line */ 919 920 #define PIN_PB05A_EIC_EXTINT5 _UINT32_(37) 921 #define MUX_PB05A_EIC_EXTINT5 _UINT32_(0) 922 #define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) 923 #define PORT_PB05A_EIC_EXTINT5 (_UINT32_(1) << 5) 924 #define PIN_PB05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB05 External Interrupt Line */ 925 926 #define PIN_PA06A_EIC_EXTINT6 _UINT32_(6) 927 #define MUX_PA06A_EIC_EXTINT6 _UINT32_(0) 928 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 929 #define PORT_PA06A_EIC_EXTINT6 (_UINT32_(1) << 6) 930 #define PIN_PA06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA06 External Interrupt Line */ 931 932 #define PIN_PA22A_EIC_EXTINT6 _UINT32_(22) 933 #define MUX_PA22A_EIC_EXTINT6 _UINT32_(0) 934 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 935 #define PORT_PA22A_EIC_EXTINT6 (_UINT32_(1) << 22) 936 #define PIN_PA22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA22 External Interrupt Line */ 937 938 #define PIN_PB06A_EIC_EXTINT6 _UINT32_(38) 939 #define MUX_PB06A_EIC_EXTINT6 _UINT32_(0) 940 #define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) 941 #define PORT_PB06A_EIC_EXTINT6 (_UINT32_(1) << 6) 942 #define PIN_PB06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB06 External Interrupt Line */ 943 944 #define PIN_PB22A_EIC_EXTINT6 _UINT32_(54) 945 #define MUX_PB22A_EIC_EXTINT6 _UINT32_(0) 946 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 947 #define PORT_PB22A_EIC_EXTINT6 (_UINT32_(1) << 22) 948 #define PIN_PB22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB22 External Interrupt Line */ 949 950 #define PIN_PA07A_EIC_EXTINT7 _UINT32_(7) 951 #define MUX_PA07A_EIC_EXTINT7 _UINT32_(0) 952 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 953 #define PORT_PA07A_EIC_EXTINT7 (_UINT32_(1) << 7) 954 #define PIN_PA07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA07 External Interrupt Line */ 955 956 #define PIN_PA23A_EIC_EXTINT7 _UINT32_(23) 957 #define MUX_PA23A_EIC_EXTINT7 _UINT32_(0) 958 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 959 #define PORT_PA23A_EIC_EXTINT7 (_UINT32_(1) << 23) 960 #define PIN_PA23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA23 External Interrupt Line */ 961 962 #define PIN_PB07A_EIC_EXTINT7 _UINT32_(39) 963 #define MUX_PB07A_EIC_EXTINT7 _UINT32_(0) 964 #define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) 965 #define PORT_PB07A_EIC_EXTINT7 (_UINT32_(1) << 7) 966 #define PIN_PB07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB07 External Interrupt Line */ 967 968 #define PIN_PB23A_EIC_EXTINT7 _UINT32_(55) 969 #define MUX_PB23A_EIC_EXTINT7 _UINT32_(0) 970 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 971 #define PORT_PB23A_EIC_EXTINT7 (_UINT32_(1) << 23) 972 #define PIN_PB23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB23 External Interrupt Line */ 973 974 #define PIN_PA24A_EIC_EXTINT8 _UINT32_(24) 975 #define MUX_PA24A_EIC_EXTINT8 _UINT32_(0) 976 #define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) 977 #define PORT_PA24A_EIC_EXTINT8 (_UINT32_(1) << 24) 978 #define PIN_PA24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PA24 External Interrupt Line */ 979 980 #define PIN_PB08A_EIC_EXTINT8 _UINT32_(40) 981 #define MUX_PB08A_EIC_EXTINT8 _UINT32_(0) 982 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 983 #define PORT_PB08A_EIC_EXTINT8 (_UINT32_(1) << 8) 984 #define PIN_PB08A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB08 External Interrupt Line */ 985 986 #define PIN_PA09A_EIC_EXTINT9 _UINT32_(9) 987 #define MUX_PA09A_EIC_EXTINT9 _UINT32_(0) 988 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 989 #define PORT_PA09A_EIC_EXTINT9 (_UINT32_(1) << 9) 990 #define PIN_PA09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA09 External Interrupt Line */ 991 992 #define PIN_PA25A_EIC_EXTINT9 _UINT32_(25) 993 #define MUX_PA25A_EIC_EXTINT9 _UINT32_(0) 994 #define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) 995 #define PORT_PA25A_EIC_EXTINT9 (_UINT32_(1) << 25) 996 #define PIN_PA25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA25 External Interrupt Line */ 997 998 #define PIN_PB09A_EIC_EXTINT9 _UINT32_(41) 999 #define MUX_PB09A_EIC_EXTINT9 _UINT32_(0) 1000 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 1001 #define PORT_PB09A_EIC_EXTINT9 (_UINT32_(1) << 9) 1002 #define PIN_PB09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB09 External Interrupt Line */ 1003 1004 #define PIN_PA10A_EIC_EXTINT10 _UINT32_(10) 1005 #define MUX_PA10A_EIC_EXTINT10 _UINT32_(0) 1006 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 1007 #define PORT_PA10A_EIC_EXTINT10 (_UINT32_(1) << 10) 1008 #define PIN_PA10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PA10 External Interrupt Line */ 1009 1010 #define PIN_PB10A_EIC_EXTINT10 _UINT32_(42) 1011 #define MUX_PB10A_EIC_EXTINT10 _UINT32_(0) 1012 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 1013 #define PORT_PB10A_EIC_EXTINT10 (_UINT32_(1) << 10) 1014 #define PIN_PB10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PB10 External Interrupt Line */ 1015 1016 #define PIN_PA11A_EIC_EXTINT11 _UINT32_(11) 1017 #define MUX_PA11A_EIC_EXTINT11 _UINT32_(0) 1018 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 1019 #define PORT_PA11A_EIC_EXTINT11 (_UINT32_(1) << 11) 1020 #define PIN_PA11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA11 External Interrupt Line */ 1021 1022 #define PIN_PA27A_EIC_EXTINT11 _UINT32_(27) 1023 #define MUX_PA27A_EIC_EXTINT11 _UINT32_(0) 1024 #define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) 1025 #define PORT_PA27A_EIC_EXTINT11 (_UINT32_(1) << 27) 1026 #define PIN_PA27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA27 External Interrupt Line */ 1027 1028 #define PIN_PB11A_EIC_EXTINT11 _UINT32_(43) 1029 #define MUX_PB11A_EIC_EXTINT11 _UINT32_(0) 1030 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 1031 #define PORT_PB11A_EIC_EXTINT11 (_UINT32_(1) << 11) 1032 #define PIN_PB11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PB11 External Interrupt Line */ 1033 1034 #define PIN_PA12A_EIC_EXTINT12 _UINT32_(12) 1035 #define MUX_PA12A_EIC_EXTINT12 _UINT32_(0) 1036 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 1037 #define PORT_PA12A_EIC_EXTINT12 (_UINT32_(1) << 12) 1038 #define PIN_PA12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PA12 External Interrupt Line */ 1039 1040 #define PIN_PB12A_EIC_EXTINT12 _UINT32_(44) 1041 #define MUX_PB12A_EIC_EXTINT12 _UINT32_(0) 1042 #define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) 1043 #define PORT_PB12A_EIC_EXTINT12 (_UINT32_(1) << 12) 1044 #define PIN_PB12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PB12 External Interrupt Line */ 1045 1046 #define PIN_PA13A_EIC_EXTINT13 _UINT32_(13) 1047 #define MUX_PA13A_EIC_EXTINT13 _UINT32_(0) 1048 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 1049 #define PORT_PA13A_EIC_EXTINT13 (_UINT32_(1) << 13) 1050 #define PIN_PA13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PA13 External Interrupt Line */ 1051 1052 #define PIN_PB13A_EIC_EXTINT13 _UINT32_(45) 1053 #define MUX_PB13A_EIC_EXTINT13 _UINT32_(0) 1054 #define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) 1055 #define PORT_PB13A_EIC_EXTINT13 (_UINT32_(1) << 13) 1056 #define PIN_PB13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PB13 External Interrupt Line */ 1057 1058 #define PIN_PA30A_EIC_EXTINT14 _UINT32_(30) 1059 #define MUX_PA30A_EIC_EXTINT14 _UINT32_(0) 1060 #define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) 1061 #define PORT_PA30A_EIC_EXTINT14 (_UINT32_(1) << 30) 1062 #define PIN_PA30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA30 External Interrupt Line */ 1063 1064 #define PIN_PB14A_EIC_EXTINT14 _UINT32_(46) 1065 #define MUX_PB14A_EIC_EXTINT14 _UINT32_(0) 1066 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) 1067 #define PORT_PB14A_EIC_EXTINT14 (_UINT32_(1) << 14) 1068 #define PIN_PB14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB14 External Interrupt Line */ 1069 1070 #define PIN_PB30A_EIC_EXTINT14 _UINT32_(62) 1071 #define MUX_PB30A_EIC_EXTINT14 _UINT32_(0) 1072 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) 1073 #define PORT_PB30A_EIC_EXTINT14 (_UINT32_(1) << 30) 1074 #define PIN_PB30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB30 External Interrupt Line */ 1075 1076 #define PIN_PA14A_EIC_EXTINT14 _UINT32_(14) 1077 #define MUX_PA14A_EIC_EXTINT14 _UINT32_(0) 1078 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 1079 #define PORT_PA14A_EIC_EXTINT14 (_UINT32_(1) << 14) 1080 #define PIN_PA14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA14 External Interrupt Line */ 1081 1082 #define PIN_PA15A_EIC_EXTINT15 _UINT32_(15) 1083 #define MUX_PA15A_EIC_EXTINT15 _UINT32_(0) 1084 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 1085 #define PORT_PA15A_EIC_EXTINT15 (_UINT32_(1) << 15) 1086 #define PIN_PA15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA15 External Interrupt Line */ 1087 1088 #define PIN_PA31A_EIC_EXTINT15 _UINT32_(31) 1089 #define MUX_PA31A_EIC_EXTINT15 _UINT32_(0) 1090 #define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) 1091 #define PORT_PA31A_EIC_EXTINT15 (_UINT32_(1) << 31) 1092 #define PIN_PA31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA31 External Interrupt Line */ 1093 1094 #define PIN_PB15A_EIC_EXTINT15 _UINT32_(47) 1095 #define MUX_PB15A_EIC_EXTINT15 _UINT32_(0) 1096 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) 1097 #define PORT_PB15A_EIC_EXTINT15 (_UINT32_(1) << 15) 1098 #define PIN_PB15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB15 External Interrupt Line */ 1099 1100 #define PIN_PB31A_EIC_EXTINT15 _UINT32_(63) 1101 #define MUX_PB31A_EIC_EXTINT15 _UINT32_(0) 1102 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) 1103 #define PORT_PB31A_EIC_EXTINT15 (_UINT32_(1) << 31) 1104 #define PIN_PB31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB31 External Interrupt Line */ 1105 1106 #define PIN_PA08A_EIC_NMI _UINT32_(8) 1107 #define MUX_PA08A_EIC_NMI _UINT32_(0) 1108 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 1109 #define PORT_PA08A_EIC_NMI (_UINT32_(1) << 8) 1110 1111 /* ================== PORT definition for GCLK peripheral =================== */ 1112 #define PIN_PA30M_GCLK_IO0 _UINT32_(30) 1113 #define MUX_PA30M_GCLK_IO0 _UINT32_(12) 1114 #define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) 1115 #define PORT_PA30M_GCLK_IO0 (_UINT32_(1) << 30) 1116 1117 #define PIN_PB14M_GCLK_IO0 _UINT32_(46) 1118 #define MUX_PB14M_GCLK_IO0 _UINT32_(12) 1119 #define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) 1120 #define PORT_PB14M_GCLK_IO0 (_UINT32_(1) << 14) 1121 1122 #define PIN_PA14M_GCLK_IO0 _UINT32_(14) 1123 #define MUX_PA14M_GCLK_IO0 _UINT32_(12) 1124 #define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) 1125 #define PORT_PA14M_GCLK_IO0 (_UINT32_(1) << 14) 1126 1127 #define PIN_PB22M_GCLK_IO0 _UINT32_(54) 1128 #define MUX_PB22M_GCLK_IO0 _UINT32_(12) 1129 #define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) 1130 #define PORT_PB22M_GCLK_IO0 (_UINT32_(1) << 22) 1131 1132 #define PIN_PB15M_GCLK_IO1 _UINT32_(47) 1133 #define MUX_PB15M_GCLK_IO1 _UINT32_(12) 1134 #define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) 1135 #define PORT_PB15M_GCLK_IO1 (_UINT32_(1) << 15) 1136 1137 #define PIN_PA15M_GCLK_IO1 _UINT32_(15) 1138 #define MUX_PA15M_GCLK_IO1 _UINT32_(12) 1139 #define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) 1140 #define PORT_PA15M_GCLK_IO1 (_UINT32_(1) << 15) 1141 1142 #define PIN_PB23M_GCLK_IO1 _UINT32_(55) 1143 #define MUX_PB23M_GCLK_IO1 _UINT32_(12) 1144 #define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) 1145 #define PORT_PB23M_GCLK_IO1 (_UINT32_(1) << 23) 1146 1147 #define PIN_PA27M_GCLK_IO1 _UINT32_(27) 1148 #define MUX_PA27M_GCLK_IO1 _UINT32_(12) 1149 #define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) 1150 #define PORT_PA27M_GCLK_IO1 (_UINT32_(1) << 27) 1151 1152 #define PIN_PA16M_GCLK_IO2 _UINT32_(16) 1153 #define MUX_PA16M_GCLK_IO2 _UINT32_(12) 1154 #define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) 1155 #define PORT_PA16M_GCLK_IO2 (_UINT32_(1) << 16) 1156 1157 #define PIN_PB16M_GCLK_IO2 _UINT32_(48) 1158 #define MUX_PB16M_GCLK_IO2 _UINT32_(12) 1159 #define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) 1160 #define PORT_PB16M_GCLK_IO2 (_UINT32_(1) << 16) 1161 1162 #define PIN_PA17M_GCLK_IO3 _UINT32_(17) 1163 #define MUX_PA17M_GCLK_IO3 _UINT32_(12) 1164 #define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) 1165 #define PORT_PA17M_GCLK_IO3 (_UINT32_(1) << 17) 1166 1167 #define PIN_PB17M_GCLK_IO3 _UINT32_(49) 1168 #define MUX_PB17M_GCLK_IO3 _UINT32_(12) 1169 #define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) 1170 #define PORT_PB17M_GCLK_IO3 (_UINT32_(1) << 17) 1171 1172 #define PIN_PA10M_GCLK_IO4 _UINT32_(10) 1173 #define MUX_PA10M_GCLK_IO4 _UINT32_(12) 1174 #define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) 1175 #define PORT_PA10M_GCLK_IO4 (_UINT32_(1) << 10) 1176 1177 #define PIN_PB10M_GCLK_IO4 _UINT32_(42) 1178 #define MUX_PB10M_GCLK_IO4 _UINT32_(12) 1179 #define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) 1180 #define PORT_PB10M_GCLK_IO4 (_UINT32_(1) << 10) 1181 1182 #define PIN_PA11M_GCLK_IO5 _UINT32_(11) 1183 #define MUX_PA11M_GCLK_IO5 _UINT32_(12) 1184 #define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) 1185 #define PORT_PA11M_GCLK_IO5 (_UINT32_(1) << 11) 1186 1187 #define PIN_PB11M_GCLK_IO5 _UINT32_(43) 1188 #define MUX_PB11M_GCLK_IO5 _UINT32_(12) 1189 #define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) 1190 #define PORT_PB11M_GCLK_IO5 (_UINT32_(1) << 11) 1191 1192 #define PIN_PB12M_GCLK_IO6 _UINT32_(44) 1193 #define MUX_PB12M_GCLK_IO6 _UINT32_(12) 1194 #define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) 1195 #define PORT_PB12M_GCLK_IO6 (_UINT32_(1) << 12) 1196 1197 #define PIN_PB13M_GCLK_IO7 _UINT32_(45) 1198 #define MUX_PB13M_GCLK_IO7 _UINT32_(12) 1199 #define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) 1200 #define PORT_PB13M_GCLK_IO7 (_UINT32_(1) << 13) 1201 1202 /* ================== PORT definition for GMAC peripheral =================== */ 1203 #define PIN_PA16L_GMAC_GCRS _UINT32_(16) 1204 #define MUX_PA16L_GMAC_GCRS _UINT32_(11) 1205 #define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) 1206 #define PORT_PA16L_GMAC_GCRS (_UINT32_(1) << 16) 1207 1208 #define PIN_PA20L_GMAC_GMDC _UINT32_(20) 1209 #define MUX_PA20L_GMAC_GMDC _UINT32_(11) 1210 #define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) 1211 #define PORT_PA20L_GMAC_GMDC (_UINT32_(1) << 20) 1212 1213 #define PIN_PB14L_GMAC_GMDC _UINT32_(46) 1214 #define MUX_PB14L_GMAC_GMDC _UINT32_(11) 1215 #define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) 1216 #define PORT_PB14L_GMAC_GMDC (_UINT32_(1) << 14) 1217 1218 #define PIN_PA21L_GMAC_GMDIO _UINT32_(21) 1219 #define MUX_PA21L_GMAC_GMDIO _UINT32_(11) 1220 #define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) 1221 #define PORT_PA21L_GMAC_GMDIO (_UINT32_(1) << 21) 1222 1223 #define PIN_PB15L_GMAC_GMDIO _UINT32_(47) 1224 #define MUX_PB15L_GMAC_GMDIO _UINT32_(11) 1225 #define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) 1226 #define PORT_PB15L_GMAC_GMDIO (_UINT32_(1) << 15) 1227 1228 #define PIN_PA13L_GMAC_GRX0 _UINT32_(13) 1229 #define MUX_PA13L_GMAC_GRX0 _UINT32_(11) 1230 #define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) 1231 #define PORT_PA13L_GMAC_GRX0 (_UINT32_(1) << 13) 1232 1233 #define PIN_PA12L_GMAC_GRX1 _UINT32_(12) 1234 #define MUX_PA12L_GMAC_GRX1 _UINT32_(11) 1235 #define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) 1236 #define PORT_PA12L_GMAC_GRX1 (_UINT32_(1) << 12) 1237 1238 #define PIN_PA16L_GMAC_GRXDV _UINT32_(16) 1239 #define MUX_PA16L_GMAC_GRXDV _UINT32_(11) 1240 #define PINMUX_PA16L_GMAC_GRXDV ((PIN_PA16L_GMAC_GRXDV << 16) | MUX_PA16L_GMAC_GRXDV) 1241 #define PORT_PA16L_GMAC_GRXDV (_UINT32_(1) << 16) 1242 1243 #define PIN_PA15L_GMAC_GRXER _UINT32_(15) 1244 #define MUX_PA15L_GMAC_GRXER _UINT32_(11) 1245 #define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) 1246 #define PORT_PA15L_GMAC_GRXER (_UINT32_(1) << 15) 1247 1248 #define PIN_PA18L_GMAC_GTX0 _UINT32_(18) 1249 #define MUX_PA18L_GMAC_GTX0 _UINT32_(11) 1250 #define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) 1251 #define PORT_PA18L_GMAC_GTX0 (_UINT32_(1) << 18) 1252 1253 #define PIN_PA19L_GMAC_GTX1 _UINT32_(19) 1254 #define MUX_PA19L_GMAC_GTX1 _UINT32_(11) 1255 #define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) 1256 #define PORT_PA19L_GMAC_GTX1 (_UINT32_(1) << 19) 1257 1258 #define PIN_PA14L_GMAC_GTXCK _UINT32_(14) 1259 #define MUX_PA14L_GMAC_GTXCK _UINT32_(11) 1260 #define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) 1261 #define PORT_PA14L_GMAC_GTXCK (_UINT32_(1) << 14) 1262 1263 #define PIN_PA17L_GMAC_GTXEN _UINT32_(17) 1264 #define MUX_PA17L_GMAC_GTXEN _UINT32_(11) 1265 #define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) 1266 #define PORT_PA17L_GMAC_GTXEN (_UINT32_(1) << 17) 1267 1268 /* =================== PORT definition for I2S peripheral =================== */ 1269 #define PIN_PA09J_I2S_FS0 _UINT32_(9) 1270 #define MUX_PA09J_I2S_FS0 _UINT32_(9) 1271 #define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) 1272 #define PORT_PA09J_I2S_FS0 (_UINT32_(1) << 9) 1273 1274 #define PIN_PA20J_I2S_FS0 _UINT32_(20) 1275 #define MUX_PA20J_I2S_FS0 _UINT32_(9) 1276 #define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) 1277 #define PORT_PA20J_I2S_FS0 (_UINT32_(1) << 20) 1278 1279 #define PIN_PA23J_I2S_FS1 _UINT32_(23) 1280 #define MUX_PA23J_I2S_FS1 _UINT32_(9) 1281 #define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) 1282 #define PORT_PA23J_I2S_FS1 (_UINT32_(1) << 23) 1283 1284 #define PIN_PB11J_I2S_FS1 _UINT32_(43) 1285 #define MUX_PB11J_I2S_FS1 _UINT32_(9) 1286 #define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) 1287 #define PORT_PB11J_I2S_FS1 (_UINT32_(1) << 11) 1288 1289 #define PIN_PA08J_I2S_MCK0 _UINT32_(8) 1290 #define MUX_PA08J_I2S_MCK0 _UINT32_(9) 1291 #define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) 1292 #define PORT_PA08J_I2S_MCK0 (_UINT32_(1) << 8) 1293 1294 #define PIN_PB17J_I2S_MCK0 _UINT32_(49) 1295 #define MUX_PB17J_I2S_MCK0 _UINT32_(9) 1296 #define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) 1297 #define PORT_PB17J_I2S_MCK0 (_UINT32_(1) << 17) 1298 1299 #define PIN_PB13J_I2S_MCK1 _UINT32_(45) 1300 #define MUX_PB13J_I2S_MCK1 _UINT32_(9) 1301 #define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) 1302 #define PORT_PB13J_I2S_MCK1 (_UINT32_(1) << 13) 1303 1304 #define PIN_PA10J_I2S_SCK0 _UINT32_(10) 1305 #define MUX_PA10J_I2S_SCK0 _UINT32_(9) 1306 #define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) 1307 #define PORT_PA10J_I2S_SCK0 (_UINT32_(1) << 10) 1308 1309 #define PIN_PB16J_I2S_SCK0 _UINT32_(48) 1310 #define MUX_PB16J_I2S_SCK0 _UINT32_(9) 1311 #define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) 1312 #define PORT_PB16J_I2S_SCK0 (_UINT32_(1) << 16) 1313 1314 #define PIN_PB12J_I2S_SCK1 _UINT32_(44) 1315 #define MUX_PB12J_I2S_SCK1 _UINT32_(9) 1316 #define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) 1317 #define PORT_PB12J_I2S_SCK1 (_UINT32_(1) << 12) 1318 1319 #define PIN_PA22J_I2S_SDI _UINT32_(22) 1320 #define MUX_PA22J_I2S_SDI _UINT32_(9) 1321 #define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) 1322 #define PORT_PA22J_I2S_SDI (_UINT32_(1) << 22) 1323 1324 #define PIN_PB10J_I2S_SDI _UINT32_(42) 1325 #define MUX_PB10J_I2S_SDI _UINT32_(9) 1326 #define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) 1327 #define PORT_PB10J_I2S_SDI (_UINT32_(1) << 10) 1328 1329 #define PIN_PA11J_I2S_SDO _UINT32_(11) 1330 #define MUX_PA11J_I2S_SDO _UINT32_(9) 1331 #define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) 1332 #define PORT_PA11J_I2S_SDO (_UINT32_(1) << 11) 1333 1334 #define PIN_PA21J_I2S_SDO _UINT32_(21) 1335 #define MUX_PA21J_I2S_SDO _UINT32_(9) 1336 #define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) 1337 #define PORT_PA21J_I2S_SDO (_UINT32_(1) << 21) 1338 1339 /* =================== PORT definition for PCC peripheral =================== */ 1340 #define PIN_PA14K_PCC_CLK _UINT32_(14) 1341 #define MUX_PA14K_PCC_CLK _UINT32_(10) 1342 #define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) 1343 #define PORT_PA14K_PCC_CLK (_UINT32_(1) << 14) 1344 1345 #define PIN_PA16K_PCC_DATA0 _UINT32_(16) 1346 #define MUX_PA16K_PCC_DATA0 _UINT32_(10) 1347 #define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) 1348 #define PORT_PA16K_PCC_DATA0 (_UINT32_(1) << 16) 1349 1350 #define PIN_PA17K_PCC_DATA1 _UINT32_(17) 1351 #define MUX_PA17K_PCC_DATA1 _UINT32_(10) 1352 #define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) 1353 #define PORT_PA17K_PCC_DATA1 (_UINT32_(1) << 17) 1354 1355 #define PIN_PA18K_PCC_DATA2 _UINT32_(18) 1356 #define MUX_PA18K_PCC_DATA2 _UINT32_(10) 1357 #define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) 1358 #define PORT_PA18K_PCC_DATA2 (_UINT32_(1) << 18) 1359 1360 #define PIN_PA19K_PCC_DATA3 _UINT32_(19) 1361 #define MUX_PA19K_PCC_DATA3 _UINT32_(10) 1362 #define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) 1363 #define PORT_PA19K_PCC_DATA3 (_UINT32_(1) << 19) 1364 1365 #define PIN_PA20K_PCC_DATA4 _UINT32_(20) 1366 #define MUX_PA20K_PCC_DATA4 _UINT32_(10) 1367 #define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) 1368 #define PORT_PA20K_PCC_DATA4 (_UINT32_(1) << 20) 1369 1370 #define PIN_PA21K_PCC_DATA5 _UINT32_(21) 1371 #define MUX_PA21K_PCC_DATA5 _UINT32_(10) 1372 #define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) 1373 #define PORT_PA21K_PCC_DATA5 (_UINT32_(1) << 21) 1374 1375 #define PIN_PA22K_PCC_DATA6 _UINT32_(22) 1376 #define MUX_PA22K_PCC_DATA6 _UINT32_(10) 1377 #define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) 1378 #define PORT_PA22K_PCC_DATA6 (_UINT32_(1) << 22) 1379 1380 #define PIN_PA23K_PCC_DATA7 _UINT32_(23) 1381 #define MUX_PA23K_PCC_DATA7 _UINT32_(10) 1382 #define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) 1383 #define PORT_PA23K_PCC_DATA7 (_UINT32_(1) << 23) 1384 1385 #define PIN_PB14K_PCC_DATA8 _UINT32_(46) 1386 #define MUX_PB14K_PCC_DATA8 _UINT32_(10) 1387 #define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) 1388 #define PORT_PB14K_PCC_DATA8 (_UINT32_(1) << 14) 1389 1390 #define PIN_PB15K_PCC_DATA9 _UINT32_(47) 1391 #define MUX_PB15K_PCC_DATA9 _UINT32_(10) 1392 #define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) 1393 #define PORT_PB15K_PCC_DATA9 (_UINT32_(1) << 15) 1394 1395 #define PIN_PA12K_PCC_DEN1 _UINT32_(12) 1396 #define MUX_PA12K_PCC_DEN1 _UINT32_(10) 1397 #define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) 1398 #define PORT_PA12K_PCC_DEN1 (_UINT32_(1) << 12) 1399 1400 #define PIN_PA13K_PCC_DEN2 _UINT32_(13) 1401 #define MUX_PA13K_PCC_DEN2 _UINT32_(10) 1402 #define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) 1403 #define PORT_PA13K_PCC_DEN2 (_UINT32_(1) << 13) 1404 1405 /* ================== PORT definition for PDEC peripheral =================== */ 1406 #define PIN_PB23G_PDEC_QDI0 _UINT32_(55) 1407 #define MUX_PB23G_PDEC_QDI0 _UINT32_(6) 1408 #define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) 1409 #define PORT_PB23G_PDEC_QDI0 (_UINT32_(1) << 23) 1410 1411 #define PIN_PA24G_PDEC_QDI0 _UINT32_(24) 1412 #define MUX_PA24G_PDEC_QDI0 _UINT32_(6) 1413 #define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) 1414 #define PORT_PA24G_PDEC_QDI0 (_UINT32_(1) << 24) 1415 1416 #define PIN_PA25G_PDEC_QDI1 _UINT32_(25) 1417 #define MUX_PA25G_PDEC_QDI1 _UINT32_(6) 1418 #define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) 1419 #define PORT_PA25G_PDEC_QDI1 (_UINT32_(1) << 25) 1420 1421 #define PIN_PB22G_PDEC_QDI2 _UINT32_(54) 1422 #define MUX_PB22G_PDEC_QDI2 _UINT32_(6) 1423 #define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) 1424 #define PORT_PB22G_PDEC_QDI2 (_UINT32_(1) << 22) 1425 1426 /* ================== PORT definition for QSPI peripheral =================== */ 1427 #define PIN_PB11H_QSPI_CS _UINT32_(43) 1428 #define MUX_PB11H_QSPI_CS _UINT32_(7) 1429 #define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) 1430 #define PORT_PB11H_QSPI_CS (_UINT32_(1) << 11) 1431 1432 #define PIN_PA08H_QSPI_DATA0 _UINT32_(8) 1433 #define MUX_PA08H_QSPI_DATA0 _UINT32_(7) 1434 #define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) 1435 #define PORT_PA08H_QSPI_DATA0 (_UINT32_(1) << 8) 1436 1437 #define PIN_PA09H_QSPI_DATA1 _UINT32_(9) 1438 #define MUX_PA09H_QSPI_DATA1 _UINT32_(7) 1439 #define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) 1440 #define PORT_PA09H_QSPI_DATA1 (_UINT32_(1) << 9) 1441 1442 #define PIN_PA10H_QSPI_DATA2 _UINT32_(10) 1443 #define MUX_PA10H_QSPI_DATA2 _UINT32_(7) 1444 #define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) 1445 #define PORT_PA10H_QSPI_DATA2 (_UINT32_(1) << 10) 1446 1447 #define PIN_PA11H_QSPI_DATA3 _UINT32_(11) 1448 #define MUX_PA11H_QSPI_DATA3 _UINT32_(7) 1449 #define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) 1450 #define PORT_PA11H_QSPI_DATA3 (_UINT32_(1) << 11) 1451 1452 #define PIN_PB10H_QSPI_SCK _UINT32_(42) 1453 #define MUX_PB10H_QSPI_SCK _UINT32_(7) 1454 #define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) 1455 #define PORT_PB10H_QSPI_SCK (_UINT32_(1) << 10) 1456 1457 /* ================== PORT definition for SDHC0 peripheral ================== */ 1458 #define PIN_PA06I_SDHC0_SDCD _UINT32_(6) 1459 #define MUX_PA06I_SDHC0_SDCD _UINT32_(8) 1460 #define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) 1461 #define PORT_PA06I_SDHC0_SDCD (_UINT32_(1) << 6) 1462 1463 #define PIN_PA12I_SDHC0_SDCD _UINT32_(12) 1464 #define MUX_PA12I_SDHC0_SDCD _UINT32_(8) 1465 #define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) 1466 #define PORT_PA12I_SDHC0_SDCD (_UINT32_(1) << 12) 1467 1468 #define PIN_PB12I_SDHC0_SDCD _UINT32_(44) 1469 #define MUX_PB12I_SDHC0_SDCD _UINT32_(8) 1470 #define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) 1471 #define PORT_PB12I_SDHC0_SDCD (_UINT32_(1) << 12) 1472 1473 #define PIN_PB11I_SDHC0_SDCK _UINT32_(43) 1474 #define MUX_PB11I_SDHC0_SDCK _UINT32_(8) 1475 #define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) 1476 #define PORT_PB11I_SDHC0_SDCK (_UINT32_(1) << 11) 1477 1478 #define PIN_PA08I_SDHC0_SDCMD _UINT32_(8) 1479 #define MUX_PA08I_SDHC0_SDCMD _UINT32_(8) 1480 #define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) 1481 #define PORT_PA08I_SDHC0_SDCMD (_UINT32_(1) << 8) 1482 1483 #define PIN_PA09I_SDHC0_SDDAT0 _UINT32_(9) 1484 #define MUX_PA09I_SDHC0_SDDAT0 _UINT32_(8) 1485 #define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) 1486 #define PORT_PA09I_SDHC0_SDDAT0 (_UINT32_(1) << 9) 1487 1488 #define PIN_PA10I_SDHC0_SDDAT1 _UINT32_(10) 1489 #define MUX_PA10I_SDHC0_SDDAT1 _UINT32_(8) 1490 #define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) 1491 #define PORT_PA10I_SDHC0_SDDAT1 (_UINT32_(1) << 10) 1492 1493 #define PIN_PA11I_SDHC0_SDDAT2 _UINT32_(11) 1494 #define MUX_PA11I_SDHC0_SDDAT2 _UINT32_(8) 1495 #define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) 1496 #define PORT_PA11I_SDHC0_SDDAT2 (_UINT32_(1) << 11) 1497 1498 #define PIN_PB10I_SDHC0_SDDAT3 _UINT32_(42) 1499 #define MUX_PB10I_SDHC0_SDDAT3 _UINT32_(8) 1500 #define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) 1501 #define PORT_PB10I_SDHC0_SDDAT3 (_UINT32_(1) << 10) 1502 1503 #define PIN_PA07I_SDHC0_SDWP _UINT32_(7) 1504 #define MUX_PA07I_SDHC0_SDWP _UINT32_(8) 1505 #define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) 1506 #define PORT_PA07I_SDHC0_SDWP (_UINT32_(1) << 7) 1507 1508 #define PIN_PA13I_SDHC0_SDWP _UINT32_(13) 1509 #define MUX_PA13I_SDHC0_SDWP _UINT32_(8) 1510 #define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) 1511 #define PORT_PA13I_SDHC0_SDWP (_UINT32_(1) << 13) 1512 1513 #define PIN_PB13I_SDHC0_SDWP _UINT32_(45) 1514 #define MUX_PB13I_SDHC0_SDWP _UINT32_(8) 1515 #define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) 1516 #define PORT_PB13I_SDHC0_SDWP (_UINT32_(1) << 13) 1517 1518 /* ================= PORT definition for SERCOM0 peripheral ================= */ 1519 #define PIN_PA04D_SERCOM0_PAD0 _UINT32_(4) 1520 #define MUX_PA04D_SERCOM0_PAD0 _UINT32_(3) 1521 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 1522 #define PORT_PA04D_SERCOM0_PAD0 (_UINT32_(1) << 4) 1523 1524 #define PIN_PA08C_SERCOM0_PAD0 _UINT32_(8) 1525 #define MUX_PA08C_SERCOM0_PAD0 _UINT32_(2) 1526 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 1527 #define PORT_PA08C_SERCOM0_PAD0 (_UINT32_(1) << 8) 1528 1529 #define PIN_PA05D_SERCOM0_PAD1 _UINT32_(5) 1530 #define MUX_PA05D_SERCOM0_PAD1 _UINT32_(3) 1531 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 1532 #define PORT_PA05D_SERCOM0_PAD1 (_UINT32_(1) << 5) 1533 1534 #define PIN_PA09C_SERCOM0_PAD1 _UINT32_(9) 1535 #define MUX_PA09C_SERCOM0_PAD1 _UINT32_(2) 1536 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 1537 #define PORT_PA09C_SERCOM0_PAD1 (_UINT32_(1) << 9) 1538 1539 #define PIN_PA06D_SERCOM0_PAD2 _UINT32_(6) 1540 #define MUX_PA06D_SERCOM0_PAD2 _UINT32_(3) 1541 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 1542 #define PORT_PA06D_SERCOM0_PAD2 (_UINT32_(1) << 6) 1543 1544 #define PIN_PA10C_SERCOM0_PAD2 _UINT32_(10) 1545 #define MUX_PA10C_SERCOM0_PAD2 _UINT32_(2) 1546 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 1547 #define PORT_PA10C_SERCOM0_PAD2 (_UINT32_(1) << 10) 1548 1549 #define PIN_PA07D_SERCOM0_PAD3 _UINT32_(7) 1550 #define MUX_PA07D_SERCOM0_PAD3 _UINT32_(3) 1551 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 1552 #define PORT_PA07D_SERCOM0_PAD3 (_UINT32_(1) << 7) 1553 1554 #define PIN_PA11C_SERCOM0_PAD3 _UINT32_(11) 1555 #define MUX_PA11C_SERCOM0_PAD3 _UINT32_(2) 1556 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 1557 #define PORT_PA11C_SERCOM0_PAD3 (_UINT32_(1) << 11) 1558 1559 /* ================= PORT definition for SERCOM1 peripheral ================= */ 1560 #define PIN_PA00D_SERCOM1_PAD0 _UINT32_(0) 1561 #define MUX_PA00D_SERCOM1_PAD0 _UINT32_(3) 1562 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 1563 #define PORT_PA00D_SERCOM1_PAD0 (_UINT32_(1) << 0) 1564 1565 #define PIN_PA16C_SERCOM1_PAD0 _UINT32_(16) 1566 #define MUX_PA16C_SERCOM1_PAD0 _UINT32_(2) 1567 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 1568 #define PORT_PA16C_SERCOM1_PAD0 (_UINT32_(1) << 16) 1569 1570 #define PIN_PA01D_SERCOM1_PAD1 _UINT32_(1) 1571 #define MUX_PA01D_SERCOM1_PAD1 _UINT32_(3) 1572 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 1573 #define PORT_PA01D_SERCOM1_PAD1 (_UINT32_(1) << 1) 1574 1575 #define PIN_PA17C_SERCOM1_PAD1 _UINT32_(17) 1576 #define MUX_PA17C_SERCOM1_PAD1 _UINT32_(2) 1577 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 1578 #define PORT_PA17C_SERCOM1_PAD1 (_UINT32_(1) << 17) 1579 1580 #define PIN_PA30D_SERCOM1_PAD2 _UINT32_(30) 1581 #define MUX_PA30D_SERCOM1_PAD2 _UINT32_(3) 1582 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 1583 #define PORT_PA30D_SERCOM1_PAD2 (_UINT32_(1) << 30) 1584 1585 #define PIN_PA18C_SERCOM1_PAD2 _UINT32_(18) 1586 #define MUX_PA18C_SERCOM1_PAD2 _UINT32_(2) 1587 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 1588 #define PORT_PA18C_SERCOM1_PAD2 (_UINT32_(1) << 18) 1589 1590 #define PIN_PB22C_SERCOM1_PAD2 _UINT32_(54) 1591 #define MUX_PB22C_SERCOM1_PAD2 _UINT32_(2) 1592 #define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) 1593 #define PORT_PB22C_SERCOM1_PAD2 (_UINT32_(1) << 22) 1594 1595 #define PIN_PA31D_SERCOM1_PAD3 _UINT32_(31) 1596 #define MUX_PA31D_SERCOM1_PAD3 _UINT32_(3) 1597 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 1598 #define PORT_PA31D_SERCOM1_PAD3 (_UINT32_(1) << 31) 1599 1600 #define PIN_PA19C_SERCOM1_PAD3 _UINT32_(19) 1601 #define MUX_PA19C_SERCOM1_PAD3 _UINT32_(2) 1602 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 1603 #define PORT_PA19C_SERCOM1_PAD3 (_UINT32_(1) << 19) 1604 1605 #define PIN_PB23C_SERCOM1_PAD3 _UINT32_(55) 1606 #define MUX_PB23C_SERCOM1_PAD3 _UINT32_(2) 1607 #define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) 1608 #define PORT_PB23C_SERCOM1_PAD3 (_UINT32_(1) << 23) 1609 1610 /* ================= PORT definition for SERCOM2 peripheral ================= */ 1611 #define PIN_PA09D_SERCOM2_PAD0 _UINT32_(9) 1612 #define MUX_PA09D_SERCOM2_PAD0 _UINT32_(3) 1613 #define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) 1614 #define PORT_PA09D_SERCOM2_PAD0 (_UINT32_(1) << 9) 1615 1616 #define PIN_PA12C_SERCOM2_PAD0 _UINT32_(12) 1617 #define MUX_PA12C_SERCOM2_PAD0 _UINT32_(2) 1618 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 1619 #define PORT_PA12C_SERCOM2_PAD0 (_UINT32_(1) << 12) 1620 1621 #define PIN_PA08D_SERCOM2_PAD1 _UINT32_(8) 1622 #define MUX_PA08D_SERCOM2_PAD1 _UINT32_(3) 1623 #define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) 1624 #define PORT_PA08D_SERCOM2_PAD1 (_UINT32_(1) << 8) 1625 1626 #define PIN_PA13C_SERCOM2_PAD1 _UINT32_(13) 1627 #define MUX_PA13C_SERCOM2_PAD1 _UINT32_(2) 1628 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 1629 #define PORT_PA13C_SERCOM2_PAD1 (_UINT32_(1) << 13) 1630 1631 #define PIN_PA10D_SERCOM2_PAD2 _UINT32_(10) 1632 #define MUX_PA10D_SERCOM2_PAD2 _UINT32_(3) 1633 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 1634 #define PORT_PA10D_SERCOM2_PAD2 (_UINT32_(1) << 10) 1635 1636 #define PIN_PA14C_SERCOM2_PAD2 _UINT32_(14) 1637 #define MUX_PA14C_SERCOM2_PAD2 _UINT32_(2) 1638 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 1639 #define PORT_PA14C_SERCOM2_PAD2 (_UINT32_(1) << 14) 1640 1641 #define PIN_PA11D_SERCOM2_PAD3 _UINT32_(11) 1642 #define MUX_PA11D_SERCOM2_PAD3 _UINT32_(3) 1643 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 1644 #define PORT_PA11D_SERCOM2_PAD3 (_UINT32_(1) << 11) 1645 1646 #define PIN_PA15C_SERCOM2_PAD3 _UINT32_(15) 1647 #define MUX_PA15C_SERCOM2_PAD3 _UINT32_(2) 1648 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 1649 #define PORT_PA15C_SERCOM2_PAD3 (_UINT32_(1) << 15) 1650 1651 /* ================= PORT definition for SERCOM3 peripheral ================= */ 1652 #define PIN_PA17D_SERCOM3_PAD0 _UINT32_(17) 1653 #define MUX_PA17D_SERCOM3_PAD0 _UINT32_(3) 1654 #define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) 1655 #define PORT_PA17D_SERCOM3_PAD0 (_UINT32_(1) << 17) 1656 1657 #define PIN_PA22C_SERCOM3_PAD0 _UINT32_(22) 1658 #define MUX_PA22C_SERCOM3_PAD0 _UINT32_(2) 1659 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 1660 #define PORT_PA22C_SERCOM3_PAD0 (_UINT32_(1) << 22) 1661 1662 #define PIN_PA16D_SERCOM3_PAD1 _UINT32_(16) 1663 #define MUX_PA16D_SERCOM3_PAD1 _UINT32_(3) 1664 #define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) 1665 #define PORT_PA16D_SERCOM3_PAD1 (_UINT32_(1) << 16) 1666 1667 #define PIN_PA23C_SERCOM3_PAD1 _UINT32_(23) 1668 #define MUX_PA23C_SERCOM3_PAD1 _UINT32_(2) 1669 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 1670 #define PORT_PA23C_SERCOM3_PAD1 (_UINT32_(1) << 23) 1671 1672 #define PIN_PA18D_SERCOM3_PAD2 _UINT32_(18) 1673 #define MUX_PA18D_SERCOM3_PAD2 _UINT32_(3) 1674 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 1675 #define PORT_PA18D_SERCOM3_PAD2 (_UINT32_(1) << 18) 1676 1677 #define PIN_PA20D_SERCOM3_PAD2 _UINT32_(20) 1678 #define MUX_PA20D_SERCOM3_PAD2 _UINT32_(3) 1679 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 1680 #define PORT_PA20D_SERCOM3_PAD2 (_UINT32_(1) << 20) 1681 1682 #define PIN_PA24C_SERCOM3_PAD2 _UINT32_(24) 1683 #define MUX_PA24C_SERCOM3_PAD2 _UINT32_(2) 1684 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 1685 #define PORT_PA24C_SERCOM3_PAD2 (_UINT32_(1) << 24) 1686 1687 #define PIN_PA19D_SERCOM3_PAD3 _UINT32_(19) 1688 #define MUX_PA19D_SERCOM3_PAD3 _UINT32_(3) 1689 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 1690 #define PORT_PA19D_SERCOM3_PAD3 (_UINT32_(1) << 19) 1691 1692 #define PIN_PA21D_SERCOM3_PAD3 _UINT32_(21) 1693 #define MUX_PA21D_SERCOM3_PAD3 _UINT32_(3) 1694 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 1695 #define PORT_PA21D_SERCOM3_PAD3 (_UINT32_(1) << 21) 1696 1697 #define PIN_PA25C_SERCOM3_PAD3 _UINT32_(25) 1698 #define MUX_PA25C_SERCOM3_PAD3 _UINT32_(2) 1699 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 1700 #define PORT_PA25C_SERCOM3_PAD3 (_UINT32_(1) << 25) 1701 1702 /* ================= PORT definition for SERCOM4 peripheral ================= */ 1703 #define PIN_PA13D_SERCOM4_PAD0 _UINT32_(13) 1704 #define MUX_PA13D_SERCOM4_PAD0 _UINT32_(3) 1705 #define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) 1706 #define PORT_PA13D_SERCOM4_PAD0 (_UINT32_(1) << 13) 1707 1708 #define PIN_PB08D_SERCOM4_PAD0 _UINT32_(40) 1709 #define MUX_PB08D_SERCOM4_PAD0 _UINT32_(3) 1710 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 1711 #define PORT_PB08D_SERCOM4_PAD0 (_UINT32_(1) << 8) 1712 1713 #define PIN_PB12C_SERCOM4_PAD0 _UINT32_(44) 1714 #define MUX_PB12C_SERCOM4_PAD0 _UINT32_(2) 1715 #define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) 1716 #define PORT_PB12C_SERCOM4_PAD0 (_UINT32_(1) << 12) 1717 1718 #define PIN_PA12D_SERCOM4_PAD1 _UINT32_(12) 1719 #define MUX_PA12D_SERCOM4_PAD1 _UINT32_(3) 1720 #define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) 1721 #define PORT_PA12D_SERCOM4_PAD1 (_UINT32_(1) << 12) 1722 1723 #define PIN_PB09D_SERCOM4_PAD1 _UINT32_(41) 1724 #define MUX_PB09D_SERCOM4_PAD1 _UINT32_(3) 1725 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 1726 #define PORT_PB09D_SERCOM4_PAD1 (_UINT32_(1) << 9) 1727 1728 #define PIN_PB13C_SERCOM4_PAD1 _UINT32_(45) 1729 #define MUX_PB13C_SERCOM4_PAD1 _UINT32_(2) 1730 #define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) 1731 #define PORT_PB13C_SERCOM4_PAD1 (_UINT32_(1) << 13) 1732 1733 #define PIN_PA14D_SERCOM4_PAD2 _UINT32_(14) 1734 #define MUX_PA14D_SERCOM4_PAD2 _UINT32_(3) 1735 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 1736 #define PORT_PA14D_SERCOM4_PAD2 (_UINT32_(1) << 14) 1737 1738 #define PIN_PB10D_SERCOM4_PAD2 _UINT32_(42) 1739 #define MUX_PB10D_SERCOM4_PAD2 _UINT32_(3) 1740 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 1741 #define PORT_PB10D_SERCOM4_PAD2 (_UINT32_(1) << 10) 1742 1743 #define PIN_PB14C_SERCOM4_PAD2 _UINT32_(46) 1744 #define MUX_PB14C_SERCOM4_PAD2 _UINT32_(2) 1745 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) 1746 #define PORT_PB14C_SERCOM4_PAD2 (_UINT32_(1) << 14) 1747 1748 #define PIN_PB11D_SERCOM4_PAD3 _UINT32_(43) 1749 #define MUX_PB11D_SERCOM4_PAD3 _UINT32_(3) 1750 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 1751 #define PORT_PB11D_SERCOM4_PAD3 (_UINT32_(1) << 11) 1752 1753 #define PIN_PA15D_SERCOM4_PAD3 _UINT32_(15) 1754 #define MUX_PA15D_SERCOM4_PAD3 _UINT32_(3) 1755 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 1756 #define PORT_PA15D_SERCOM4_PAD3 (_UINT32_(1) << 15) 1757 1758 #define PIN_PB15C_SERCOM4_PAD3 _UINT32_(47) 1759 #define MUX_PB15C_SERCOM4_PAD3 _UINT32_(2) 1760 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) 1761 #define PORT_PB15C_SERCOM4_PAD3 (_UINT32_(1) << 15) 1762 1763 /* ================= PORT definition for SERCOM5 peripheral ================= */ 1764 #define PIN_PA23D_SERCOM5_PAD0 _UINT32_(23) 1765 #define MUX_PA23D_SERCOM5_PAD0 _UINT32_(3) 1766 #define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) 1767 #define PORT_PA23D_SERCOM5_PAD0 (_UINT32_(1) << 23) 1768 1769 #define PIN_PB02D_SERCOM5_PAD0 _UINT32_(34) 1770 #define MUX_PB02D_SERCOM5_PAD0 _UINT32_(3) 1771 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 1772 #define PORT_PB02D_SERCOM5_PAD0 (_UINT32_(1) << 2) 1773 1774 #define PIN_PB31D_SERCOM5_PAD0 _UINT32_(63) 1775 #define MUX_PB31D_SERCOM5_PAD0 _UINT32_(3) 1776 #define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) 1777 #define PORT_PB31D_SERCOM5_PAD0 (_UINT32_(1) << 31) 1778 1779 #define PIN_PB16C_SERCOM5_PAD0 _UINT32_(48) 1780 #define MUX_PB16C_SERCOM5_PAD0 _UINT32_(2) 1781 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) 1782 #define PORT_PB16C_SERCOM5_PAD0 (_UINT32_(1) << 16) 1783 1784 #define PIN_PA22D_SERCOM5_PAD1 _UINT32_(22) 1785 #define MUX_PA22D_SERCOM5_PAD1 _UINT32_(3) 1786 #define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) 1787 #define PORT_PA22D_SERCOM5_PAD1 (_UINT32_(1) << 22) 1788 1789 #define PIN_PB03D_SERCOM5_PAD1 _UINT32_(35) 1790 #define MUX_PB03D_SERCOM5_PAD1 _UINT32_(3) 1791 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 1792 #define PORT_PB03D_SERCOM5_PAD1 (_UINT32_(1) << 3) 1793 1794 #define PIN_PB30D_SERCOM5_PAD1 _UINT32_(62) 1795 #define MUX_PB30D_SERCOM5_PAD1 _UINT32_(3) 1796 #define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) 1797 #define PORT_PB30D_SERCOM5_PAD1 (_UINT32_(1) << 30) 1798 1799 #define PIN_PB17C_SERCOM5_PAD1 _UINT32_(49) 1800 #define MUX_PB17C_SERCOM5_PAD1 _UINT32_(2) 1801 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) 1802 #define PORT_PB17C_SERCOM5_PAD1 (_UINT32_(1) << 17) 1803 1804 #define PIN_PA24D_SERCOM5_PAD2 _UINT32_(24) 1805 #define MUX_PA24D_SERCOM5_PAD2 _UINT32_(3) 1806 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 1807 #define PORT_PA24D_SERCOM5_PAD2 (_UINT32_(1) << 24) 1808 1809 #define PIN_PB00D_SERCOM5_PAD2 _UINT32_(32) 1810 #define MUX_PB00D_SERCOM5_PAD2 _UINT32_(3) 1811 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) 1812 #define PORT_PB00D_SERCOM5_PAD2 (_UINT32_(1) << 0) 1813 1814 #define PIN_PB22D_SERCOM5_PAD2 _UINT32_(54) 1815 #define MUX_PB22D_SERCOM5_PAD2 _UINT32_(3) 1816 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 1817 #define PORT_PB22D_SERCOM5_PAD2 (_UINT32_(1) << 22) 1818 1819 #define PIN_PA20C_SERCOM5_PAD2 _UINT32_(20) 1820 #define MUX_PA20C_SERCOM5_PAD2 _UINT32_(2) 1821 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 1822 #define PORT_PA20C_SERCOM5_PAD2 (_UINT32_(1) << 20) 1823 1824 #define PIN_PA25D_SERCOM5_PAD3 _UINT32_(25) 1825 #define MUX_PA25D_SERCOM5_PAD3 _UINT32_(3) 1826 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 1827 #define PORT_PA25D_SERCOM5_PAD3 (_UINT32_(1) << 25) 1828 1829 #define PIN_PB01D_SERCOM5_PAD3 _UINT32_(33) 1830 #define MUX_PB01D_SERCOM5_PAD3 _UINT32_(3) 1831 #define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) 1832 #define PORT_PB01D_SERCOM5_PAD3 (_UINT32_(1) << 1) 1833 1834 #define PIN_PB23D_SERCOM5_PAD3 _UINT32_(55) 1835 #define MUX_PB23D_SERCOM5_PAD3 _UINT32_(3) 1836 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 1837 #define PORT_PB23D_SERCOM5_PAD3 (_UINT32_(1) << 23) 1838 1839 #define PIN_PA21C_SERCOM5_PAD3 _UINT32_(21) 1840 #define MUX_PA21C_SERCOM5_PAD3 _UINT32_(2) 1841 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 1842 #define PORT_PA21C_SERCOM5_PAD3 (_UINT32_(1) << 21) 1843 1844 /* =================== PORT definition for TC0 peripheral =================== */ 1845 #define PIN_PA04E_TC0_WO0 _UINT32_(4) 1846 #define MUX_PA04E_TC0_WO0 _UINT32_(4) 1847 #define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) 1848 #define PORT_PA04E_TC0_WO0 (_UINT32_(1) << 4) 1849 1850 #define PIN_PA08E_TC0_WO0 _UINT32_(8) 1851 #define MUX_PA08E_TC0_WO0 _UINT32_(4) 1852 #define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) 1853 #define PORT_PA08E_TC0_WO0 (_UINT32_(1) << 8) 1854 1855 #define PIN_PB30E_TC0_WO0 _UINT32_(62) 1856 #define MUX_PB30E_TC0_WO0 _UINT32_(4) 1857 #define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) 1858 #define PORT_PB30E_TC0_WO0 (_UINT32_(1) << 30) 1859 1860 #define PIN_PA05E_TC0_WO1 _UINT32_(5) 1861 #define MUX_PA05E_TC0_WO1 _UINT32_(4) 1862 #define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) 1863 #define PORT_PA05E_TC0_WO1 (_UINT32_(1) << 5) 1864 1865 #define PIN_PA09E_TC0_WO1 _UINT32_(9) 1866 #define MUX_PA09E_TC0_WO1 _UINT32_(4) 1867 #define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) 1868 #define PORT_PA09E_TC0_WO1 (_UINT32_(1) << 9) 1869 1870 #define PIN_PB31E_TC0_WO1 _UINT32_(63) 1871 #define MUX_PB31E_TC0_WO1 _UINT32_(4) 1872 #define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) 1873 #define PORT_PB31E_TC0_WO1 (_UINT32_(1) << 31) 1874 1875 /* =================== PORT definition for TC1 peripheral =================== */ 1876 #define PIN_PA06E_TC1_WO0 _UINT32_(6) 1877 #define MUX_PA06E_TC1_WO0 _UINT32_(4) 1878 #define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) 1879 #define PORT_PA06E_TC1_WO0 (_UINT32_(1) << 6) 1880 1881 #define PIN_PA10E_TC1_WO0 _UINT32_(10) 1882 #define MUX_PA10E_TC1_WO0 _UINT32_(4) 1883 #define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) 1884 #define PORT_PA10E_TC1_WO0 (_UINT32_(1) << 10) 1885 1886 #define PIN_PA07E_TC1_WO1 _UINT32_(7) 1887 #define MUX_PA07E_TC1_WO1 _UINT32_(4) 1888 #define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) 1889 #define PORT_PA07E_TC1_WO1 (_UINT32_(1) << 7) 1890 1891 #define PIN_PA11E_TC1_WO1 _UINT32_(11) 1892 #define MUX_PA11E_TC1_WO1 _UINT32_(4) 1893 #define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) 1894 #define PORT_PA11E_TC1_WO1 (_UINT32_(1) << 11) 1895 1896 /* =================== PORT definition for TC2 peripheral =================== */ 1897 #define PIN_PA12E_TC2_WO0 _UINT32_(12) 1898 #define MUX_PA12E_TC2_WO0 _UINT32_(4) 1899 #define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) 1900 #define PORT_PA12E_TC2_WO0 (_UINT32_(1) << 12) 1901 1902 #define PIN_PA16E_TC2_WO0 _UINT32_(16) 1903 #define MUX_PA16E_TC2_WO0 _UINT32_(4) 1904 #define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) 1905 #define PORT_PA16E_TC2_WO0 (_UINT32_(1) << 16) 1906 1907 #define PIN_PA00E_TC2_WO0 _UINT32_(0) 1908 #define MUX_PA00E_TC2_WO0 _UINT32_(4) 1909 #define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) 1910 #define PORT_PA00E_TC2_WO0 (_UINT32_(1) << 0) 1911 1912 #define PIN_PA01E_TC2_WO1 _UINT32_(1) 1913 #define MUX_PA01E_TC2_WO1 _UINT32_(4) 1914 #define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) 1915 #define PORT_PA01E_TC2_WO1 (_UINT32_(1) << 1) 1916 1917 #define PIN_PA13E_TC2_WO1 _UINT32_(13) 1918 #define MUX_PA13E_TC2_WO1 _UINT32_(4) 1919 #define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) 1920 #define PORT_PA13E_TC2_WO1 (_UINT32_(1) << 13) 1921 1922 #define PIN_PA17E_TC2_WO1 _UINT32_(17) 1923 #define MUX_PA17E_TC2_WO1 _UINT32_(4) 1924 #define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) 1925 #define PORT_PA17E_TC2_WO1 (_UINT32_(1) << 17) 1926 1927 /* =================== PORT definition for TC3 peripheral =================== */ 1928 #define PIN_PA18E_TC3_WO0 _UINT32_(18) 1929 #define MUX_PA18E_TC3_WO0 _UINT32_(4) 1930 #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) 1931 #define PORT_PA18E_TC3_WO0 (_UINT32_(1) << 18) 1932 1933 #define PIN_PA14E_TC3_WO0 _UINT32_(14) 1934 #define MUX_PA14E_TC3_WO0 _UINT32_(4) 1935 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) 1936 #define PORT_PA14E_TC3_WO0 (_UINT32_(1) << 14) 1937 1938 #define PIN_PA15E_TC3_WO1 _UINT32_(15) 1939 #define MUX_PA15E_TC3_WO1 _UINT32_(4) 1940 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) 1941 #define PORT_PA15E_TC3_WO1 (_UINT32_(1) << 15) 1942 1943 #define PIN_PA19E_TC3_WO1 _UINT32_(19) 1944 #define MUX_PA19E_TC3_WO1 _UINT32_(4) 1945 #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) 1946 #define PORT_PA19E_TC3_WO1 (_UINT32_(1) << 19) 1947 1948 /* =================== PORT definition for TC4 peripheral =================== */ 1949 #define PIN_PA22E_TC4_WO0 _UINT32_(22) 1950 #define MUX_PA22E_TC4_WO0 _UINT32_(4) 1951 #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) 1952 #define PORT_PA22E_TC4_WO0 (_UINT32_(1) << 22) 1953 1954 #define PIN_PB08E_TC4_WO0 _UINT32_(40) 1955 #define MUX_PB08E_TC4_WO0 _UINT32_(4) 1956 #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) 1957 #define PORT_PB08E_TC4_WO0 (_UINT32_(1) << 8) 1958 1959 #define PIN_PB12E_TC4_WO0 _UINT32_(44) 1960 #define MUX_PB12E_TC4_WO0 _UINT32_(4) 1961 #define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) 1962 #define PORT_PB12E_TC4_WO0 (_UINT32_(1) << 12) 1963 1964 #define PIN_PA23E_TC4_WO1 _UINT32_(23) 1965 #define MUX_PA23E_TC4_WO1 _UINT32_(4) 1966 #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) 1967 #define PORT_PA23E_TC4_WO1 (_UINT32_(1) << 23) 1968 1969 #define PIN_PB09E_TC4_WO1 _UINT32_(41) 1970 #define MUX_PB09E_TC4_WO1 _UINT32_(4) 1971 #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) 1972 #define PORT_PB09E_TC4_WO1 (_UINT32_(1) << 9) 1973 1974 #define PIN_PB13E_TC4_WO1 _UINT32_(45) 1975 #define MUX_PB13E_TC4_WO1 _UINT32_(4) 1976 #define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) 1977 #define PORT_PB13E_TC4_WO1 (_UINT32_(1) << 13) 1978 1979 /* =================== PORT definition for TC5 peripheral =================== */ 1980 #define PIN_PA24E_TC5_WO0 _UINT32_(24) 1981 #define MUX_PA24E_TC5_WO0 _UINT32_(4) 1982 #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) 1983 #define PORT_PA24E_TC5_WO0 (_UINT32_(1) << 24) 1984 1985 #define PIN_PB10E_TC5_WO0 _UINT32_(42) 1986 #define MUX_PB10E_TC5_WO0 _UINT32_(4) 1987 #define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) 1988 #define PORT_PB10E_TC5_WO0 (_UINT32_(1) << 10) 1989 1990 #define PIN_PB14E_TC5_WO0 _UINT32_(46) 1991 #define MUX_PB14E_TC5_WO0 _UINT32_(4) 1992 #define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) 1993 #define PORT_PB14E_TC5_WO0 (_UINT32_(1) << 14) 1994 1995 #define PIN_PA25E_TC5_WO1 _UINT32_(25) 1996 #define MUX_PA25E_TC5_WO1 _UINT32_(4) 1997 #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) 1998 #define PORT_PA25E_TC5_WO1 (_UINT32_(1) << 25) 1999 2000 #define PIN_PB11E_TC5_WO1 _UINT32_(43) 2001 #define MUX_PB11E_TC5_WO1 _UINT32_(4) 2002 #define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) 2003 #define PORT_PB11E_TC5_WO1 (_UINT32_(1) << 11) 2004 2005 #define PIN_PB15E_TC5_WO1 _UINT32_(47) 2006 #define MUX_PB15E_TC5_WO1 _UINT32_(4) 2007 #define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) 2008 #define PORT_PB15E_TC5_WO1 (_UINT32_(1) << 15) 2009 2010 /* ================== PORT definition for TCC0 peripheral =================== */ 2011 #define PIN_PA20G_TCC0_WO0 _UINT32_(20) 2012 #define MUX_PA20G_TCC0_WO0 _UINT32_(6) 2013 #define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) 2014 #define PORT_PA20G_TCC0_WO0 (_UINT32_(1) << 20) 2015 2016 #define PIN_PB12G_TCC0_WO0 _UINT32_(44) 2017 #define MUX_PB12G_TCC0_WO0 _UINT32_(6) 2018 #define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) 2019 #define PORT_PB12G_TCC0_WO0 (_UINT32_(1) << 12) 2020 2021 #define PIN_PA08F_TCC0_WO0 _UINT32_(8) 2022 #define MUX_PA08F_TCC0_WO0 _UINT32_(5) 2023 #define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) 2024 #define PORT_PA08F_TCC0_WO0 (_UINT32_(1) << 8) 2025 2026 #define PIN_PA21G_TCC0_WO1 _UINT32_(21) 2027 #define MUX_PA21G_TCC0_WO1 _UINT32_(6) 2028 #define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) 2029 #define PORT_PA21G_TCC0_WO1 (_UINT32_(1) << 21) 2030 2031 #define PIN_PB13G_TCC0_WO1 _UINT32_(45) 2032 #define MUX_PB13G_TCC0_WO1 _UINT32_(6) 2033 #define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) 2034 #define PORT_PB13G_TCC0_WO1 (_UINT32_(1) << 13) 2035 2036 #define PIN_PA09F_TCC0_WO1 _UINT32_(9) 2037 #define MUX_PA09F_TCC0_WO1 _UINT32_(5) 2038 #define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) 2039 #define PORT_PA09F_TCC0_WO1 (_UINT32_(1) << 9) 2040 2041 #define PIN_PA22G_TCC0_WO2 _UINT32_(22) 2042 #define MUX_PA22G_TCC0_WO2 _UINT32_(6) 2043 #define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) 2044 #define PORT_PA22G_TCC0_WO2 (_UINT32_(1) << 22) 2045 2046 #define PIN_PB14G_TCC0_WO2 _UINT32_(46) 2047 #define MUX_PB14G_TCC0_WO2 _UINT32_(6) 2048 #define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) 2049 #define PORT_PB14G_TCC0_WO2 (_UINT32_(1) << 14) 2050 2051 #define PIN_PA10F_TCC0_WO2 _UINT32_(10) 2052 #define MUX_PA10F_TCC0_WO2 _UINT32_(5) 2053 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 2054 #define PORT_PA10F_TCC0_WO2 (_UINT32_(1) << 10) 2055 2056 #define PIN_PA23G_TCC0_WO3 _UINT32_(23) 2057 #define MUX_PA23G_TCC0_WO3 _UINT32_(6) 2058 #define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) 2059 #define PORT_PA23G_TCC0_WO3 (_UINT32_(1) << 23) 2060 2061 #define PIN_PB15G_TCC0_WO3 _UINT32_(47) 2062 #define MUX_PB15G_TCC0_WO3 _UINT32_(6) 2063 #define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) 2064 #define PORT_PB15G_TCC0_WO3 (_UINT32_(1) << 15) 2065 2066 #define PIN_PA11F_TCC0_WO3 _UINT32_(11) 2067 #define MUX_PA11F_TCC0_WO3 _UINT32_(5) 2068 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 2069 #define PORT_PA11F_TCC0_WO3 (_UINT32_(1) << 11) 2070 2071 #define PIN_PA16G_TCC0_WO4 _UINT32_(16) 2072 #define MUX_PA16G_TCC0_WO4 _UINT32_(6) 2073 #define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) 2074 #define PORT_PA16G_TCC0_WO4 (_UINT32_(1) << 16) 2075 2076 #define PIN_PB16G_TCC0_WO4 _UINT32_(48) 2077 #define MUX_PB16G_TCC0_WO4 _UINT32_(6) 2078 #define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) 2079 #define PORT_PB16G_TCC0_WO4 (_UINT32_(1) << 16) 2080 2081 #define PIN_PB10F_TCC0_WO4 _UINT32_(42) 2082 #define MUX_PB10F_TCC0_WO4 _UINT32_(5) 2083 #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) 2084 #define PORT_PB10F_TCC0_WO4 (_UINT32_(1) << 10) 2085 2086 #define PIN_PA17G_TCC0_WO5 _UINT32_(17) 2087 #define MUX_PA17G_TCC0_WO5 _UINT32_(6) 2088 #define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) 2089 #define PORT_PA17G_TCC0_WO5 (_UINT32_(1) << 17) 2090 2091 #define PIN_PB17G_TCC0_WO5 _UINT32_(49) 2092 #define MUX_PB17G_TCC0_WO5 _UINT32_(6) 2093 #define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) 2094 #define PORT_PB17G_TCC0_WO5 (_UINT32_(1) << 17) 2095 2096 #define PIN_PB11F_TCC0_WO5 _UINT32_(43) 2097 #define MUX_PB11F_TCC0_WO5 _UINT32_(5) 2098 #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) 2099 #define PORT_PB11F_TCC0_WO5 (_UINT32_(1) << 11) 2100 2101 #define PIN_PA18G_TCC0_WO6 _UINT32_(18) 2102 #define MUX_PA18G_TCC0_WO6 _UINT32_(6) 2103 #define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) 2104 #define PORT_PA18G_TCC0_WO6 (_UINT32_(1) << 18) 2105 2106 #define PIN_PB30G_TCC0_WO6 _UINT32_(62) 2107 #define MUX_PB30G_TCC0_WO6 _UINT32_(6) 2108 #define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) 2109 #define PORT_PB30G_TCC0_WO6 (_UINT32_(1) << 30) 2110 2111 #define PIN_PA12F_TCC0_WO6 _UINT32_(12) 2112 #define MUX_PA12F_TCC0_WO6 _UINT32_(5) 2113 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) 2114 #define PORT_PA12F_TCC0_WO6 (_UINT32_(1) << 12) 2115 2116 #define PIN_PA19G_TCC0_WO7 _UINT32_(19) 2117 #define MUX_PA19G_TCC0_WO7 _UINT32_(6) 2118 #define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) 2119 #define PORT_PA19G_TCC0_WO7 (_UINT32_(1) << 19) 2120 2121 #define PIN_PB31G_TCC0_WO7 _UINT32_(63) 2122 #define MUX_PB31G_TCC0_WO7 _UINT32_(6) 2123 #define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) 2124 #define PORT_PB31G_TCC0_WO7 (_UINT32_(1) << 31) 2125 2126 #define PIN_PA13F_TCC0_WO7 _UINT32_(13) 2127 #define MUX_PA13F_TCC0_WO7 _UINT32_(5) 2128 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) 2129 #define PORT_PA13F_TCC0_WO7 (_UINT32_(1) << 13) 2130 2131 /* ================== PORT definition for TCC1 peripheral =================== */ 2132 #define PIN_PB10G_TCC1_WO0 _UINT32_(42) 2133 #define MUX_PB10G_TCC1_WO0 _UINT32_(6) 2134 #define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) 2135 #define PORT_PB10G_TCC1_WO0 (_UINT32_(1) << 10) 2136 2137 #define PIN_PA16F_TCC1_WO0 _UINT32_(16) 2138 #define MUX_PA16F_TCC1_WO0 _UINT32_(5) 2139 #define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) 2140 #define PORT_PA16F_TCC1_WO0 (_UINT32_(1) << 16) 2141 2142 #define PIN_PB11G_TCC1_WO1 _UINT32_(43) 2143 #define MUX_PB11G_TCC1_WO1 _UINT32_(6) 2144 #define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) 2145 #define PORT_PB11G_TCC1_WO1 (_UINT32_(1) << 11) 2146 2147 #define PIN_PA17F_TCC1_WO1 _UINT32_(17) 2148 #define MUX_PA17F_TCC1_WO1 _UINT32_(5) 2149 #define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) 2150 #define PORT_PA17F_TCC1_WO1 (_UINT32_(1) << 17) 2151 2152 #define PIN_PA12G_TCC1_WO2 _UINT32_(12) 2153 #define MUX_PA12G_TCC1_WO2 _UINT32_(6) 2154 #define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) 2155 #define PORT_PA12G_TCC1_WO2 (_UINT32_(1) << 12) 2156 2157 #define PIN_PA14G_TCC1_WO2 _UINT32_(14) 2158 #define MUX_PA14G_TCC1_WO2 _UINT32_(6) 2159 #define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) 2160 #define PORT_PA14G_TCC1_WO2 (_UINT32_(1) << 14) 2161 2162 #define PIN_PA18F_TCC1_WO2 _UINT32_(18) 2163 #define MUX_PA18F_TCC1_WO2 _UINT32_(5) 2164 #define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) 2165 #define PORT_PA18F_TCC1_WO2 (_UINT32_(1) << 18) 2166 2167 #define PIN_PA13G_TCC1_WO3 _UINT32_(13) 2168 #define MUX_PA13G_TCC1_WO3 _UINT32_(6) 2169 #define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) 2170 #define PORT_PA13G_TCC1_WO3 (_UINT32_(1) << 13) 2171 2172 #define PIN_PA15G_TCC1_WO3 _UINT32_(15) 2173 #define MUX_PA15G_TCC1_WO3 _UINT32_(6) 2174 #define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) 2175 #define PORT_PA15G_TCC1_WO3 (_UINT32_(1) << 15) 2176 2177 #define PIN_PA19F_TCC1_WO3 _UINT32_(19) 2178 #define MUX_PA19F_TCC1_WO3 _UINT32_(5) 2179 #define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) 2180 #define PORT_PA19F_TCC1_WO3 (_UINT32_(1) << 19) 2181 2182 #define PIN_PA08G_TCC1_WO4 _UINT32_(8) 2183 #define MUX_PA08G_TCC1_WO4 _UINT32_(6) 2184 #define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) 2185 #define PORT_PA08G_TCC1_WO4 (_UINT32_(1) << 8) 2186 2187 #define PIN_PA20F_TCC1_WO4 _UINT32_(20) 2188 #define MUX_PA20F_TCC1_WO4 _UINT32_(5) 2189 #define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) 2190 #define PORT_PA20F_TCC1_WO4 (_UINT32_(1) << 20) 2191 2192 #define PIN_PA09G_TCC1_WO5 _UINT32_(9) 2193 #define MUX_PA09G_TCC1_WO5 _UINT32_(6) 2194 #define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) 2195 #define PORT_PA09G_TCC1_WO5 (_UINT32_(1) << 9) 2196 2197 #define PIN_PA21F_TCC1_WO5 _UINT32_(21) 2198 #define MUX_PA21F_TCC1_WO5 _UINT32_(5) 2199 #define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) 2200 #define PORT_PA21F_TCC1_WO5 (_UINT32_(1) << 21) 2201 2202 #define PIN_PA10G_TCC1_WO6 _UINT32_(10) 2203 #define MUX_PA10G_TCC1_WO6 _UINT32_(6) 2204 #define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) 2205 #define PORT_PA10G_TCC1_WO6 (_UINT32_(1) << 10) 2206 2207 #define PIN_PA22F_TCC1_WO6 _UINT32_(22) 2208 #define MUX_PA22F_TCC1_WO6 _UINT32_(5) 2209 #define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) 2210 #define PORT_PA22F_TCC1_WO6 (_UINT32_(1) << 22) 2211 2212 #define PIN_PA11G_TCC1_WO7 _UINT32_(11) 2213 #define MUX_PA11G_TCC1_WO7 _UINT32_(6) 2214 #define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) 2215 #define PORT_PA11G_TCC1_WO7 (_UINT32_(1) << 11) 2216 2217 #define PIN_PA23F_TCC1_WO7 _UINT32_(23) 2218 #define MUX_PA23F_TCC1_WO7 _UINT32_(5) 2219 #define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) 2220 #define PORT_PA23F_TCC1_WO7 (_UINT32_(1) << 23) 2221 2222 /* ================== PORT definition for TCC2 peripheral =================== */ 2223 #define PIN_PA14F_TCC2_WO0 _UINT32_(14) 2224 #define MUX_PA14F_TCC2_WO0 _UINT32_(5) 2225 #define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) 2226 #define PORT_PA14F_TCC2_WO0 (_UINT32_(1) << 14) 2227 2228 #define PIN_PA30F_TCC2_WO0 _UINT32_(30) 2229 #define MUX_PA30F_TCC2_WO0 _UINT32_(5) 2230 #define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) 2231 #define PORT_PA30F_TCC2_WO0 (_UINT32_(1) << 30) 2232 2233 #define PIN_PA15F_TCC2_WO1 _UINT32_(15) 2234 #define MUX_PA15F_TCC2_WO1 _UINT32_(5) 2235 #define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) 2236 #define PORT_PA15F_TCC2_WO1 (_UINT32_(1) << 15) 2237 2238 #define PIN_PA31F_TCC2_WO1 _UINT32_(31) 2239 #define MUX_PA31F_TCC2_WO1 _UINT32_(5) 2240 #define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) 2241 #define PORT_PA31F_TCC2_WO1 (_UINT32_(1) << 31) 2242 2243 #define PIN_PA24F_TCC2_WO2 _UINT32_(24) 2244 #define MUX_PA24F_TCC2_WO2 _UINT32_(5) 2245 #define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) 2246 #define PORT_PA24F_TCC2_WO2 (_UINT32_(1) << 24) 2247 2248 #define PIN_PB02F_TCC2_WO2 _UINT32_(34) 2249 #define MUX_PB02F_TCC2_WO2 _UINT32_(5) 2250 #define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) 2251 #define PORT_PB02F_TCC2_WO2 (_UINT32_(1) << 2) 2252 2253 /* ================== PORT definition for TCC3 peripheral =================== */ 2254 #define PIN_PB12F_TCC3_WO0 _UINT32_(44) 2255 #define MUX_PB12F_TCC3_WO0 _UINT32_(5) 2256 #define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) 2257 #define PORT_PB12F_TCC3_WO0 (_UINT32_(1) << 12) 2258 2259 #define PIN_PB16F_TCC3_WO0 _UINT32_(48) 2260 #define MUX_PB16F_TCC3_WO0 _UINT32_(5) 2261 #define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) 2262 #define PORT_PB16F_TCC3_WO0 (_UINT32_(1) << 16) 2263 2264 #define PIN_PB13F_TCC3_WO1 _UINT32_(45) 2265 #define MUX_PB13F_TCC3_WO1 _UINT32_(5) 2266 #define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) 2267 #define PORT_PB13F_TCC3_WO1 (_UINT32_(1) << 13) 2268 2269 #define PIN_PB17F_TCC3_WO1 _UINT32_(49) 2270 #define MUX_PB17F_TCC3_WO1 _UINT32_(5) 2271 #define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) 2272 #define PORT_PB17F_TCC3_WO1 (_UINT32_(1) << 17) 2273 2274 /* ================== PORT definition for TCC4 peripheral =================== */ 2275 #define PIN_PB14F_TCC4_WO0 _UINT32_(46) 2276 #define MUX_PB14F_TCC4_WO0 _UINT32_(5) 2277 #define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) 2278 #define PORT_PB14F_TCC4_WO0 (_UINT32_(1) << 14) 2279 2280 #define PIN_PB30F_TCC4_WO0 _UINT32_(62) 2281 #define MUX_PB30F_TCC4_WO0 _UINT32_(5) 2282 #define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) 2283 #define PORT_PB30F_TCC4_WO0 (_UINT32_(1) << 30) 2284 2285 #define PIN_PB15F_TCC4_WO1 _UINT32_(47) 2286 #define MUX_PB15F_TCC4_WO1 _UINT32_(5) 2287 #define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) 2288 #define PORT_PB15F_TCC4_WO1 (_UINT32_(1) << 15) 2289 2290 #define PIN_PB31F_TCC4_WO1 _UINT32_(63) 2291 #define MUX_PB31F_TCC4_WO1 _UINT32_(5) 2292 #define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) 2293 #define PORT_PB31F_TCC4_WO1 (_UINT32_(1) << 31) 2294 2295 /* =================== PORT definition for USB peripheral =================== */ 2296 #define PIN_PA24H_USB_DM _UINT32_(24) 2297 #define MUX_PA24H_USB_DM _UINT32_(7) 2298 #define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) 2299 #define PORT_PA24H_USB_DM (_UINT32_(1) << 24) 2300 2301 #define PIN_PA25H_USB_DP _UINT32_(25) 2302 #define MUX_PA25H_USB_DP _UINT32_(7) 2303 #define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) 2304 #define PORT_PA25H_USB_DP (_UINT32_(1) << 25) 2305 2306 #define PIN_PA23H_USB_SOF_1KHZ _UINT32_(23) 2307 #define MUX_PA23H_USB_SOF_1KHZ _UINT32_(7) 2308 #define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) 2309 #define PORT_PA23H_USB_SOF_1KHZ (_UINT32_(1) << 23) 2310 2311 #define PIN_PB22H_USB_SOF_1KHZ _UINT32_(54) 2312 #define MUX_PB22H_USB_SOF_1KHZ _UINT32_(7) 2313 #define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) 2314 #define PORT_PB22H_USB_SOF_1KHZ (_UINT32_(1) << 22) 2315 2316 2317 2318 #endif /* _PIC32CX1025SG41064_GPIO_H_ */ 2319 2320