1 /* 2 * Component description for GMAC 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_GMAC_COMPONENT_H_ 22 #define _PIC32CXSG41_GMAC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR GMAC */ 26 /* ************************************************************************** */ 27 28 /* -------- GMAC_SAB : (GMAC Offset: 0x00) (R/W 32) Specific Address Bottom [31:0] Register -------- */ 29 #define GMAC_SAB_RESETVALUE _UINT32_(0x00) /* (GMAC_SAB) Specific Address Bottom [31:0] Register Reset Value */ 30 31 #define GMAC_SAB_ADDR_Pos _UINT32_(0) /* (GMAC_SAB) Specific Address 1 Position */ 32 #define GMAC_SAB_ADDR_Msk (_UINT32_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos) /* (GMAC_SAB) Specific Address 1 Mask */ 33 #define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & (_UINT32_(value) << GMAC_SAB_ADDR_Pos)) /* Assignment of value for ADDR in the GMAC_SAB register */ 34 #define GMAC_SAB_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_SAB) Register Mask */ 35 36 37 /* -------- GMAC_SAT : (GMAC Offset: 0x04) (R/W 32) Specific Address Top [47:32] Register -------- */ 38 #define GMAC_SAT_RESETVALUE _UINT32_(0x00) /* (GMAC_SAT) Specific Address Top [47:32] Register Reset Value */ 39 40 #define GMAC_SAT_ADDR_Pos _UINT32_(0) /* (GMAC_SAT) Specific Address 1 Position */ 41 #define GMAC_SAT_ADDR_Msk (_UINT32_(0xFFFF) << GMAC_SAT_ADDR_Pos) /* (GMAC_SAT) Specific Address 1 Mask */ 42 #define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & (_UINT32_(value) << GMAC_SAT_ADDR_Pos)) /* Assignment of value for ADDR in the GMAC_SAT register */ 43 #define GMAC_SAT_Msk _UINT32_(0x0000FFFF) /* (GMAC_SAT) Register Mask */ 44 45 46 /* -------- GMAC_NCR : (GMAC Offset: 0x00) (R/W 32) Network Control Register -------- */ 47 #define GMAC_NCR_RESETVALUE _UINT32_(0x00) /* (GMAC_NCR) Network Control Register Reset Value */ 48 49 #define GMAC_NCR_LBL_Pos _UINT32_(1) /* (GMAC_NCR) Loop Back Local Position */ 50 #define GMAC_NCR_LBL_Msk (_UINT32_(0x1) << GMAC_NCR_LBL_Pos) /* (GMAC_NCR) Loop Back Local Mask */ 51 #define GMAC_NCR_LBL(value) (GMAC_NCR_LBL_Msk & (_UINT32_(value) << GMAC_NCR_LBL_Pos)) /* Assignment of value for LBL in the GMAC_NCR register */ 52 #define GMAC_NCR_RXEN_Pos _UINT32_(2) /* (GMAC_NCR) Receive Enable Position */ 53 #define GMAC_NCR_RXEN_Msk (_UINT32_(0x1) << GMAC_NCR_RXEN_Pos) /* (GMAC_NCR) Receive Enable Mask */ 54 #define GMAC_NCR_RXEN(value) (GMAC_NCR_RXEN_Msk & (_UINT32_(value) << GMAC_NCR_RXEN_Pos)) /* Assignment of value for RXEN in the GMAC_NCR register */ 55 #define GMAC_NCR_TXEN_Pos _UINT32_(3) /* (GMAC_NCR) Transmit Enable Position */ 56 #define GMAC_NCR_TXEN_Msk (_UINT32_(0x1) << GMAC_NCR_TXEN_Pos) /* (GMAC_NCR) Transmit Enable Mask */ 57 #define GMAC_NCR_TXEN(value) (GMAC_NCR_TXEN_Msk & (_UINT32_(value) << GMAC_NCR_TXEN_Pos)) /* Assignment of value for TXEN in the GMAC_NCR register */ 58 #define GMAC_NCR_MPE_Pos _UINT32_(4) /* (GMAC_NCR) Management Port Enable Position */ 59 #define GMAC_NCR_MPE_Msk (_UINT32_(0x1) << GMAC_NCR_MPE_Pos) /* (GMAC_NCR) Management Port Enable Mask */ 60 #define GMAC_NCR_MPE(value) (GMAC_NCR_MPE_Msk & (_UINT32_(value) << GMAC_NCR_MPE_Pos)) /* Assignment of value for MPE in the GMAC_NCR register */ 61 #define GMAC_NCR_CLRSTAT_Pos _UINT32_(5) /* (GMAC_NCR) Clear Statistics Registers Position */ 62 #define GMAC_NCR_CLRSTAT_Msk (_UINT32_(0x1) << GMAC_NCR_CLRSTAT_Pos) /* (GMAC_NCR) Clear Statistics Registers Mask */ 63 #define GMAC_NCR_CLRSTAT(value) (GMAC_NCR_CLRSTAT_Msk & (_UINT32_(value) << GMAC_NCR_CLRSTAT_Pos)) /* Assignment of value for CLRSTAT in the GMAC_NCR register */ 64 #define GMAC_NCR_INCSTAT_Pos _UINT32_(6) /* (GMAC_NCR) Increment Statistics Registers Position */ 65 #define GMAC_NCR_INCSTAT_Msk (_UINT32_(0x1) << GMAC_NCR_INCSTAT_Pos) /* (GMAC_NCR) Increment Statistics Registers Mask */ 66 #define GMAC_NCR_INCSTAT(value) (GMAC_NCR_INCSTAT_Msk & (_UINT32_(value) << GMAC_NCR_INCSTAT_Pos)) /* Assignment of value for INCSTAT in the GMAC_NCR register */ 67 #define GMAC_NCR_WESTAT_Pos _UINT32_(7) /* (GMAC_NCR) Write Enable for Statistics Registers Position */ 68 #define GMAC_NCR_WESTAT_Msk (_UINT32_(0x1) << GMAC_NCR_WESTAT_Pos) /* (GMAC_NCR) Write Enable for Statistics Registers Mask */ 69 #define GMAC_NCR_WESTAT(value) (GMAC_NCR_WESTAT_Msk & (_UINT32_(value) << GMAC_NCR_WESTAT_Pos)) /* Assignment of value for WESTAT in the GMAC_NCR register */ 70 #define GMAC_NCR_BP_Pos _UINT32_(8) /* (GMAC_NCR) Back pressure Position */ 71 #define GMAC_NCR_BP_Msk (_UINT32_(0x1) << GMAC_NCR_BP_Pos) /* (GMAC_NCR) Back pressure Mask */ 72 #define GMAC_NCR_BP(value) (GMAC_NCR_BP_Msk & (_UINT32_(value) << GMAC_NCR_BP_Pos)) /* Assignment of value for BP in the GMAC_NCR register */ 73 #define GMAC_NCR_TSTART_Pos _UINT32_(9) /* (GMAC_NCR) Start Transmission Position */ 74 #define GMAC_NCR_TSTART_Msk (_UINT32_(0x1) << GMAC_NCR_TSTART_Pos) /* (GMAC_NCR) Start Transmission Mask */ 75 #define GMAC_NCR_TSTART(value) (GMAC_NCR_TSTART_Msk & (_UINT32_(value) << GMAC_NCR_TSTART_Pos)) /* Assignment of value for TSTART in the GMAC_NCR register */ 76 #define GMAC_NCR_THALT_Pos _UINT32_(10) /* (GMAC_NCR) Transmit Halt Position */ 77 #define GMAC_NCR_THALT_Msk (_UINT32_(0x1) << GMAC_NCR_THALT_Pos) /* (GMAC_NCR) Transmit Halt Mask */ 78 #define GMAC_NCR_THALT(value) (GMAC_NCR_THALT_Msk & (_UINT32_(value) << GMAC_NCR_THALT_Pos)) /* Assignment of value for THALT in the GMAC_NCR register */ 79 #define GMAC_NCR_TXPF_Pos _UINT32_(11) /* (GMAC_NCR) Transmit Pause Frame Position */ 80 #define GMAC_NCR_TXPF_Msk (_UINT32_(0x1) << GMAC_NCR_TXPF_Pos) /* (GMAC_NCR) Transmit Pause Frame Mask */ 81 #define GMAC_NCR_TXPF(value) (GMAC_NCR_TXPF_Msk & (_UINT32_(value) << GMAC_NCR_TXPF_Pos)) /* Assignment of value for TXPF in the GMAC_NCR register */ 82 #define GMAC_NCR_TXZQPF_Pos _UINT32_(12) /* (GMAC_NCR) Transmit Zero Quantum Pause Frame Position */ 83 #define GMAC_NCR_TXZQPF_Msk (_UINT32_(0x1) << GMAC_NCR_TXZQPF_Pos) /* (GMAC_NCR) Transmit Zero Quantum Pause Frame Mask */ 84 #define GMAC_NCR_TXZQPF(value) (GMAC_NCR_TXZQPF_Msk & (_UINT32_(value) << GMAC_NCR_TXZQPF_Pos)) /* Assignment of value for TXZQPF in the GMAC_NCR register */ 85 #define GMAC_NCR_SRTSM_Pos _UINT32_(15) /* (GMAC_NCR) Store Receive Time Stamp to Memory Position */ 86 #define GMAC_NCR_SRTSM_Msk (_UINT32_(0x1) << GMAC_NCR_SRTSM_Pos) /* (GMAC_NCR) Store Receive Time Stamp to Memory Mask */ 87 #define GMAC_NCR_SRTSM(value) (GMAC_NCR_SRTSM_Msk & (_UINT32_(value) << GMAC_NCR_SRTSM_Pos)) /* Assignment of value for SRTSM in the GMAC_NCR register */ 88 #define GMAC_NCR_ENPBPR_Pos _UINT32_(16) /* (GMAC_NCR) Enable PFC Priority-based Pause Reception Position */ 89 #define GMAC_NCR_ENPBPR_Msk (_UINT32_(0x1) << GMAC_NCR_ENPBPR_Pos) /* (GMAC_NCR) Enable PFC Priority-based Pause Reception Mask */ 90 #define GMAC_NCR_ENPBPR(value) (GMAC_NCR_ENPBPR_Msk & (_UINT32_(value) << GMAC_NCR_ENPBPR_Pos)) /* Assignment of value for ENPBPR in the GMAC_NCR register */ 91 #define GMAC_NCR_TXPBPF_Pos _UINT32_(17) /* (GMAC_NCR) Transmit PFC Priority-based Pause Frame Position */ 92 #define GMAC_NCR_TXPBPF_Msk (_UINT32_(0x1) << GMAC_NCR_TXPBPF_Pos) /* (GMAC_NCR) Transmit PFC Priority-based Pause Frame Mask */ 93 #define GMAC_NCR_TXPBPF(value) (GMAC_NCR_TXPBPF_Msk & (_UINT32_(value) << GMAC_NCR_TXPBPF_Pos)) /* Assignment of value for TXPBPF in the GMAC_NCR register */ 94 #define GMAC_NCR_FNP_Pos _UINT32_(18) /* (GMAC_NCR) Flush Next Packet Position */ 95 #define GMAC_NCR_FNP_Msk (_UINT32_(0x1) << GMAC_NCR_FNP_Pos) /* (GMAC_NCR) Flush Next Packet Mask */ 96 #define GMAC_NCR_FNP(value) (GMAC_NCR_FNP_Msk & (_UINT32_(value) << GMAC_NCR_FNP_Pos)) /* Assignment of value for FNP in the GMAC_NCR register */ 97 #define GMAC_NCR_LPI_Pos _UINT32_(19) /* (GMAC_NCR) Low Power Idle Enable Position */ 98 #define GMAC_NCR_LPI_Msk (_UINT32_(0x1) << GMAC_NCR_LPI_Pos) /* (GMAC_NCR) Low Power Idle Enable Mask */ 99 #define GMAC_NCR_LPI(value) (GMAC_NCR_LPI_Msk & (_UINT32_(value) << GMAC_NCR_LPI_Pos)) /* Assignment of value for LPI in the GMAC_NCR register */ 100 #define GMAC_NCR_Msk _UINT32_(0x000F9FFE) /* (GMAC_NCR) Register Mask */ 101 102 103 /* -------- GMAC_NCFGR : (GMAC Offset: 0x04) (R/W 32) Network Configuration Register -------- */ 104 #define GMAC_NCFGR_RESETVALUE _UINT32_(0x80000) /* (GMAC_NCFGR) Network Configuration Register Reset Value */ 105 106 #define GMAC_NCFGR_SPD_Pos _UINT32_(0) /* (GMAC_NCFGR) Speed Position */ 107 #define GMAC_NCFGR_SPD_Msk (_UINT32_(0x1) << GMAC_NCFGR_SPD_Pos) /* (GMAC_NCFGR) Speed Mask */ 108 #define GMAC_NCFGR_SPD(value) (GMAC_NCFGR_SPD_Msk & (_UINT32_(value) << GMAC_NCFGR_SPD_Pos)) /* Assignment of value for SPD in the GMAC_NCFGR register */ 109 #define GMAC_NCFGR_FD_Pos _UINT32_(1) /* (GMAC_NCFGR) Full Duplex Position */ 110 #define GMAC_NCFGR_FD_Msk (_UINT32_(0x1) << GMAC_NCFGR_FD_Pos) /* (GMAC_NCFGR) Full Duplex Mask */ 111 #define GMAC_NCFGR_FD(value) (GMAC_NCFGR_FD_Msk & (_UINT32_(value) << GMAC_NCFGR_FD_Pos)) /* Assignment of value for FD in the GMAC_NCFGR register */ 112 #define GMAC_NCFGR_DNVLAN_Pos _UINT32_(2) /* (GMAC_NCFGR) Discard Non-VLAN FRAMES Position */ 113 #define GMAC_NCFGR_DNVLAN_Msk (_UINT32_(0x1) << GMAC_NCFGR_DNVLAN_Pos) /* (GMAC_NCFGR) Discard Non-VLAN FRAMES Mask */ 114 #define GMAC_NCFGR_DNVLAN(value) (GMAC_NCFGR_DNVLAN_Msk & (_UINT32_(value) << GMAC_NCFGR_DNVLAN_Pos)) /* Assignment of value for DNVLAN in the GMAC_NCFGR register */ 115 #define GMAC_NCFGR_JFRAME_Pos _UINT32_(3) /* (GMAC_NCFGR) Jumbo Frame Size Position */ 116 #define GMAC_NCFGR_JFRAME_Msk (_UINT32_(0x1) << GMAC_NCFGR_JFRAME_Pos) /* (GMAC_NCFGR) Jumbo Frame Size Mask */ 117 #define GMAC_NCFGR_JFRAME(value) (GMAC_NCFGR_JFRAME_Msk & (_UINT32_(value) << GMAC_NCFGR_JFRAME_Pos)) /* Assignment of value for JFRAME in the GMAC_NCFGR register */ 118 #define GMAC_NCFGR_CAF_Pos _UINT32_(4) /* (GMAC_NCFGR) Copy All Frames Position */ 119 #define GMAC_NCFGR_CAF_Msk (_UINT32_(0x1) << GMAC_NCFGR_CAF_Pos) /* (GMAC_NCFGR) Copy All Frames Mask */ 120 #define GMAC_NCFGR_CAF(value) (GMAC_NCFGR_CAF_Msk & (_UINT32_(value) << GMAC_NCFGR_CAF_Pos)) /* Assignment of value for CAF in the GMAC_NCFGR register */ 121 #define GMAC_NCFGR_NBC_Pos _UINT32_(5) /* (GMAC_NCFGR) No Broadcast Position */ 122 #define GMAC_NCFGR_NBC_Msk (_UINT32_(0x1) << GMAC_NCFGR_NBC_Pos) /* (GMAC_NCFGR) No Broadcast Mask */ 123 #define GMAC_NCFGR_NBC(value) (GMAC_NCFGR_NBC_Msk & (_UINT32_(value) << GMAC_NCFGR_NBC_Pos)) /* Assignment of value for NBC in the GMAC_NCFGR register */ 124 #define GMAC_NCFGR_MTIHEN_Pos _UINT32_(6) /* (GMAC_NCFGR) Multicast Hash Enable Position */ 125 #define GMAC_NCFGR_MTIHEN_Msk (_UINT32_(0x1) << GMAC_NCFGR_MTIHEN_Pos) /* (GMAC_NCFGR) Multicast Hash Enable Mask */ 126 #define GMAC_NCFGR_MTIHEN(value) (GMAC_NCFGR_MTIHEN_Msk & (_UINT32_(value) << GMAC_NCFGR_MTIHEN_Pos)) /* Assignment of value for MTIHEN in the GMAC_NCFGR register */ 127 #define GMAC_NCFGR_UNIHEN_Pos _UINT32_(7) /* (GMAC_NCFGR) Unicast Hash Enable Position */ 128 #define GMAC_NCFGR_UNIHEN_Msk (_UINT32_(0x1) << GMAC_NCFGR_UNIHEN_Pos) /* (GMAC_NCFGR) Unicast Hash Enable Mask */ 129 #define GMAC_NCFGR_UNIHEN(value) (GMAC_NCFGR_UNIHEN_Msk & (_UINT32_(value) << GMAC_NCFGR_UNIHEN_Pos)) /* Assignment of value for UNIHEN in the GMAC_NCFGR register */ 130 #define GMAC_NCFGR_MAXFS_Pos _UINT32_(8) /* (GMAC_NCFGR) 1536 Maximum Frame Size Position */ 131 #define GMAC_NCFGR_MAXFS_Msk (_UINT32_(0x1) << GMAC_NCFGR_MAXFS_Pos) /* (GMAC_NCFGR) 1536 Maximum Frame Size Mask */ 132 #define GMAC_NCFGR_MAXFS(value) (GMAC_NCFGR_MAXFS_Msk & (_UINT32_(value) << GMAC_NCFGR_MAXFS_Pos)) /* Assignment of value for MAXFS in the GMAC_NCFGR register */ 133 #define GMAC_NCFGR_RTY_Pos _UINT32_(12) /* (GMAC_NCFGR) Retry Test Position */ 134 #define GMAC_NCFGR_RTY_Msk (_UINT32_(0x1) << GMAC_NCFGR_RTY_Pos) /* (GMAC_NCFGR) Retry Test Mask */ 135 #define GMAC_NCFGR_RTY(value) (GMAC_NCFGR_RTY_Msk & (_UINT32_(value) << GMAC_NCFGR_RTY_Pos)) /* Assignment of value for RTY in the GMAC_NCFGR register */ 136 #define GMAC_NCFGR_PEN_Pos _UINT32_(13) /* (GMAC_NCFGR) Pause Enable Position */ 137 #define GMAC_NCFGR_PEN_Msk (_UINT32_(0x1) << GMAC_NCFGR_PEN_Pos) /* (GMAC_NCFGR) Pause Enable Mask */ 138 #define GMAC_NCFGR_PEN(value) (GMAC_NCFGR_PEN_Msk & (_UINT32_(value) << GMAC_NCFGR_PEN_Pos)) /* Assignment of value for PEN in the GMAC_NCFGR register */ 139 #define GMAC_NCFGR_RXBUFO_Pos _UINT32_(14) /* (GMAC_NCFGR) Receive Buffer Offset Position */ 140 #define GMAC_NCFGR_RXBUFO_Msk (_UINT32_(0x3) << GMAC_NCFGR_RXBUFO_Pos) /* (GMAC_NCFGR) Receive Buffer Offset Mask */ 141 #define GMAC_NCFGR_RXBUFO(value) (GMAC_NCFGR_RXBUFO_Msk & (_UINT32_(value) << GMAC_NCFGR_RXBUFO_Pos)) /* Assignment of value for RXBUFO in the GMAC_NCFGR register */ 142 #define GMAC_NCFGR_LFERD_Pos _UINT32_(16) /* (GMAC_NCFGR) Length Field Error Frame Discard Position */ 143 #define GMAC_NCFGR_LFERD_Msk (_UINT32_(0x1) << GMAC_NCFGR_LFERD_Pos) /* (GMAC_NCFGR) Length Field Error Frame Discard Mask */ 144 #define GMAC_NCFGR_LFERD(value) (GMAC_NCFGR_LFERD_Msk & (_UINT32_(value) << GMAC_NCFGR_LFERD_Pos)) /* Assignment of value for LFERD in the GMAC_NCFGR register */ 145 #define GMAC_NCFGR_RFCS_Pos _UINT32_(17) /* (GMAC_NCFGR) Remove FCS Position */ 146 #define GMAC_NCFGR_RFCS_Msk (_UINT32_(0x1) << GMAC_NCFGR_RFCS_Pos) /* (GMAC_NCFGR) Remove FCS Mask */ 147 #define GMAC_NCFGR_RFCS(value) (GMAC_NCFGR_RFCS_Msk & (_UINT32_(value) << GMAC_NCFGR_RFCS_Pos)) /* Assignment of value for RFCS in the GMAC_NCFGR register */ 148 #define GMAC_NCFGR_CLK_Pos _UINT32_(18) /* (GMAC_NCFGR) MDC CLock Division Position */ 149 #define GMAC_NCFGR_CLK_Msk (_UINT32_(0x7) << GMAC_NCFGR_CLK_Pos) /* (GMAC_NCFGR) MDC CLock Division Mask */ 150 #define GMAC_NCFGR_CLK(value) (GMAC_NCFGR_CLK_Msk & (_UINT32_(value) << GMAC_NCFGR_CLK_Pos)) /* Assignment of value for CLK in the GMAC_NCFGR register */ 151 #define GMAC_NCFGR_CLK_MCK8_Val _UINT32_(0x0) /* (GMAC_NCFGR) MCK divided by 8 */ 152 #define GMAC_NCFGR_CLK_MCK16_Val _UINT32_(0x1) /* (GMAC_NCFGR) MCK divided by 16 */ 153 #define GMAC_NCFGR_CLK_MCK32_Val _UINT32_(0x2) /* (GMAC_NCFGR) MCK divided by 32 */ 154 #define GMAC_NCFGR_CLK_MCK48_Val _UINT32_(0x3) /* (GMAC_NCFGR) MCK divided by 48 */ 155 #define GMAC_NCFGR_CLK_MCK64_Val _UINT32_(0x4) /* (GMAC_NCFGR) MCK divided by 64 */ 156 #define GMAC_NCFGR_CLK_MCK96_Val _UINT32_(0x5) /* (GMAC_NCFGR) MCK divided by 96 */ 157 #define GMAC_NCFGR_CLK_MCK8 (GMAC_NCFGR_CLK_MCK8_Val << GMAC_NCFGR_CLK_Pos) /* (GMAC_NCFGR) MCK divided by 8 Position */ 158 #define GMAC_NCFGR_CLK_MCK16 (GMAC_NCFGR_CLK_MCK16_Val << GMAC_NCFGR_CLK_Pos) /* (GMAC_NCFGR) MCK divided by 16 Position */ 159 #define GMAC_NCFGR_CLK_MCK32 (GMAC_NCFGR_CLK_MCK32_Val << GMAC_NCFGR_CLK_Pos) /* (GMAC_NCFGR) MCK divided by 32 Position */ 160 #define GMAC_NCFGR_CLK_MCK48 (GMAC_NCFGR_CLK_MCK48_Val << GMAC_NCFGR_CLK_Pos) /* (GMAC_NCFGR) MCK divided by 48 Position */ 161 #define GMAC_NCFGR_CLK_MCK64 (GMAC_NCFGR_CLK_MCK64_Val << GMAC_NCFGR_CLK_Pos) /* (GMAC_NCFGR) MCK divided by 64 Position */ 162 #define GMAC_NCFGR_CLK_MCK96 (GMAC_NCFGR_CLK_MCK96_Val << GMAC_NCFGR_CLK_Pos) /* (GMAC_NCFGR) MCK divided by 96 Position */ 163 #define GMAC_NCFGR_DBW_Pos _UINT32_(21) /* (GMAC_NCFGR) Data Bus Width Position */ 164 #define GMAC_NCFGR_DBW_Msk (_UINT32_(0x3) << GMAC_NCFGR_DBW_Pos) /* (GMAC_NCFGR) Data Bus Width Mask */ 165 #define GMAC_NCFGR_DBW(value) (GMAC_NCFGR_DBW_Msk & (_UINT32_(value) << GMAC_NCFGR_DBW_Pos)) /* Assignment of value for DBW in the GMAC_NCFGR register */ 166 #define GMAC_NCFGR_DCPF_Pos _UINT32_(23) /* (GMAC_NCFGR) Disable Copy of Pause Frames Position */ 167 #define GMAC_NCFGR_DCPF_Msk (_UINT32_(0x1) << GMAC_NCFGR_DCPF_Pos) /* (GMAC_NCFGR) Disable Copy of Pause Frames Mask */ 168 #define GMAC_NCFGR_DCPF(value) (GMAC_NCFGR_DCPF_Msk & (_UINT32_(value) << GMAC_NCFGR_DCPF_Pos)) /* Assignment of value for DCPF in the GMAC_NCFGR register */ 169 #define GMAC_NCFGR_RXCOEN_Pos _UINT32_(24) /* (GMAC_NCFGR) Receive Checksum Offload Enable Position */ 170 #define GMAC_NCFGR_RXCOEN_Msk (_UINT32_(0x1) << GMAC_NCFGR_RXCOEN_Pos) /* (GMAC_NCFGR) Receive Checksum Offload Enable Mask */ 171 #define GMAC_NCFGR_RXCOEN(value) (GMAC_NCFGR_RXCOEN_Msk & (_UINT32_(value) << GMAC_NCFGR_RXCOEN_Pos)) /* Assignment of value for RXCOEN in the GMAC_NCFGR register */ 172 #define GMAC_NCFGR_EFRHD_Pos _UINT32_(25) /* (GMAC_NCFGR) Enable Frames Received in Half Duplex Position */ 173 #define GMAC_NCFGR_EFRHD_Msk (_UINT32_(0x1) << GMAC_NCFGR_EFRHD_Pos) /* (GMAC_NCFGR) Enable Frames Received in Half Duplex Mask */ 174 #define GMAC_NCFGR_EFRHD(value) (GMAC_NCFGR_EFRHD_Msk & (_UINT32_(value) << GMAC_NCFGR_EFRHD_Pos)) /* Assignment of value for EFRHD in the GMAC_NCFGR register */ 175 #define GMAC_NCFGR_IRXFCS_Pos _UINT32_(26) /* (GMAC_NCFGR) Ignore RX FCS Position */ 176 #define GMAC_NCFGR_IRXFCS_Msk (_UINT32_(0x1) << GMAC_NCFGR_IRXFCS_Pos) /* (GMAC_NCFGR) Ignore RX FCS Mask */ 177 #define GMAC_NCFGR_IRXFCS(value) (GMAC_NCFGR_IRXFCS_Msk & (_UINT32_(value) << GMAC_NCFGR_IRXFCS_Pos)) /* Assignment of value for IRXFCS in the GMAC_NCFGR register */ 178 #define GMAC_NCFGR_IPGSEN_Pos _UINT32_(28) /* (GMAC_NCFGR) IP Stretch Enable Position */ 179 #define GMAC_NCFGR_IPGSEN_Msk (_UINT32_(0x1) << GMAC_NCFGR_IPGSEN_Pos) /* (GMAC_NCFGR) IP Stretch Enable Mask */ 180 #define GMAC_NCFGR_IPGSEN(value) (GMAC_NCFGR_IPGSEN_Msk & (_UINT32_(value) << GMAC_NCFGR_IPGSEN_Pos)) /* Assignment of value for IPGSEN in the GMAC_NCFGR register */ 181 #define GMAC_NCFGR_RXBP_Pos _UINT32_(29) /* (GMAC_NCFGR) Receive Bad Preamble Position */ 182 #define GMAC_NCFGR_RXBP_Msk (_UINT32_(0x1) << GMAC_NCFGR_RXBP_Pos) /* (GMAC_NCFGR) Receive Bad Preamble Mask */ 183 #define GMAC_NCFGR_RXBP(value) (GMAC_NCFGR_RXBP_Msk & (_UINT32_(value) << GMAC_NCFGR_RXBP_Pos)) /* Assignment of value for RXBP in the GMAC_NCFGR register */ 184 #define GMAC_NCFGR_IRXER_Pos _UINT32_(30) /* (GMAC_NCFGR) Ignore IPG GRXER Position */ 185 #define GMAC_NCFGR_IRXER_Msk (_UINT32_(0x1) << GMAC_NCFGR_IRXER_Pos) /* (GMAC_NCFGR) Ignore IPG GRXER Mask */ 186 #define GMAC_NCFGR_IRXER(value) (GMAC_NCFGR_IRXER_Msk & (_UINT32_(value) << GMAC_NCFGR_IRXER_Pos)) /* Assignment of value for IRXER in the GMAC_NCFGR register */ 187 #define GMAC_NCFGR_Msk _UINT32_(0x77FFF1FF) /* (GMAC_NCFGR) Register Mask */ 188 189 190 /* -------- GMAC_NSR : (GMAC Offset: 0x08) ( R/ 32) Network Status Register -------- */ 191 #define GMAC_NSR_RESETVALUE _UINT32_(0x04) /* (GMAC_NSR) Network Status Register Reset Value */ 192 193 #define GMAC_NSR_MDIO_Pos _UINT32_(1) /* (GMAC_NSR) MDIO Input Status Position */ 194 #define GMAC_NSR_MDIO_Msk (_UINT32_(0x1) << GMAC_NSR_MDIO_Pos) /* (GMAC_NSR) MDIO Input Status Mask */ 195 #define GMAC_NSR_MDIO(value) (GMAC_NSR_MDIO_Msk & (_UINT32_(value) << GMAC_NSR_MDIO_Pos)) /* Assignment of value for MDIO in the GMAC_NSR register */ 196 #define GMAC_NSR_IDLE_Pos _UINT32_(2) /* (GMAC_NSR) PHY Management Logic Idle Position */ 197 #define GMAC_NSR_IDLE_Msk (_UINT32_(0x1) << GMAC_NSR_IDLE_Pos) /* (GMAC_NSR) PHY Management Logic Idle Mask */ 198 #define GMAC_NSR_IDLE(value) (GMAC_NSR_IDLE_Msk & (_UINT32_(value) << GMAC_NSR_IDLE_Pos)) /* Assignment of value for IDLE in the GMAC_NSR register */ 199 #define GMAC_NSR_Msk _UINT32_(0x00000006) /* (GMAC_NSR) Register Mask */ 200 201 202 /* -------- GMAC_UR : (GMAC Offset: 0x0C) (R/W 32) User Register -------- */ 203 #define GMAC_UR_RESETVALUE _UINT32_(0x00) /* (GMAC_UR) User Register Reset Value */ 204 205 #define GMAC_UR_MII_Pos _UINT32_(0) /* (GMAC_UR) MII Mode Position */ 206 #define GMAC_UR_MII_Msk (_UINT32_(0x1) << GMAC_UR_MII_Pos) /* (GMAC_UR) MII Mode Mask */ 207 #define GMAC_UR_MII(value) (GMAC_UR_MII_Msk & (_UINT32_(value) << GMAC_UR_MII_Pos)) /* Assignment of value for MII in the GMAC_UR register */ 208 #define GMAC_UR_Msk _UINT32_(0x00000001) /* (GMAC_UR) Register Mask */ 209 210 211 /* -------- GMAC_DCFGR : (GMAC Offset: 0x10) (R/W 32) DMA Configuration Register -------- */ 212 #define GMAC_DCFGR_RESETVALUE _UINT32_(0x20704) /* (GMAC_DCFGR) DMA Configuration Register Reset Value */ 213 214 #define GMAC_DCFGR_FBLDO_Pos _UINT32_(0) /* (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Position */ 215 #define GMAC_DCFGR_FBLDO_Msk (_UINT32_(0x1F) << GMAC_DCFGR_FBLDO_Pos) /* (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Mask */ 216 #define GMAC_DCFGR_FBLDO(value) (GMAC_DCFGR_FBLDO_Msk & (_UINT32_(value) << GMAC_DCFGR_FBLDO_Pos)) /* Assignment of value for FBLDO in the GMAC_DCFGR register */ 217 #define GMAC_DCFGR_FBLDO_SINGLE_Val _UINT32_(0x1) /* (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ 218 #define GMAC_DCFGR_FBLDO_INCR4_Val _UINT32_(0x4) /* (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ 219 #define GMAC_DCFGR_FBLDO_INCR8_Val _UINT32_(0x8) /* (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ 220 #define GMAC_DCFGR_FBLDO_INCR16_Val _UINT32_(0x10) /* (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ 221 #define GMAC_DCFGR_FBLDO_SINGLE (GMAC_DCFGR_FBLDO_SINGLE_Val << GMAC_DCFGR_FBLDO_Pos) /* (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts Position */ 222 #define GMAC_DCFGR_FBLDO_INCR4 (GMAC_DCFGR_FBLDO_INCR4_Val << GMAC_DCFGR_FBLDO_Pos) /* (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) Position */ 223 #define GMAC_DCFGR_FBLDO_INCR8 (GMAC_DCFGR_FBLDO_INCR8_Val << GMAC_DCFGR_FBLDO_Pos) /* (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts Position */ 224 #define GMAC_DCFGR_FBLDO_INCR16 (GMAC_DCFGR_FBLDO_INCR16_Val << GMAC_DCFGR_FBLDO_Pos) /* (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts Position */ 225 #define GMAC_DCFGR_ESMA_Pos _UINT32_(6) /* (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Position */ 226 #define GMAC_DCFGR_ESMA_Msk (_UINT32_(0x1) << GMAC_DCFGR_ESMA_Pos) /* (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Mask */ 227 #define GMAC_DCFGR_ESMA(value) (GMAC_DCFGR_ESMA_Msk & (_UINT32_(value) << GMAC_DCFGR_ESMA_Pos)) /* Assignment of value for ESMA in the GMAC_DCFGR register */ 228 #define GMAC_DCFGR_ESPA_Pos _UINT32_(7) /* (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Position */ 229 #define GMAC_DCFGR_ESPA_Msk (_UINT32_(0x1) << GMAC_DCFGR_ESPA_Pos) /* (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Mask */ 230 #define GMAC_DCFGR_ESPA(value) (GMAC_DCFGR_ESPA_Msk & (_UINT32_(value) << GMAC_DCFGR_ESPA_Pos)) /* Assignment of value for ESPA in the GMAC_DCFGR register */ 231 #define GMAC_DCFGR_RXBMS_Pos _UINT32_(8) /* (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Position */ 232 #define GMAC_DCFGR_RXBMS_Msk (_UINT32_(0x3) << GMAC_DCFGR_RXBMS_Pos) /* (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Mask */ 233 #define GMAC_DCFGR_RXBMS(value) (GMAC_DCFGR_RXBMS_Msk & (_UINT32_(value) << GMAC_DCFGR_RXBMS_Pos)) /* Assignment of value for RXBMS in the GMAC_DCFGR register */ 234 #define GMAC_DCFGR_RXBMS_EIGHTH_Val _UINT32_(0x0) /* (GMAC_DCFGR) RECEIVE_BUFFER_SIZE/8 Kbyte Memory Size */ 235 #define GMAC_DCFGR_RXBMS_QUARTER_Val _UINT32_(0x1) /* (GMAC_DCFGR) RECEIVE_BUFFER_SIZE/4 Kbytes Memory Size */ 236 #define GMAC_DCFGR_RXBMS_HALF_Val _UINT32_(0x2) /* (GMAC_DCFGR) RECEIVE_BUFFER_SIZE/2 Kbytes Memory Size */ 237 #define GMAC_DCFGR_RXBMS_FULL_Val _UINT32_(0x3) /* (GMAC_DCFGR) RECEIVE_BUFFER_SIZE Kbytes Memory Size */ 238 #define GMAC_DCFGR_RXBMS_EIGHTH (GMAC_DCFGR_RXBMS_EIGHTH_Val << GMAC_DCFGR_RXBMS_Pos) /* (GMAC_DCFGR) RECEIVE_BUFFER_SIZE/8 Kbyte Memory Size Position */ 239 #define GMAC_DCFGR_RXBMS_QUARTER (GMAC_DCFGR_RXBMS_QUARTER_Val << GMAC_DCFGR_RXBMS_Pos) /* (GMAC_DCFGR) RECEIVE_BUFFER_SIZE/4 Kbytes Memory Size Position */ 240 #define GMAC_DCFGR_RXBMS_HALF (GMAC_DCFGR_RXBMS_HALF_Val << GMAC_DCFGR_RXBMS_Pos) /* (GMAC_DCFGR) RECEIVE_BUFFER_SIZE/2 Kbytes Memory Size Position */ 241 #define GMAC_DCFGR_RXBMS_FULL (GMAC_DCFGR_RXBMS_FULL_Val << GMAC_DCFGR_RXBMS_Pos) /* (GMAC_DCFGR) RECEIVE_BUFFER_SIZE Kbytes Memory Size Position */ 242 #define GMAC_DCFGR_TXPBMS_Pos _UINT32_(10) /* (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Position */ 243 #define GMAC_DCFGR_TXPBMS_Msk (_UINT32_(0x1) << GMAC_DCFGR_TXPBMS_Pos) /* (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Mask */ 244 #define GMAC_DCFGR_TXPBMS(value) (GMAC_DCFGR_TXPBMS_Msk & (_UINT32_(value) << GMAC_DCFGR_TXPBMS_Pos)) /* Assignment of value for TXPBMS in the GMAC_DCFGR register */ 245 #define GMAC_DCFGR_TXCOEN_Pos _UINT32_(11) /* (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Position */ 246 #define GMAC_DCFGR_TXCOEN_Msk (_UINT32_(0x1) << GMAC_DCFGR_TXCOEN_Pos) /* (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Mask */ 247 #define GMAC_DCFGR_TXCOEN(value) (GMAC_DCFGR_TXCOEN_Msk & (_UINT32_(value) << GMAC_DCFGR_TXCOEN_Pos)) /* Assignment of value for TXCOEN in the GMAC_DCFGR register */ 248 #define GMAC_DCFGR_DRBS_Pos _UINT32_(16) /* (GMAC_DCFGR) DMA Receive Buffer Size Position */ 249 #define GMAC_DCFGR_DRBS_Msk (_UINT32_(0xFF) << GMAC_DCFGR_DRBS_Pos) /* (GMAC_DCFGR) DMA Receive Buffer Size Mask */ 250 #define GMAC_DCFGR_DRBS(value) (GMAC_DCFGR_DRBS_Msk & (_UINT32_(value) << GMAC_DCFGR_DRBS_Pos)) /* Assignment of value for DRBS in the GMAC_DCFGR register */ 251 #define GMAC_DCFGR_DDRP_Pos _UINT32_(24) /* (GMAC_DCFGR) DMA Discard Receive Packets Position */ 252 #define GMAC_DCFGR_DDRP_Msk (_UINT32_(0x1) << GMAC_DCFGR_DDRP_Pos) /* (GMAC_DCFGR) DMA Discard Receive Packets Mask */ 253 #define GMAC_DCFGR_DDRP(value) (GMAC_DCFGR_DDRP_Msk & (_UINT32_(value) << GMAC_DCFGR_DDRP_Pos)) /* Assignment of value for DDRP in the GMAC_DCFGR register */ 254 #define GMAC_DCFGR_Msk _UINT32_(0x01FF0FDF) /* (GMAC_DCFGR) Register Mask */ 255 256 257 /* -------- GMAC_TSR : (GMAC Offset: 0x14) (R/W 32) Transmit Status Register -------- */ 258 #define GMAC_TSR_RESETVALUE _UINT32_(0x00) /* (GMAC_TSR) Transmit Status Register Reset Value */ 259 260 #define GMAC_TSR_UBR_Pos _UINT32_(0) /* (GMAC_TSR) Used Bit Read Position */ 261 #define GMAC_TSR_UBR_Msk (_UINT32_(0x1) << GMAC_TSR_UBR_Pos) /* (GMAC_TSR) Used Bit Read Mask */ 262 #define GMAC_TSR_UBR(value) (GMAC_TSR_UBR_Msk & (_UINT32_(value) << GMAC_TSR_UBR_Pos)) /* Assignment of value for UBR in the GMAC_TSR register */ 263 #define GMAC_TSR_COL_Pos _UINT32_(1) /* (GMAC_TSR) Collision Occurred Position */ 264 #define GMAC_TSR_COL_Msk (_UINT32_(0x1) << GMAC_TSR_COL_Pos) /* (GMAC_TSR) Collision Occurred Mask */ 265 #define GMAC_TSR_COL(value) (GMAC_TSR_COL_Msk & (_UINT32_(value) << GMAC_TSR_COL_Pos)) /* Assignment of value for COL in the GMAC_TSR register */ 266 #define GMAC_TSR_RLE_Pos _UINT32_(2) /* (GMAC_TSR) Retry Limit Exceeded Position */ 267 #define GMAC_TSR_RLE_Msk (_UINT32_(0x1) << GMAC_TSR_RLE_Pos) /* (GMAC_TSR) Retry Limit Exceeded Mask */ 268 #define GMAC_TSR_RLE(value) (GMAC_TSR_RLE_Msk & (_UINT32_(value) << GMAC_TSR_RLE_Pos)) /* Assignment of value for RLE in the GMAC_TSR register */ 269 #define GMAC_TSR_TXGO_Pos _UINT32_(3) /* (GMAC_TSR) Transmit Go Position */ 270 #define GMAC_TSR_TXGO_Msk (_UINT32_(0x1) << GMAC_TSR_TXGO_Pos) /* (GMAC_TSR) Transmit Go Mask */ 271 #define GMAC_TSR_TXGO(value) (GMAC_TSR_TXGO_Msk & (_UINT32_(value) << GMAC_TSR_TXGO_Pos)) /* Assignment of value for TXGO in the GMAC_TSR register */ 272 #define GMAC_TSR_TFC_Pos _UINT32_(4) /* (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Position */ 273 #define GMAC_TSR_TFC_Msk (_UINT32_(0x1) << GMAC_TSR_TFC_Pos) /* (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Mask */ 274 #define GMAC_TSR_TFC(value) (GMAC_TSR_TFC_Msk & (_UINT32_(value) << GMAC_TSR_TFC_Pos)) /* Assignment of value for TFC in the GMAC_TSR register */ 275 #define GMAC_TSR_TXCOMP_Pos _UINT32_(5) /* (GMAC_TSR) Transmit Complete Position */ 276 #define GMAC_TSR_TXCOMP_Msk (_UINT32_(0x1) << GMAC_TSR_TXCOMP_Pos) /* (GMAC_TSR) Transmit Complete Mask */ 277 #define GMAC_TSR_TXCOMP(value) (GMAC_TSR_TXCOMP_Msk & (_UINT32_(value) << GMAC_TSR_TXCOMP_Pos)) /* Assignment of value for TXCOMP in the GMAC_TSR register */ 278 #define GMAC_TSR_UND_Pos _UINT32_(6) /* (GMAC_TSR) Transmit Underrun Position */ 279 #define GMAC_TSR_UND_Msk (_UINT32_(0x1) << GMAC_TSR_UND_Pos) /* (GMAC_TSR) Transmit Underrun Mask */ 280 #define GMAC_TSR_UND(value) (GMAC_TSR_UND_Msk & (_UINT32_(value) << GMAC_TSR_UND_Pos)) /* Assignment of value for UND in the GMAC_TSR register */ 281 #define GMAC_TSR_HRESP_Pos _UINT32_(8) /* (GMAC_TSR) HRESP Not OK Position */ 282 #define GMAC_TSR_HRESP_Msk (_UINT32_(0x1) << GMAC_TSR_HRESP_Pos) /* (GMAC_TSR) HRESP Not OK Mask */ 283 #define GMAC_TSR_HRESP(value) (GMAC_TSR_HRESP_Msk & (_UINT32_(value) << GMAC_TSR_HRESP_Pos)) /* Assignment of value for HRESP in the GMAC_TSR register */ 284 #define GMAC_TSR_Msk _UINT32_(0x0000017F) /* (GMAC_TSR) Register Mask */ 285 286 287 /* -------- GMAC_RBQB : (GMAC Offset: 0x18) (R/W 32) Receive Buffer Queue Base Address -------- */ 288 #define GMAC_RBQB_RESETVALUE _UINT32_(0x00) /* (GMAC_RBQB) Receive Buffer Queue Base Address Reset Value */ 289 290 #define GMAC_RBQB_ADDR_Pos _UINT32_(2) /* (GMAC_RBQB) Receive Buffer Queue Base Address Position */ 291 #define GMAC_RBQB_ADDR_Msk (_UINT32_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos) /* (GMAC_RBQB) Receive Buffer Queue Base Address Mask */ 292 #define GMAC_RBQB_ADDR(value) (GMAC_RBQB_ADDR_Msk & (_UINT32_(value) << GMAC_RBQB_ADDR_Pos)) /* Assignment of value for ADDR in the GMAC_RBQB register */ 293 #define GMAC_RBQB_Msk _UINT32_(0xFFFFFFFC) /* (GMAC_RBQB) Register Mask */ 294 295 296 /* -------- GMAC_TBQB : (GMAC Offset: 0x1C) (R/W 32) Transmit Buffer Queue Base Address -------- */ 297 #define GMAC_TBQB_RESETVALUE _UINT32_(0x00) /* (GMAC_TBQB) Transmit Buffer Queue Base Address Reset Value */ 298 299 #define GMAC_TBQB_ADDR_Pos _UINT32_(2) /* (GMAC_TBQB) Transmit Buffer Queue Base Address Position */ 300 #define GMAC_TBQB_ADDR_Msk (_UINT32_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos) /* (GMAC_TBQB) Transmit Buffer Queue Base Address Mask */ 301 #define GMAC_TBQB_ADDR(value) (GMAC_TBQB_ADDR_Msk & (_UINT32_(value) << GMAC_TBQB_ADDR_Pos)) /* Assignment of value for ADDR in the GMAC_TBQB register */ 302 #define GMAC_TBQB_Msk _UINT32_(0xFFFFFFFC) /* (GMAC_TBQB) Register Mask */ 303 304 305 /* -------- GMAC_RSR : (GMAC Offset: 0x20) (R/W 32) Receive Status Register -------- */ 306 #define GMAC_RSR_RESETVALUE _UINT32_(0x00) /* (GMAC_RSR) Receive Status Register Reset Value */ 307 308 #define GMAC_RSR_BNA_Pos _UINT32_(0) /* (GMAC_RSR) Buffer Not Available Position */ 309 #define GMAC_RSR_BNA_Msk (_UINT32_(0x1) << GMAC_RSR_BNA_Pos) /* (GMAC_RSR) Buffer Not Available Mask */ 310 #define GMAC_RSR_BNA(value) (GMAC_RSR_BNA_Msk & (_UINT32_(value) << GMAC_RSR_BNA_Pos)) /* Assignment of value for BNA in the GMAC_RSR register */ 311 #define GMAC_RSR_REC_Pos _UINT32_(1) /* (GMAC_RSR) Frame Received Position */ 312 #define GMAC_RSR_REC_Msk (_UINT32_(0x1) << GMAC_RSR_REC_Pos) /* (GMAC_RSR) Frame Received Mask */ 313 #define GMAC_RSR_REC(value) (GMAC_RSR_REC_Msk & (_UINT32_(value) << GMAC_RSR_REC_Pos)) /* Assignment of value for REC in the GMAC_RSR register */ 314 #define GMAC_RSR_RXOVR_Pos _UINT32_(2) /* (GMAC_RSR) Receive Overrun Position */ 315 #define GMAC_RSR_RXOVR_Msk (_UINT32_(0x1) << GMAC_RSR_RXOVR_Pos) /* (GMAC_RSR) Receive Overrun Mask */ 316 #define GMAC_RSR_RXOVR(value) (GMAC_RSR_RXOVR_Msk & (_UINT32_(value) << GMAC_RSR_RXOVR_Pos)) /* Assignment of value for RXOVR in the GMAC_RSR register */ 317 #define GMAC_RSR_HNO_Pos _UINT32_(3) /* (GMAC_RSR) HRESP Not OK Position */ 318 #define GMAC_RSR_HNO_Msk (_UINT32_(0x1) << GMAC_RSR_HNO_Pos) /* (GMAC_RSR) HRESP Not OK Mask */ 319 #define GMAC_RSR_HNO(value) (GMAC_RSR_HNO_Msk & (_UINT32_(value) << GMAC_RSR_HNO_Pos)) /* Assignment of value for HNO in the GMAC_RSR register */ 320 #define GMAC_RSR_Msk _UINT32_(0x0000000F) /* (GMAC_RSR) Register Mask */ 321 322 323 /* -------- GMAC_ISR : (GMAC Offset: 0x24) (R/W 32) Interrupt Status Register -------- */ 324 #define GMAC_ISR_RESETVALUE _UINT32_(0x00) /* (GMAC_ISR) Interrupt Status Register Reset Value */ 325 326 #define GMAC_ISR_MFS_Pos _UINT32_(0) /* (GMAC_ISR) Management Frame Sent Position */ 327 #define GMAC_ISR_MFS_Msk (_UINT32_(0x1) << GMAC_ISR_MFS_Pos) /* (GMAC_ISR) Management Frame Sent Mask */ 328 #define GMAC_ISR_MFS(value) (GMAC_ISR_MFS_Msk & (_UINT32_(value) << GMAC_ISR_MFS_Pos)) /* Assignment of value for MFS in the GMAC_ISR register */ 329 #define GMAC_ISR_RCOMP_Pos _UINT32_(1) /* (GMAC_ISR) Receive Complete Position */ 330 #define GMAC_ISR_RCOMP_Msk (_UINT32_(0x1) << GMAC_ISR_RCOMP_Pos) /* (GMAC_ISR) Receive Complete Mask */ 331 #define GMAC_ISR_RCOMP(value) (GMAC_ISR_RCOMP_Msk & (_UINT32_(value) << GMAC_ISR_RCOMP_Pos)) /* Assignment of value for RCOMP in the GMAC_ISR register */ 332 #define GMAC_ISR_RXUBR_Pos _UINT32_(2) /* (GMAC_ISR) RX Used Bit Read Position */ 333 #define GMAC_ISR_RXUBR_Msk (_UINT32_(0x1) << GMAC_ISR_RXUBR_Pos) /* (GMAC_ISR) RX Used Bit Read Mask */ 334 #define GMAC_ISR_RXUBR(value) (GMAC_ISR_RXUBR_Msk & (_UINT32_(value) << GMAC_ISR_RXUBR_Pos)) /* Assignment of value for RXUBR in the GMAC_ISR register */ 335 #define GMAC_ISR_TXUBR_Pos _UINT32_(3) /* (GMAC_ISR) TX Used Bit Read Position */ 336 #define GMAC_ISR_TXUBR_Msk (_UINT32_(0x1) << GMAC_ISR_TXUBR_Pos) /* (GMAC_ISR) TX Used Bit Read Mask */ 337 #define GMAC_ISR_TXUBR(value) (GMAC_ISR_TXUBR_Msk & (_UINT32_(value) << GMAC_ISR_TXUBR_Pos)) /* Assignment of value for TXUBR in the GMAC_ISR register */ 338 #define GMAC_ISR_TUR_Pos _UINT32_(4) /* (GMAC_ISR) Transmit Underrun Position */ 339 #define GMAC_ISR_TUR_Msk (_UINT32_(0x1) << GMAC_ISR_TUR_Pos) /* (GMAC_ISR) Transmit Underrun Mask */ 340 #define GMAC_ISR_TUR(value) (GMAC_ISR_TUR_Msk & (_UINT32_(value) << GMAC_ISR_TUR_Pos)) /* Assignment of value for TUR in the GMAC_ISR register */ 341 #define GMAC_ISR_RLEX_Pos _UINT32_(5) /* (GMAC_ISR) Retry Limit Exceeded Position */ 342 #define GMAC_ISR_RLEX_Msk (_UINT32_(0x1) << GMAC_ISR_RLEX_Pos) /* (GMAC_ISR) Retry Limit Exceeded Mask */ 343 #define GMAC_ISR_RLEX(value) (GMAC_ISR_RLEX_Msk & (_UINT32_(value) << GMAC_ISR_RLEX_Pos)) /* Assignment of value for RLEX in the GMAC_ISR register */ 344 #define GMAC_ISR_TFC_Pos _UINT32_(6) /* (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Position */ 345 #define GMAC_ISR_TFC_Msk (_UINT32_(0x1) << GMAC_ISR_TFC_Pos) /* (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Mask */ 346 #define GMAC_ISR_TFC(value) (GMAC_ISR_TFC_Msk & (_UINT32_(value) << GMAC_ISR_TFC_Pos)) /* Assignment of value for TFC in the GMAC_ISR register */ 347 #define GMAC_ISR_TCOMP_Pos _UINT32_(7) /* (GMAC_ISR) Transmit Complete Position */ 348 #define GMAC_ISR_TCOMP_Msk (_UINT32_(0x1) << GMAC_ISR_TCOMP_Pos) /* (GMAC_ISR) Transmit Complete Mask */ 349 #define GMAC_ISR_TCOMP(value) (GMAC_ISR_TCOMP_Msk & (_UINT32_(value) << GMAC_ISR_TCOMP_Pos)) /* Assignment of value for TCOMP in the GMAC_ISR register */ 350 #define GMAC_ISR_ROVR_Pos _UINT32_(10) /* (GMAC_ISR) Receive Overrun Position */ 351 #define GMAC_ISR_ROVR_Msk (_UINT32_(0x1) << GMAC_ISR_ROVR_Pos) /* (GMAC_ISR) Receive Overrun Mask */ 352 #define GMAC_ISR_ROVR(value) (GMAC_ISR_ROVR_Msk & (_UINT32_(value) << GMAC_ISR_ROVR_Pos)) /* Assignment of value for ROVR in the GMAC_ISR register */ 353 #define GMAC_ISR_HRESP_Pos _UINT32_(11) /* (GMAC_ISR) HRESP Not OK Position */ 354 #define GMAC_ISR_HRESP_Msk (_UINT32_(0x1) << GMAC_ISR_HRESP_Pos) /* (GMAC_ISR) HRESP Not OK Mask */ 355 #define GMAC_ISR_HRESP(value) (GMAC_ISR_HRESP_Msk & (_UINT32_(value) << GMAC_ISR_HRESP_Pos)) /* Assignment of value for HRESP in the GMAC_ISR register */ 356 #define GMAC_ISR_PFNZ_Pos _UINT32_(12) /* (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Position */ 357 #define GMAC_ISR_PFNZ_Msk (_UINT32_(0x1) << GMAC_ISR_PFNZ_Pos) /* (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Mask */ 358 #define GMAC_ISR_PFNZ(value) (GMAC_ISR_PFNZ_Msk & (_UINT32_(value) << GMAC_ISR_PFNZ_Pos)) /* Assignment of value for PFNZ in the GMAC_ISR register */ 359 #define GMAC_ISR_PTZ_Pos _UINT32_(13) /* (GMAC_ISR) Pause Time Zero Position */ 360 #define GMAC_ISR_PTZ_Msk (_UINT32_(0x1) << GMAC_ISR_PTZ_Pos) /* (GMAC_ISR) Pause Time Zero Mask */ 361 #define GMAC_ISR_PTZ(value) (GMAC_ISR_PTZ_Msk & (_UINT32_(value) << GMAC_ISR_PTZ_Pos)) /* Assignment of value for PTZ in the GMAC_ISR register */ 362 #define GMAC_ISR_PFTR_Pos _UINT32_(14) /* (GMAC_ISR) Pause Frame Transmitted Position */ 363 #define GMAC_ISR_PFTR_Msk (_UINT32_(0x1) << GMAC_ISR_PFTR_Pos) /* (GMAC_ISR) Pause Frame Transmitted Mask */ 364 #define GMAC_ISR_PFTR(value) (GMAC_ISR_PFTR_Msk & (_UINT32_(value) << GMAC_ISR_PFTR_Pos)) /* Assignment of value for PFTR in the GMAC_ISR register */ 365 #define GMAC_ISR_DRQFR_Pos _UINT32_(18) /* (GMAC_ISR) PTP Delay Request Frame Received Position */ 366 #define GMAC_ISR_DRQFR_Msk (_UINT32_(0x1) << GMAC_ISR_DRQFR_Pos) /* (GMAC_ISR) PTP Delay Request Frame Received Mask */ 367 #define GMAC_ISR_DRQFR(value) (GMAC_ISR_DRQFR_Msk & (_UINT32_(value) << GMAC_ISR_DRQFR_Pos)) /* Assignment of value for DRQFR in the GMAC_ISR register */ 368 #define GMAC_ISR_SFR_Pos _UINT32_(19) /* (GMAC_ISR) PTP Sync Frame Received Position */ 369 #define GMAC_ISR_SFR_Msk (_UINT32_(0x1) << GMAC_ISR_SFR_Pos) /* (GMAC_ISR) PTP Sync Frame Received Mask */ 370 #define GMAC_ISR_SFR(value) (GMAC_ISR_SFR_Msk & (_UINT32_(value) << GMAC_ISR_SFR_Pos)) /* Assignment of value for SFR in the GMAC_ISR register */ 371 #define GMAC_ISR_DRQFT_Pos _UINT32_(20) /* (GMAC_ISR) PTP Delay Request Frame Transmitted Position */ 372 #define GMAC_ISR_DRQFT_Msk (_UINT32_(0x1) << GMAC_ISR_DRQFT_Pos) /* (GMAC_ISR) PTP Delay Request Frame Transmitted Mask */ 373 #define GMAC_ISR_DRQFT(value) (GMAC_ISR_DRQFT_Msk & (_UINT32_(value) << GMAC_ISR_DRQFT_Pos)) /* Assignment of value for DRQFT in the GMAC_ISR register */ 374 #define GMAC_ISR_SFT_Pos _UINT32_(21) /* (GMAC_ISR) PTP Sync Frame Transmitted Position */ 375 #define GMAC_ISR_SFT_Msk (_UINT32_(0x1) << GMAC_ISR_SFT_Pos) /* (GMAC_ISR) PTP Sync Frame Transmitted Mask */ 376 #define GMAC_ISR_SFT(value) (GMAC_ISR_SFT_Msk & (_UINT32_(value) << GMAC_ISR_SFT_Pos)) /* Assignment of value for SFT in the GMAC_ISR register */ 377 #define GMAC_ISR_PDRQFR_Pos _UINT32_(22) /* (GMAC_ISR) PDelay Request Frame Received Position */ 378 #define GMAC_ISR_PDRQFR_Msk (_UINT32_(0x1) << GMAC_ISR_PDRQFR_Pos) /* (GMAC_ISR) PDelay Request Frame Received Mask */ 379 #define GMAC_ISR_PDRQFR(value) (GMAC_ISR_PDRQFR_Msk & (_UINT32_(value) << GMAC_ISR_PDRQFR_Pos)) /* Assignment of value for PDRQFR in the GMAC_ISR register */ 380 #define GMAC_ISR_PDRSFR_Pos _UINT32_(23) /* (GMAC_ISR) PDelay Response Frame Received Position */ 381 #define GMAC_ISR_PDRSFR_Msk (_UINT32_(0x1) << GMAC_ISR_PDRSFR_Pos) /* (GMAC_ISR) PDelay Response Frame Received Mask */ 382 #define GMAC_ISR_PDRSFR(value) (GMAC_ISR_PDRSFR_Msk & (_UINT32_(value) << GMAC_ISR_PDRSFR_Pos)) /* Assignment of value for PDRSFR in the GMAC_ISR register */ 383 #define GMAC_ISR_PDRQFT_Pos _UINT32_(24) /* (GMAC_ISR) PDelay Request Frame Transmitted Position */ 384 #define GMAC_ISR_PDRQFT_Msk (_UINT32_(0x1) << GMAC_ISR_PDRQFT_Pos) /* (GMAC_ISR) PDelay Request Frame Transmitted Mask */ 385 #define GMAC_ISR_PDRQFT(value) (GMAC_ISR_PDRQFT_Msk & (_UINT32_(value) << GMAC_ISR_PDRQFT_Pos)) /* Assignment of value for PDRQFT in the GMAC_ISR register */ 386 #define GMAC_ISR_PDRSFT_Pos _UINT32_(25) /* (GMAC_ISR) PDelay Response Frame Transmitted Position */ 387 #define GMAC_ISR_PDRSFT_Msk (_UINT32_(0x1) << GMAC_ISR_PDRSFT_Pos) /* (GMAC_ISR) PDelay Response Frame Transmitted Mask */ 388 #define GMAC_ISR_PDRSFT(value) (GMAC_ISR_PDRSFT_Msk & (_UINT32_(value) << GMAC_ISR_PDRSFT_Pos)) /* Assignment of value for PDRSFT in the GMAC_ISR register */ 389 #define GMAC_ISR_SRI_Pos _UINT32_(26) /* (GMAC_ISR) TSU Seconds Register Increment Position */ 390 #define GMAC_ISR_SRI_Msk (_UINT32_(0x1) << GMAC_ISR_SRI_Pos) /* (GMAC_ISR) TSU Seconds Register Increment Mask */ 391 #define GMAC_ISR_SRI(value) (GMAC_ISR_SRI_Msk & (_UINT32_(value) << GMAC_ISR_SRI_Pos)) /* Assignment of value for SRI in the GMAC_ISR register */ 392 #define GMAC_ISR_RXLPISBC_Pos _UINT32_(27) /* (GMAC_ISR) Enable RX LPI Indication Position */ 393 #define GMAC_ISR_RXLPISBC_Msk (_UINT32_(0x1) << GMAC_ISR_RXLPISBC_Pos) /* (GMAC_ISR) Enable RX LPI Indication Mask */ 394 #define GMAC_ISR_RXLPISBC(value) (GMAC_ISR_RXLPISBC_Msk & (_UINT32_(value) << GMAC_ISR_RXLPISBC_Pos)) /* Assignment of value for RXLPISBC in the GMAC_ISR register */ 395 #define GMAC_ISR_WOL_Pos _UINT32_(28) /* (GMAC_ISR) Wake On LAN Position */ 396 #define GMAC_ISR_WOL_Msk (_UINT32_(0x1) << GMAC_ISR_WOL_Pos) /* (GMAC_ISR) Wake On LAN Mask */ 397 #define GMAC_ISR_WOL(value) (GMAC_ISR_WOL_Msk & (_UINT32_(value) << GMAC_ISR_WOL_Pos)) /* Assignment of value for WOL in the GMAC_ISR register */ 398 #define GMAC_ISR_TSUCMP_Pos _UINT32_(29) /* (GMAC_ISR) Tsu timer comparison Position */ 399 #define GMAC_ISR_TSUCMP_Msk (_UINT32_(0x1) << GMAC_ISR_TSUCMP_Pos) /* (GMAC_ISR) Tsu timer comparison Mask */ 400 #define GMAC_ISR_TSUCMP(value) (GMAC_ISR_TSUCMP_Msk & (_UINT32_(value) << GMAC_ISR_TSUCMP_Pos)) /* Assignment of value for TSUCMP in the GMAC_ISR register */ 401 #define GMAC_ISR_Msk _UINT32_(0x3FFC7CFF) /* (GMAC_ISR) Register Mask */ 402 403 404 /* -------- GMAC_IER : (GMAC Offset: 0x28) ( /W 32) Interrupt Enable Register -------- */ 405 #define GMAC_IER_MFS_Pos _UINT32_(0) /* (GMAC_IER) Management Frame Sent Position */ 406 #define GMAC_IER_MFS_Msk (_UINT32_(0x1) << GMAC_IER_MFS_Pos) /* (GMAC_IER) Management Frame Sent Mask */ 407 #define GMAC_IER_MFS(value) (GMAC_IER_MFS_Msk & (_UINT32_(value) << GMAC_IER_MFS_Pos)) /* Assignment of value for MFS in the GMAC_IER register */ 408 #define GMAC_IER_RCOMP_Pos _UINT32_(1) /* (GMAC_IER) Receive Complete Position */ 409 #define GMAC_IER_RCOMP_Msk (_UINT32_(0x1) << GMAC_IER_RCOMP_Pos) /* (GMAC_IER) Receive Complete Mask */ 410 #define GMAC_IER_RCOMP(value) (GMAC_IER_RCOMP_Msk & (_UINT32_(value) << GMAC_IER_RCOMP_Pos)) /* Assignment of value for RCOMP in the GMAC_IER register */ 411 #define GMAC_IER_RXUBR_Pos _UINT32_(2) /* (GMAC_IER) RX Used Bit Read Position */ 412 #define GMAC_IER_RXUBR_Msk (_UINT32_(0x1) << GMAC_IER_RXUBR_Pos) /* (GMAC_IER) RX Used Bit Read Mask */ 413 #define GMAC_IER_RXUBR(value) (GMAC_IER_RXUBR_Msk & (_UINT32_(value) << GMAC_IER_RXUBR_Pos)) /* Assignment of value for RXUBR in the GMAC_IER register */ 414 #define GMAC_IER_TXUBR_Pos _UINT32_(3) /* (GMAC_IER) TX Used Bit Read Position */ 415 #define GMAC_IER_TXUBR_Msk (_UINT32_(0x1) << GMAC_IER_TXUBR_Pos) /* (GMAC_IER) TX Used Bit Read Mask */ 416 #define GMAC_IER_TXUBR(value) (GMAC_IER_TXUBR_Msk & (_UINT32_(value) << GMAC_IER_TXUBR_Pos)) /* Assignment of value for TXUBR in the GMAC_IER register */ 417 #define GMAC_IER_TUR_Pos _UINT32_(4) /* (GMAC_IER) Transmit Underrun Position */ 418 #define GMAC_IER_TUR_Msk (_UINT32_(0x1) << GMAC_IER_TUR_Pos) /* (GMAC_IER) Transmit Underrun Mask */ 419 #define GMAC_IER_TUR(value) (GMAC_IER_TUR_Msk & (_UINT32_(value) << GMAC_IER_TUR_Pos)) /* Assignment of value for TUR in the GMAC_IER register */ 420 #define GMAC_IER_RLEX_Pos _UINT32_(5) /* (GMAC_IER) Retry Limit Exceeded or Late Collision Position */ 421 #define GMAC_IER_RLEX_Msk (_UINT32_(0x1) << GMAC_IER_RLEX_Pos) /* (GMAC_IER) Retry Limit Exceeded or Late Collision Mask */ 422 #define GMAC_IER_RLEX(value) (GMAC_IER_RLEX_Msk & (_UINT32_(value) << GMAC_IER_RLEX_Pos)) /* Assignment of value for RLEX in the GMAC_IER register */ 423 #define GMAC_IER_TFC_Pos _UINT32_(6) /* (GMAC_IER) Transmit Frame Corruption Due to AHB Error Position */ 424 #define GMAC_IER_TFC_Msk (_UINT32_(0x1) << GMAC_IER_TFC_Pos) /* (GMAC_IER) Transmit Frame Corruption Due to AHB Error Mask */ 425 #define GMAC_IER_TFC(value) (GMAC_IER_TFC_Msk & (_UINT32_(value) << GMAC_IER_TFC_Pos)) /* Assignment of value for TFC in the GMAC_IER register */ 426 #define GMAC_IER_TCOMP_Pos _UINT32_(7) /* (GMAC_IER) Transmit Complete Position */ 427 #define GMAC_IER_TCOMP_Msk (_UINT32_(0x1) << GMAC_IER_TCOMP_Pos) /* (GMAC_IER) Transmit Complete Mask */ 428 #define GMAC_IER_TCOMP(value) (GMAC_IER_TCOMP_Msk & (_UINT32_(value) << GMAC_IER_TCOMP_Pos)) /* Assignment of value for TCOMP in the GMAC_IER register */ 429 #define GMAC_IER_ROVR_Pos _UINT32_(10) /* (GMAC_IER) Receive Overrun Position */ 430 #define GMAC_IER_ROVR_Msk (_UINT32_(0x1) << GMAC_IER_ROVR_Pos) /* (GMAC_IER) Receive Overrun Mask */ 431 #define GMAC_IER_ROVR(value) (GMAC_IER_ROVR_Msk & (_UINT32_(value) << GMAC_IER_ROVR_Pos)) /* Assignment of value for ROVR in the GMAC_IER register */ 432 #define GMAC_IER_HRESP_Pos _UINT32_(11) /* (GMAC_IER) HRESP Not OK Position */ 433 #define GMAC_IER_HRESP_Msk (_UINT32_(0x1) << GMAC_IER_HRESP_Pos) /* (GMAC_IER) HRESP Not OK Mask */ 434 #define GMAC_IER_HRESP(value) (GMAC_IER_HRESP_Msk & (_UINT32_(value) << GMAC_IER_HRESP_Pos)) /* Assignment of value for HRESP in the GMAC_IER register */ 435 #define GMAC_IER_PFNZ_Pos _UINT32_(12) /* (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Position */ 436 #define GMAC_IER_PFNZ_Msk (_UINT32_(0x1) << GMAC_IER_PFNZ_Pos) /* (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Mask */ 437 #define GMAC_IER_PFNZ(value) (GMAC_IER_PFNZ_Msk & (_UINT32_(value) << GMAC_IER_PFNZ_Pos)) /* Assignment of value for PFNZ in the GMAC_IER register */ 438 #define GMAC_IER_PTZ_Pos _UINT32_(13) /* (GMAC_IER) Pause Time Zero Position */ 439 #define GMAC_IER_PTZ_Msk (_UINT32_(0x1) << GMAC_IER_PTZ_Pos) /* (GMAC_IER) Pause Time Zero Mask */ 440 #define GMAC_IER_PTZ(value) (GMAC_IER_PTZ_Msk & (_UINT32_(value) << GMAC_IER_PTZ_Pos)) /* Assignment of value for PTZ in the GMAC_IER register */ 441 #define GMAC_IER_PFTR_Pos _UINT32_(14) /* (GMAC_IER) Pause Frame Transmitted Position */ 442 #define GMAC_IER_PFTR_Msk (_UINT32_(0x1) << GMAC_IER_PFTR_Pos) /* (GMAC_IER) Pause Frame Transmitted Mask */ 443 #define GMAC_IER_PFTR(value) (GMAC_IER_PFTR_Msk & (_UINT32_(value) << GMAC_IER_PFTR_Pos)) /* Assignment of value for PFTR in the GMAC_IER register */ 444 #define GMAC_IER_EXINT_Pos _UINT32_(15) /* (GMAC_IER) External Interrupt Position */ 445 #define GMAC_IER_EXINT_Msk (_UINT32_(0x1) << GMAC_IER_EXINT_Pos) /* (GMAC_IER) External Interrupt Mask */ 446 #define GMAC_IER_EXINT(value) (GMAC_IER_EXINT_Msk & (_UINT32_(value) << GMAC_IER_EXINT_Pos)) /* Assignment of value for EXINT in the GMAC_IER register */ 447 #define GMAC_IER_DRQFR_Pos _UINT32_(18) /* (GMAC_IER) PTP Delay Request Frame Received Position */ 448 #define GMAC_IER_DRQFR_Msk (_UINT32_(0x1) << GMAC_IER_DRQFR_Pos) /* (GMAC_IER) PTP Delay Request Frame Received Mask */ 449 #define GMAC_IER_DRQFR(value) (GMAC_IER_DRQFR_Msk & (_UINT32_(value) << GMAC_IER_DRQFR_Pos)) /* Assignment of value for DRQFR in the GMAC_IER register */ 450 #define GMAC_IER_SFR_Pos _UINT32_(19) /* (GMAC_IER) PTP Sync Frame Received Position */ 451 #define GMAC_IER_SFR_Msk (_UINT32_(0x1) << GMAC_IER_SFR_Pos) /* (GMAC_IER) PTP Sync Frame Received Mask */ 452 #define GMAC_IER_SFR(value) (GMAC_IER_SFR_Msk & (_UINT32_(value) << GMAC_IER_SFR_Pos)) /* Assignment of value for SFR in the GMAC_IER register */ 453 #define GMAC_IER_DRQFT_Pos _UINT32_(20) /* (GMAC_IER) PTP Delay Request Frame Transmitted Position */ 454 #define GMAC_IER_DRQFT_Msk (_UINT32_(0x1) << GMAC_IER_DRQFT_Pos) /* (GMAC_IER) PTP Delay Request Frame Transmitted Mask */ 455 #define GMAC_IER_DRQFT(value) (GMAC_IER_DRQFT_Msk & (_UINT32_(value) << GMAC_IER_DRQFT_Pos)) /* Assignment of value for DRQFT in the GMAC_IER register */ 456 #define GMAC_IER_SFT_Pos _UINT32_(21) /* (GMAC_IER) PTP Sync Frame Transmitted Position */ 457 #define GMAC_IER_SFT_Msk (_UINT32_(0x1) << GMAC_IER_SFT_Pos) /* (GMAC_IER) PTP Sync Frame Transmitted Mask */ 458 #define GMAC_IER_SFT(value) (GMAC_IER_SFT_Msk & (_UINT32_(value) << GMAC_IER_SFT_Pos)) /* Assignment of value for SFT in the GMAC_IER register */ 459 #define GMAC_IER_PDRQFR_Pos _UINT32_(22) /* (GMAC_IER) PDelay Request Frame Received Position */ 460 #define GMAC_IER_PDRQFR_Msk (_UINT32_(0x1) << GMAC_IER_PDRQFR_Pos) /* (GMAC_IER) PDelay Request Frame Received Mask */ 461 #define GMAC_IER_PDRQFR(value) (GMAC_IER_PDRQFR_Msk & (_UINT32_(value) << GMAC_IER_PDRQFR_Pos)) /* Assignment of value for PDRQFR in the GMAC_IER register */ 462 #define GMAC_IER_PDRSFR_Pos _UINT32_(23) /* (GMAC_IER) PDelay Response Frame Received Position */ 463 #define GMAC_IER_PDRSFR_Msk (_UINT32_(0x1) << GMAC_IER_PDRSFR_Pos) /* (GMAC_IER) PDelay Response Frame Received Mask */ 464 #define GMAC_IER_PDRSFR(value) (GMAC_IER_PDRSFR_Msk & (_UINT32_(value) << GMAC_IER_PDRSFR_Pos)) /* Assignment of value for PDRSFR in the GMAC_IER register */ 465 #define GMAC_IER_PDRQFT_Pos _UINT32_(24) /* (GMAC_IER) PDelay Request Frame Transmitted Position */ 466 #define GMAC_IER_PDRQFT_Msk (_UINT32_(0x1) << GMAC_IER_PDRQFT_Pos) /* (GMAC_IER) PDelay Request Frame Transmitted Mask */ 467 #define GMAC_IER_PDRQFT(value) (GMAC_IER_PDRQFT_Msk & (_UINT32_(value) << GMAC_IER_PDRQFT_Pos)) /* Assignment of value for PDRQFT in the GMAC_IER register */ 468 #define GMAC_IER_PDRSFT_Pos _UINT32_(25) /* (GMAC_IER) PDelay Response Frame Transmitted Position */ 469 #define GMAC_IER_PDRSFT_Msk (_UINT32_(0x1) << GMAC_IER_PDRSFT_Pos) /* (GMAC_IER) PDelay Response Frame Transmitted Mask */ 470 #define GMAC_IER_PDRSFT(value) (GMAC_IER_PDRSFT_Msk & (_UINT32_(value) << GMAC_IER_PDRSFT_Pos)) /* Assignment of value for PDRSFT in the GMAC_IER register */ 471 #define GMAC_IER_SRI_Pos _UINT32_(26) /* (GMAC_IER) TSU Seconds Register Increment Position */ 472 #define GMAC_IER_SRI_Msk (_UINT32_(0x1) << GMAC_IER_SRI_Pos) /* (GMAC_IER) TSU Seconds Register Increment Mask */ 473 #define GMAC_IER_SRI(value) (GMAC_IER_SRI_Msk & (_UINT32_(value) << GMAC_IER_SRI_Pos)) /* Assignment of value for SRI in the GMAC_IER register */ 474 #define GMAC_IER_RXLPISBC_Pos _UINT32_(27) /* (GMAC_IER) Enable RX LPI Indication Position */ 475 #define GMAC_IER_RXLPISBC_Msk (_UINT32_(0x1) << GMAC_IER_RXLPISBC_Pos) /* (GMAC_IER) Enable RX LPI Indication Mask */ 476 #define GMAC_IER_RXLPISBC(value) (GMAC_IER_RXLPISBC_Msk & (_UINT32_(value) << GMAC_IER_RXLPISBC_Pos)) /* Assignment of value for RXLPISBC in the GMAC_IER register */ 477 #define GMAC_IER_WOL_Pos _UINT32_(28) /* (GMAC_IER) Wake On LAN Position */ 478 #define GMAC_IER_WOL_Msk (_UINT32_(0x1) << GMAC_IER_WOL_Pos) /* (GMAC_IER) Wake On LAN Mask */ 479 #define GMAC_IER_WOL(value) (GMAC_IER_WOL_Msk & (_UINT32_(value) << GMAC_IER_WOL_Pos)) /* Assignment of value for WOL in the GMAC_IER register */ 480 #define GMAC_IER_TSUCMP_Pos _UINT32_(29) /* (GMAC_IER) Tsu timer comparison Position */ 481 #define GMAC_IER_TSUCMP_Msk (_UINT32_(0x1) << GMAC_IER_TSUCMP_Pos) /* (GMAC_IER) Tsu timer comparison Mask */ 482 #define GMAC_IER_TSUCMP(value) (GMAC_IER_TSUCMP_Msk & (_UINT32_(value) << GMAC_IER_TSUCMP_Pos)) /* Assignment of value for TSUCMP in the GMAC_IER register */ 483 #define GMAC_IER_Msk _UINT32_(0x3FFCFCFF) /* (GMAC_IER) Register Mask */ 484 485 486 /* -------- GMAC_IDR : (GMAC Offset: 0x2C) ( /W 32) Interrupt Disable Register -------- */ 487 #define GMAC_IDR_MFS_Pos _UINT32_(0) /* (GMAC_IDR) Management Frame Sent Position */ 488 #define GMAC_IDR_MFS_Msk (_UINT32_(0x1) << GMAC_IDR_MFS_Pos) /* (GMAC_IDR) Management Frame Sent Mask */ 489 #define GMAC_IDR_MFS(value) (GMAC_IDR_MFS_Msk & (_UINT32_(value) << GMAC_IDR_MFS_Pos)) /* Assignment of value for MFS in the GMAC_IDR register */ 490 #define GMAC_IDR_RCOMP_Pos _UINT32_(1) /* (GMAC_IDR) Receive Complete Position */ 491 #define GMAC_IDR_RCOMP_Msk (_UINT32_(0x1) << GMAC_IDR_RCOMP_Pos) /* (GMAC_IDR) Receive Complete Mask */ 492 #define GMAC_IDR_RCOMP(value) (GMAC_IDR_RCOMP_Msk & (_UINT32_(value) << GMAC_IDR_RCOMP_Pos)) /* Assignment of value for RCOMP in the GMAC_IDR register */ 493 #define GMAC_IDR_RXUBR_Pos _UINT32_(2) /* (GMAC_IDR) RX Used Bit Read Position */ 494 #define GMAC_IDR_RXUBR_Msk (_UINT32_(0x1) << GMAC_IDR_RXUBR_Pos) /* (GMAC_IDR) RX Used Bit Read Mask */ 495 #define GMAC_IDR_RXUBR(value) (GMAC_IDR_RXUBR_Msk & (_UINT32_(value) << GMAC_IDR_RXUBR_Pos)) /* Assignment of value for RXUBR in the GMAC_IDR register */ 496 #define GMAC_IDR_TXUBR_Pos _UINT32_(3) /* (GMAC_IDR) TX Used Bit Read Position */ 497 #define GMAC_IDR_TXUBR_Msk (_UINT32_(0x1) << GMAC_IDR_TXUBR_Pos) /* (GMAC_IDR) TX Used Bit Read Mask */ 498 #define GMAC_IDR_TXUBR(value) (GMAC_IDR_TXUBR_Msk & (_UINT32_(value) << GMAC_IDR_TXUBR_Pos)) /* Assignment of value for TXUBR in the GMAC_IDR register */ 499 #define GMAC_IDR_TUR_Pos _UINT32_(4) /* (GMAC_IDR) Transmit Underrun Position */ 500 #define GMAC_IDR_TUR_Msk (_UINT32_(0x1) << GMAC_IDR_TUR_Pos) /* (GMAC_IDR) Transmit Underrun Mask */ 501 #define GMAC_IDR_TUR(value) (GMAC_IDR_TUR_Msk & (_UINT32_(value) << GMAC_IDR_TUR_Pos)) /* Assignment of value for TUR in the GMAC_IDR register */ 502 #define GMAC_IDR_RLEX_Pos _UINT32_(5) /* (GMAC_IDR) Retry Limit Exceeded or Late Collision Position */ 503 #define GMAC_IDR_RLEX_Msk (_UINT32_(0x1) << GMAC_IDR_RLEX_Pos) /* (GMAC_IDR) Retry Limit Exceeded or Late Collision Mask */ 504 #define GMAC_IDR_RLEX(value) (GMAC_IDR_RLEX_Msk & (_UINT32_(value) << GMAC_IDR_RLEX_Pos)) /* Assignment of value for RLEX in the GMAC_IDR register */ 505 #define GMAC_IDR_TFC_Pos _UINT32_(6) /* (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Position */ 506 #define GMAC_IDR_TFC_Msk (_UINT32_(0x1) << GMAC_IDR_TFC_Pos) /* (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Mask */ 507 #define GMAC_IDR_TFC(value) (GMAC_IDR_TFC_Msk & (_UINT32_(value) << GMAC_IDR_TFC_Pos)) /* Assignment of value for TFC in the GMAC_IDR register */ 508 #define GMAC_IDR_TCOMP_Pos _UINT32_(7) /* (GMAC_IDR) Transmit Complete Position */ 509 #define GMAC_IDR_TCOMP_Msk (_UINT32_(0x1) << GMAC_IDR_TCOMP_Pos) /* (GMAC_IDR) Transmit Complete Mask */ 510 #define GMAC_IDR_TCOMP(value) (GMAC_IDR_TCOMP_Msk & (_UINT32_(value) << GMAC_IDR_TCOMP_Pos)) /* Assignment of value for TCOMP in the GMAC_IDR register */ 511 #define GMAC_IDR_ROVR_Pos _UINT32_(10) /* (GMAC_IDR) Receive Overrun Position */ 512 #define GMAC_IDR_ROVR_Msk (_UINT32_(0x1) << GMAC_IDR_ROVR_Pos) /* (GMAC_IDR) Receive Overrun Mask */ 513 #define GMAC_IDR_ROVR(value) (GMAC_IDR_ROVR_Msk & (_UINT32_(value) << GMAC_IDR_ROVR_Pos)) /* Assignment of value for ROVR in the GMAC_IDR register */ 514 #define GMAC_IDR_HRESP_Pos _UINT32_(11) /* (GMAC_IDR) HRESP Not OK Position */ 515 #define GMAC_IDR_HRESP_Msk (_UINT32_(0x1) << GMAC_IDR_HRESP_Pos) /* (GMAC_IDR) HRESP Not OK Mask */ 516 #define GMAC_IDR_HRESP(value) (GMAC_IDR_HRESP_Msk & (_UINT32_(value) << GMAC_IDR_HRESP_Pos)) /* Assignment of value for HRESP in the GMAC_IDR register */ 517 #define GMAC_IDR_PFNZ_Pos _UINT32_(12) /* (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Position */ 518 #define GMAC_IDR_PFNZ_Msk (_UINT32_(0x1) << GMAC_IDR_PFNZ_Pos) /* (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Mask */ 519 #define GMAC_IDR_PFNZ(value) (GMAC_IDR_PFNZ_Msk & (_UINT32_(value) << GMAC_IDR_PFNZ_Pos)) /* Assignment of value for PFNZ in the GMAC_IDR register */ 520 #define GMAC_IDR_PTZ_Pos _UINT32_(13) /* (GMAC_IDR) Pause Time Zero Position */ 521 #define GMAC_IDR_PTZ_Msk (_UINT32_(0x1) << GMAC_IDR_PTZ_Pos) /* (GMAC_IDR) Pause Time Zero Mask */ 522 #define GMAC_IDR_PTZ(value) (GMAC_IDR_PTZ_Msk & (_UINT32_(value) << GMAC_IDR_PTZ_Pos)) /* Assignment of value for PTZ in the GMAC_IDR register */ 523 #define GMAC_IDR_PFTR_Pos _UINT32_(14) /* (GMAC_IDR) Pause Frame Transmitted Position */ 524 #define GMAC_IDR_PFTR_Msk (_UINT32_(0x1) << GMAC_IDR_PFTR_Pos) /* (GMAC_IDR) Pause Frame Transmitted Mask */ 525 #define GMAC_IDR_PFTR(value) (GMAC_IDR_PFTR_Msk & (_UINT32_(value) << GMAC_IDR_PFTR_Pos)) /* Assignment of value for PFTR in the GMAC_IDR register */ 526 #define GMAC_IDR_EXINT_Pos _UINT32_(15) /* (GMAC_IDR) External Interrupt Position */ 527 #define GMAC_IDR_EXINT_Msk (_UINT32_(0x1) << GMAC_IDR_EXINT_Pos) /* (GMAC_IDR) External Interrupt Mask */ 528 #define GMAC_IDR_EXINT(value) (GMAC_IDR_EXINT_Msk & (_UINT32_(value) << GMAC_IDR_EXINT_Pos)) /* Assignment of value for EXINT in the GMAC_IDR register */ 529 #define GMAC_IDR_DRQFR_Pos _UINT32_(18) /* (GMAC_IDR) PTP Delay Request Frame Received Position */ 530 #define GMAC_IDR_DRQFR_Msk (_UINT32_(0x1) << GMAC_IDR_DRQFR_Pos) /* (GMAC_IDR) PTP Delay Request Frame Received Mask */ 531 #define GMAC_IDR_DRQFR(value) (GMAC_IDR_DRQFR_Msk & (_UINT32_(value) << GMAC_IDR_DRQFR_Pos)) /* Assignment of value for DRQFR in the GMAC_IDR register */ 532 #define GMAC_IDR_SFR_Pos _UINT32_(19) /* (GMAC_IDR) PTP Sync Frame Received Position */ 533 #define GMAC_IDR_SFR_Msk (_UINT32_(0x1) << GMAC_IDR_SFR_Pos) /* (GMAC_IDR) PTP Sync Frame Received Mask */ 534 #define GMAC_IDR_SFR(value) (GMAC_IDR_SFR_Msk & (_UINT32_(value) << GMAC_IDR_SFR_Pos)) /* Assignment of value for SFR in the GMAC_IDR register */ 535 #define GMAC_IDR_DRQFT_Pos _UINT32_(20) /* (GMAC_IDR) PTP Delay Request Frame Transmitted Position */ 536 #define GMAC_IDR_DRQFT_Msk (_UINT32_(0x1) << GMAC_IDR_DRQFT_Pos) /* (GMAC_IDR) PTP Delay Request Frame Transmitted Mask */ 537 #define GMAC_IDR_DRQFT(value) (GMAC_IDR_DRQFT_Msk & (_UINT32_(value) << GMAC_IDR_DRQFT_Pos)) /* Assignment of value for DRQFT in the GMAC_IDR register */ 538 #define GMAC_IDR_SFT_Pos _UINT32_(21) /* (GMAC_IDR) PTP Sync Frame Transmitted Position */ 539 #define GMAC_IDR_SFT_Msk (_UINT32_(0x1) << GMAC_IDR_SFT_Pos) /* (GMAC_IDR) PTP Sync Frame Transmitted Mask */ 540 #define GMAC_IDR_SFT(value) (GMAC_IDR_SFT_Msk & (_UINT32_(value) << GMAC_IDR_SFT_Pos)) /* Assignment of value for SFT in the GMAC_IDR register */ 541 #define GMAC_IDR_PDRQFR_Pos _UINT32_(22) /* (GMAC_IDR) PDelay Request Frame Received Position */ 542 #define GMAC_IDR_PDRQFR_Msk (_UINT32_(0x1) << GMAC_IDR_PDRQFR_Pos) /* (GMAC_IDR) PDelay Request Frame Received Mask */ 543 #define GMAC_IDR_PDRQFR(value) (GMAC_IDR_PDRQFR_Msk & (_UINT32_(value) << GMAC_IDR_PDRQFR_Pos)) /* Assignment of value for PDRQFR in the GMAC_IDR register */ 544 #define GMAC_IDR_PDRSFR_Pos _UINT32_(23) /* (GMAC_IDR) PDelay Response Frame Received Position */ 545 #define GMAC_IDR_PDRSFR_Msk (_UINT32_(0x1) << GMAC_IDR_PDRSFR_Pos) /* (GMAC_IDR) PDelay Response Frame Received Mask */ 546 #define GMAC_IDR_PDRSFR(value) (GMAC_IDR_PDRSFR_Msk & (_UINT32_(value) << GMAC_IDR_PDRSFR_Pos)) /* Assignment of value for PDRSFR in the GMAC_IDR register */ 547 #define GMAC_IDR_PDRQFT_Pos _UINT32_(24) /* (GMAC_IDR) PDelay Request Frame Transmitted Position */ 548 #define GMAC_IDR_PDRQFT_Msk (_UINT32_(0x1) << GMAC_IDR_PDRQFT_Pos) /* (GMAC_IDR) PDelay Request Frame Transmitted Mask */ 549 #define GMAC_IDR_PDRQFT(value) (GMAC_IDR_PDRQFT_Msk & (_UINT32_(value) << GMAC_IDR_PDRQFT_Pos)) /* Assignment of value for PDRQFT in the GMAC_IDR register */ 550 #define GMAC_IDR_PDRSFT_Pos _UINT32_(25) /* (GMAC_IDR) PDelay Response Frame Transmitted Position */ 551 #define GMAC_IDR_PDRSFT_Msk (_UINT32_(0x1) << GMAC_IDR_PDRSFT_Pos) /* (GMAC_IDR) PDelay Response Frame Transmitted Mask */ 552 #define GMAC_IDR_PDRSFT(value) (GMAC_IDR_PDRSFT_Msk & (_UINT32_(value) << GMAC_IDR_PDRSFT_Pos)) /* Assignment of value for PDRSFT in the GMAC_IDR register */ 553 #define GMAC_IDR_SRI_Pos _UINT32_(26) /* (GMAC_IDR) TSU Seconds Register Increment Position */ 554 #define GMAC_IDR_SRI_Msk (_UINT32_(0x1) << GMAC_IDR_SRI_Pos) /* (GMAC_IDR) TSU Seconds Register Increment Mask */ 555 #define GMAC_IDR_SRI(value) (GMAC_IDR_SRI_Msk & (_UINT32_(value) << GMAC_IDR_SRI_Pos)) /* Assignment of value for SRI in the GMAC_IDR register */ 556 #define GMAC_IDR_RXLPISBC_Pos _UINT32_(27) /* (GMAC_IDR) Enable RX LPI Indication Position */ 557 #define GMAC_IDR_RXLPISBC_Msk (_UINT32_(0x1) << GMAC_IDR_RXLPISBC_Pos) /* (GMAC_IDR) Enable RX LPI Indication Mask */ 558 #define GMAC_IDR_RXLPISBC(value) (GMAC_IDR_RXLPISBC_Msk & (_UINT32_(value) << GMAC_IDR_RXLPISBC_Pos)) /* Assignment of value for RXLPISBC in the GMAC_IDR register */ 559 #define GMAC_IDR_WOL_Pos _UINT32_(28) /* (GMAC_IDR) Wake On LAN Position */ 560 #define GMAC_IDR_WOL_Msk (_UINT32_(0x1) << GMAC_IDR_WOL_Pos) /* (GMAC_IDR) Wake On LAN Mask */ 561 #define GMAC_IDR_WOL(value) (GMAC_IDR_WOL_Msk & (_UINT32_(value) << GMAC_IDR_WOL_Pos)) /* Assignment of value for WOL in the GMAC_IDR register */ 562 #define GMAC_IDR_TSUCMP_Pos _UINT32_(29) /* (GMAC_IDR) Tsu timer comparison Position */ 563 #define GMAC_IDR_TSUCMP_Msk (_UINT32_(0x1) << GMAC_IDR_TSUCMP_Pos) /* (GMAC_IDR) Tsu timer comparison Mask */ 564 #define GMAC_IDR_TSUCMP(value) (GMAC_IDR_TSUCMP_Msk & (_UINT32_(value) << GMAC_IDR_TSUCMP_Pos)) /* Assignment of value for TSUCMP in the GMAC_IDR register */ 565 #define GMAC_IDR_Msk _UINT32_(0x3FFCFCFF) /* (GMAC_IDR) Register Mask */ 566 567 568 /* -------- GMAC_IMR : (GMAC Offset: 0x30) ( R/ 32) Interrupt Mask Register -------- */ 569 #define GMAC_IMR_RESETVALUE _UINT32_(0x3FFFFFFF) /* (GMAC_IMR) Interrupt Mask Register Reset Value */ 570 571 #define GMAC_IMR_MFS_Pos _UINT32_(0) /* (GMAC_IMR) Management Frame Sent Position */ 572 #define GMAC_IMR_MFS_Msk (_UINT32_(0x1) << GMAC_IMR_MFS_Pos) /* (GMAC_IMR) Management Frame Sent Mask */ 573 #define GMAC_IMR_MFS(value) (GMAC_IMR_MFS_Msk & (_UINT32_(value) << GMAC_IMR_MFS_Pos)) /* Assignment of value for MFS in the GMAC_IMR register */ 574 #define GMAC_IMR_RCOMP_Pos _UINT32_(1) /* (GMAC_IMR) Receive Complete Position */ 575 #define GMAC_IMR_RCOMP_Msk (_UINT32_(0x1) << GMAC_IMR_RCOMP_Pos) /* (GMAC_IMR) Receive Complete Mask */ 576 #define GMAC_IMR_RCOMP(value) (GMAC_IMR_RCOMP_Msk & (_UINT32_(value) << GMAC_IMR_RCOMP_Pos)) /* Assignment of value for RCOMP in the GMAC_IMR register */ 577 #define GMAC_IMR_RXUBR_Pos _UINT32_(2) /* (GMAC_IMR) RX Used Bit Read Position */ 578 #define GMAC_IMR_RXUBR_Msk (_UINT32_(0x1) << GMAC_IMR_RXUBR_Pos) /* (GMAC_IMR) RX Used Bit Read Mask */ 579 #define GMAC_IMR_RXUBR(value) (GMAC_IMR_RXUBR_Msk & (_UINT32_(value) << GMAC_IMR_RXUBR_Pos)) /* Assignment of value for RXUBR in the GMAC_IMR register */ 580 #define GMAC_IMR_TXUBR_Pos _UINT32_(3) /* (GMAC_IMR) TX Used Bit Read Position */ 581 #define GMAC_IMR_TXUBR_Msk (_UINT32_(0x1) << GMAC_IMR_TXUBR_Pos) /* (GMAC_IMR) TX Used Bit Read Mask */ 582 #define GMAC_IMR_TXUBR(value) (GMAC_IMR_TXUBR_Msk & (_UINT32_(value) << GMAC_IMR_TXUBR_Pos)) /* Assignment of value for TXUBR in the GMAC_IMR register */ 583 #define GMAC_IMR_TUR_Pos _UINT32_(4) /* (GMAC_IMR) Transmit Underrun Position */ 584 #define GMAC_IMR_TUR_Msk (_UINT32_(0x1) << GMAC_IMR_TUR_Pos) /* (GMAC_IMR) Transmit Underrun Mask */ 585 #define GMAC_IMR_TUR(value) (GMAC_IMR_TUR_Msk & (_UINT32_(value) << GMAC_IMR_TUR_Pos)) /* Assignment of value for TUR in the GMAC_IMR register */ 586 #define GMAC_IMR_RLEX_Pos _UINT32_(5) /* (GMAC_IMR) Retry Limit Exceeded Position */ 587 #define GMAC_IMR_RLEX_Msk (_UINT32_(0x1) << GMAC_IMR_RLEX_Pos) /* (GMAC_IMR) Retry Limit Exceeded Mask */ 588 #define GMAC_IMR_RLEX(value) (GMAC_IMR_RLEX_Msk & (_UINT32_(value) << GMAC_IMR_RLEX_Pos)) /* Assignment of value for RLEX in the GMAC_IMR register */ 589 #define GMAC_IMR_TFC_Pos _UINT32_(6) /* (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Position */ 590 #define GMAC_IMR_TFC_Msk (_UINT32_(0x1) << GMAC_IMR_TFC_Pos) /* (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Mask */ 591 #define GMAC_IMR_TFC(value) (GMAC_IMR_TFC_Msk & (_UINT32_(value) << GMAC_IMR_TFC_Pos)) /* Assignment of value for TFC in the GMAC_IMR register */ 592 #define GMAC_IMR_TCOMP_Pos _UINT32_(7) /* (GMAC_IMR) Transmit Complete Position */ 593 #define GMAC_IMR_TCOMP_Msk (_UINT32_(0x1) << GMAC_IMR_TCOMP_Pos) /* (GMAC_IMR) Transmit Complete Mask */ 594 #define GMAC_IMR_TCOMP(value) (GMAC_IMR_TCOMP_Msk & (_UINT32_(value) << GMAC_IMR_TCOMP_Pos)) /* Assignment of value for TCOMP in the GMAC_IMR register */ 595 #define GMAC_IMR_ROVR_Pos _UINT32_(10) /* (GMAC_IMR) Receive Overrun Position */ 596 #define GMAC_IMR_ROVR_Msk (_UINT32_(0x1) << GMAC_IMR_ROVR_Pos) /* (GMAC_IMR) Receive Overrun Mask */ 597 #define GMAC_IMR_ROVR(value) (GMAC_IMR_ROVR_Msk & (_UINT32_(value) << GMAC_IMR_ROVR_Pos)) /* Assignment of value for ROVR in the GMAC_IMR register */ 598 #define GMAC_IMR_HRESP_Pos _UINT32_(11) /* (GMAC_IMR) HRESP Not OK Position */ 599 #define GMAC_IMR_HRESP_Msk (_UINT32_(0x1) << GMAC_IMR_HRESP_Pos) /* (GMAC_IMR) HRESP Not OK Mask */ 600 #define GMAC_IMR_HRESP(value) (GMAC_IMR_HRESP_Msk & (_UINT32_(value) << GMAC_IMR_HRESP_Pos)) /* Assignment of value for HRESP in the GMAC_IMR register */ 601 #define GMAC_IMR_PFNZ_Pos _UINT32_(12) /* (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Position */ 602 #define GMAC_IMR_PFNZ_Msk (_UINT32_(0x1) << GMAC_IMR_PFNZ_Pos) /* (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Mask */ 603 #define GMAC_IMR_PFNZ(value) (GMAC_IMR_PFNZ_Msk & (_UINT32_(value) << GMAC_IMR_PFNZ_Pos)) /* Assignment of value for PFNZ in the GMAC_IMR register */ 604 #define GMAC_IMR_PTZ_Pos _UINT32_(13) /* (GMAC_IMR) Pause Time Zero Position */ 605 #define GMAC_IMR_PTZ_Msk (_UINT32_(0x1) << GMAC_IMR_PTZ_Pos) /* (GMAC_IMR) Pause Time Zero Mask */ 606 #define GMAC_IMR_PTZ(value) (GMAC_IMR_PTZ_Msk & (_UINT32_(value) << GMAC_IMR_PTZ_Pos)) /* Assignment of value for PTZ in the GMAC_IMR register */ 607 #define GMAC_IMR_PFTR_Pos _UINT32_(14) /* (GMAC_IMR) Pause Frame Transmitted Position */ 608 #define GMAC_IMR_PFTR_Msk (_UINT32_(0x1) << GMAC_IMR_PFTR_Pos) /* (GMAC_IMR) Pause Frame Transmitted Mask */ 609 #define GMAC_IMR_PFTR(value) (GMAC_IMR_PFTR_Msk & (_UINT32_(value) << GMAC_IMR_PFTR_Pos)) /* Assignment of value for PFTR in the GMAC_IMR register */ 610 #define GMAC_IMR_EXINT_Pos _UINT32_(15) /* (GMAC_IMR) External Interrupt Position */ 611 #define GMAC_IMR_EXINT_Msk (_UINT32_(0x1) << GMAC_IMR_EXINT_Pos) /* (GMAC_IMR) External Interrupt Mask */ 612 #define GMAC_IMR_EXINT(value) (GMAC_IMR_EXINT_Msk & (_UINT32_(value) << GMAC_IMR_EXINT_Pos)) /* Assignment of value for EXINT in the GMAC_IMR register */ 613 #define GMAC_IMR_DRQFR_Pos _UINT32_(18) /* (GMAC_IMR) PTP Delay Request Frame Received Position */ 614 #define GMAC_IMR_DRQFR_Msk (_UINT32_(0x1) << GMAC_IMR_DRQFR_Pos) /* (GMAC_IMR) PTP Delay Request Frame Received Mask */ 615 #define GMAC_IMR_DRQFR(value) (GMAC_IMR_DRQFR_Msk & (_UINT32_(value) << GMAC_IMR_DRQFR_Pos)) /* Assignment of value for DRQFR in the GMAC_IMR register */ 616 #define GMAC_IMR_SFR_Pos _UINT32_(19) /* (GMAC_IMR) PTP Sync Frame Received Position */ 617 #define GMAC_IMR_SFR_Msk (_UINT32_(0x1) << GMAC_IMR_SFR_Pos) /* (GMAC_IMR) PTP Sync Frame Received Mask */ 618 #define GMAC_IMR_SFR(value) (GMAC_IMR_SFR_Msk & (_UINT32_(value) << GMAC_IMR_SFR_Pos)) /* Assignment of value for SFR in the GMAC_IMR register */ 619 #define GMAC_IMR_DRQFT_Pos _UINT32_(20) /* (GMAC_IMR) PTP Delay Request Frame Transmitted Position */ 620 #define GMAC_IMR_DRQFT_Msk (_UINT32_(0x1) << GMAC_IMR_DRQFT_Pos) /* (GMAC_IMR) PTP Delay Request Frame Transmitted Mask */ 621 #define GMAC_IMR_DRQFT(value) (GMAC_IMR_DRQFT_Msk & (_UINT32_(value) << GMAC_IMR_DRQFT_Pos)) /* Assignment of value for DRQFT in the GMAC_IMR register */ 622 #define GMAC_IMR_SFT_Pos _UINT32_(21) /* (GMAC_IMR) PTP Sync Frame Transmitted Position */ 623 #define GMAC_IMR_SFT_Msk (_UINT32_(0x1) << GMAC_IMR_SFT_Pos) /* (GMAC_IMR) PTP Sync Frame Transmitted Mask */ 624 #define GMAC_IMR_SFT(value) (GMAC_IMR_SFT_Msk & (_UINT32_(value) << GMAC_IMR_SFT_Pos)) /* Assignment of value for SFT in the GMAC_IMR register */ 625 #define GMAC_IMR_PDRQFR_Pos _UINT32_(22) /* (GMAC_IMR) PDelay Request Frame Received Position */ 626 #define GMAC_IMR_PDRQFR_Msk (_UINT32_(0x1) << GMAC_IMR_PDRQFR_Pos) /* (GMAC_IMR) PDelay Request Frame Received Mask */ 627 #define GMAC_IMR_PDRQFR(value) (GMAC_IMR_PDRQFR_Msk & (_UINT32_(value) << GMAC_IMR_PDRQFR_Pos)) /* Assignment of value for PDRQFR in the GMAC_IMR register */ 628 #define GMAC_IMR_PDRSFR_Pos _UINT32_(23) /* (GMAC_IMR) PDelay Response Frame Received Position */ 629 #define GMAC_IMR_PDRSFR_Msk (_UINT32_(0x1) << GMAC_IMR_PDRSFR_Pos) /* (GMAC_IMR) PDelay Response Frame Received Mask */ 630 #define GMAC_IMR_PDRSFR(value) (GMAC_IMR_PDRSFR_Msk & (_UINT32_(value) << GMAC_IMR_PDRSFR_Pos)) /* Assignment of value for PDRSFR in the GMAC_IMR register */ 631 #define GMAC_IMR_PDRQFT_Pos _UINT32_(24) /* (GMAC_IMR) PDelay Request Frame Transmitted Position */ 632 #define GMAC_IMR_PDRQFT_Msk (_UINT32_(0x1) << GMAC_IMR_PDRQFT_Pos) /* (GMAC_IMR) PDelay Request Frame Transmitted Mask */ 633 #define GMAC_IMR_PDRQFT(value) (GMAC_IMR_PDRQFT_Msk & (_UINT32_(value) << GMAC_IMR_PDRQFT_Pos)) /* Assignment of value for PDRQFT in the GMAC_IMR register */ 634 #define GMAC_IMR_PDRSFT_Pos _UINT32_(25) /* (GMAC_IMR) PDelay Response Frame Transmitted Position */ 635 #define GMAC_IMR_PDRSFT_Msk (_UINT32_(0x1) << GMAC_IMR_PDRSFT_Pos) /* (GMAC_IMR) PDelay Response Frame Transmitted Mask */ 636 #define GMAC_IMR_PDRSFT(value) (GMAC_IMR_PDRSFT_Msk & (_UINT32_(value) << GMAC_IMR_PDRSFT_Pos)) /* Assignment of value for PDRSFT in the GMAC_IMR register */ 637 #define GMAC_IMR_SRI_Pos _UINT32_(26) /* (GMAC_IMR) TSU Seconds Register Increment Position */ 638 #define GMAC_IMR_SRI_Msk (_UINT32_(0x1) << GMAC_IMR_SRI_Pos) /* (GMAC_IMR) TSU Seconds Register Increment Mask */ 639 #define GMAC_IMR_SRI(value) (GMAC_IMR_SRI_Msk & (_UINT32_(value) << GMAC_IMR_SRI_Pos)) /* Assignment of value for SRI in the GMAC_IMR register */ 640 #define GMAC_IMR_RXLPISBC_Pos _UINT32_(27) /* (GMAC_IMR) Enable RX LPI Indication Position */ 641 #define GMAC_IMR_RXLPISBC_Msk (_UINT32_(0x1) << GMAC_IMR_RXLPISBC_Pos) /* (GMAC_IMR) Enable RX LPI Indication Mask */ 642 #define GMAC_IMR_RXLPISBC(value) (GMAC_IMR_RXLPISBC_Msk & (_UINT32_(value) << GMAC_IMR_RXLPISBC_Pos)) /* Assignment of value for RXLPISBC in the GMAC_IMR register */ 643 #define GMAC_IMR_WOL_Pos _UINT32_(28) /* (GMAC_IMR) Wake On Lan Position */ 644 #define GMAC_IMR_WOL_Msk (_UINT32_(0x1) << GMAC_IMR_WOL_Pos) /* (GMAC_IMR) Wake On Lan Mask */ 645 #define GMAC_IMR_WOL(value) (GMAC_IMR_WOL_Msk & (_UINT32_(value) << GMAC_IMR_WOL_Pos)) /* Assignment of value for WOL in the GMAC_IMR register */ 646 #define GMAC_IMR_TSUCMP_Pos _UINT32_(29) /* (GMAC_IMR) Tsu timer comparison Position */ 647 #define GMAC_IMR_TSUCMP_Msk (_UINT32_(0x1) << GMAC_IMR_TSUCMP_Pos) /* (GMAC_IMR) Tsu timer comparison Mask */ 648 #define GMAC_IMR_TSUCMP(value) (GMAC_IMR_TSUCMP_Msk & (_UINT32_(value) << GMAC_IMR_TSUCMP_Pos)) /* Assignment of value for TSUCMP in the GMAC_IMR register */ 649 #define GMAC_IMR_Msk _UINT32_(0x3FFCFCFF) /* (GMAC_IMR) Register Mask */ 650 651 652 /* -------- GMAC_MAN : (GMAC Offset: 0x34) (R/W 32) PHY Maintenance Register -------- */ 653 #define GMAC_MAN_RESETVALUE _UINT32_(0x00) /* (GMAC_MAN) PHY Maintenance Register Reset Value */ 654 655 #define GMAC_MAN_DATA_Pos _UINT32_(0) /* (GMAC_MAN) PHY Data Position */ 656 #define GMAC_MAN_DATA_Msk (_UINT32_(0xFFFF) << GMAC_MAN_DATA_Pos) /* (GMAC_MAN) PHY Data Mask */ 657 #define GMAC_MAN_DATA(value) (GMAC_MAN_DATA_Msk & (_UINT32_(value) << GMAC_MAN_DATA_Pos)) /* Assignment of value for DATA in the GMAC_MAN register */ 658 #define GMAC_MAN_WTN_Pos _UINT32_(16) /* (GMAC_MAN) Write Ten Position */ 659 #define GMAC_MAN_WTN_Msk (_UINT32_(0x3) << GMAC_MAN_WTN_Pos) /* (GMAC_MAN) Write Ten Mask */ 660 #define GMAC_MAN_WTN(value) (GMAC_MAN_WTN_Msk & (_UINT32_(value) << GMAC_MAN_WTN_Pos)) /* Assignment of value for WTN in the GMAC_MAN register */ 661 #define GMAC_MAN_REGA_Pos _UINT32_(18) /* (GMAC_MAN) Register Address Position */ 662 #define GMAC_MAN_REGA_Msk (_UINT32_(0x1F) << GMAC_MAN_REGA_Pos) /* (GMAC_MAN) Register Address Mask */ 663 #define GMAC_MAN_REGA(value) (GMAC_MAN_REGA_Msk & (_UINT32_(value) << GMAC_MAN_REGA_Pos)) /* Assignment of value for REGA in the GMAC_MAN register */ 664 #define GMAC_MAN_PHYA_Pos _UINT32_(23) /* (GMAC_MAN) PHY Address Position */ 665 #define GMAC_MAN_PHYA_Msk (_UINT32_(0x1F) << GMAC_MAN_PHYA_Pos) /* (GMAC_MAN) PHY Address Mask */ 666 #define GMAC_MAN_PHYA(value) (GMAC_MAN_PHYA_Msk & (_UINT32_(value) << GMAC_MAN_PHYA_Pos)) /* Assignment of value for PHYA in the GMAC_MAN register */ 667 #define GMAC_MAN_OP_Pos _UINT32_(28) /* (GMAC_MAN) Operation Position */ 668 #define GMAC_MAN_OP_Msk (_UINT32_(0x3) << GMAC_MAN_OP_Pos) /* (GMAC_MAN) Operation Mask */ 669 #define GMAC_MAN_OP(value) (GMAC_MAN_OP_Msk & (_UINT32_(value) << GMAC_MAN_OP_Pos)) /* Assignment of value for OP in the GMAC_MAN register */ 670 #define GMAC_MAN_CLTTO_Pos _UINT32_(30) /* (GMAC_MAN) Clause 22 Operation Position */ 671 #define GMAC_MAN_CLTTO_Msk (_UINT32_(0x1) << GMAC_MAN_CLTTO_Pos) /* (GMAC_MAN) Clause 22 Operation Mask */ 672 #define GMAC_MAN_CLTTO(value) (GMAC_MAN_CLTTO_Msk & (_UINT32_(value) << GMAC_MAN_CLTTO_Pos)) /* Assignment of value for CLTTO in the GMAC_MAN register */ 673 #define GMAC_MAN_WZO_Pos _UINT32_(31) /* (GMAC_MAN) Write ZERO Position */ 674 #define GMAC_MAN_WZO_Msk (_UINT32_(0x1) << GMAC_MAN_WZO_Pos) /* (GMAC_MAN) Write ZERO Mask */ 675 #define GMAC_MAN_WZO(value) (GMAC_MAN_WZO_Msk & (_UINT32_(value) << GMAC_MAN_WZO_Pos)) /* Assignment of value for WZO in the GMAC_MAN register */ 676 #define GMAC_MAN_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_MAN) Register Mask */ 677 678 679 /* -------- GMAC_RPQ : (GMAC Offset: 0x38) ( R/ 32) Received Pause Quantum Register -------- */ 680 #define GMAC_RPQ_RESETVALUE _UINT32_(0x00) /* (GMAC_RPQ) Received Pause Quantum Register Reset Value */ 681 682 #define GMAC_RPQ_RPQ_Pos _UINT32_(0) /* (GMAC_RPQ) Received Pause Quantum Position */ 683 #define GMAC_RPQ_RPQ_Msk (_UINT32_(0xFFFF) << GMAC_RPQ_RPQ_Pos) /* (GMAC_RPQ) Received Pause Quantum Mask */ 684 #define GMAC_RPQ_RPQ(value) (GMAC_RPQ_RPQ_Msk & (_UINT32_(value) << GMAC_RPQ_RPQ_Pos)) /* Assignment of value for RPQ in the GMAC_RPQ register */ 685 #define GMAC_RPQ_Msk _UINT32_(0x0000FFFF) /* (GMAC_RPQ) Register Mask */ 686 687 688 /* -------- GMAC_TPQ : (GMAC Offset: 0x3C) (R/W 32) Transmit Pause Quantum Register -------- */ 689 #define GMAC_TPQ_RESETVALUE _UINT32_(0xFFFF) /* (GMAC_TPQ) Transmit Pause Quantum Register Reset Value */ 690 691 #define GMAC_TPQ_TPQ_Pos _UINT32_(0) /* (GMAC_TPQ) Transmit Pause Quantum Position */ 692 #define GMAC_TPQ_TPQ_Msk (_UINT32_(0xFFFF) << GMAC_TPQ_TPQ_Pos) /* (GMAC_TPQ) Transmit Pause Quantum Mask */ 693 #define GMAC_TPQ_TPQ(value) (GMAC_TPQ_TPQ_Msk & (_UINT32_(value) << GMAC_TPQ_TPQ_Pos)) /* Assignment of value for TPQ in the GMAC_TPQ register */ 694 #define GMAC_TPQ_Msk _UINT32_(0x0000FFFF) /* (GMAC_TPQ) Register Mask */ 695 696 697 /* -------- GMAC_TPSF : (GMAC Offset: 0x40) (R/W 32) TX partial store and forward Register -------- */ 698 #define GMAC_TPSF_RESETVALUE _UINT32_(0x3FF) /* (GMAC_TPSF) TX partial store and forward Register Reset Value */ 699 700 #define GMAC_TPSF_TPB1ADR_Pos _UINT32_(0) /* (GMAC_TPSF) TX packet buffer address Position */ 701 #define GMAC_TPSF_TPB1ADR_Msk (_UINT32_(0x3FF) << GMAC_TPSF_TPB1ADR_Pos) /* (GMAC_TPSF) TX packet buffer address Mask */ 702 #define GMAC_TPSF_TPB1ADR(value) (GMAC_TPSF_TPB1ADR_Msk & (_UINT32_(value) << GMAC_TPSF_TPB1ADR_Pos)) /* Assignment of value for TPB1ADR in the GMAC_TPSF register */ 703 #define GMAC_TPSF_ENTXP_Pos _UINT32_(31) /* (GMAC_TPSF) Enable TX partial store and forward operation Position */ 704 #define GMAC_TPSF_ENTXP_Msk (_UINT32_(0x1) << GMAC_TPSF_ENTXP_Pos) /* (GMAC_TPSF) Enable TX partial store and forward operation Mask */ 705 #define GMAC_TPSF_ENTXP(value) (GMAC_TPSF_ENTXP_Msk & (_UINT32_(value) << GMAC_TPSF_ENTXP_Pos)) /* Assignment of value for ENTXP in the GMAC_TPSF register */ 706 #define GMAC_TPSF_Msk _UINT32_(0x800003FF) /* (GMAC_TPSF) Register Mask */ 707 708 709 /* -------- GMAC_RPSF : (GMAC Offset: 0x44) (R/W 32) RX partial store and forward Register -------- */ 710 #define GMAC_RPSF_RESETVALUE _UINT32_(0x3FF) /* (GMAC_RPSF) RX partial store and forward Register Reset Value */ 711 712 #define GMAC_RPSF_RPB1ADR_Pos _UINT32_(0) /* (GMAC_RPSF) RX packet buffer address Position */ 713 #define GMAC_RPSF_RPB1ADR_Msk (_UINT32_(0x3FF) << GMAC_RPSF_RPB1ADR_Pos) /* (GMAC_RPSF) RX packet buffer address Mask */ 714 #define GMAC_RPSF_RPB1ADR(value) (GMAC_RPSF_RPB1ADR_Msk & (_UINT32_(value) << GMAC_RPSF_RPB1ADR_Pos)) /* Assignment of value for RPB1ADR in the GMAC_RPSF register */ 715 #define GMAC_RPSF_ENRXP_Pos _UINT32_(31) /* (GMAC_RPSF) Enable RX partial store and forward operation Position */ 716 #define GMAC_RPSF_ENRXP_Msk (_UINT32_(0x1) << GMAC_RPSF_ENRXP_Pos) /* (GMAC_RPSF) Enable RX partial store and forward operation Mask */ 717 #define GMAC_RPSF_ENRXP(value) (GMAC_RPSF_ENRXP_Msk & (_UINT32_(value) << GMAC_RPSF_ENRXP_Pos)) /* Assignment of value for ENRXP in the GMAC_RPSF register */ 718 #define GMAC_RPSF_Msk _UINT32_(0x800003FF) /* (GMAC_RPSF) Register Mask */ 719 720 721 /* -------- GMAC_RJFML : (GMAC Offset: 0x48) (R/W 32) RX Jumbo Frame Max Length Register -------- */ 722 #define GMAC_RJFML_RESETVALUE _UINT32_(0x3FFF) /* (GMAC_RJFML) RX Jumbo Frame Max Length Register Reset Value */ 723 724 #define GMAC_RJFML_FML_Pos _UINT32_(0) /* (GMAC_RJFML) Frame Max Length Position */ 725 #define GMAC_RJFML_FML_Msk (_UINT32_(0x3FFF) << GMAC_RJFML_FML_Pos) /* (GMAC_RJFML) Frame Max Length Mask */ 726 #define GMAC_RJFML_FML(value) (GMAC_RJFML_FML_Msk & (_UINT32_(value) << GMAC_RJFML_FML_Pos)) /* Assignment of value for FML in the GMAC_RJFML register */ 727 #define GMAC_RJFML_Msk _UINT32_(0x00003FFF) /* (GMAC_RJFML) Register Mask */ 728 729 730 /* -------- GMAC_HRB : (GMAC Offset: 0x80) (R/W 32) Hash Register Bottom [31:0] -------- */ 731 #define GMAC_HRB_RESETVALUE _UINT32_(0x00) /* (GMAC_HRB) Hash Register Bottom [31:0] Reset Value */ 732 733 #define GMAC_HRB_ADDR_Pos _UINT32_(0) /* (GMAC_HRB) Hash Address Position */ 734 #define GMAC_HRB_ADDR_Msk (_UINT32_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos) /* (GMAC_HRB) Hash Address Mask */ 735 #define GMAC_HRB_ADDR(value) (GMAC_HRB_ADDR_Msk & (_UINT32_(value) << GMAC_HRB_ADDR_Pos)) /* Assignment of value for ADDR in the GMAC_HRB register */ 736 #define GMAC_HRB_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_HRB) Register Mask */ 737 738 739 /* -------- GMAC_HRT : (GMAC Offset: 0x84) (R/W 32) Hash Register Top [63:32] -------- */ 740 #define GMAC_HRT_RESETVALUE _UINT32_(0x00) /* (GMAC_HRT) Hash Register Top [63:32] Reset Value */ 741 742 #define GMAC_HRT_ADDR_Pos _UINT32_(0) /* (GMAC_HRT) Hash Address Position */ 743 #define GMAC_HRT_ADDR_Msk (_UINT32_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos) /* (GMAC_HRT) Hash Address Mask */ 744 #define GMAC_HRT_ADDR(value) (GMAC_HRT_ADDR_Msk & (_UINT32_(value) << GMAC_HRT_ADDR_Pos)) /* Assignment of value for ADDR in the GMAC_HRT register */ 745 #define GMAC_HRT_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_HRT) Register Mask */ 746 747 748 /* -------- GMAC_TIDM : (GMAC Offset: 0xA8) (R/W 32) Type ID Match n Register -------- */ 749 #define GMAC_TIDM_RESETVALUE _UINT32_(0x00) /* (GMAC_TIDM) Type ID Match n Register Reset Value */ 750 751 #define GMAC_TIDM_TID_Pos _UINT32_(0) /* (GMAC_TIDM) Type ID Match n Position */ 752 #define GMAC_TIDM_TID_Msk (_UINT32_(0xFFFF) << GMAC_TIDM_TID_Pos) /* (GMAC_TIDM) Type ID Match n Mask */ 753 #define GMAC_TIDM_TID(value) (GMAC_TIDM_TID_Msk & (_UINT32_(value) << GMAC_TIDM_TID_Pos)) /* Assignment of value for TID in the GMAC_TIDM register */ 754 #define GMAC_TIDM_ENID_Pos _UINT32_(31) /* (GMAC_TIDM) Enable Copying of TID n Matched Frames Position */ 755 #define GMAC_TIDM_ENID_Msk (_UINT32_(0x1) << GMAC_TIDM_ENID_Pos) /* (GMAC_TIDM) Enable Copying of TID n Matched Frames Mask */ 756 #define GMAC_TIDM_ENID(value) (GMAC_TIDM_ENID_Msk & (_UINT32_(value) << GMAC_TIDM_ENID_Pos)) /* Assignment of value for ENID in the GMAC_TIDM register */ 757 #define GMAC_TIDM_Msk _UINT32_(0x8000FFFF) /* (GMAC_TIDM) Register Mask */ 758 759 760 /* -------- GMAC_WOL : (GMAC Offset: 0xB8) (R/W 32) Wake on LAN -------- */ 761 #define GMAC_WOL_RESETVALUE _UINT32_(0x00) /* (GMAC_WOL) Wake on LAN Reset Value */ 762 763 #define GMAC_WOL_IP_Pos _UINT32_(0) /* (GMAC_WOL) IP address Position */ 764 #define GMAC_WOL_IP_Msk (_UINT32_(0xFFFF) << GMAC_WOL_IP_Pos) /* (GMAC_WOL) IP address Mask */ 765 #define GMAC_WOL_IP(value) (GMAC_WOL_IP_Msk & (_UINT32_(value) << GMAC_WOL_IP_Pos)) /* Assignment of value for IP in the GMAC_WOL register */ 766 #define GMAC_WOL_MAG_Pos _UINT32_(16) /* (GMAC_WOL) Event enable Position */ 767 #define GMAC_WOL_MAG_Msk (_UINT32_(0x1) << GMAC_WOL_MAG_Pos) /* (GMAC_WOL) Event enable Mask */ 768 #define GMAC_WOL_MAG(value) (GMAC_WOL_MAG_Msk & (_UINT32_(value) << GMAC_WOL_MAG_Pos)) /* Assignment of value for MAG in the GMAC_WOL register */ 769 #define GMAC_WOL_ARP_Pos _UINT32_(17) /* (GMAC_WOL) LAN ARP req Position */ 770 #define GMAC_WOL_ARP_Msk (_UINT32_(0x1) << GMAC_WOL_ARP_Pos) /* (GMAC_WOL) LAN ARP req Mask */ 771 #define GMAC_WOL_ARP(value) (GMAC_WOL_ARP_Msk & (_UINT32_(value) << GMAC_WOL_ARP_Pos)) /* Assignment of value for ARP in the GMAC_WOL register */ 772 #define GMAC_WOL_SA1_Pos _UINT32_(18) /* (GMAC_WOL) WOL specific address reg 1 Position */ 773 #define GMAC_WOL_SA1_Msk (_UINT32_(0x1) << GMAC_WOL_SA1_Pos) /* (GMAC_WOL) WOL specific address reg 1 Mask */ 774 #define GMAC_WOL_SA1(value) (GMAC_WOL_SA1_Msk & (_UINT32_(value) << GMAC_WOL_SA1_Pos)) /* Assignment of value for SA1 in the GMAC_WOL register */ 775 #define GMAC_WOL_MTI_Pos _UINT32_(19) /* (GMAC_WOL) WOL LAN multicast Position */ 776 #define GMAC_WOL_MTI_Msk (_UINT32_(0x1) << GMAC_WOL_MTI_Pos) /* (GMAC_WOL) WOL LAN multicast Mask */ 777 #define GMAC_WOL_MTI(value) (GMAC_WOL_MTI_Msk & (_UINT32_(value) << GMAC_WOL_MTI_Pos)) /* Assignment of value for MTI in the GMAC_WOL register */ 778 #define GMAC_WOL_Msk _UINT32_(0x000FFFFF) /* (GMAC_WOL) Register Mask */ 779 780 #define GMAC_WOL_SA_Pos _UINT32_(18) /* (GMAC_WOL Position) WOL specific address reg x */ 781 #define GMAC_WOL_SA_Msk (_UINT32_(0x1) << GMAC_WOL_SA_Pos) /* (GMAC_WOL Mask) SA */ 782 #define GMAC_WOL_SA(value) (GMAC_WOL_SA_Msk & (_UINT32_(value) << GMAC_WOL_SA_Pos)) 783 784 /* -------- GMAC_IPGS : (GMAC Offset: 0xBC) (R/W 32) IPG Stretch Register -------- */ 785 #define GMAC_IPGS_RESETVALUE _UINT32_(0x00) /* (GMAC_IPGS) IPG Stretch Register Reset Value */ 786 787 #define GMAC_IPGS_FL_Pos _UINT32_(0) /* (GMAC_IPGS) Frame Length Position */ 788 #define GMAC_IPGS_FL_Msk (_UINT32_(0xFFFF) << GMAC_IPGS_FL_Pos) /* (GMAC_IPGS) Frame Length Mask */ 789 #define GMAC_IPGS_FL(value) (GMAC_IPGS_FL_Msk & (_UINT32_(value) << GMAC_IPGS_FL_Pos)) /* Assignment of value for FL in the GMAC_IPGS register */ 790 #define GMAC_IPGS_Msk _UINT32_(0x0000FFFF) /* (GMAC_IPGS) Register Mask */ 791 792 793 /* -------- GMAC_SVLAN : (GMAC Offset: 0xC0) (R/W 32) Stacked VLAN Register -------- */ 794 #define GMAC_SVLAN_RESETVALUE _UINT32_(0x00) /* (GMAC_SVLAN) Stacked VLAN Register Reset Value */ 795 796 #define GMAC_SVLAN_VLAN_TYPE_Pos _UINT32_(0) /* (GMAC_SVLAN) User Defined VLAN_TYPE Field Position */ 797 #define GMAC_SVLAN_VLAN_TYPE_Msk (_UINT32_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos) /* (GMAC_SVLAN) User Defined VLAN_TYPE Field Mask */ 798 #define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & (_UINT32_(value) << GMAC_SVLAN_VLAN_TYPE_Pos)) /* Assignment of value for VLAN_TYPE in the GMAC_SVLAN register */ 799 #define GMAC_SVLAN_ESVLAN_Pos _UINT32_(31) /* (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Position */ 800 #define GMAC_SVLAN_ESVLAN_Msk (_UINT32_(0x1) << GMAC_SVLAN_ESVLAN_Pos) /* (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Mask */ 801 #define GMAC_SVLAN_ESVLAN(value) (GMAC_SVLAN_ESVLAN_Msk & (_UINT32_(value) << GMAC_SVLAN_ESVLAN_Pos)) /* Assignment of value for ESVLAN in the GMAC_SVLAN register */ 802 #define GMAC_SVLAN_Msk _UINT32_(0x8000FFFF) /* (GMAC_SVLAN) Register Mask */ 803 804 805 /* -------- GMAC_TPFCP : (GMAC Offset: 0xC4) (R/W 32) Transmit PFC Pause Register -------- */ 806 #define GMAC_TPFCP_RESETVALUE _UINT32_(0x00) /* (GMAC_TPFCP) Transmit PFC Pause Register Reset Value */ 807 808 #define GMAC_TPFCP_PEV_Pos _UINT32_(0) /* (GMAC_TPFCP) Priority Enable Vector Position */ 809 #define GMAC_TPFCP_PEV_Msk (_UINT32_(0xFF) << GMAC_TPFCP_PEV_Pos) /* (GMAC_TPFCP) Priority Enable Vector Mask */ 810 #define GMAC_TPFCP_PEV(value) (GMAC_TPFCP_PEV_Msk & (_UINT32_(value) << GMAC_TPFCP_PEV_Pos)) /* Assignment of value for PEV in the GMAC_TPFCP register */ 811 #define GMAC_TPFCP_PQ_Pos _UINT32_(8) /* (GMAC_TPFCP) Pause Quantum Position */ 812 #define GMAC_TPFCP_PQ_Msk (_UINT32_(0xFF) << GMAC_TPFCP_PQ_Pos) /* (GMAC_TPFCP) Pause Quantum Mask */ 813 #define GMAC_TPFCP_PQ(value) (GMAC_TPFCP_PQ_Msk & (_UINT32_(value) << GMAC_TPFCP_PQ_Pos)) /* Assignment of value for PQ in the GMAC_TPFCP register */ 814 #define GMAC_TPFCP_Msk _UINT32_(0x0000FFFF) /* (GMAC_TPFCP) Register Mask */ 815 816 817 /* -------- GMAC_SAMB1 : (GMAC Offset: 0xC8) (R/W 32) Specific Address 1 Mask Bottom [31:0] Register -------- */ 818 #define GMAC_SAMB1_RESETVALUE _UINT32_(0x00) /* (GMAC_SAMB1) Specific Address 1 Mask Bottom [31:0] Register Reset Value */ 819 820 #define GMAC_SAMB1_ADDR_Pos _UINT32_(0) /* (GMAC_SAMB1) Specific Address 1 Mask Position */ 821 #define GMAC_SAMB1_ADDR_Msk (_UINT32_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos) /* (GMAC_SAMB1) Specific Address 1 Mask Mask */ 822 #define GMAC_SAMB1_ADDR(value) (GMAC_SAMB1_ADDR_Msk & (_UINT32_(value) << GMAC_SAMB1_ADDR_Pos)) /* Assignment of value for ADDR in the GMAC_SAMB1 register */ 823 #define GMAC_SAMB1_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_SAMB1) Register Mask */ 824 825 826 /* -------- GMAC_SAMT1 : (GMAC Offset: 0xCC) (R/W 32) Specific Address 1 Mask Top [47:32] Register -------- */ 827 #define GMAC_SAMT1_RESETVALUE _UINT32_(0x00) /* (GMAC_SAMT1) Specific Address 1 Mask Top [47:32] Register Reset Value */ 828 829 #define GMAC_SAMT1_ADDR_Pos _UINT32_(0) /* (GMAC_SAMT1) Specific Address 1 Mask Position */ 830 #define GMAC_SAMT1_ADDR_Msk (_UINT32_(0xFFFF) << GMAC_SAMT1_ADDR_Pos) /* (GMAC_SAMT1) Specific Address 1 Mask Mask */ 831 #define GMAC_SAMT1_ADDR(value) (GMAC_SAMT1_ADDR_Msk & (_UINT32_(value) << GMAC_SAMT1_ADDR_Pos)) /* Assignment of value for ADDR in the GMAC_SAMT1 register */ 832 #define GMAC_SAMT1_Msk _UINT32_(0x0000FFFF) /* (GMAC_SAMT1) Register Mask */ 833 834 835 /* -------- GMAC_NSC : (GMAC Offset: 0xDC) (R/W 32) Tsu timer comparison nanoseconds Register -------- */ 836 #define GMAC_NSC_RESETVALUE _UINT32_(0x00) /* (GMAC_NSC) Tsu timer comparison nanoseconds Register Reset Value */ 837 838 #define GMAC_NSC_NANOSEC_Pos _UINT32_(0) /* (GMAC_NSC) 1588 Timer Nanosecond comparison value Position */ 839 #define GMAC_NSC_NANOSEC_Msk (_UINT32_(0x1FFFFF) << GMAC_NSC_NANOSEC_Pos) /* (GMAC_NSC) 1588 Timer Nanosecond comparison value Mask */ 840 #define GMAC_NSC_NANOSEC(value) (GMAC_NSC_NANOSEC_Msk & (_UINT32_(value) << GMAC_NSC_NANOSEC_Pos)) /* Assignment of value for NANOSEC in the GMAC_NSC register */ 841 #define GMAC_NSC_Msk _UINT32_(0x001FFFFF) /* (GMAC_NSC) Register Mask */ 842 843 844 /* -------- GMAC_SCL : (GMAC Offset: 0xE0) (R/W 32) Tsu timer second comparison Register -------- */ 845 #define GMAC_SCL_RESETVALUE _UINT32_(0x00) /* (GMAC_SCL) Tsu timer second comparison Register Reset Value */ 846 847 #define GMAC_SCL_SEC_Pos _UINT32_(0) /* (GMAC_SCL) 1588 Timer Second comparison value Position */ 848 #define GMAC_SCL_SEC_Msk (_UINT32_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos) /* (GMAC_SCL) 1588 Timer Second comparison value Mask */ 849 #define GMAC_SCL_SEC(value) (GMAC_SCL_SEC_Msk & (_UINT32_(value) << GMAC_SCL_SEC_Pos)) /* Assignment of value for SEC in the GMAC_SCL register */ 850 #define GMAC_SCL_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_SCL) Register Mask */ 851 852 853 /* -------- GMAC_SCH : (GMAC Offset: 0xE4) (R/W 32) Tsu timer second comparison Register -------- */ 854 #define GMAC_SCH_RESETVALUE _UINT32_(0x00) /* (GMAC_SCH) Tsu timer second comparison Register Reset Value */ 855 856 #define GMAC_SCH_SEC_Pos _UINT32_(0) /* (GMAC_SCH) 1588 Timer Second comparison value Position */ 857 #define GMAC_SCH_SEC_Msk (_UINT32_(0xFFFF) << GMAC_SCH_SEC_Pos) /* (GMAC_SCH) 1588 Timer Second comparison value Mask */ 858 #define GMAC_SCH_SEC(value) (GMAC_SCH_SEC_Msk & (_UINT32_(value) << GMAC_SCH_SEC_Pos)) /* Assignment of value for SEC in the GMAC_SCH register */ 859 #define GMAC_SCH_Msk _UINT32_(0x0000FFFF) /* (GMAC_SCH) Register Mask */ 860 861 862 /* -------- GMAC_EFTSH : (GMAC Offset: 0xE8) ( R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */ 863 #define GMAC_EFTSH_RESETVALUE _UINT32_(0x00) /* (GMAC_EFTSH) PTP Event Frame Transmitted Seconds High Register Reset Value */ 864 865 #define GMAC_EFTSH_RUD_Pos _UINT32_(0) /* (GMAC_EFTSH) Register Update Position */ 866 #define GMAC_EFTSH_RUD_Msk (_UINT32_(0xFFFF) << GMAC_EFTSH_RUD_Pos) /* (GMAC_EFTSH) Register Update Mask */ 867 #define GMAC_EFTSH_RUD(value) (GMAC_EFTSH_RUD_Msk & (_UINT32_(value) << GMAC_EFTSH_RUD_Pos)) /* Assignment of value for RUD in the GMAC_EFTSH register */ 868 #define GMAC_EFTSH_Msk _UINT32_(0x0000FFFF) /* (GMAC_EFTSH) Register Mask */ 869 870 871 /* -------- GMAC_EFRSH : (GMAC Offset: 0xEC) ( R/ 32) PTP Event Frame Received Seconds High Register -------- */ 872 #define GMAC_EFRSH_RESETVALUE _UINT32_(0x00) /* (GMAC_EFRSH) PTP Event Frame Received Seconds High Register Reset Value */ 873 874 #define GMAC_EFRSH_RUD_Pos _UINT32_(0) /* (GMAC_EFRSH) Register Update Position */ 875 #define GMAC_EFRSH_RUD_Msk (_UINT32_(0xFFFF) << GMAC_EFRSH_RUD_Pos) /* (GMAC_EFRSH) Register Update Mask */ 876 #define GMAC_EFRSH_RUD(value) (GMAC_EFRSH_RUD_Msk & (_UINT32_(value) << GMAC_EFRSH_RUD_Pos)) /* Assignment of value for RUD in the GMAC_EFRSH register */ 877 #define GMAC_EFRSH_Msk _UINT32_(0x0000FFFF) /* (GMAC_EFRSH) Register Mask */ 878 879 880 /* -------- GMAC_PEFTSH : (GMAC Offset: 0xF0) ( R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */ 881 #define GMAC_PEFTSH_RESETVALUE _UINT32_(0x00) /* (GMAC_PEFTSH) PTP Peer Event Frame Transmitted Seconds High Register Reset Value */ 882 883 #define GMAC_PEFTSH_RUD_Pos _UINT32_(0) /* (GMAC_PEFTSH) Register Update Position */ 884 #define GMAC_PEFTSH_RUD_Msk (_UINT32_(0xFFFF) << GMAC_PEFTSH_RUD_Pos) /* (GMAC_PEFTSH) Register Update Mask */ 885 #define GMAC_PEFTSH_RUD(value) (GMAC_PEFTSH_RUD_Msk & (_UINT32_(value) << GMAC_PEFTSH_RUD_Pos)) /* Assignment of value for RUD in the GMAC_PEFTSH register */ 886 #define GMAC_PEFTSH_Msk _UINT32_(0x0000FFFF) /* (GMAC_PEFTSH) Register Mask */ 887 888 889 /* -------- GMAC_PEFRSH : (GMAC Offset: 0xF4) ( R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */ 890 #define GMAC_PEFRSH_RESETVALUE _UINT32_(0x00) /* (GMAC_PEFRSH) PTP Peer Event Frame Received Seconds High Register Reset Value */ 891 892 #define GMAC_PEFRSH_RUD_Pos _UINT32_(0) /* (GMAC_PEFRSH) Register Update Position */ 893 #define GMAC_PEFRSH_RUD_Msk (_UINT32_(0xFFFF) << GMAC_PEFRSH_RUD_Pos) /* (GMAC_PEFRSH) Register Update Mask */ 894 #define GMAC_PEFRSH_RUD(value) (GMAC_PEFRSH_RUD_Msk & (_UINT32_(value) << GMAC_PEFRSH_RUD_Pos)) /* Assignment of value for RUD in the GMAC_PEFRSH register */ 895 #define GMAC_PEFRSH_Msk _UINT32_(0x0000FFFF) /* (GMAC_PEFRSH) Register Mask */ 896 897 898 /* -------- GMAC_OTLO : (GMAC Offset: 0x100) ( R/ 32) Octets Transmitted [31:0] Register -------- */ 899 #define GMAC_OTLO_RESETVALUE _UINT32_(0x00) /* (GMAC_OTLO) Octets Transmitted [31:0] Register Reset Value */ 900 901 #define GMAC_OTLO_TXO_Pos _UINT32_(0) /* (GMAC_OTLO) Transmitted Octets Position */ 902 #define GMAC_OTLO_TXO_Msk (_UINT32_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos) /* (GMAC_OTLO) Transmitted Octets Mask */ 903 #define GMAC_OTLO_TXO(value) (GMAC_OTLO_TXO_Msk & (_UINT32_(value) << GMAC_OTLO_TXO_Pos)) /* Assignment of value for TXO in the GMAC_OTLO register */ 904 #define GMAC_OTLO_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_OTLO) Register Mask */ 905 906 907 /* -------- GMAC_OTHI : (GMAC Offset: 0x104) ( R/ 32) Octets Transmitted [47:32] Register -------- */ 908 #define GMAC_OTHI_RESETVALUE _UINT32_(0x00) /* (GMAC_OTHI) Octets Transmitted [47:32] Register Reset Value */ 909 910 #define GMAC_OTHI_TXO_Pos _UINT32_(0) /* (GMAC_OTHI) Transmitted Octets Position */ 911 #define GMAC_OTHI_TXO_Msk (_UINT32_(0xFFFF) << GMAC_OTHI_TXO_Pos) /* (GMAC_OTHI) Transmitted Octets Mask */ 912 #define GMAC_OTHI_TXO(value) (GMAC_OTHI_TXO_Msk & (_UINT32_(value) << GMAC_OTHI_TXO_Pos)) /* Assignment of value for TXO in the GMAC_OTHI register */ 913 #define GMAC_OTHI_Msk _UINT32_(0x0000FFFF) /* (GMAC_OTHI) Register Mask */ 914 915 916 /* -------- GMAC_FT : (GMAC Offset: 0x108) ( R/ 32) Frames Transmitted Register -------- */ 917 #define GMAC_FT_RESETVALUE _UINT32_(0x00) /* (GMAC_FT) Frames Transmitted Register Reset Value */ 918 919 #define GMAC_FT_FTX_Pos _UINT32_(0) /* (GMAC_FT) Frames Transmitted without Error Position */ 920 #define GMAC_FT_FTX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_FT_FTX_Pos) /* (GMAC_FT) Frames Transmitted without Error Mask */ 921 #define GMAC_FT_FTX(value) (GMAC_FT_FTX_Msk & (_UINT32_(value) << GMAC_FT_FTX_Pos)) /* Assignment of value for FTX in the GMAC_FT register */ 922 #define GMAC_FT_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_FT) Register Mask */ 923 924 925 /* -------- GMAC_BCFT : (GMAC Offset: 0x10C) ( R/ 32) Broadcast Frames Transmitted Register -------- */ 926 #define GMAC_BCFT_RESETVALUE _UINT32_(0x00) /* (GMAC_BCFT) Broadcast Frames Transmitted Register Reset Value */ 927 928 #define GMAC_BCFT_BFTX_Pos _UINT32_(0) /* (GMAC_BCFT) Broadcast Frames Transmitted without Error Position */ 929 #define GMAC_BCFT_BFTX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos) /* (GMAC_BCFT) Broadcast Frames Transmitted without Error Mask */ 930 #define GMAC_BCFT_BFTX(value) (GMAC_BCFT_BFTX_Msk & (_UINT32_(value) << GMAC_BCFT_BFTX_Pos)) /* Assignment of value for BFTX in the GMAC_BCFT register */ 931 #define GMAC_BCFT_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_BCFT) Register Mask */ 932 933 934 /* -------- GMAC_MFT : (GMAC Offset: 0x110) ( R/ 32) Multicast Frames Transmitted Register -------- */ 935 #define GMAC_MFT_RESETVALUE _UINT32_(0x00) /* (GMAC_MFT) Multicast Frames Transmitted Register Reset Value */ 936 937 #define GMAC_MFT_MFTX_Pos _UINT32_(0) /* (GMAC_MFT) Multicast Frames Transmitted without Error Position */ 938 #define GMAC_MFT_MFTX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos) /* (GMAC_MFT) Multicast Frames Transmitted without Error Mask */ 939 #define GMAC_MFT_MFTX(value) (GMAC_MFT_MFTX_Msk & (_UINT32_(value) << GMAC_MFT_MFTX_Pos)) /* Assignment of value for MFTX in the GMAC_MFT register */ 940 #define GMAC_MFT_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_MFT) Register Mask */ 941 942 943 /* -------- GMAC_PFT : (GMAC Offset: 0x114) ( R/ 32) Pause Frames Transmitted Register -------- */ 944 #define GMAC_PFT_RESETVALUE _UINT32_(0x00) /* (GMAC_PFT) Pause Frames Transmitted Register Reset Value */ 945 946 #define GMAC_PFT_PFTX_Pos _UINT32_(0) /* (GMAC_PFT) Pause Frames Transmitted Register Position */ 947 #define GMAC_PFT_PFTX_Msk (_UINT32_(0xFFFF) << GMAC_PFT_PFTX_Pos) /* (GMAC_PFT) Pause Frames Transmitted Register Mask */ 948 #define GMAC_PFT_PFTX(value) (GMAC_PFT_PFTX_Msk & (_UINT32_(value) << GMAC_PFT_PFTX_Pos)) /* Assignment of value for PFTX in the GMAC_PFT register */ 949 #define GMAC_PFT_Msk _UINT32_(0x0000FFFF) /* (GMAC_PFT) Register Mask */ 950 951 952 /* -------- GMAC_BFT64 : (GMAC Offset: 0x118) ( R/ 32) 64 Byte Frames Transmitted Register -------- */ 953 #define GMAC_BFT64_RESETVALUE _UINT32_(0x00) /* (GMAC_BFT64) 64 Byte Frames Transmitted Register Reset Value */ 954 955 #define GMAC_BFT64_NFTX_Pos _UINT32_(0) /* (GMAC_BFT64) 64 Byte Frames Transmitted without Error Position */ 956 #define GMAC_BFT64_NFTX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos) /* (GMAC_BFT64) 64 Byte Frames Transmitted without Error Mask */ 957 #define GMAC_BFT64_NFTX(value) (GMAC_BFT64_NFTX_Msk & (_UINT32_(value) << GMAC_BFT64_NFTX_Pos)) /* Assignment of value for NFTX in the GMAC_BFT64 register */ 958 #define GMAC_BFT64_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_BFT64) Register Mask */ 959 960 961 /* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) ( R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */ 962 #define GMAC_TBFT127_RESETVALUE _UINT32_(0x00) /* (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted Register Reset Value */ 963 964 #define GMAC_TBFT127_NFTX_Pos _UINT32_(0) /* (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Position */ 965 #define GMAC_TBFT127_NFTX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos) /* (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Mask */ 966 #define GMAC_TBFT127_NFTX(value) (GMAC_TBFT127_NFTX_Msk & (_UINT32_(value) << GMAC_TBFT127_NFTX_Pos)) /* Assignment of value for NFTX in the GMAC_TBFT127 register */ 967 #define GMAC_TBFT127_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TBFT127) Register Mask */ 968 969 970 /* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) ( R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */ 971 #define GMAC_TBFT255_RESETVALUE _UINT32_(0x00) /* (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted Register Reset Value */ 972 973 #define GMAC_TBFT255_NFTX_Pos _UINT32_(0) /* (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Position */ 974 #define GMAC_TBFT255_NFTX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos) /* (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Mask */ 975 #define GMAC_TBFT255_NFTX(value) (GMAC_TBFT255_NFTX_Msk & (_UINT32_(value) << GMAC_TBFT255_NFTX_Pos)) /* Assignment of value for NFTX in the GMAC_TBFT255 register */ 976 #define GMAC_TBFT255_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TBFT255) Register Mask */ 977 978 979 /* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) ( R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */ 980 #define GMAC_TBFT511_RESETVALUE _UINT32_(0x00) /* (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted Register Reset Value */ 981 982 #define GMAC_TBFT511_NFTX_Pos _UINT32_(0) /* (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Position */ 983 #define GMAC_TBFT511_NFTX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos) /* (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Mask */ 984 #define GMAC_TBFT511_NFTX(value) (GMAC_TBFT511_NFTX_Msk & (_UINT32_(value) << GMAC_TBFT511_NFTX_Pos)) /* Assignment of value for NFTX in the GMAC_TBFT511 register */ 985 #define GMAC_TBFT511_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TBFT511) Register Mask */ 986 987 988 /* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) ( R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */ 989 #define GMAC_TBFT1023_RESETVALUE _UINT32_(0x00) /* (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted Register Reset Value */ 990 991 #define GMAC_TBFT1023_NFTX_Pos _UINT32_(0) /* (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Position */ 992 #define GMAC_TBFT1023_NFTX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos) /* (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Mask */ 993 #define GMAC_TBFT1023_NFTX(value) (GMAC_TBFT1023_NFTX_Msk & (_UINT32_(value) << GMAC_TBFT1023_NFTX_Pos)) /* Assignment of value for NFTX in the GMAC_TBFT1023 register */ 994 #define GMAC_TBFT1023_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TBFT1023) Register Mask */ 995 996 997 /* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) ( R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */ 998 #define GMAC_TBFT1518_RESETVALUE _UINT32_(0x00) /* (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted Register Reset Value */ 999 1000 #define GMAC_TBFT1518_NFTX_Pos _UINT32_(0) /* (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Position */ 1001 #define GMAC_TBFT1518_NFTX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos) /* (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Mask */ 1002 #define GMAC_TBFT1518_NFTX(value) (GMAC_TBFT1518_NFTX_Msk & (_UINT32_(value) << GMAC_TBFT1518_NFTX_Pos)) /* Assignment of value for NFTX in the GMAC_TBFT1518 register */ 1003 #define GMAC_TBFT1518_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TBFT1518) Register Mask */ 1004 1005 1006 /* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) ( R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */ 1007 #define GMAC_GTBFT1518_RESETVALUE _UINT32_(0x00) /* (GMAC_GTBFT1518) Greater Than 1518 Byte Frames Transmitted Register Reset Value */ 1008 1009 #define GMAC_GTBFT1518_NFTX_Pos _UINT32_(0) /* (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Position */ 1010 #define GMAC_GTBFT1518_NFTX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos) /* (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Mask */ 1011 #define GMAC_GTBFT1518_NFTX(value) (GMAC_GTBFT1518_NFTX_Msk & (_UINT32_(value) << GMAC_GTBFT1518_NFTX_Pos)) /* Assignment of value for NFTX in the GMAC_GTBFT1518 register */ 1012 #define GMAC_GTBFT1518_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_GTBFT1518) Register Mask */ 1013 1014 1015 /* -------- GMAC_TUR : (GMAC Offset: 0x134) ( R/ 32) Transmit Underruns Register -------- */ 1016 #define GMAC_TUR_RESETVALUE _UINT32_(0x00) /* (GMAC_TUR) Transmit Underruns Register Reset Value */ 1017 1018 #define GMAC_TUR_TXUNR_Pos _UINT32_(0) /* (GMAC_TUR) Transmit Underruns Position */ 1019 #define GMAC_TUR_TXUNR_Msk (_UINT32_(0x3FF) << GMAC_TUR_TXUNR_Pos) /* (GMAC_TUR) Transmit Underruns Mask */ 1020 #define GMAC_TUR_TXUNR(value) (GMAC_TUR_TXUNR_Msk & (_UINT32_(value) << GMAC_TUR_TXUNR_Pos)) /* Assignment of value for TXUNR in the GMAC_TUR register */ 1021 #define GMAC_TUR_Msk _UINT32_(0x000003FF) /* (GMAC_TUR) Register Mask */ 1022 1023 1024 /* -------- GMAC_SCF : (GMAC Offset: 0x138) ( R/ 32) Single Collision Frames Register -------- */ 1025 #define GMAC_SCF_RESETVALUE _UINT32_(0x00) /* (GMAC_SCF) Single Collision Frames Register Reset Value */ 1026 1027 #define GMAC_SCF_SCOL_Pos _UINT32_(0) /* (GMAC_SCF) Single Collision Position */ 1028 #define GMAC_SCF_SCOL_Msk (_UINT32_(0x3FFFF) << GMAC_SCF_SCOL_Pos) /* (GMAC_SCF) Single Collision Mask */ 1029 #define GMAC_SCF_SCOL(value) (GMAC_SCF_SCOL_Msk & (_UINT32_(value) << GMAC_SCF_SCOL_Pos)) /* Assignment of value for SCOL in the GMAC_SCF register */ 1030 #define GMAC_SCF_Msk _UINT32_(0x0003FFFF) /* (GMAC_SCF) Register Mask */ 1031 1032 1033 /* -------- GMAC_MCF : (GMAC Offset: 0x13C) ( R/ 32) Multiple Collision Frames Register -------- */ 1034 #define GMAC_MCF_RESETVALUE _UINT32_(0x00) /* (GMAC_MCF) Multiple Collision Frames Register Reset Value */ 1035 1036 #define GMAC_MCF_MCOL_Pos _UINT32_(0) /* (GMAC_MCF) Multiple Collision Position */ 1037 #define GMAC_MCF_MCOL_Msk (_UINT32_(0x3FFFF) << GMAC_MCF_MCOL_Pos) /* (GMAC_MCF) Multiple Collision Mask */ 1038 #define GMAC_MCF_MCOL(value) (GMAC_MCF_MCOL_Msk & (_UINT32_(value) << GMAC_MCF_MCOL_Pos)) /* Assignment of value for MCOL in the GMAC_MCF register */ 1039 #define GMAC_MCF_Msk _UINT32_(0x0003FFFF) /* (GMAC_MCF) Register Mask */ 1040 1041 1042 /* -------- GMAC_EC : (GMAC Offset: 0x140) ( R/ 32) Excessive Collisions Register -------- */ 1043 #define GMAC_EC_RESETVALUE _UINT32_(0x00) /* (GMAC_EC) Excessive Collisions Register Reset Value */ 1044 1045 #define GMAC_EC_XCOL_Pos _UINT32_(0) /* (GMAC_EC) Excessive Collisions Position */ 1046 #define GMAC_EC_XCOL_Msk (_UINT32_(0x3FF) << GMAC_EC_XCOL_Pos) /* (GMAC_EC) Excessive Collisions Mask */ 1047 #define GMAC_EC_XCOL(value) (GMAC_EC_XCOL_Msk & (_UINT32_(value) << GMAC_EC_XCOL_Pos)) /* Assignment of value for XCOL in the GMAC_EC register */ 1048 #define GMAC_EC_Msk _UINT32_(0x000003FF) /* (GMAC_EC) Register Mask */ 1049 1050 1051 /* -------- GMAC_LC : (GMAC Offset: 0x144) ( R/ 32) Late Collisions Register -------- */ 1052 #define GMAC_LC_RESETVALUE _UINT32_(0x00) /* (GMAC_LC) Late Collisions Register Reset Value */ 1053 1054 #define GMAC_LC_LCOL_Pos _UINT32_(0) /* (GMAC_LC) Late Collisions Position */ 1055 #define GMAC_LC_LCOL_Msk (_UINT32_(0x3FF) << GMAC_LC_LCOL_Pos) /* (GMAC_LC) Late Collisions Mask */ 1056 #define GMAC_LC_LCOL(value) (GMAC_LC_LCOL_Msk & (_UINT32_(value) << GMAC_LC_LCOL_Pos)) /* Assignment of value for LCOL in the GMAC_LC register */ 1057 #define GMAC_LC_Msk _UINT32_(0x000003FF) /* (GMAC_LC) Register Mask */ 1058 1059 1060 /* -------- GMAC_DTF : (GMAC Offset: 0x148) ( R/ 32) Deferred Transmission Frames Register -------- */ 1061 #define GMAC_DTF_RESETVALUE _UINT32_(0x00) /* (GMAC_DTF) Deferred Transmission Frames Register Reset Value */ 1062 1063 #define GMAC_DTF_DEFT_Pos _UINT32_(0) /* (GMAC_DTF) Deferred Transmission Position */ 1064 #define GMAC_DTF_DEFT_Msk (_UINT32_(0x3FFFF) << GMAC_DTF_DEFT_Pos) /* (GMAC_DTF) Deferred Transmission Mask */ 1065 #define GMAC_DTF_DEFT(value) (GMAC_DTF_DEFT_Msk & (_UINT32_(value) << GMAC_DTF_DEFT_Pos)) /* Assignment of value for DEFT in the GMAC_DTF register */ 1066 #define GMAC_DTF_Msk _UINT32_(0x0003FFFF) /* (GMAC_DTF) Register Mask */ 1067 1068 1069 /* -------- GMAC_CSE : (GMAC Offset: 0x14C) ( R/ 32) Carrier Sense Errors Register -------- */ 1070 #define GMAC_CSE_RESETVALUE _UINT32_(0x00) /* (GMAC_CSE) Carrier Sense Errors Register Reset Value */ 1071 1072 #define GMAC_CSE_CSR_Pos _UINT32_(0) /* (GMAC_CSE) Carrier Sense Error Position */ 1073 #define GMAC_CSE_CSR_Msk (_UINT32_(0x3FF) << GMAC_CSE_CSR_Pos) /* (GMAC_CSE) Carrier Sense Error Mask */ 1074 #define GMAC_CSE_CSR(value) (GMAC_CSE_CSR_Msk & (_UINT32_(value) << GMAC_CSE_CSR_Pos)) /* Assignment of value for CSR in the GMAC_CSE register */ 1075 #define GMAC_CSE_Msk _UINT32_(0x000003FF) /* (GMAC_CSE) Register Mask */ 1076 1077 1078 /* -------- GMAC_ORLO : (GMAC Offset: 0x150) ( R/ 32) Octets Received [31:0] Received -------- */ 1079 #define GMAC_ORLO_RESETVALUE _UINT32_(0x00) /* (GMAC_ORLO) Octets Received [31:0] Received Reset Value */ 1080 1081 #define GMAC_ORLO_RXO_Pos _UINT32_(0) /* (GMAC_ORLO) Received Octets Position */ 1082 #define GMAC_ORLO_RXO_Msk (_UINT32_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos) /* (GMAC_ORLO) Received Octets Mask */ 1083 #define GMAC_ORLO_RXO(value) (GMAC_ORLO_RXO_Msk & (_UINT32_(value) << GMAC_ORLO_RXO_Pos)) /* Assignment of value for RXO in the GMAC_ORLO register */ 1084 #define GMAC_ORLO_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_ORLO) Register Mask */ 1085 1086 1087 /* -------- GMAC_ORHI : (GMAC Offset: 0x154) ( R/ 32) Octets Received [47:32] Received -------- */ 1088 #define GMAC_ORHI_RESETVALUE _UINT32_(0x00) /* (GMAC_ORHI) Octets Received [47:32] Received Reset Value */ 1089 1090 #define GMAC_ORHI_RXO_Pos _UINT32_(0) /* (GMAC_ORHI) Received Octets Position */ 1091 #define GMAC_ORHI_RXO_Msk (_UINT32_(0xFFFF) << GMAC_ORHI_RXO_Pos) /* (GMAC_ORHI) Received Octets Mask */ 1092 #define GMAC_ORHI_RXO(value) (GMAC_ORHI_RXO_Msk & (_UINT32_(value) << GMAC_ORHI_RXO_Pos)) /* Assignment of value for RXO in the GMAC_ORHI register */ 1093 #define GMAC_ORHI_Msk _UINT32_(0x0000FFFF) /* (GMAC_ORHI) Register Mask */ 1094 1095 1096 /* -------- GMAC_FR : (GMAC Offset: 0x158) ( R/ 32) Frames Received Register -------- */ 1097 #define GMAC_FR_RESETVALUE _UINT32_(0x00) /* (GMAC_FR) Frames Received Register Reset Value */ 1098 1099 #define GMAC_FR_FRX_Pos _UINT32_(0) /* (GMAC_FR) Frames Received without Error Position */ 1100 #define GMAC_FR_FRX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_FR_FRX_Pos) /* (GMAC_FR) Frames Received without Error Mask */ 1101 #define GMAC_FR_FRX(value) (GMAC_FR_FRX_Msk & (_UINT32_(value) << GMAC_FR_FRX_Pos)) /* Assignment of value for FRX in the GMAC_FR register */ 1102 #define GMAC_FR_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_FR) Register Mask */ 1103 1104 1105 /* -------- GMAC_BCFR : (GMAC Offset: 0x15C) ( R/ 32) Broadcast Frames Received Register -------- */ 1106 #define GMAC_BCFR_RESETVALUE _UINT32_(0x00) /* (GMAC_BCFR) Broadcast Frames Received Register Reset Value */ 1107 1108 #define GMAC_BCFR_BFRX_Pos _UINT32_(0) /* (GMAC_BCFR) Broadcast Frames Received without Error Position */ 1109 #define GMAC_BCFR_BFRX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos) /* (GMAC_BCFR) Broadcast Frames Received without Error Mask */ 1110 #define GMAC_BCFR_BFRX(value) (GMAC_BCFR_BFRX_Msk & (_UINT32_(value) << GMAC_BCFR_BFRX_Pos)) /* Assignment of value for BFRX in the GMAC_BCFR register */ 1111 #define GMAC_BCFR_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_BCFR) Register Mask */ 1112 1113 1114 /* -------- GMAC_MFR : (GMAC Offset: 0x160) ( R/ 32) Multicast Frames Received Register -------- */ 1115 #define GMAC_MFR_RESETVALUE _UINT32_(0x00) /* (GMAC_MFR) Multicast Frames Received Register Reset Value */ 1116 1117 #define GMAC_MFR_MFRX_Pos _UINT32_(0) /* (GMAC_MFR) Multicast Frames Received without Error Position */ 1118 #define GMAC_MFR_MFRX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos) /* (GMAC_MFR) Multicast Frames Received without Error Mask */ 1119 #define GMAC_MFR_MFRX(value) (GMAC_MFR_MFRX_Msk & (_UINT32_(value) << GMAC_MFR_MFRX_Pos)) /* Assignment of value for MFRX in the GMAC_MFR register */ 1120 #define GMAC_MFR_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_MFR) Register Mask */ 1121 1122 1123 /* -------- GMAC_PFR : (GMAC Offset: 0x164) ( R/ 32) Pause Frames Received Register -------- */ 1124 #define GMAC_PFR_RESETVALUE _UINT32_(0x00) /* (GMAC_PFR) Pause Frames Received Register Reset Value */ 1125 1126 #define GMAC_PFR_PFRX_Pos _UINT32_(0) /* (GMAC_PFR) Pause Frames Received Register Position */ 1127 #define GMAC_PFR_PFRX_Msk (_UINT32_(0xFFFF) << GMAC_PFR_PFRX_Pos) /* (GMAC_PFR) Pause Frames Received Register Mask */ 1128 #define GMAC_PFR_PFRX(value) (GMAC_PFR_PFRX_Msk & (_UINT32_(value) << GMAC_PFR_PFRX_Pos)) /* Assignment of value for PFRX in the GMAC_PFR register */ 1129 #define GMAC_PFR_Msk _UINT32_(0x0000FFFF) /* (GMAC_PFR) Register Mask */ 1130 1131 1132 /* -------- GMAC_BFR64 : (GMAC Offset: 0x168) ( R/ 32) 64 Byte Frames Received Register -------- */ 1133 #define GMAC_BFR64_RESETVALUE _UINT32_(0x00) /* (GMAC_BFR64) 64 Byte Frames Received Register Reset Value */ 1134 1135 #define GMAC_BFR64_NFRX_Pos _UINT32_(0) /* (GMAC_BFR64) 64 Byte Frames Received without Error Position */ 1136 #define GMAC_BFR64_NFRX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos) /* (GMAC_BFR64) 64 Byte Frames Received without Error Mask */ 1137 #define GMAC_BFR64_NFRX(value) (GMAC_BFR64_NFRX_Msk & (_UINT32_(value) << GMAC_BFR64_NFRX_Pos)) /* Assignment of value for NFRX in the GMAC_BFR64 register */ 1138 #define GMAC_BFR64_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_BFR64) Register Mask */ 1139 1140 1141 /* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) ( R/ 32) 65 to 127 Byte Frames Received Register -------- */ 1142 #define GMAC_TBFR127_RESETVALUE _UINT32_(0x00) /* (GMAC_TBFR127) 65 to 127 Byte Frames Received Register Reset Value */ 1143 1144 #define GMAC_TBFR127_NFRX_Pos _UINT32_(0) /* (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Position */ 1145 #define GMAC_TBFR127_NFRX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos) /* (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Mask */ 1146 #define GMAC_TBFR127_NFRX(value) (GMAC_TBFR127_NFRX_Msk & (_UINT32_(value) << GMAC_TBFR127_NFRX_Pos)) /* Assignment of value for NFRX in the GMAC_TBFR127 register */ 1147 #define GMAC_TBFR127_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TBFR127) Register Mask */ 1148 1149 1150 /* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) ( R/ 32) 128 to 255 Byte Frames Received Register -------- */ 1151 #define GMAC_TBFR255_RESETVALUE _UINT32_(0x00) /* (GMAC_TBFR255) 128 to 255 Byte Frames Received Register Reset Value */ 1152 1153 #define GMAC_TBFR255_NFRX_Pos _UINT32_(0) /* (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Position */ 1154 #define GMAC_TBFR255_NFRX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos) /* (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Mask */ 1155 #define GMAC_TBFR255_NFRX(value) (GMAC_TBFR255_NFRX_Msk & (_UINT32_(value) << GMAC_TBFR255_NFRX_Pos)) /* Assignment of value for NFRX in the GMAC_TBFR255 register */ 1156 #define GMAC_TBFR255_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TBFR255) Register Mask */ 1157 1158 1159 /* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) ( R/ 32) 256 to 511Byte Frames Received Register -------- */ 1160 #define GMAC_TBFR511_RESETVALUE _UINT32_(0x00) /* (GMAC_TBFR511) 256 to 511Byte Frames Received Register Reset Value */ 1161 1162 #define GMAC_TBFR511_NFRX_Pos _UINT32_(0) /* (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Position */ 1163 #define GMAC_TBFR511_NFRX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos) /* (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Mask */ 1164 #define GMAC_TBFR511_NFRX(value) (GMAC_TBFR511_NFRX_Msk & (_UINT32_(value) << GMAC_TBFR511_NFRX_Pos)) /* Assignment of value for NFRX in the GMAC_TBFR511 register */ 1165 #define GMAC_TBFR511_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TBFR511) Register Mask */ 1166 1167 1168 /* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) ( R/ 32) 512 to 1023 Byte Frames Received Register -------- */ 1169 #define GMAC_TBFR1023_RESETVALUE _UINT32_(0x00) /* (GMAC_TBFR1023) 512 to 1023 Byte Frames Received Register Reset Value */ 1170 1171 #define GMAC_TBFR1023_NFRX_Pos _UINT32_(0) /* (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Position */ 1172 #define GMAC_TBFR1023_NFRX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos) /* (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Mask */ 1173 #define GMAC_TBFR1023_NFRX(value) (GMAC_TBFR1023_NFRX_Msk & (_UINT32_(value) << GMAC_TBFR1023_NFRX_Pos)) /* Assignment of value for NFRX in the GMAC_TBFR1023 register */ 1174 #define GMAC_TBFR1023_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TBFR1023) Register Mask */ 1175 1176 1177 /* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) ( R/ 32) 1024 to 1518 Byte Frames Received Register -------- */ 1178 #define GMAC_TBFR1518_RESETVALUE _UINT32_(0x00) /* (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received Register Reset Value */ 1179 1180 #define GMAC_TBFR1518_NFRX_Pos _UINT32_(0) /* (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Position */ 1181 #define GMAC_TBFR1518_NFRX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos) /* (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Mask */ 1182 #define GMAC_TBFR1518_NFRX(value) (GMAC_TBFR1518_NFRX_Msk & (_UINT32_(value) << GMAC_TBFR1518_NFRX_Pos)) /* Assignment of value for NFRX in the GMAC_TBFR1518 register */ 1183 #define GMAC_TBFR1518_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TBFR1518) Register Mask */ 1184 1185 1186 /* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) ( R/ 32) 1519 to Maximum Byte Frames Received Register -------- */ 1187 #define GMAC_TMXBFR_RESETVALUE _UINT32_(0x00) /* (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received Register Reset Value */ 1188 1189 #define GMAC_TMXBFR_NFRX_Pos _UINT32_(0) /* (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Position */ 1190 #define GMAC_TMXBFR_NFRX_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos) /* (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Mask */ 1191 #define GMAC_TMXBFR_NFRX(value) (GMAC_TMXBFR_NFRX_Msk & (_UINT32_(value) << GMAC_TMXBFR_NFRX_Pos)) /* Assignment of value for NFRX in the GMAC_TMXBFR register */ 1192 #define GMAC_TMXBFR_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TMXBFR) Register Mask */ 1193 1194 1195 /* -------- GMAC_UFR : (GMAC Offset: 0x184) ( R/ 32) Undersize Frames Received Register -------- */ 1196 #define GMAC_UFR_RESETVALUE _UINT32_(0x00) /* (GMAC_UFR) Undersize Frames Received Register Reset Value */ 1197 1198 #define GMAC_UFR_UFRX_Pos _UINT32_(0) /* (GMAC_UFR) Undersize Frames Received Position */ 1199 #define GMAC_UFR_UFRX_Msk (_UINT32_(0x3FF) << GMAC_UFR_UFRX_Pos) /* (GMAC_UFR) Undersize Frames Received Mask */ 1200 #define GMAC_UFR_UFRX(value) (GMAC_UFR_UFRX_Msk & (_UINT32_(value) << GMAC_UFR_UFRX_Pos)) /* Assignment of value for UFRX in the GMAC_UFR register */ 1201 #define GMAC_UFR_Msk _UINT32_(0x000003FF) /* (GMAC_UFR) Register Mask */ 1202 1203 1204 /* -------- GMAC_OFR : (GMAC Offset: 0x188) ( R/ 32) Oversize Frames Received Register -------- */ 1205 #define GMAC_OFR_RESETVALUE _UINT32_(0x00) /* (GMAC_OFR) Oversize Frames Received Register Reset Value */ 1206 1207 #define GMAC_OFR_OFRX_Pos _UINT32_(0) /* (GMAC_OFR) Oversized Frames Received Position */ 1208 #define GMAC_OFR_OFRX_Msk (_UINT32_(0x3FF) << GMAC_OFR_OFRX_Pos) /* (GMAC_OFR) Oversized Frames Received Mask */ 1209 #define GMAC_OFR_OFRX(value) (GMAC_OFR_OFRX_Msk & (_UINT32_(value) << GMAC_OFR_OFRX_Pos)) /* Assignment of value for OFRX in the GMAC_OFR register */ 1210 #define GMAC_OFR_Msk _UINT32_(0x000003FF) /* (GMAC_OFR) Register Mask */ 1211 1212 1213 /* -------- GMAC_JR : (GMAC Offset: 0x18C) ( R/ 32) Jabbers Received Register -------- */ 1214 #define GMAC_JR_RESETVALUE _UINT32_(0x00) /* (GMAC_JR) Jabbers Received Register Reset Value */ 1215 1216 #define GMAC_JR_JRX_Pos _UINT32_(0) /* (GMAC_JR) Jabbers Received Position */ 1217 #define GMAC_JR_JRX_Msk (_UINT32_(0x3FF) << GMAC_JR_JRX_Pos) /* (GMAC_JR) Jabbers Received Mask */ 1218 #define GMAC_JR_JRX(value) (GMAC_JR_JRX_Msk & (_UINT32_(value) << GMAC_JR_JRX_Pos)) /* Assignment of value for JRX in the GMAC_JR register */ 1219 #define GMAC_JR_Msk _UINT32_(0x000003FF) /* (GMAC_JR) Register Mask */ 1220 1221 1222 /* -------- GMAC_FCSE : (GMAC Offset: 0x190) ( R/ 32) Frame Check Sequence Errors Register -------- */ 1223 #define GMAC_FCSE_RESETVALUE _UINT32_(0x00) /* (GMAC_FCSE) Frame Check Sequence Errors Register Reset Value */ 1224 1225 #define GMAC_FCSE_FCKR_Pos _UINT32_(0) /* (GMAC_FCSE) Frame Check Sequence Errors Position */ 1226 #define GMAC_FCSE_FCKR_Msk (_UINT32_(0x3FF) << GMAC_FCSE_FCKR_Pos) /* (GMAC_FCSE) Frame Check Sequence Errors Mask */ 1227 #define GMAC_FCSE_FCKR(value) (GMAC_FCSE_FCKR_Msk & (_UINT32_(value) << GMAC_FCSE_FCKR_Pos)) /* Assignment of value for FCKR in the GMAC_FCSE register */ 1228 #define GMAC_FCSE_Msk _UINT32_(0x000003FF) /* (GMAC_FCSE) Register Mask */ 1229 1230 1231 /* -------- GMAC_LFFE : (GMAC Offset: 0x194) ( R/ 32) Length Field Frame Errors Register -------- */ 1232 #define GMAC_LFFE_RESETVALUE _UINT32_(0x00) /* (GMAC_LFFE) Length Field Frame Errors Register Reset Value */ 1233 1234 #define GMAC_LFFE_LFER_Pos _UINT32_(0) /* (GMAC_LFFE) Length Field Frame Errors Position */ 1235 #define GMAC_LFFE_LFER_Msk (_UINT32_(0x3FF) << GMAC_LFFE_LFER_Pos) /* (GMAC_LFFE) Length Field Frame Errors Mask */ 1236 #define GMAC_LFFE_LFER(value) (GMAC_LFFE_LFER_Msk & (_UINT32_(value) << GMAC_LFFE_LFER_Pos)) /* Assignment of value for LFER in the GMAC_LFFE register */ 1237 #define GMAC_LFFE_Msk _UINT32_(0x000003FF) /* (GMAC_LFFE) Register Mask */ 1238 1239 1240 /* -------- GMAC_RSE : (GMAC Offset: 0x198) ( R/ 32) Receive Symbol Errors Register -------- */ 1241 #define GMAC_RSE_RESETVALUE _UINT32_(0x00) /* (GMAC_RSE) Receive Symbol Errors Register Reset Value */ 1242 1243 #define GMAC_RSE_RXSE_Pos _UINT32_(0) /* (GMAC_RSE) Receive Symbol Errors Position */ 1244 #define GMAC_RSE_RXSE_Msk (_UINT32_(0x3FF) << GMAC_RSE_RXSE_Pos) /* (GMAC_RSE) Receive Symbol Errors Mask */ 1245 #define GMAC_RSE_RXSE(value) (GMAC_RSE_RXSE_Msk & (_UINT32_(value) << GMAC_RSE_RXSE_Pos)) /* Assignment of value for RXSE in the GMAC_RSE register */ 1246 #define GMAC_RSE_Msk _UINT32_(0x000003FF) /* (GMAC_RSE) Register Mask */ 1247 1248 1249 /* -------- GMAC_AE : (GMAC Offset: 0x19C) ( R/ 32) Alignment Errors Register -------- */ 1250 #define GMAC_AE_RESETVALUE _UINT32_(0x00) /* (GMAC_AE) Alignment Errors Register Reset Value */ 1251 1252 #define GMAC_AE_AER_Pos _UINT32_(0) /* (GMAC_AE) Alignment Errors Position */ 1253 #define GMAC_AE_AER_Msk (_UINT32_(0x3FF) << GMAC_AE_AER_Pos) /* (GMAC_AE) Alignment Errors Mask */ 1254 #define GMAC_AE_AER(value) (GMAC_AE_AER_Msk & (_UINT32_(value) << GMAC_AE_AER_Pos)) /* Assignment of value for AER in the GMAC_AE register */ 1255 #define GMAC_AE_Msk _UINT32_(0x000003FF) /* (GMAC_AE) Register Mask */ 1256 1257 1258 /* -------- GMAC_RRE : (GMAC Offset: 0x1A0) ( R/ 32) Receive Resource Errors Register -------- */ 1259 #define GMAC_RRE_RESETVALUE _UINT32_(0x00) /* (GMAC_RRE) Receive Resource Errors Register Reset Value */ 1260 1261 #define GMAC_RRE_RXRER_Pos _UINT32_(0) /* (GMAC_RRE) Receive Resource Errors Position */ 1262 #define GMAC_RRE_RXRER_Msk (_UINT32_(0x3FFFF) << GMAC_RRE_RXRER_Pos) /* (GMAC_RRE) Receive Resource Errors Mask */ 1263 #define GMAC_RRE_RXRER(value) (GMAC_RRE_RXRER_Msk & (_UINT32_(value) << GMAC_RRE_RXRER_Pos)) /* Assignment of value for RXRER in the GMAC_RRE register */ 1264 #define GMAC_RRE_Msk _UINT32_(0x0003FFFF) /* (GMAC_RRE) Register Mask */ 1265 1266 1267 /* -------- GMAC_ROE : (GMAC Offset: 0x1A4) ( R/ 32) Receive Overrun Register -------- */ 1268 #define GMAC_ROE_RESETVALUE _UINT32_(0x00) /* (GMAC_ROE) Receive Overrun Register Reset Value */ 1269 1270 #define GMAC_ROE_RXOVR_Pos _UINT32_(0) /* (GMAC_ROE) Receive Overruns Position */ 1271 #define GMAC_ROE_RXOVR_Msk (_UINT32_(0x3FF) << GMAC_ROE_RXOVR_Pos) /* (GMAC_ROE) Receive Overruns Mask */ 1272 #define GMAC_ROE_RXOVR(value) (GMAC_ROE_RXOVR_Msk & (_UINT32_(value) << GMAC_ROE_RXOVR_Pos)) /* Assignment of value for RXOVR in the GMAC_ROE register */ 1273 #define GMAC_ROE_Msk _UINT32_(0x000003FF) /* (GMAC_ROE) Register Mask */ 1274 1275 1276 /* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) ( R/ 32) IP Header Checksum Errors Register -------- */ 1277 #define GMAC_IHCE_RESETVALUE _UINT32_(0x00) /* (GMAC_IHCE) IP Header Checksum Errors Register Reset Value */ 1278 1279 #define GMAC_IHCE_HCKER_Pos _UINT32_(0) /* (GMAC_IHCE) IP Header Checksum Errors Position */ 1280 #define GMAC_IHCE_HCKER_Msk (_UINT32_(0xFF) << GMAC_IHCE_HCKER_Pos) /* (GMAC_IHCE) IP Header Checksum Errors Mask */ 1281 #define GMAC_IHCE_HCKER(value) (GMAC_IHCE_HCKER_Msk & (_UINT32_(value) << GMAC_IHCE_HCKER_Pos)) /* Assignment of value for HCKER in the GMAC_IHCE register */ 1282 #define GMAC_IHCE_Msk _UINT32_(0x000000FF) /* (GMAC_IHCE) Register Mask */ 1283 1284 1285 /* -------- GMAC_TCE : (GMAC Offset: 0x1AC) ( R/ 32) TCP Checksum Errors Register -------- */ 1286 #define GMAC_TCE_RESETVALUE _UINT32_(0x00) /* (GMAC_TCE) TCP Checksum Errors Register Reset Value */ 1287 1288 #define GMAC_TCE_TCKER_Pos _UINT32_(0) /* (GMAC_TCE) TCP Checksum Errors Position */ 1289 #define GMAC_TCE_TCKER_Msk (_UINT32_(0xFF) << GMAC_TCE_TCKER_Pos) /* (GMAC_TCE) TCP Checksum Errors Mask */ 1290 #define GMAC_TCE_TCKER(value) (GMAC_TCE_TCKER_Msk & (_UINT32_(value) << GMAC_TCE_TCKER_Pos)) /* Assignment of value for TCKER in the GMAC_TCE register */ 1291 #define GMAC_TCE_Msk _UINT32_(0x000000FF) /* (GMAC_TCE) Register Mask */ 1292 1293 1294 /* -------- GMAC_UCE : (GMAC Offset: 0x1B0) ( R/ 32) UDP Checksum Errors Register -------- */ 1295 #define GMAC_UCE_RESETVALUE _UINT32_(0x00) /* (GMAC_UCE) UDP Checksum Errors Register Reset Value */ 1296 1297 #define GMAC_UCE_UCKER_Pos _UINT32_(0) /* (GMAC_UCE) UDP Checksum Errors Position */ 1298 #define GMAC_UCE_UCKER_Msk (_UINT32_(0xFF) << GMAC_UCE_UCKER_Pos) /* (GMAC_UCE) UDP Checksum Errors Mask */ 1299 #define GMAC_UCE_UCKER(value) (GMAC_UCE_UCKER_Msk & (_UINT32_(value) << GMAC_UCE_UCKER_Pos)) /* Assignment of value for UCKER in the GMAC_UCE register */ 1300 #define GMAC_UCE_Msk _UINT32_(0x000000FF) /* (GMAC_UCE) Register Mask */ 1301 1302 1303 /* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register -------- */ 1304 #define GMAC_TISUBN_RESETVALUE _UINT32_(0x00) /* (GMAC_TISUBN) 1588 Timer Increment [15:0] Sub-Nanoseconds Register Reset Value */ 1305 1306 #define GMAC_TISUBN_LSBTIR_Pos _UINT32_(0) /* (GMAC_TISUBN) Lower Significant Bits of Timer Increment Position */ 1307 #define GMAC_TISUBN_LSBTIR_Msk (_UINT32_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos) /* (GMAC_TISUBN) Lower Significant Bits of Timer Increment Mask */ 1308 #define GMAC_TISUBN_LSBTIR(value) (GMAC_TISUBN_LSBTIR_Msk & (_UINT32_(value) << GMAC_TISUBN_LSBTIR_Pos)) /* Assignment of value for LSBTIR in the GMAC_TISUBN register */ 1309 #define GMAC_TISUBN_Msk _UINT32_(0x0000FFFF) /* (GMAC_TISUBN) Register Mask */ 1310 1311 1312 /* -------- GMAC_TSH : (GMAC Offset: 0x1C0) (R/W 32) 1588 Timer Seconds High [15:0] Register -------- */ 1313 #define GMAC_TSH_RESETVALUE _UINT32_(0x00) /* (GMAC_TSH) 1588 Timer Seconds High [15:0] Register Reset Value */ 1314 1315 #define GMAC_TSH_TCS_Pos _UINT32_(0) /* (GMAC_TSH) Timer Count in Seconds Position */ 1316 #define GMAC_TSH_TCS_Msk (_UINT32_(0xFFFF) << GMAC_TSH_TCS_Pos) /* (GMAC_TSH) Timer Count in Seconds Mask */ 1317 #define GMAC_TSH_TCS(value) (GMAC_TSH_TCS_Msk & (_UINT32_(value) << GMAC_TSH_TCS_Pos)) /* Assignment of value for TCS in the GMAC_TSH register */ 1318 #define GMAC_TSH_Msk _UINT32_(0x0000FFFF) /* (GMAC_TSH) Register Mask */ 1319 1320 1321 /* -------- GMAC_TSSSL : (GMAC Offset: 0x1C8) (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register -------- */ 1322 #define GMAC_TSSSL_RESETVALUE _UINT32_(0x00) /* (GMAC_TSSSL) 1588 Timer Sync Strobe Seconds [31:0] Register Reset Value */ 1323 1324 #define GMAC_TSSSL_VTS_Pos _UINT32_(0) /* (GMAC_TSSSL) Value of Timer Seconds Register Capture Position */ 1325 #define GMAC_TSSSL_VTS_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TSSSL_VTS_Pos) /* (GMAC_TSSSL) Value of Timer Seconds Register Capture Mask */ 1326 #define GMAC_TSSSL_VTS(value) (GMAC_TSSSL_VTS_Msk & (_UINT32_(value) << GMAC_TSSSL_VTS_Pos)) /* Assignment of value for VTS in the GMAC_TSSSL register */ 1327 #define GMAC_TSSSL_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TSSSL) Register Mask */ 1328 1329 1330 /* -------- GMAC_TSSN : (GMAC Offset: 0x1CC) (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register -------- */ 1331 #define GMAC_TSSN_RESETVALUE _UINT32_(0x00) /* (GMAC_TSSN) 1588 Timer Sync Strobe Nanoseconds Register Reset Value */ 1332 1333 #define GMAC_TSSN_VTN_Pos _UINT32_(0) /* (GMAC_TSSN) Value Timer Nanoseconds Register Capture Position */ 1334 #define GMAC_TSSN_VTN_Msk (_UINT32_(0x3FFFFFFF) << GMAC_TSSN_VTN_Pos) /* (GMAC_TSSN) Value Timer Nanoseconds Register Capture Mask */ 1335 #define GMAC_TSSN_VTN(value) (GMAC_TSSN_VTN_Msk & (_UINT32_(value) << GMAC_TSSN_VTN_Pos)) /* Assignment of value for VTN in the GMAC_TSSN register */ 1336 #define GMAC_TSSN_Msk _UINT32_(0x3FFFFFFF) /* (GMAC_TSSN) Register Mask */ 1337 1338 1339 /* -------- GMAC_TSL : (GMAC Offset: 0x1D0) (R/W 32) 1588 Timer Seconds [31:0] Register -------- */ 1340 #define GMAC_TSL_RESETVALUE _UINT32_(0x00) /* (GMAC_TSL) 1588 Timer Seconds [31:0] Register Reset Value */ 1341 1342 #define GMAC_TSL_TCS_Pos _UINT32_(0) /* (GMAC_TSL) Timer Count in Seconds Position */ 1343 #define GMAC_TSL_TCS_Msk (_UINT32_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos) /* (GMAC_TSL) Timer Count in Seconds Mask */ 1344 #define GMAC_TSL_TCS(value) (GMAC_TSL_TCS_Msk & (_UINT32_(value) << GMAC_TSL_TCS_Pos)) /* Assignment of value for TCS in the GMAC_TSL register */ 1345 #define GMAC_TSL_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_TSL) Register Mask */ 1346 1347 1348 /* -------- GMAC_TN : (GMAC Offset: 0x1D4) (R/W 32) 1588 Timer Nanoseconds Register -------- */ 1349 #define GMAC_TN_RESETVALUE _UINT32_(0x00) /* (GMAC_TN) 1588 Timer Nanoseconds Register Reset Value */ 1350 1351 #define GMAC_TN_TNS_Pos _UINT32_(0) /* (GMAC_TN) Timer Count in Nanoseconds Position */ 1352 #define GMAC_TN_TNS_Msk (_UINT32_(0x3FFFFFFF) << GMAC_TN_TNS_Pos) /* (GMAC_TN) Timer Count in Nanoseconds Mask */ 1353 #define GMAC_TN_TNS(value) (GMAC_TN_TNS_Msk & (_UINT32_(value) << GMAC_TN_TNS_Pos)) /* Assignment of value for TNS in the GMAC_TN register */ 1354 #define GMAC_TN_Msk _UINT32_(0x3FFFFFFF) /* (GMAC_TN) Register Mask */ 1355 1356 1357 /* -------- GMAC_TA : (GMAC Offset: 0x1D8) ( /W 32) 1588 Timer Adjust Register -------- */ 1358 #define GMAC_TA_RESETVALUE _UINT32_(0x00) /* (GMAC_TA) 1588 Timer Adjust Register Reset Value */ 1359 1360 #define GMAC_TA_ITDT_Pos _UINT32_(0) /* (GMAC_TA) Increment/Decrement Position */ 1361 #define GMAC_TA_ITDT_Msk (_UINT32_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos) /* (GMAC_TA) Increment/Decrement Mask */ 1362 #define GMAC_TA_ITDT(value) (GMAC_TA_ITDT_Msk & (_UINT32_(value) << GMAC_TA_ITDT_Pos)) /* Assignment of value for ITDT in the GMAC_TA register */ 1363 #define GMAC_TA_ADJ_Pos _UINT32_(31) /* (GMAC_TA) Adjust 1588 Timer Position */ 1364 #define GMAC_TA_ADJ_Msk (_UINT32_(0x1) << GMAC_TA_ADJ_Pos) /* (GMAC_TA) Adjust 1588 Timer Mask */ 1365 #define GMAC_TA_ADJ(value) (GMAC_TA_ADJ_Msk & (_UINT32_(value) << GMAC_TA_ADJ_Pos)) /* Assignment of value for ADJ in the GMAC_TA register */ 1366 #define GMAC_TA_Msk _UINT32_(0xBFFFFFFF) /* (GMAC_TA) Register Mask */ 1367 1368 1369 /* -------- GMAC_TI : (GMAC Offset: 0x1DC) (R/W 32) 1588 Timer Increment Register -------- */ 1370 #define GMAC_TI_RESETVALUE _UINT32_(0x00) /* (GMAC_TI) 1588 Timer Increment Register Reset Value */ 1371 1372 #define GMAC_TI_CNS_Pos _UINT32_(0) /* (GMAC_TI) Count Nanoseconds Position */ 1373 #define GMAC_TI_CNS_Msk (_UINT32_(0xFF) << GMAC_TI_CNS_Pos) /* (GMAC_TI) Count Nanoseconds Mask */ 1374 #define GMAC_TI_CNS(value) (GMAC_TI_CNS_Msk & (_UINT32_(value) << GMAC_TI_CNS_Pos)) /* Assignment of value for CNS in the GMAC_TI register */ 1375 #define GMAC_TI_ACNS_Pos _UINT32_(8) /* (GMAC_TI) Alternative Count Nanoseconds Position */ 1376 #define GMAC_TI_ACNS_Msk (_UINT32_(0xFF) << GMAC_TI_ACNS_Pos) /* (GMAC_TI) Alternative Count Nanoseconds Mask */ 1377 #define GMAC_TI_ACNS(value) (GMAC_TI_ACNS_Msk & (_UINT32_(value) << GMAC_TI_ACNS_Pos)) /* Assignment of value for ACNS in the GMAC_TI register */ 1378 #define GMAC_TI_NIT_Pos _UINT32_(16) /* (GMAC_TI) Number of Increments Position */ 1379 #define GMAC_TI_NIT_Msk (_UINT32_(0xFF) << GMAC_TI_NIT_Pos) /* (GMAC_TI) Number of Increments Mask */ 1380 #define GMAC_TI_NIT(value) (GMAC_TI_NIT_Msk & (_UINT32_(value) << GMAC_TI_NIT_Pos)) /* Assignment of value for NIT in the GMAC_TI register */ 1381 #define GMAC_TI_Msk _UINT32_(0x00FFFFFF) /* (GMAC_TI) Register Mask */ 1382 1383 1384 /* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) ( R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */ 1385 #define GMAC_EFTSL_RESETVALUE _UINT32_(0x00) /* (GMAC_EFTSL) PTP Event Frame Transmitted Seconds Low Register Reset Value */ 1386 1387 #define GMAC_EFTSL_RUD_Pos _UINT32_(0) /* (GMAC_EFTSL) Register Update Position */ 1388 #define GMAC_EFTSL_RUD_Msk (_UINT32_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos) /* (GMAC_EFTSL) Register Update Mask */ 1389 #define GMAC_EFTSL_RUD(value) (GMAC_EFTSL_RUD_Msk & (_UINT32_(value) << GMAC_EFTSL_RUD_Pos)) /* Assignment of value for RUD in the GMAC_EFTSL register */ 1390 #define GMAC_EFTSL_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_EFTSL) Register Mask */ 1391 1392 1393 /* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) ( R/ 32) PTP Event Frame Transmitted Nanoseconds -------- */ 1394 #define GMAC_EFTN_RESETVALUE _UINT32_(0x00) /* (GMAC_EFTN) PTP Event Frame Transmitted Nanoseconds Reset Value */ 1395 1396 #define GMAC_EFTN_RUD_Pos _UINT32_(0) /* (GMAC_EFTN) Register Update Position */ 1397 #define GMAC_EFTN_RUD_Msk (_UINT32_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos) /* (GMAC_EFTN) Register Update Mask */ 1398 #define GMAC_EFTN_RUD(value) (GMAC_EFTN_RUD_Msk & (_UINT32_(value) << GMAC_EFTN_RUD_Pos)) /* Assignment of value for RUD in the GMAC_EFTN register */ 1399 #define GMAC_EFTN_Msk _UINT32_(0x3FFFFFFF) /* (GMAC_EFTN) Register Mask */ 1400 1401 1402 /* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) ( R/ 32) PTP Event Frame Received Seconds Low Register -------- */ 1403 #define GMAC_EFRSL_RESETVALUE _UINT32_(0x00) /* (GMAC_EFRSL) PTP Event Frame Received Seconds Low Register Reset Value */ 1404 1405 #define GMAC_EFRSL_RUD_Pos _UINT32_(0) /* (GMAC_EFRSL) Register Update Position */ 1406 #define GMAC_EFRSL_RUD_Msk (_UINT32_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos) /* (GMAC_EFRSL) Register Update Mask */ 1407 #define GMAC_EFRSL_RUD(value) (GMAC_EFRSL_RUD_Msk & (_UINT32_(value) << GMAC_EFRSL_RUD_Pos)) /* Assignment of value for RUD in the GMAC_EFRSL register */ 1408 #define GMAC_EFRSL_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_EFRSL) Register Mask */ 1409 1410 1411 /* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) ( R/ 32) PTP Event Frame Received Nanoseconds -------- */ 1412 #define GMAC_EFRN_RESETVALUE _UINT32_(0x00) /* (GMAC_EFRN) PTP Event Frame Received Nanoseconds Reset Value */ 1413 1414 #define GMAC_EFRN_RUD_Pos _UINT32_(0) /* (GMAC_EFRN) Register Update Position */ 1415 #define GMAC_EFRN_RUD_Msk (_UINT32_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos) /* (GMAC_EFRN) Register Update Mask */ 1416 #define GMAC_EFRN_RUD(value) (GMAC_EFRN_RUD_Msk & (_UINT32_(value) << GMAC_EFRN_RUD_Pos)) /* Assignment of value for RUD in the GMAC_EFRN register */ 1417 #define GMAC_EFRN_Msk _UINT32_(0x3FFFFFFF) /* (GMAC_EFRN) Register Mask */ 1418 1419 1420 /* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) ( R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ 1421 #define GMAC_PEFTSL_RESETVALUE _UINT32_(0x00) /* (GMAC_PEFTSL) PTP Peer Event Frame Transmitted Seconds Low Register Reset Value */ 1422 1423 #define GMAC_PEFTSL_RUD_Pos _UINT32_(0) /* (GMAC_PEFTSL) Register Update Position */ 1424 #define GMAC_PEFTSL_RUD_Msk (_UINT32_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos) /* (GMAC_PEFTSL) Register Update Mask */ 1425 #define GMAC_PEFTSL_RUD(value) (GMAC_PEFTSL_RUD_Msk & (_UINT32_(value) << GMAC_PEFTSL_RUD_Pos)) /* Assignment of value for RUD in the GMAC_PEFTSL register */ 1426 #define GMAC_PEFTSL_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_PEFTSL) Register Mask */ 1427 1428 1429 /* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) ( R/ 32) PTP Peer Event Frame Transmitted Nanoseconds -------- */ 1430 #define GMAC_PEFTN_RESETVALUE _UINT32_(0x00) /* (GMAC_PEFTN) PTP Peer Event Frame Transmitted Nanoseconds Reset Value */ 1431 1432 #define GMAC_PEFTN_RUD_Pos _UINT32_(0) /* (GMAC_PEFTN) Register Update Position */ 1433 #define GMAC_PEFTN_RUD_Msk (_UINT32_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos) /* (GMAC_PEFTN) Register Update Mask */ 1434 #define GMAC_PEFTN_RUD(value) (GMAC_PEFTN_RUD_Msk & (_UINT32_(value) << GMAC_PEFTN_RUD_Pos)) /* Assignment of value for RUD in the GMAC_PEFTN register */ 1435 #define GMAC_PEFTN_Msk _UINT32_(0x3FFFFFFF) /* (GMAC_PEFTN) Register Mask */ 1436 1437 1438 /* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) ( R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */ 1439 #define GMAC_PEFRSL_RESETVALUE _UINT32_(0x00) /* (GMAC_PEFRSL) PTP Peer Event Frame Received Seconds Low Register Reset Value */ 1440 1441 #define GMAC_PEFRSL_RUD_Pos _UINT32_(0) /* (GMAC_PEFRSL) Register Update Position */ 1442 #define GMAC_PEFRSL_RUD_Msk (_UINT32_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos) /* (GMAC_PEFRSL) Register Update Mask */ 1443 #define GMAC_PEFRSL_RUD(value) (GMAC_PEFRSL_RUD_Msk & (_UINT32_(value) << GMAC_PEFRSL_RUD_Pos)) /* Assignment of value for RUD in the GMAC_PEFRSL register */ 1444 #define GMAC_PEFRSL_Msk _UINT32_(0xFFFFFFFF) /* (GMAC_PEFRSL) Register Mask */ 1445 1446 1447 /* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) ( R/ 32) PTP Peer Event Frame Received Nanoseconds -------- */ 1448 #define GMAC_PEFRN_RESETVALUE _UINT32_(0x00) /* (GMAC_PEFRN) PTP Peer Event Frame Received Nanoseconds Reset Value */ 1449 1450 #define GMAC_PEFRN_RUD_Pos _UINT32_(0) /* (GMAC_PEFRN) Register Update Position */ 1451 #define GMAC_PEFRN_RUD_Msk (_UINT32_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos) /* (GMAC_PEFRN) Register Update Mask */ 1452 #define GMAC_PEFRN_RUD(value) (GMAC_PEFRN_RUD_Msk & (_UINT32_(value) << GMAC_PEFRN_RUD_Pos)) /* Assignment of value for RUD in the GMAC_PEFRN register */ 1453 #define GMAC_PEFRN_Msk _UINT32_(0x3FFFFFFF) /* (GMAC_PEFRN) Register Mask */ 1454 1455 1456 /* -------- GMAC_RLPITR : (GMAC Offset: 0x270) ( R/ 32) Receive LPI transition Register -------- */ 1457 #define GMAC_RLPITR_RESETVALUE _UINT32_(0x00) /* (GMAC_RLPITR) Receive LPI transition Register Reset Value */ 1458 1459 #define GMAC_RLPITR_RLPITR_Pos _UINT32_(0) /* (GMAC_RLPITR) Count number of times transition from rx normal idle to low power idle Position */ 1460 #define GMAC_RLPITR_RLPITR_Msk (_UINT32_(0xFFFF) << GMAC_RLPITR_RLPITR_Pos) /* (GMAC_RLPITR) Count number of times transition from rx normal idle to low power idle Mask */ 1461 #define GMAC_RLPITR_RLPITR(value) (GMAC_RLPITR_RLPITR_Msk & (_UINT32_(value) << GMAC_RLPITR_RLPITR_Pos)) /* Assignment of value for RLPITR in the GMAC_RLPITR register */ 1462 #define GMAC_RLPITR_Msk _UINT32_(0x0000FFFF) /* (GMAC_RLPITR) Register Mask */ 1463 1464 1465 /* -------- GMAC_RLPITI : (GMAC Offset: 0x274) ( R/ 32) Receive LPI Time Register -------- */ 1466 #define GMAC_RLPITI_RESETVALUE _UINT32_(0x00) /* (GMAC_RLPITI) Receive LPI Time Register Reset Value */ 1467 1468 #define GMAC_RLPITI_RLPITI_Pos _UINT32_(0) /* (GMAC_RLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode Position */ 1469 #define GMAC_RLPITI_RLPITI_Msk (_UINT32_(0xFFFFFF) << GMAC_RLPITI_RLPITI_Pos) /* (GMAC_RLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode Mask */ 1470 #define GMAC_RLPITI_RLPITI(value) (GMAC_RLPITI_RLPITI_Msk & (_UINT32_(value) << GMAC_RLPITI_RLPITI_Pos)) /* Assignment of value for RLPITI in the GMAC_RLPITI register */ 1471 #define GMAC_RLPITI_Msk _UINT32_(0x00FFFFFF) /* (GMAC_RLPITI) Register Mask */ 1472 1473 1474 /* -------- GMAC_TLPITR : (GMAC Offset: 0x278) ( R/ 32) Receive LPI transition Register -------- */ 1475 #define GMAC_TLPITR_RESETVALUE _UINT32_(0x00) /* (GMAC_TLPITR) Receive LPI transition Register Reset Value */ 1476 1477 #define GMAC_TLPITR_TLPITR_Pos _UINT32_(0) /* (GMAC_TLPITR) Count number of times enable LPI tx bit 20 goes from low to high Position */ 1478 #define GMAC_TLPITR_TLPITR_Msk (_UINT32_(0xFFFF) << GMAC_TLPITR_TLPITR_Pos) /* (GMAC_TLPITR) Count number of times enable LPI tx bit 20 goes from low to high Mask */ 1479 #define GMAC_TLPITR_TLPITR(value) (GMAC_TLPITR_TLPITR_Msk & (_UINT32_(value) << GMAC_TLPITR_TLPITR_Pos)) /* Assignment of value for TLPITR in the GMAC_TLPITR register */ 1480 #define GMAC_TLPITR_Msk _UINT32_(0x0000FFFF) /* (GMAC_TLPITR) Register Mask */ 1481 1482 1483 /* -------- GMAC_TLPITI : (GMAC Offset: 0x27C) ( R/ 32) Receive LPI Time Register -------- */ 1484 #define GMAC_TLPITI_RESETVALUE _UINT32_(0x00) /* (GMAC_TLPITI) Receive LPI Time Register Reset Value */ 1485 1486 #define GMAC_TLPITI_TLPITI_Pos _UINT32_(0) /* (GMAC_TLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode Position */ 1487 #define GMAC_TLPITI_TLPITI_Msk (_UINT32_(0xFFFFFF) << GMAC_TLPITI_TLPITI_Pos) /* (GMAC_TLPITI) Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode Mask */ 1488 #define GMAC_TLPITI_TLPITI(value) (GMAC_TLPITI_TLPITI_Msk & (_UINT32_(value) << GMAC_TLPITI_TLPITI_Pos)) /* Assignment of value for TLPITI in the GMAC_TLPITI register */ 1489 #define GMAC_TLPITI_Msk _UINT32_(0x00FFFFFF) /* (GMAC_TLPITI) Register Mask */ 1490 1491 1492 /* GMAC register offsets definitions */ 1493 #define GMAC_SAB_REG_OFST _UINT32_(0x00) /* (GMAC_SAB) Specific Address Bottom [31:0] Register Offset */ 1494 #define GMAC_SAT_REG_OFST _UINT32_(0x04) /* (GMAC_SAT) Specific Address Top [47:32] Register Offset */ 1495 #define GMAC_NCR_REG_OFST _UINT32_(0x00) /* (GMAC_NCR) Network Control Register Offset */ 1496 #define GMAC_NCFGR_REG_OFST _UINT32_(0x04) /* (GMAC_NCFGR) Network Configuration Register Offset */ 1497 #define GMAC_NSR_REG_OFST _UINT32_(0x08) /* (GMAC_NSR) Network Status Register Offset */ 1498 #define GMAC_UR_REG_OFST _UINT32_(0x0C) /* (GMAC_UR) User Register Offset */ 1499 #define GMAC_DCFGR_REG_OFST _UINT32_(0x10) /* (GMAC_DCFGR) DMA Configuration Register Offset */ 1500 #define GMAC_TSR_REG_OFST _UINT32_(0x14) /* (GMAC_TSR) Transmit Status Register Offset */ 1501 #define GMAC_RBQB_REG_OFST _UINT32_(0x18) /* (GMAC_RBQB) Receive Buffer Queue Base Address Offset */ 1502 #define GMAC_TBQB_REG_OFST _UINT32_(0x1C) /* (GMAC_TBQB) Transmit Buffer Queue Base Address Offset */ 1503 #define GMAC_RSR_REG_OFST _UINT32_(0x20) /* (GMAC_RSR) Receive Status Register Offset */ 1504 #define GMAC_ISR_REG_OFST _UINT32_(0x24) /* (GMAC_ISR) Interrupt Status Register Offset */ 1505 #define GMAC_IER_REG_OFST _UINT32_(0x28) /* (GMAC_IER) Interrupt Enable Register Offset */ 1506 #define GMAC_IDR_REG_OFST _UINT32_(0x2C) /* (GMAC_IDR) Interrupt Disable Register Offset */ 1507 #define GMAC_IMR_REG_OFST _UINT32_(0x30) /* (GMAC_IMR) Interrupt Mask Register Offset */ 1508 #define GMAC_MAN_REG_OFST _UINT32_(0x34) /* (GMAC_MAN) PHY Maintenance Register Offset */ 1509 #define GMAC_RPQ_REG_OFST _UINT32_(0x38) /* (GMAC_RPQ) Received Pause Quantum Register Offset */ 1510 #define GMAC_TPQ_REG_OFST _UINT32_(0x3C) /* (GMAC_TPQ) Transmit Pause Quantum Register Offset */ 1511 #define GMAC_TPSF_REG_OFST _UINT32_(0x40) /* (GMAC_TPSF) TX partial store and forward Register Offset */ 1512 #define GMAC_RPSF_REG_OFST _UINT32_(0x44) /* (GMAC_RPSF) RX partial store and forward Register Offset */ 1513 #define GMAC_RJFML_REG_OFST _UINT32_(0x48) /* (GMAC_RJFML) RX Jumbo Frame Max Length Register Offset */ 1514 #define GMAC_HRB_REG_OFST _UINT32_(0x80) /* (GMAC_HRB) Hash Register Bottom [31:0] Offset */ 1515 #define GMAC_HRT_REG_OFST _UINT32_(0x84) /* (GMAC_HRT) Hash Register Top [63:32] Offset */ 1516 #define GMAC_TIDM_REG_OFST _UINT32_(0xA8) /* (GMAC_TIDM) Type ID Match n Register Offset */ 1517 #define GMAC_TIDM0_REG_OFST _UINT32_(0xA8) /* (GMAC_TIDM0) Type ID Match n Register Offset */ 1518 #define GMAC_TIDM1_REG_OFST _UINT32_(0xAC) /* (GMAC_TIDM1) Type ID Match n Register Offset */ 1519 #define GMAC_TIDM2_REG_OFST _UINT32_(0xB0) /* (GMAC_TIDM2) Type ID Match n Register Offset */ 1520 #define GMAC_TIDM3_REG_OFST _UINT32_(0xB4) /* (GMAC_TIDM3) Type ID Match n Register Offset */ 1521 #define GMAC_WOL_REG_OFST _UINT32_(0xB8) /* (GMAC_WOL) Wake on LAN Offset */ 1522 #define GMAC_IPGS_REG_OFST _UINT32_(0xBC) /* (GMAC_IPGS) IPG Stretch Register Offset */ 1523 #define GMAC_SVLAN_REG_OFST _UINT32_(0xC0) /* (GMAC_SVLAN) Stacked VLAN Register Offset */ 1524 #define GMAC_TPFCP_REG_OFST _UINT32_(0xC4) /* (GMAC_TPFCP) Transmit PFC Pause Register Offset */ 1525 #define GMAC_SAMB1_REG_OFST _UINT32_(0xC8) /* (GMAC_SAMB1) Specific Address 1 Mask Bottom [31:0] Register Offset */ 1526 #define GMAC_SAMT1_REG_OFST _UINT32_(0xCC) /* (GMAC_SAMT1) Specific Address 1 Mask Top [47:32] Register Offset */ 1527 #define GMAC_NSC_REG_OFST _UINT32_(0xDC) /* (GMAC_NSC) Tsu timer comparison nanoseconds Register Offset */ 1528 #define GMAC_SCL_REG_OFST _UINT32_(0xE0) /* (GMAC_SCL) Tsu timer second comparison Register Offset */ 1529 #define GMAC_SCH_REG_OFST _UINT32_(0xE4) /* (GMAC_SCH) Tsu timer second comparison Register Offset */ 1530 #define GMAC_EFTSH_REG_OFST _UINT32_(0xE8) /* (GMAC_EFTSH) PTP Event Frame Transmitted Seconds High Register Offset */ 1531 #define GMAC_EFRSH_REG_OFST _UINT32_(0xEC) /* (GMAC_EFRSH) PTP Event Frame Received Seconds High Register Offset */ 1532 #define GMAC_PEFTSH_REG_OFST _UINT32_(0xF0) /* (GMAC_PEFTSH) PTP Peer Event Frame Transmitted Seconds High Register Offset */ 1533 #define GMAC_PEFRSH_REG_OFST _UINT32_(0xF4) /* (GMAC_PEFRSH) PTP Peer Event Frame Received Seconds High Register Offset */ 1534 #define GMAC_OTLO_REG_OFST _UINT32_(0x100) /* (GMAC_OTLO) Octets Transmitted [31:0] Register Offset */ 1535 #define GMAC_OTHI_REG_OFST _UINT32_(0x104) /* (GMAC_OTHI) Octets Transmitted [47:32] Register Offset */ 1536 #define GMAC_FT_REG_OFST _UINT32_(0x108) /* (GMAC_FT) Frames Transmitted Register Offset */ 1537 #define GMAC_BCFT_REG_OFST _UINT32_(0x10C) /* (GMAC_BCFT) Broadcast Frames Transmitted Register Offset */ 1538 #define GMAC_MFT_REG_OFST _UINT32_(0x110) /* (GMAC_MFT) Multicast Frames Transmitted Register Offset */ 1539 #define GMAC_PFT_REG_OFST _UINT32_(0x114) /* (GMAC_PFT) Pause Frames Transmitted Register Offset */ 1540 #define GMAC_BFT64_REG_OFST _UINT32_(0x118) /* (GMAC_BFT64) 64 Byte Frames Transmitted Register Offset */ 1541 #define GMAC_TBFT127_REG_OFST _UINT32_(0x11C) /* (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted Register Offset */ 1542 #define GMAC_TBFT255_REG_OFST _UINT32_(0x120) /* (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted Register Offset */ 1543 #define GMAC_TBFT511_REG_OFST _UINT32_(0x124) /* (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted Register Offset */ 1544 #define GMAC_TBFT1023_REG_OFST _UINT32_(0x128) /* (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted Register Offset */ 1545 #define GMAC_TBFT1518_REG_OFST _UINT32_(0x12C) /* (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted Register Offset */ 1546 #define GMAC_GTBFT1518_REG_OFST _UINT32_(0x130) /* (GMAC_GTBFT1518) Greater Than 1518 Byte Frames Transmitted Register Offset */ 1547 #define GMAC_TUR_REG_OFST _UINT32_(0x134) /* (GMAC_TUR) Transmit Underruns Register Offset */ 1548 #define GMAC_SCF_REG_OFST _UINT32_(0x138) /* (GMAC_SCF) Single Collision Frames Register Offset */ 1549 #define GMAC_MCF_REG_OFST _UINT32_(0x13C) /* (GMAC_MCF) Multiple Collision Frames Register Offset */ 1550 #define GMAC_EC_REG_OFST _UINT32_(0x140) /* (GMAC_EC) Excessive Collisions Register Offset */ 1551 #define GMAC_LC_REG_OFST _UINT32_(0x144) /* (GMAC_LC) Late Collisions Register Offset */ 1552 #define GMAC_DTF_REG_OFST _UINT32_(0x148) /* (GMAC_DTF) Deferred Transmission Frames Register Offset */ 1553 #define GMAC_CSE_REG_OFST _UINT32_(0x14C) /* (GMAC_CSE) Carrier Sense Errors Register Offset */ 1554 #define GMAC_ORLO_REG_OFST _UINT32_(0x150) /* (GMAC_ORLO) Octets Received [31:0] Received Offset */ 1555 #define GMAC_ORHI_REG_OFST _UINT32_(0x154) /* (GMAC_ORHI) Octets Received [47:32] Received Offset */ 1556 #define GMAC_FR_REG_OFST _UINT32_(0x158) /* (GMAC_FR) Frames Received Register Offset */ 1557 #define GMAC_BCFR_REG_OFST _UINT32_(0x15C) /* (GMAC_BCFR) Broadcast Frames Received Register Offset */ 1558 #define GMAC_MFR_REG_OFST _UINT32_(0x160) /* (GMAC_MFR) Multicast Frames Received Register Offset */ 1559 #define GMAC_PFR_REG_OFST _UINT32_(0x164) /* (GMAC_PFR) Pause Frames Received Register Offset */ 1560 #define GMAC_BFR64_REG_OFST _UINT32_(0x168) /* (GMAC_BFR64) 64 Byte Frames Received Register Offset */ 1561 #define GMAC_TBFR127_REG_OFST _UINT32_(0x16C) /* (GMAC_TBFR127) 65 to 127 Byte Frames Received Register Offset */ 1562 #define GMAC_TBFR255_REG_OFST _UINT32_(0x170) /* (GMAC_TBFR255) 128 to 255 Byte Frames Received Register Offset */ 1563 #define GMAC_TBFR511_REG_OFST _UINT32_(0x174) /* (GMAC_TBFR511) 256 to 511Byte Frames Received Register Offset */ 1564 #define GMAC_TBFR1023_REG_OFST _UINT32_(0x178) /* (GMAC_TBFR1023) 512 to 1023 Byte Frames Received Register Offset */ 1565 #define GMAC_TBFR1518_REG_OFST _UINT32_(0x17C) /* (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received Register Offset */ 1566 #define GMAC_TMXBFR_REG_OFST _UINT32_(0x180) /* (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received Register Offset */ 1567 #define GMAC_UFR_REG_OFST _UINT32_(0x184) /* (GMAC_UFR) Undersize Frames Received Register Offset */ 1568 #define GMAC_OFR_REG_OFST _UINT32_(0x188) /* (GMAC_OFR) Oversize Frames Received Register Offset */ 1569 #define GMAC_JR_REG_OFST _UINT32_(0x18C) /* (GMAC_JR) Jabbers Received Register Offset */ 1570 #define GMAC_FCSE_REG_OFST _UINT32_(0x190) /* (GMAC_FCSE) Frame Check Sequence Errors Register Offset */ 1571 #define GMAC_LFFE_REG_OFST _UINT32_(0x194) /* (GMAC_LFFE) Length Field Frame Errors Register Offset */ 1572 #define GMAC_RSE_REG_OFST _UINT32_(0x198) /* (GMAC_RSE) Receive Symbol Errors Register Offset */ 1573 #define GMAC_AE_REG_OFST _UINT32_(0x19C) /* (GMAC_AE) Alignment Errors Register Offset */ 1574 #define GMAC_RRE_REG_OFST _UINT32_(0x1A0) /* (GMAC_RRE) Receive Resource Errors Register Offset */ 1575 #define GMAC_ROE_REG_OFST _UINT32_(0x1A4) /* (GMAC_ROE) Receive Overrun Register Offset */ 1576 #define GMAC_IHCE_REG_OFST _UINT32_(0x1A8) /* (GMAC_IHCE) IP Header Checksum Errors Register Offset */ 1577 #define GMAC_TCE_REG_OFST _UINT32_(0x1AC) /* (GMAC_TCE) TCP Checksum Errors Register Offset */ 1578 #define GMAC_UCE_REG_OFST _UINT32_(0x1B0) /* (GMAC_UCE) UDP Checksum Errors Register Offset */ 1579 #define GMAC_TISUBN_REG_OFST _UINT32_(0x1BC) /* (GMAC_TISUBN) 1588 Timer Increment [15:0] Sub-Nanoseconds Register Offset */ 1580 #define GMAC_TSH_REG_OFST _UINT32_(0x1C0) /* (GMAC_TSH) 1588 Timer Seconds High [15:0] Register Offset */ 1581 #define GMAC_TSSSL_REG_OFST _UINT32_(0x1C8) /* (GMAC_TSSSL) 1588 Timer Sync Strobe Seconds [31:0] Register Offset */ 1582 #define GMAC_TSSN_REG_OFST _UINT32_(0x1CC) /* (GMAC_TSSN) 1588 Timer Sync Strobe Nanoseconds Register Offset */ 1583 #define GMAC_TSL_REG_OFST _UINT32_(0x1D0) /* (GMAC_TSL) 1588 Timer Seconds [31:0] Register Offset */ 1584 #define GMAC_TN_REG_OFST _UINT32_(0x1D4) /* (GMAC_TN) 1588 Timer Nanoseconds Register Offset */ 1585 #define GMAC_TA_REG_OFST _UINT32_(0x1D8) /* (GMAC_TA) 1588 Timer Adjust Register Offset */ 1586 #define GMAC_TI_REG_OFST _UINT32_(0x1DC) /* (GMAC_TI) 1588 Timer Increment Register Offset */ 1587 #define GMAC_EFTSL_REG_OFST _UINT32_(0x1E0) /* (GMAC_EFTSL) PTP Event Frame Transmitted Seconds Low Register Offset */ 1588 #define GMAC_EFTN_REG_OFST _UINT32_(0x1E4) /* (GMAC_EFTN) PTP Event Frame Transmitted Nanoseconds Offset */ 1589 #define GMAC_EFRSL_REG_OFST _UINT32_(0x1E8) /* (GMAC_EFRSL) PTP Event Frame Received Seconds Low Register Offset */ 1590 #define GMAC_EFRN_REG_OFST _UINT32_(0x1EC) /* (GMAC_EFRN) PTP Event Frame Received Nanoseconds Offset */ 1591 #define GMAC_PEFTSL_REG_OFST _UINT32_(0x1F0) /* (GMAC_PEFTSL) PTP Peer Event Frame Transmitted Seconds Low Register Offset */ 1592 #define GMAC_PEFTN_REG_OFST _UINT32_(0x1F4) /* (GMAC_PEFTN) PTP Peer Event Frame Transmitted Nanoseconds Offset */ 1593 #define GMAC_PEFRSL_REG_OFST _UINT32_(0x1F8) /* (GMAC_PEFRSL) PTP Peer Event Frame Received Seconds Low Register Offset */ 1594 #define GMAC_PEFRN_REG_OFST _UINT32_(0x1FC) /* (GMAC_PEFRN) PTP Peer Event Frame Received Nanoseconds Offset */ 1595 #define GMAC_RLPITR_REG_OFST _UINT32_(0x270) /* (GMAC_RLPITR) Receive LPI transition Register Offset */ 1596 #define GMAC_RLPITI_REG_OFST _UINT32_(0x274) /* (GMAC_RLPITI) Receive LPI Time Register Offset */ 1597 #define GMAC_TLPITR_REG_OFST _UINT32_(0x278) /* (GMAC_TLPITR) Receive LPI transition Register Offset */ 1598 #define GMAC_TLPITI_REG_OFST _UINT32_(0x27C) /* (GMAC_TLPITI) Receive LPI Time Register Offset */ 1599 1600 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1601 /* SA register API structure */ 1602 typedef struct 1603 { 1604 __IO uint32_t GMAC_SAB; /* Offset: 0x00 (R/W 32) Specific Address Bottom [31:0] Register */ 1605 __IO uint32_t GMAC_SAT; /* Offset: 0x04 (R/W 32) Specific Address Top [47:32] Register */ 1606 } gmac_sa_registers_t; 1607 1608 #define GMAC_SA_NUMBER 4 1609 1610 /* GMAC register API structure */ 1611 typedef struct 1612 { /* Ethernet MAC */ 1613 __IO uint32_t GMAC_NCR; /* Offset: 0x00 (R/W 32) Network Control Register */ 1614 __IO uint32_t GMAC_NCFGR; /* Offset: 0x04 (R/W 32) Network Configuration Register */ 1615 __I uint32_t GMAC_NSR; /* Offset: 0x08 (R/ 32) Network Status Register */ 1616 __IO uint32_t GMAC_UR; /* Offset: 0x0C (R/W 32) User Register */ 1617 __IO uint32_t GMAC_DCFGR; /* Offset: 0x10 (R/W 32) DMA Configuration Register */ 1618 __IO uint32_t GMAC_TSR; /* Offset: 0x14 (R/W 32) Transmit Status Register */ 1619 __IO uint32_t GMAC_RBQB; /* Offset: 0x18 (R/W 32) Receive Buffer Queue Base Address */ 1620 __IO uint32_t GMAC_TBQB; /* Offset: 0x1C (R/W 32) Transmit Buffer Queue Base Address */ 1621 __IO uint32_t GMAC_RSR; /* Offset: 0x20 (R/W 32) Receive Status Register */ 1622 __IO uint32_t GMAC_ISR; /* Offset: 0x24 (R/W 32) Interrupt Status Register */ 1623 __O uint32_t GMAC_IER; /* Offset: 0x28 ( /W 32) Interrupt Enable Register */ 1624 __O uint32_t GMAC_IDR; /* Offset: 0x2C ( /W 32) Interrupt Disable Register */ 1625 __I uint32_t GMAC_IMR; /* Offset: 0x30 (R/ 32) Interrupt Mask Register */ 1626 __IO uint32_t GMAC_MAN; /* Offset: 0x34 (R/W 32) PHY Maintenance Register */ 1627 __I uint32_t GMAC_RPQ; /* Offset: 0x38 (R/ 32) Received Pause Quantum Register */ 1628 __IO uint32_t GMAC_TPQ; /* Offset: 0x3C (R/W 32) Transmit Pause Quantum Register */ 1629 __IO uint32_t GMAC_TPSF; /* Offset: 0x40 (R/W 32) TX partial store and forward Register */ 1630 __IO uint32_t GMAC_RPSF; /* Offset: 0x44 (R/W 32) RX partial store and forward Register */ 1631 __IO uint32_t GMAC_RJFML; /* Offset: 0x48 (R/W 32) RX Jumbo Frame Max Length Register */ 1632 __I uint8_t Reserved1[0x34]; 1633 __IO uint32_t GMAC_HRB; /* Offset: 0x80 (R/W 32) Hash Register Bottom [31:0] */ 1634 __IO uint32_t GMAC_HRT; /* Offset: 0x84 (R/W 32) Hash Register Top [63:32] */ 1635 gmac_sa_registers_t SA[GMAC_SA_NUMBER]; /* Offset: 0x88 */ 1636 __IO uint32_t GMAC_TIDM[4]; /* Offset: 0xA8 (R/W 32) Type ID Match n Register */ 1637 __IO uint32_t GMAC_WOL; /* Offset: 0xB8 (R/W 32) Wake on LAN */ 1638 __IO uint32_t GMAC_IPGS; /* Offset: 0xBC (R/W 32) IPG Stretch Register */ 1639 __IO uint32_t GMAC_SVLAN; /* Offset: 0xC0 (R/W 32) Stacked VLAN Register */ 1640 __IO uint32_t GMAC_TPFCP; /* Offset: 0xC4 (R/W 32) Transmit PFC Pause Register */ 1641 __IO uint32_t GMAC_SAMB1; /* Offset: 0xC8 (R/W 32) Specific Address 1 Mask Bottom [31:0] Register */ 1642 __IO uint32_t GMAC_SAMT1; /* Offset: 0xCC (R/W 32) Specific Address 1 Mask Top [47:32] Register */ 1643 __I uint8_t Reserved2[0x0C]; 1644 __IO uint32_t GMAC_NSC; /* Offset: 0xDC (R/W 32) Tsu timer comparison nanoseconds Register */ 1645 __IO uint32_t GMAC_SCL; /* Offset: 0xE0 (R/W 32) Tsu timer second comparison Register */ 1646 __IO uint32_t GMAC_SCH; /* Offset: 0xE4 (R/W 32) Tsu timer second comparison Register */ 1647 __I uint32_t GMAC_EFTSH; /* Offset: 0xE8 (R/ 32) PTP Event Frame Transmitted Seconds High Register */ 1648 __I uint32_t GMAC_EFRSH; /* Offset: 0xEC (R/ 32) PTP Event Frame Received Seconds High Register */ 1649 __I uint32_t GMAC_PEFTSH; /* Offset: 0xF0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register */ 1650 __I uint32_t GMAC_PEFRSH; /* Offset: 0xF4 (R/ 32) PTP Peer Event Frame Received Seconds High Register */ 1651 __I uint8_t Reserved3[0x08]; 1652 __I uint32_t GMAC_OTLO; /* Offset: 0x100 (R/ 32) Octets Transmitted [31:0] Register */ 1653 __I uint32_t GMAC_OTHI; /* Offset: 0x104 (R/ 32) Octets Transmitted [47:32] Register */ 1654 __I uint32_t GMAC_FT; /* Offset: 0x108 (R/ 32) Frames Transmitted Register */ 1655 __I uint32_t GMAC_BCFT; /* Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register */ 1656 __I uint32_t GMAC_MFT; /* Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register */ 1657 __I uint32_t GMAC_PFT; /* Offset: 0x114 (R/ 32) Pause Frames Transmitted Register */ 1658 __I uint32_t GMAC_BFT64; /* Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register */ 1659 __I uint32_t GMAC_TBFT127; /* Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register */ 1660 __I uint32_t GMAC_TBFT255; /* Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register */ 1661 __I uint32_t GMAC_TBFT511; /* Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register */ 1662 __I uint32_t GMAC_TBFT1023; /* Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register */ 1663 __I uint32_t GMAC_TBFT1518; /* Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register */ 1664 __I uint32_t GMAC_GTBFT1518; /* Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register */ 1665 __I uint32_t GMAC_TUR; /* Offset: 0x134 (R/ 32) Transmit Underruns Register */ 1666 __I uint32_t GMAC_SCF; /* Offset: 0x138 (R/ 32) Single Collision Frames Register */ 1667 __I uint32_t GMAC_MCF; /* Offset: 0x13C (R/ 32) Multiple Collision Frames Register */ 1668 __I uint32_t GMAC_EC; /* Offset: 0x140 (R/ 32) Excessive Collisions Register */ 1669 __I uint32_t GMAC_LC; /* Offset: 0x144 (R/ 32) Late Collisions Register */ 1670 __I uint32_t GMAC_DTF; /* Offset: 0x148 (R/ 32) Deferred Transmission Frames Register */ 1671 __I uint32_t GMAC_CSE; /* Offset: 0x14C (R/ 32) Carrier Sense Errors Register */ 1672 __I uint32_t GMAC_ORLO; /* Offset: 0x150 (R/ 32) Octets Received [31:0] Received */ 1673 __I uint32_t GMAC_ORHI; /* Offset: 0x154 (R/ 32) Octets Received [47:32] Received */ 1674 __I uint32_t GMAC_FR; /* Offset: 0x158 (R/ 32) Frames Received Register */ 1675 __I uint32_t GMAC_BCFR; /* Offset: 0x15C (R/ 32) Broadcast Frames Received Register */ 1676 __I uint32_t GMAC_MFR; /* Offset: 0x160 (R/ 32) Multicast Frames Received Register */ 1677 __I uint32_t GMAC_PFR; /* Offset: 0x164 (R/ 32) Pause Frames Received Register */ 1678 __I uint32_t GMAC_BFR64; /* Offset: 0x168 (R/ 32) 64 Byte Frames Received Register */ 1679 __I uint32_t GMAC_TBFR127; /* Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register */ 1680 __I uint32_t GMAC_TBFR255; /* Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register */ 1681 __I uint32_t GMAC_TBFR511; /* Offset: 0x174 (R/ 32) 256 to 511Byte Frames Received Register */ 1682 __I uint32_t GMAC_TBFR1023; /* Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register */ 1683 __I uint32_t GMAC_TBFR1518; /* Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register */ 1684 __I uint32_t GMAC_TMXBFR; /* Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register */ 1685 __I uint32_t GMAC_UFR; /* Offset: 0x184 (R/ 32) Undersize Frames Received Register */ 1686 __I uint32_t GMAC_OFR; /* Offset: 0x188 (R/ 32) Oversize Frames Received Register */ 1687 __I uint32_t GMAC_JR; /* Offset: 0x18C (R/ 32) Jabbers Received Register */ 1688 __I uint32_t GMAC_FCSE; /* Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register */ 1689 __I uint32_t GMAC_LFFE; /* Offset: 0x194 (R/ 32) Length Field Frame Errors Register */ 1690 __I uint32_t GMAC_RSE; /* Offset: 0x198 (R/ 32) Receive Symbol Errors Register */ 1691 __I uint32_t GMAC_AE; /* Offset: 0x19C (R/ 32) Alignment Errors Register */ 1692 __I uint32_t GMAC_RRE; /* Offset: 0x1A0 (R/ 32) Receive Resource Errors Register */ 1693 __I uint32_t GMAC_ROE; /* Offset: 0x1A4 (R/ 32) Receive Overrun Register */ 1694 __I uint32_t GMAC_IHCE; /* Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register */ 1695 __I uint32_t GMAC_TCE; /* Offset: 0x1AC (R/ 32) TCP Checksum Errors Register */ 1696 __I uint32_t GMAC_UCE; /* Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register */ 1697 __I uint8_t Reserved4[0x08]; 1698 __IO uint32_t GMAC_TISUBN; /* Offset: 0x1BC (R/W 32) 1588 Timer Increment [15:0] Sub-Nanoseconds Register */ 1699 __IO uint32_t GMAC_TSH; /* Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High [15:0] Register */ 1700 __I uint8_t Reserved5[0x04]; 1701 __IO uint32_t GMAC_TSSSL; /* Offset: 0x1C8 (R/W 32) 1588 Timer Sync Strobe Seconds [31:0] Register */ 1702 __IO uint32_t GMAC_TSSN; /* Offset: 0x1CC (R/W 32) 1588 Timer Sync Strobe Nanoseconds Register */ 1703 __IO uint32_t GMAC_TSL; /* Offset: 0x1D0 (R/W 32) 1588 Timer Seconds [31:0] Register */ 1704 __IO uint32_t GMAC_TN; /* Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */ 1705 __O uint32_t GMAC_TA; /* Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */ 1706 __IO uint32_t GMAC_TI; /* Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */ 1707 __I uint32_t GMAC_EFTSL; /* Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register */ 1708 __I uint32_t GMAC_EFTN; /* Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds */ 1709 __I uint32_t GMAC_EFRSL; /* Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register */ 1710 __I uint32_t GMAC_EFRN; /* Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds */ 1711 __I uint32_t GMAC_PEFTSL; /* Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register */ 1712 __I uint32_t GMAC_PEFTN; /* Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds */ 1713 __I uint32_t GMAC_PEFRSL; /* Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register */ 1714 __I uint32_t GMAC_PEFRN; /* Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds */ 1715 __I uint8_t Reserved6[0x70]; 1716 __I uint32_t GMAC_RLPITR; /* Offset: 0x270 (R/ 32) Receive LPI transition Register */ 1717 __I uint32_t GMAC_RLPITI; /* Offset: 0x274 (R/ 32) Receive LPI Time Register */ 1718 __I uint32_t GMAC_TLPITR; /* Offset: 0x278 (R/ 32) Receive LPI transition Register */ 1719 __I uint32_t GMAC_TLPITI; /* Offset: 0x27C (R/ 32) Receive LPI Time Register */ 1720 } gmac_registers_t; 1721 1722 1723 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1724 #endif /* _PIC32CXSG41_GMAC_COMPONENT_H_ */ 1725
