1 /* 2 * Component description for CAN 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_CAN_COMPONENT_H_ 22 #define _PIC32CXSG41_CAN_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR CAN */ 26 /* ************************************************************************** */ 27 28 /* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ 29 #define CAN_RXBE_0_ID_Pos _UINT32_(0) /* (CAN_RXBE_0) Identifier Position */ 30 #define CAN_RXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) /* (CAN_RXBE_0) Identifier Mask */ 31 #define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & (_UINT32_(value) << CAN_RXBE_0_ID_Pos)) /* Assignment of value for ID in the CAN_RXBE_0 register */ 32 #define CAN_RXBE_0_RTR_Pos _UINT32_(29) /* (CAN_RXBE_0) Remote Transmission Request Position */ 33 #define CAN_RXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_RXBE_0_RTR_Pos) /* (CAN_RXBE_0) Remote Transmission Request Mask */ 34 #define CAN_RXBE_0_RTR(value) (CAN_RXBE_0_RTR_Msk & (_UINT32_(value) << CAN_RXBE_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_RXBE_0 register */ 35 #define CAN_RXBE_0_XTD_Pos _UINT32_(30) /* (CAN_RXBE_0) Extended Identifier Position */ 36 #define CAN_RXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_RXBE_0_XTD_Pos) /* (CAN_RXBE_0) Extended Identifier Mask */ 37 #define CAN_RXBE_0_XTD(value) (CAN_RXBE_0_XTD_Msk & (_UINT32_(value) << CAN_RXBE_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_RXBE_0 register */ 38 #define CAN_RXBE_0_ESI_Pos _UINT32_(31) /* (CAN_RXBE_0) Error State Indicator Position */ 39 #define CAN_RXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_RXBE_0_ESI_Pos) /* (CAN_RXBE_0) Error State Indicator Mask */ 40 #define CAN_RXBE_0_ESI(value) (CAN_RXBE_0_ESI_Msk & (_UINT32_(value) << CAN_RXBE_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_RXBE_0 register */ 41 #define CAN_RXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_0) Register Mask */ 42 43 44 /* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ 45 #define CAN_RXBE_1_RXTS_Pos _UINT32_(0) /* (CAN_RXBE_1) Rx Timestamp Position */ 46 #define CAN_RXBE_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) /* (CAN_RXBE_1) Rx Timestamp Mask */ 47 #define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & (_UINT32_(value) << CAN_RXBE_1_RXTS_Pos)) /* Assignment of value for RXTS in the CAN_RXBE_1 register */ 48 #define CAN_RXBE_1_DLC_Pos _UINT32_(16) /* (CAN_RXBE_1) Data Length Code Position */ 49 #define CAN_RXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_RXBE_1_DLC_Pos) /* (CAN_RXBE_1) Data Length Code Mask */ 50 #define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & (_UINT32_(value) << CAN_RXBE_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_RXBE_1 register */ 51 #define CAN_RXBE_1_BRS_Pos _UINT32_(20) /* (CAN_RXBE_1) Bit Rate Switch Position */ 52 #define CAN_RXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_RXBE_1_BRS_Pos) /* (CAN_RXBE_1) Bit Rate Switch Mask */ 53 #define CAN_RXBE_1_BRS(value) (CAN_RXBE_1_BRS_Msk & (_UINT32_(value) << CAN_RXBE_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_RXBE_1 register */ 54 #define CAN_RXBE_1_FDF_Pos _UINT32_(21) /* (CAN_RXBE_1) FD Format Position */ 55 #define CAN_RXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_RXBE_1_FDF_Pos) /* (CAN_RXBE_1) FD Format Mask */ 56 #define CAN_RXBE_1_FDF(value) (CAN_RXBE_1_FDF_Msk & (_UINT32_(value) << CAN_RXBE_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_RXBE_1 register */ 57 #define CAN_RXBE_1_FIDX_Pos _UINT32_(24) /* (CAN_RXBE_1) Filter Index Position */ 58 #define CAN_RXBE_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXBE_1_FIDX_Pos) /* (CAN_RXBE_1) Filter Index Mask */ 59 #define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & (_UINT32_(value) << CAN_RXBE_1_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_RXBE_1 register */ 60 #define CAN_RXBE_1_ANMF_Pos _UINT32_(31) /* (CAN_RXBE_1) Accepted Non-matching Frame Position */ 61 #define CAN_RXBE_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXBE_1_ANMF_Pos) /* (CAN_RXBE_1) Accepted Non-matching Frame Mask */ 62 #define CAN_RXBE_1_ANMF(value) (CAN_RXBE_1_ANMF_Msk & (_UINT32_(value) << CAN_RXBE_1_ANMF_Pos)) /* Assignment of value for ANMF in the CAN_RXBE_1 register */ 63 #define CAN_RXBE_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXBE_1) Register Mask */ 64 65 66 /* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ 67 #define CAN_RXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXBE_DATA) Data Byte 0 Position */ 68 #define CAN_RXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB0_Pos) /* (CAN_RXBE_DATA) Data Byte 0 Mask */ 69 #define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_RXBE_DATA register */ 70 #define CAN_RXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXBE_DATA) Data Byte 1 Position */ 71 #define CAN_RXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB1_Pos) /* (CAN_RXBE_DATA) Data Byte 1 Mask */ 72 #define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_RXBE_DATA register */ 73 #define CAN_RXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXBE_DATA) Data Byte 2 Position */ 74 #define CAN_RXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB2_Pos) /* (CAN_RXBE_DATA) Data Byte 2 Mask */ 75 #define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_RXBE_DATA register */ 76 #define CAN_RXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXBE_DATA) Data Byte 3 Position */ 77 #define CAN_RXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXBE_DATA_DB3_Pos) /* (CAN_RXBE_DATA) Data Byte 3 Mask */ 78 #define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXBE_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_RXBE_DATA register */ 79 #define CAN_RXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXBE_DATA) Register Mask */ 80 81 82 /* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ 83 #define CAN_RXF0E_0_ID_Pos _UINT32_(0) /* (CAN_RXF0E_0) Identifier Position */ 84 #define CAN_RXF0E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) /* (CAN_RXF0E_0) Identifier Mask */ 85 #define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & (_UINT32_(value) << CAN_RXF0E_0_ID_Pos)) /* Assignment of value for ID in the CAN_RXF0E_0 register */ 86 #define CAN_RXF0E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF0E_0) Remote Transmission Request Position */ 87 #define CAN_RXF0E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF0E_0_RTR_Pos) /* (CAN_RXF0E_0) Remote Transmission Request Mask */ 88 #define CAN_RXF0E_0_RTR(value) (CAN_RXF0E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF0E_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_RXF0E_0 register */ 89 #define CAN_RXF0E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF0E_0) Extended Identifier Position */ 90 #define CAN_RXF0E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF0E_0_XTD_Pos) /* (CAN_RXF0E_0) Extended Identifier Mask */ 91 #define CAN_RXF0E_0_XTD(value) (CAN_RXF0E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF0E_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_RXF0E_0 register */ 92 #define CAN_RXF0E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF0E_0) Error State Indicator Position */ 93 #define CAN_RXF0E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF0E_0_ESI_Pos) /* (CAN_RXF0E_0) Error State Indicator Mask */ 94 #define CAN_RXF0E_0_ESI(value) (CAN_RXF0E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF0E_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_RXF0E_0 register */ 95 #define CAN_RXF0E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_0) Register Mask */ 96 97 98 /* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ 99 #define CAN_RXF0E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF0E_1) Rx Timestamp Position */ 100 #define CAN_RXF0E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) /* (CAN_RXF0E_1) Rx Timestamp Mask */ 101 #define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF0E_1_RXTS_Pos)) /* Assignment of value for RXTS in the CAN_RXF0E_1 register */ 102 #define CAN_RXF0E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF0E_1) Data Length Code Position */ 103 #define CAN_RXF0E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF0E_1_DLC_Pos) /* (CAN_RXF0E_1) Data Length Code Mask */ 104 #define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF0E_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_RXF0E_1 register */ 105 #define CAN_RXF0E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF0E_1) Bit Rate Switch Position */ 106 #define CAN_RXF0E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF0E_1_BRS_Pos) /* (CAN_RXF0E_1) Bit Rate Switch Mask */ 107 #define CAN_RXF0E_1_BRS(value) (CAN_RXF0E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF0E_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_RXF0E_1 register */ 108 #define CAN_RXF0E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF0E_1) FD Format Position */ 109 #define CAN_RXF0E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_FDF_Pos) /* (CAN_RXF0E_1) FD Format Mask */ 110 #define CAN_RXF0E_1_FDF(value) (CAN_RXF0E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF0E_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_RXF0E_1 register */ 111 #define CAN_RXF0E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF0E_1) Filter Index Position */ 112 #define CAN_RXF0E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF0E_1_FIDX_Pos) /* (CAN_RXF0E_1) Filter Index Mask */ 113 #define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF0E_1_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_RXF0E_1 register */ 114 #define CAN_RXF0E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF0E_1) Accepted Non-matching Frame Position */ 115 #define CAN_RXF0E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF0E_1_ANMF_Pos) /* (CAN_RXF0E_1) Accepted Non-matching Frame Mask */ 116 #define CAN_RXF0E_1_ANMF(value) (CAN_RXF0E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF0E_1_ANMF_Pos)) /* Assignment of value for ANMF in the CAN_RXF0E_1 register */ 117 #define CAN_RXF0E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF0E_1) Register Mask */ 118 119 120 /* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ 121 #define CAN_RXF0E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF0E_DATA) Data Byte 0 Position */ 122 #define CAN_RXF0E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) /* (CAN_RXF0E_DATA) Data Byte 0 Mask */ 123 #define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_RXF0E_DATA register */ 124 #define CAN_RXF0E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF0E_DATA) Data Byte 1 Position */ 125 #define CAN_RXF0E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) /* (CAN_RXF0E_DATA) Data Byte 1 Mask */ 126 #define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_RXF0E_DATA register */ 127 #define CAN_RXF0E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF0E_DATA) Data Byte 2 Position */ 128 #define CAN_RXF0E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) /* (CAN_RXF0E_DATA) Data Byte 2 Mask */ 129 #define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_RXF0E_DATA register */ 130 #define CAN_RXF0E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF0E_DATA) Data Byte 3 Position */ 131 #define CAN_RXF0E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) /* (CAN_RXF0E_DATA) Data Byte 3 Mask */ 132 #define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF0E_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_RXF0E_DATA register */ 133 #define CAN_RXF0E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF0E_DATA) Register Mask */ 134 135 136 /* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ 137 #define CAN_RXF1E_0_ID_Pos _UINT32_(0) /* (CAN_RXF1E_0) Identifier Position */ 138 #define CAN_RXF1E_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) /* (CAN_RXF1E_0) Identifier Mask */ 139 #define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & (_UINT32_(value) << CAN_RXF1E_0_ID_Pos)) /* Assignment of value for ID in the CAN_RXF1E_0 register */ 140 #define CAN_RXF1E_0_RTR_Pos _UINT32_(29) /* (CAN_RXF1E_0) Remote Transmission Request Position */ 141 #define CAN_RXF1E_0_RTR_Msk (_UINT32_(0x1) << CAN_RXF1E_0_RTR_Pos) /* (CAN_RXF1E_0) Remote Transmission Request Mask */ 142 #define CAN_RXF1E_0_RTR(value) (CAN_RXF1E_0_RTR_Msk & (_UINT32_(value) << CAN_RXF1E_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_RXF1E_0 register */ 143 #define CAN_RXF1E_0_XTD_Pos _UINT32_(30) /* (CAN_RXF1E_0) Extended Identifier Position */ 144 #define CAN_RXF1E_0_XTD_Msk (_UINT32_(0x1) << CAN_RXF1E_0_XTD_Pos) /* (CAN_RXF1E_0) Extended Identifier Mask */ 145 #define CAN_RXF1E_0_XTD(value) (CAN_RXF1E_0_XTD_Msk & (_UINT32_(value) << CAN_RXF1E_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_RXF1E_0 register */ 146 #define CAN_RXF1E_0_ESI_Pos _UINT32_(31) /* (CAN_RXF1E_0) Error State Indicator Position */ 147 #define CAN_RXF1E_0_ESI_Msk (_UINT32_(0x1) << CAN_RXF1E_0_ESI_Pos) /* (CAN_RXF1E_0) Error State Indicator Mask */ 148 #define CAN_RXF1E_0_ESI(value) (CAN_RXF1E_0_ESI_Msk & (_UINT32_(value) << CAN_RXF1E_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_RXF1E_0 register */ 149 #define CAN_RXF1E_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_0) Register Mask */ 150 151 152 /* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ 153 #define CAN_RXF1E_1_RXTS_Pos _UINT32_(0) /* (CAN_RXF1E_1) Rx Timestamp Position */ 154 #define CAN_RXF1E_1_RXTS_Msk (_UINT32_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) /* (CAN_RXF1E_1) Rx Timestamp Mask */ 155 #define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & (_UINT32_(value) << CAN_RXF1E_1_RXTS_Pos)) /* Assignment of value for RXTS in the CAN_RXF1E_1 register */ 156 #define CAN_RXF1E_1_DLC_Pos _UINT32_(16) /* (CAN_RXF1E_1) Data Length Code Position */ 157 #define CAN_RXF1E_1_DLC_Msk (_UINT32_(0xF) << CAN_RXF1E_1_DLC_Pos) /* (CAN_RXF1E_1) Data Length Code Mask */ 158 #define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & (_UINT32_(value) << CAN_RXF1E_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_RXF1E_1 register */ 159 #define CAN_RXF1E_1_BRS_Pos _UINT32_(20) /* (CAN_RXF1E_1) Bit Rate Switch Position */ 160 #define CAN_RXF1E_1_BRS_Msk (_UINT32_(0x1) << CAN_RXF1E_1_BRS_Pos) /* (CAN_RXF1E_1) Bit Rate Switch Mask */ 161 #define CAN_RXF1E_1_BRS(value) (CAN_RXF1E_1_BRS_Msk & (_UINT32_(value) << CAN_RXF1E_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_RXF1E_1 register */ 162 #define CAN_RXF1E_1_FDF_Pos _UINT32_(21) /* (CAN_RXF1E_1) FD Format Position */ 163 #define CAN_RXF1E_1_FDF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_FDF_Pos) /* (CAN_RXF1E_1) FD Format Mask */ 164 #define CAN_RXF1E_1_FDF(value) (CAN_RXF1E_1_FDF_Msk & (_UINT32_(value) << CAN_RXF1E_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_RXF1E_1 register */ 165 #define CAN_RXF1E_1_FIDX_Pos _UINT32_(24) /* (CAN_RXF1E_1) Filter Index Position */ 166 #define CAN_RXF1E_1_FIDX_Msk (_UINT32_(0x7F) << CAN_RXF1E_1_FIDX_Pos) /* (CAN_RXF1E_1) Filter Index Mask */ 167 #define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & (_UINT32_(value) << CAN_RXF1E_1_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_RXF1E_1 register */ 168 #define CAN_RXF1E_1_ANMF_Pos _UINT32_(31) /* (CAN_RXF1E_1) Accepted Non-matching Frame Position */ 169 #define CAN_RXF1E_1_ANMF_Msk (_UINT32_(0x1) << CAN_RXF1E_1_ANMF_Pos) /* (CAN_RXF1E_1) Accepted Non-matching Frame Mask */ 170 #define CAN_RXF1E_1_ANMF(value) (CAN_RXF1E_1_ANMF_Msk & (_UINT32_(value) << CAN_RXF1E_1_ANMF_Pos)) /* Assignment of value for ANMF in the CAN_RXF1E_1 register */ 171 #define CAN_RXF1E_1_Msk _UINT32_(0xFF3FFFFF) /* (CAN_RXF1E_1) Register Mask */ 172 173 174 /* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ 175 #define CAN_RXF1E_DATA_DB0_Pos _UINT32_(0) /* (CAN_RXF1E_DATA) Data Byte 0 Position */ 176 #define CAN_RXF1E_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) /* (CAN_RXF1E_DATA) Data Byte 0 Mask */ 177 #define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_RXF1E_DATA register */ 178 #define CAN_RXF1E_DATA_DB1_Pos _UINT32_(8) /* (CAN_RXF1E_DATA) Data Byte 1 Position */ 179 #define CAN_RXF1E_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) /* (CAN_RXF1E_DATA) Data Byte 1 Mask */ 180 #define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_RXF1E_DATA register */ 181 #define CAN_RXF1E_DATA_DB2_Pos _UINT32_(16) /* (CAN_RXF1E_DATA) Data Byte 2 Position */ 182 #define CAN_RXF1E_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) /* (CAN_RXF1E_DATA) Data Byte 2 Mask */ 183 #define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_RXF1E_DATA register */ 184 #define CAN_RXF1E_DATA_DB3_Pos _UINT32_(24) /* (CAN_RXF1E_DATA) Data Byte 3 Position */ 185 #define CAN_RXF1E_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) /* (CAN_RXF1E_DATA) Data Byte 3 Mask */ 186 #define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & (_UINT32_(value) << CAN_RXF1E_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_RXF1E_DATA register */ 187 #define CAN_RXF1E_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_RXF1E_DATA) Register Mask */ 188 189 190 /* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ 191 #define CAN_TXBE_0_ID_Pos _UINT32_(0) /* (CAN_TXBE_0) Identifier Position */ 192 #define CAN_TXBE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) /* (CAN_TXBE_0) Identifier Mask */ 193 #define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & (_UINT32_(value) << CAN_TXBE_0_ID_Pos)) /* Assignment of value for ID in the CAN_TXBE_0 register */ 194 #define CAN_TXBE_0_RTR_Pos _UINT32_(29) /* (CAN_TXBE_0) Remote Transmission Request Position */ 195 #define CAN_TXBE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXBE_0_RTR_Pos) /* (CAN_TXBE_0) Remote Transmission Request Mask */ 196 #define CAN_TXBE_0_RTR(value) (CAN_TXBE_0_RTR_Msk & (_UINT32_(value) << CAN_TXBE_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_TXBE_0 register */ 197 #define CAN_TXBE_0_XTD_Pos _UINT32_(30) /* (CAN_TXBE_0) Extended Identifier Position */ 198 #define CAN_TXBE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXBE_0_XTD_Pos) /* (CAN_TXBE_0) Extended Identifier Mask */ 199 #define CAN_TXBE_0_XTD(value) (CAN_TXBE_0_XTD_Msk & (_UINT32_(value) << CAN_TXBE_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_TXBE_0 register */ 200 #define CAN_TXBE_0_ESI_Pos _UINT32_(31) /* (CAN_TXBE_0) Error State Indicator Position */ 201 #define CAN_TXBE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXBE_0_ESI_Pos) /* (CAN_TXBE_0) Error State Indicator Mask */ 202 #define CAN_TXBE_0_ESI(value) (CAN_TXBE_0_ESI_Msk & (_UINT32_(value) << CAN_TXBE_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_TXBE_0 register */ 203 #define CAN_TXBE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_0) Register Mask */ 204 205 206 /* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ 207 #define CAN_TXBE_1_DLC_Pos _UINT32_(16) /* (CAN_TXBE_1) Data Length Code Position */ 208 #define CAN_TXBE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXBE_1_DLC_Pos) /* (CAN_TXBE_1) Data Length Code Mask */ 209 #define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & (_UINT32_(value) << CAN_TXBE_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_TXBE_1 register */ 210 #define CAN_TXBE_1_BRS_Pos _UINT32_(20) /* (CAN_TXBE_1) Bit Rate Switch Position */ 211 #define CAN_TXBE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXBE_1_BRS_Pos) /* (CAN_TXBE_1) Bit Rate Switch Mask */ 212 #define CAN_TXBE_1_BRS(value) (CAN_TXBE_1_BRS_Msk & (_UINT32_(value) << CAN_TXBE_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_TXBE_1 register */ 213 #define CAN_TXBE_1_FDF_Pos _UINT32_(21) /* (CAN_TXBE_1) FD Format Position */ 214 #define CAN_TXBE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXBE_1_FDF_Pos) /* (CAN_TXBE_1) FD Format Mask */ 215 #define CAN_TXBE_1_FDF(value) (CAN_TXBE_1_FDF_Msk & (_UINT32_(value) << CAN_TXBE_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_TXBE_1 register */ 216 #define CAN_TXBE_1_EFC_Pos _UINT32_(23) /* (CAN_TXBE_1) Event FIFO Control Position */ 217 #define CAN_TXBE_1_EFC_Msk (_UINT32_(0x1) << CAN_TXBE_1_EFC_Pos) /* (CAN_TXBE_1) Event FIFO Control Mask */ 218 #define CAN_TXBE_1_EFC(value) (CAN_TXBE_1_EFC_Msk & (_UINT32_(value) << CAN_TXBE_1_EFC_Pos)) /* Assignment of value for EFC in the CAN_TXBE_1 register */ 219 #define CAN_TXBE_1_MM_Pos _UINT32_(24) /* (CAN_TXBE_1) Message Marker Position */ 220 #define CAN_TXBE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXBE_1_MM_Pos) /* (CAN_TXBE_1) Message Marker Mask */ 221 #define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & (_UINT32_(value) << CAN_TXBE_1_MM_Pos)) /* Assignment of value for MM in the CAN_TXBE_1 register */ 222 #define CAN_TXBE_1_Msk _UINT32_(0xFFBF0000) /* (CAN_TXBE_1) Register Mask */ 223 224 225 /* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ 226 #define CAN_TXBE_DATA_DB0_Pos _UINT32_(0) /* (CAN_TXBE_DATA) Data Byte 0 Position */ 227 #define CAN_TXBE_DATA_DB0_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB0_Pos) /* (CAN_TXBE_DATA) Data Byte 0 Mask */ 228 #define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB0_Pos)) /* Assignment of value for DB0 in the CAN_TXBE_DATA register */ 229 #define CAN_TXBE_DATA_DB1_Pos _UINT32_(8) /* (CAN_TXBE_DATA) Data Byte 1 Position */ 230 #define CAN_TXBE_DATA_DB1_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB1_Pos) /* (CAN_TXBE_DATA) Data Byte 1 Mask */ 231 #define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB1_Pos)) /* Assignment of value for DB1 in the CAN_TXBE_DATA register */ 232 #define CAN_TXBE_DATA_DB2_Pos _UINT32_(16) /* (CAN_TXBE_DATA) Data Byte 2 Position */ 233 #define CAN_TXBE_DATA_DB2_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB2_Pos) /* (CAN_TXBE_DATA) Data Byte 2 Mask */ 234 #define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB2_Pos)) /* Assignment of value for DB2 in the CAN_TXBE_DATA register */ 235 #define CAN_TXBE_DATA_DB3_Pos _UINT32_(24) /* (CAN_TXBE_DATA) Data Byte 3 Position */ 236 #define CAN_TXBE_DATA_DB3_Msk (_UINT32_(0xFF) << CAN_TXBE_DATA_DB3_Pos) /* (CAN_TXBE_DATA) Data Byte 3 Mask */ 237 #define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & (_UINT32_(value) << CAN_TXBE_DATA_DB3_Pos)) /* Assignment of value for DB3 in the CAN_TXBE_DATA register */ 238 #define CAN_TXBE_DATA_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBE_DATA) Register Mask */ 239 240 241 /* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ 242 #define CAN_TXEFE_0_ID_Pos _UINT32_(0) /* (CAN_TXEFE_0) Identifier Position */ 243 #define CAN_TXEFE_0_ID_Msk (_UINT32_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) /* (CAN_TXEFE_0) Identifier Mask */ 244 #define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & (_UINT32_(value) << CAN_TXEFE_0_ID_Pos)) /* Assignment of value for ID in the CAN_TXEFE_0 register */ 245 #define CAN_TXEFE_0_RTR_Pos _UINT32_(29) /* (CAN_TXEFE_0) Remote Transmission Request Position */ 246 #define CAN_TXEFE_0_RTR_Msk (_UINT32_(0x1) << CAN_TXEFE_0_RTR_Pos) /* (CAN_TXEFE_0) Remote Transmission Request Mask */ 247 #define CAN_TXEFE_0_RTR(value) (CAN_TXEFE_0_RTR_Msk & (_UINT32_(value) << CAN_TXEFE_0_RTR_Pos)) /* Assignment of value for RTR in the CAN_TXEFE_0 register */ 248 #define CAN_TXEFE_0_XTD_Pos _UINT32_(30) /* (CAN_TXEFE_0) Extended Identifier Position */ 249 #define CAN_TXEFE_0_XTD_Msk (_UINT32_(0x1) << CAN_TXEFE_0_XTD_Pos) /* (CAN_TXEFE_0) Extended Identifier Mask */ 250 #define CAN_TXEFE_0_XTD(value) (CAN_TXEFE_0_XTD_Msk & (_UINT32_(value) << CAN_TXEFE_0_XTD_Pos)) /* Assignment of value for XTD in the CAN_TXEFE_0 register */ 251 #define CAN_TXEFE_0_ESI_Pos _UINT32_(31) /* (CAN_TXEFE_0) Error State Indicator Position */ 252 #define CAN_TXEFE_0_ESI_Msk (_UINT32_(0x1) << CAN_TXEFE_0_ESI_Pos) /* (CAN_TXEFE_0) Error State Indicator Mask */ 253 #define CAN_TXEFE_0_ESI(value) (CAN_TXEFE_0_ESI_Msk & (_UINT32_(value) << CAN_TXEFE_0_ESI_Pos)) /* Assignment of value for ESI in the CAN_TXEFE_0 register */ 254 #define CAN_TXEFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_0) Register Mask */ 255 256 257 /* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ 258 #define CAN_TXEFE_1_TXTS_Pos _UINT32_(0) /* (CAN_TXEFE_1) Tx Timestamp Position */ 259 #define CAN_TXEFE_1_TXTS_Msk (_UINT32_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) /* (CAN_TXEFE_1) Tx Timestamp Mask */ 260 #define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & (_UINT32_(value) << CAN_TXEFE_1_TXTS_Pos)) /* Assignment of value for TXTS in the CAN_TXEFE_1 register */ 261 #define CAN_TXEFE_1_DLC_Pos _UINT32_(16) /* (CAN_TXEFE_1) Data Length Code Position */ 262 #define CAN_TXEFE_1_DLC_Msk (_UINT32_(0xF) << CAN_TXEFE_1_DLC_Pos) /* (CAN_TXEFE_1) Data Length Code Mask */ 263 #define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & (_UINT32_(value) << CAN_TXEFE_1_DLC_Pos)) /* Assignment of value for DLC in the CAN_TXEFE_1 register */ 264 #define CAN_TXEFE_1_BRS_Pos _UINT32_(20) /* (CAN_TXEFE_1) Bit Rate Switch Position */ 265 #define CAN_TXEFE_1_BRS_Msk (_UINT32_(0x1) << CAN_TXEFE_1_BRS_Pos) /* (CAN_TXEFE_1) Bit Rate Switch Mask */ 266 #define CAN_TXEFE_1_BRS(value) (CAN_TXEFE_1_BRS_Msk & (_UINT32_(value) << CAN_TXEFE_1_BRS_Pos)) /* Assignment of value for BRS in the CAN_TXEFE_1 register */ 267 #define CAN_TXEFE_1_FDF_Pos _UINT32_(21) /* (CAN_TXEFE_1) FD Format Position */ 268 #define CAN_TXEFE_1_FDF_Msk (_UINT32_(0x1) << CAN_TXEFE_1_FDF_Pos) /* (CAN_TXEFE_1) FD Format Mask */ 269 #define CAN_TXEFE_1_FDF(value) (CAN_TXEFE_1_FDF_Msk & (_UINT32_(value) << CAN_TXEFE_1_FDF_Pos)) /* Assignment of value for FDF in the CAN_TXEFE_1 register */ 270 #define CAN_TXEFE_1_ET_Pos _UINT32_(22) /* (CAN_TXEFE_1) Event Type Position */ 271 #define CAN_TXEFE_1_ET_Msk (_UINT32_(0x3) << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Event Type Mask */ 272 #define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & (_UINT32_(value) << CAN_TXEFE_1_ET_Pos)) /* Assignment of value for ET in the CAN_TXEFE_1 register */ 273 #define CAN_TXEFE_1_ET_TXE_Val _UINT32_(0x1) /* (CAN_TXEFE_1) Tx event */ 274 #define CAN_TXEFE_1_ET_TXC_Val _UINT32_(0x2) /* (CAN_TXEFE_1) Transmission in spite of cancellation */ 275 #define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Tx event Position */ 276 #define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) /* (CAN_TXEFE_1) Transmission in spite of cancellation Position */ 277 #define CAN_TXEFE_1_MM_Pos _UINT32_(24) /* (CAN_TXEFE_1) Message Marker Position */ 278 #define CAN_TXEFE_1_MM_Msk (_UINT32_(0xFF) << CAN_TXEFE_1_MM_Pos) /* (CAN_TXEFE_1) Message Marker Mask */ 279 #define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & (_UINT32_(value) << CAN_TXEFE_1_MM_Pos)) /* Assignment of value for MM in the CAN_TXEFE_1 register */ 280 #define CAN_TXEFE_1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXEFE_1) Register Mask */ 281 282 283 /* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ 284 #define CAN_SIDFE_0_SFID2_Pos _UINT32_(0) /* (CAN_SIDFE_0) Standard Filter ID 2 Position */ 285 #define CAN_SIDFE_0_SFID2_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) /* (CAN_SIDFE_0) Standard Filter ID 2 Mask */ 286 #define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID2_Pos)) /* Assignment of value for SFID2 in the CAN_SIDFE_0 register */ 287 #define CAN_SIDFE_0_SFID1_Pos _UINT32_(16) /* (CAN_SIDFE_0) Standard Filter ID 1 Position */ 288 #define CAN_SIDFE_0_SFID1_Msk (_UINT32_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) /* (CAN_SIDFE_0) Standard Filter ID 1 Mask */ 289 #define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFID1_Pos)) /* Assignment of value for SFID1 in the CAN_SIDFE_0 register */ 290 #define CAN_SIDFE_0_SFEC_Pos _UINT32_(27) /* (CAN_SIDFE_0) Standard Filter Element Configuration Position */ 291 #define CAN_SIDFE_0_SFEC_Msk (_UINT32_(0x7) << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Standard Filter Element Configuration Mask */ 292 #define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFEC_Pos)) /* Assignment of value for SFEC in the CAN_SIDFE_0 register */ 293 #define CAN_SIDFE_0_SFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Disable filter element */ 294 #define CAN_SIDFE_0_SFEC_STF0M_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ 295 #define CAN_SIDFE_0_SFEC_STF1M_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ 296 #define CAN_SIDFE_0_SFEC_REJECT_Val _UINT32_(0x3) /* (CAN_SIDFE_0) Reject ID if filter match */ 297 #define CAN_SIDFE_0_SFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_SIDFE_0) Set priority if filter match */ 298 #define CAN_SIDFE_0_SFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ 299 #define CAN_SIDFE_0_SFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ 300 #define CAN_SIDFE_0_SFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_SIDFE_0) Store into Rx Buffer */ 301 #define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Disable filter element Position */ 302 #define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match Position */ 303 #define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match Position */ 304 #define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Reject ID if filter match Position */ 305 #define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority if filter match Position */ 306 #define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match Position */ 307 #define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match Position */ 308 #define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) /* (CAN_SIDFE_0) Store into Rx Buffer Position */ 309 #define CAN_SIDFE_0_SFT_Pos _UINT32_(30) /* (CAN_SIDFE_0) Standard Filter Type Position */ 310 #define CAN_SIDFE_0_SFT_Msk (_UINT32_(0x3) << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Standard Filter Type Mask */ 311 #define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & (_UINT32_(value) << CAN_SIDFE_0_SFT_Pos)) /* Assignment of value for SFT in the CAN_SIDFE_0 register */ 312 #define CAN_SIDFE_0_SFT_RANGE_Val _UINT32_(0x0) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ 313 #define CAN_SIDFE_0_SFT_DUAL_Val _UINT32_(0x1) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ 314 #define CAN_SIDFE_0_SFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_SIDFE_0) Classic filter */ 315 #define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ 316 #define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 Position */ 317 #define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) /* (CAN_SIDFE_0) Classic filter Position */ 318 #define CAN_SIDFE_0_Msk _UINT32_(0xFFFF07FF) /* (CAN_SIDFE_0) Register Mask */ 319 320 321 /* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ 322 #define CAN_XIDFE_0_EFID1_Pos _UINT32_(0) /* (CAN_XIDFE_0) Extended Filter ID 1 Position */ 323 #define CAN_XIDFE_0_EFID1_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) /* (CAN_XIDFE_0) Extended Filter ID 1 Mask */ 324 #define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFID1_Pos)) /* Assignment of value for EFID1 in the CAN_XIDFE_0 register */ 325 #define CAN_XIDFE_0_EFEC_Pos _UINT32_(29) /* (CAN_XIDFE_0) Extended Filter Element Configuration Position */ 326 #define CAN_XIDFE_0_EFEC_Msk (_UINT32_(0x7) << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Extended Filter Element Configuration Mask */ 327 #define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & (_UINT32_(value) << CAN_XIDFE_0_EFEC_Pos)) /* Assignment of value for EFEC in the CAN_XIDFE_0 register */ 328 #define CAN_XIDFE_0_EFEC_DISABLE_Val _UINT32_(0x0) /* (CAN_XIDFE_0) Disable filter element */ 329 #define CAN_XIDFE_0_EFEC_STF0M_Val _UINT32_(0x1) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ 330 #define CAN_XIDFE_0_EFEC_STF1M_Val _UINT32_(0x2) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ 331 #define CAN_XIDFE_0_EFEC_REJECT_Val _UINT32_(0x3) /* (CAN_XIDFE_0) Reject ID if filter match */ 332 #define CAN_XIDFE_0_EFEC_PRIORITY_Val _UINT32_(0x4) /* (CAN_XIDFE_0) Set priority if filter match */ 333 #define CAN_XIDFE_0_EFEC_PRIF0M_Val _UINT32_(0x5) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ 334 #define CAN_XIDFE_0_EFEC_PRIF1M_Val _UINT32_(0x6) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ 335 #define CAN_XIDFE_0_EFEC_STRXBUF_Val _UINT32_(0x7) /* (CAN_XIDFE_0) Store into Rx Buffer */ 336 #define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Disable filter element Position */ 337 #define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match Position */ 338 #define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match Position */ 339 #define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Reject ID if filter match Position */ 340 #define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority if filter match Position */ 341 #define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match Position */ 342 #define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match Position */ 343 #define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) /* (CAN_XIDFE_0) Store into Rx Buffer Position */ 344 #define CAN_XIDFE_0_Msk _UINT32_(0xFFFFFFFF) /* (CAN_XIDFE_0) Register Mask */ 345 346 347 /* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ 348 #define CAN_XIDFE_1_EFID2_Pos _UINT32_(0) /* (CAN_XIDFE_1) Extended Filter ID 2 Position */ 349 #define CAN_XIDFE_1_EFID2_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) /* (CAN_XIDFE_1) Extended Filter ID 2 Mask */ 350 #define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFID2_Pos)) /* Assignment of value for EFID2 in the CAN_XIDFE_1 register */ 351 #define CAN_XIDFE_1_EFT_Pos _UINT32_(30) /* (CAN_XIDFE_1) Extended Filter Type Position */ 352 #define CAN_XIDFE_1_EFT_Msk (_UINT32_(0x3) << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Extended Filter Type Mask */ 353 #define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & (_UINT32_(value) << CAN_XIDFE_1_EFT_Pos)) /* Assignment of value for EFT in the CAN_XIDFE_1 register */ 354 #define CAN_XIDFE_1_EFT_RANGEM_Val _UINT32_(0x0) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ 355 #define CAN_XIDFE_1_EFT_DUAL_Val _UINT32_(0x1) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ 356 #define CAN_XIDFE_1_EFT_CLASSIC_Val _UINT32_(0x2) /* (CAN_XIDFE_1) Classic filter */ 357 #define CAN_XIDFE_1_EFT_RANGE_Val _UINT32_(0x3) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ 358 #define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ 359 #define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ 360 #define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Classic filter Position */ 361 #define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) /* (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ 362 #define CAN_XIDFE_1_Msk _UINT32_(0xDFFFFFFF) /* (CAN_XIDFE_1) Register Mask */ 363 364 365 /* -------- CAN_CREL : (CAN Offset: 0x00) ( R/ 32) Core Release -------- */ 366 #define CAN_CREL_RESETVALUE _UINT32_(0x32100000) /* (CAN_CREL) Core Release Reset Value */ 367 368 #define CAN_CREL_SUBSTEP_Pos _UINT32_(20) /* (CAN_CREL) Sub-step of Core Release Position */ 369 #define CAN_CREL_SUBSTEP_Msk (_UINT32_(0xF) << CAN_CREL_SUBSTEP_Pos) /* (CAN_CREL) Sub-step of Core Release Mask */ 370 #define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & (_UINT32_(value) << CAN_CREL_SUBSTEP_Pos)) /* Assignment of value for SUBSTEP in the CAN_CREL register */ 371 #define CAN_CREL_STEP_Pos _UINT32_(24) /* (CAN_CREL) Step of Core Release Position */ 372 #define CAN_CREL_STEP_Msk (_UINT32_(0xF) << CAN_CREL_STEP_Pos) /* (CAN_CREL) Step of Core Release Mask */ 373 #define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & (_UINT32_(value) << CAN_CREL_STEP_Pos)) /* Assignment of value for STEP in the CAN_CREL register */ 374 #define CAN_CREL_REL_Pos _UINT32_(28) /* (CAN_CREL) Core Release Position */ 375 #define CAN_CREL_REL_Msk (_UINT32_(0xF) << CAN_CREL_REL_Pos) /* (CAN_CREL) Core Release Mask */ 376 #define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & (_UINT32_(value) << CAN_CREL_REL_Pos)) /* Assignment of value for REL in the CAN_CREL register */ 377 #define CAN_CREL_Msk _UINT32_(0xFFF00000) /* (CAN_CREL) Register Mask */ 378 379 380 /* -------- CAN_ENDN : (CAN Offset: 0x04) ( R/ 32) Endian -------- */ 381 #define CAN_ENDN_RESETVALUE _UINT32_(0x87654321) /* (CAN_ENDN) Endian Reset Value */ 382 383 #define CAN_ENDN_ETV_Pos _UINT32_(0) /* (CAN_ENDN) Endianness Test Value Position */ 384 #define CAN_ENDN_ETV_Msk (_UINT32_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) /* (CAN_ENDN) Endianness Test Value Mask */ 385 #define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & (_UINT32_(value) << CAN_ENDN_ETV_Pos)) /* Assignment of value for ETV in the CAN_ENDN register */ 386 #define CAN_ENDN_Msk _UINT32_(0xFFFFFFFF) /* (CAN_ENDN) Register Mask */ 387 388 389 /* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ 390 #define CAN_MRCFG_RESETVALUE _UINT32_(0x02) /* (CAN_MRCFG) Message RAM Configuration Reset Value */ 391 392 #define CAN_MRCFG_QOS_Pos _UINT32_(0) /* (CAN_MRCFG) Quality of Service Position */ 393 #define CAN_MRCFG_QOS_Msk (_UINT32_(0x3) << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Quality of Service Mask */ 394 #define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & (_UINT32_(value) << CAN_MRCFG_QOS_Pos)) /* Assignment of value for QOS in the CAN_MRCFG register */ 395 #define CAN_MRCFG_QOS_DISABLE_Val _UINT32_(0x0) /* (CAN_MRCFG) Background (no sensitive operation) */ 396 #define CAN_MRCFG_QOS_LOW_Val _UINT32_(0x1) /* (CAN_MRCFG) Sensitive Bandwidth */ 397 #define CAN_MRCFG_QOS_MEDIUM_Val _UINT32_(0x2) /* (CAN_MRCFG) Sensitive Latency */ 398 #define CAN_MRCFG_QOS_HIGH_Val _UINT32_(0x3) /* (CAN_MRCFG) Critical Latency */ 399 #define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Background (no sensitive operation) Position */ 400 #define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Bandwidth Position */ 401 #define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Sensitive Latency Position */ 402 #define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) /* (CAN_MRCFG) Critical Latency Position */ 403 #define CAN_MRCFG_Msk _UINT32_(0x00000003) /* (CAN_MRCFG) Register Mask */ 404 405 406 /* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ 407 #define CAN_DBTP_RESETVALUE _UINT32_(0xA33) /* (CAN_DBTP) Fast Bit Timing and Prescaler Reset Value */ 408 409 #define CAN_DBTP_DSJW_Pos _UINT32_(0) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Position */ 410 #define CAN_DBTP_DSJW_Msk (_UINT32_(0xF) << CAN_DBTP_DSJW_Pos) /* (CAN_DBTP) Data (Re)Synchronization Jump Width Mask */ 411 #define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & (_UINT32_(value) << CAN_DBTP_DSJW_Pos)) /* Assignment of value for DSJW in the CAN_DBTP register */ 412 #define CAN_DBTP_DTSEG2_Pos _UINT32_(4) /* (CAN_DBTP) Data time segment after sample point Position */ 413 #define CAN_DBTP_DTSEG2_Msk (_UINT32_(0xF) << CAN_DBTP_DTSEG2_Pos) /* (CAN_DBTP) Data time segment after sample point Mask */ 414 #define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG2_Pos)) /* Assignment of value for DTSEG2 in the CAN_DBTP register */ 415 #define CAN_DBTP_DTSEG1_Pos _UINT32_(8) /* (CAN_DBTP) Data time segment before sample point Position */ 416 #define CAN_DBTP_DTSEG1_Msk (_UINT32_(0x1F) << CAN_DBTP_DTSEG1_Pos) /* (CAN_DBTP) Data time segment before sample point Mask */ 417 #define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & (_UINT32_(value) << CAN_DBTP_DTSEG1_Pos)) /* Assignment of value for DTSEG1 in the CAN_DBTP register */ 418 #define CAN_DBTP_DBRP_Pos _UINT32_(16) /* (CAN_DBTP) Data Baud Rate Prescaler Position */ 419 #define CAN_DBTP_DBRP_Msk (_UINT32_(0x1F) << CAN_DBTP_DBRP_Pos) /* (CAN_DBTP) Data Baud Rate Prescaler Mask */ 420 #define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & (_UINT32_(value) << CAN_DBTP_DBRP_Pos)) /* Assignment of value for DBRP in the CAN_DBTP register */ 421 #define CAN_DBTP_TDC_Pos _UINT32_(23) /* (CAN_DBTP) Tranceiver Delay Compensation Position */ 422 #define CAN_DBTP_TDC_Msk (_UINT32_(0x1) << CAN_DBTP_TDC_Pos) /* (CAN_DBTP) Tranceiver Delay Compensation Mask */ 423 #define CAN_DBTP_TDC(value) (CAN_DBTP_TDC_Msk & (_UINT32_(value) << CAN_DBTP_TDC_Pos)) /* Assignment of value for TDC in the CAN_DBTP register */ 424 #define CAN_DBTP_Msk _UINT32_(0x009F1FFF) /* (CAN_DBTP) Register Mask */ 425 426 427 /* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ 428 #define CAN_TEST_RESETVALUE _UINT32_(0x00) /* (CAN_TEST) Test Reset Value */ 429 430 #define CAN_TEST_LBCK_Pos _UINT32_(4) /* (CAN_TEST) Loop Back Mode Position */ 431 #define CAN_TEST_LBCK_Msk (_UINT32_(0x1) << CAN_TEST_LBCK_Pos) /* (CAN_TEST) Loop Back Mode Mask */ 432 #define CAN_TEST_LBCK(value) (CAN_TEST_LBCK_Msk & (_UINT32_(value) << CAN_TEST_LBCK_Pos)) /* Assignment of value for LBCK in the CAN_TEST register */ 433 #define CAN_TEST_TX_Pos _UINT32_(5) /* (CAN_TEST) Control of Transmit Pin Position */ 434 #define CAN_TEST_TX_Msk (_UINT32_(0x3) << CAN_TEST_TX_Pos) /* (CAN_TEST) Control of Transmit Pin Mask */ 435 #define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & (_UINT32_(value) << CAN_TEST_TX_Pos)) /* Assignment of value for TX in the CAN_TEST register */ 436 #define CAN_TEST_TX_CORE_Val _UINT32_(0x0) /* (CAN_TEST) TX controlled by CAN core */ 437 #define CAN_TEST_TX_SAMPLE_Val _UINT32_(0x1) /* (CAN_TEST) TX monitoring sample point */ 438 #define CAN_TEST_TX_DOMINANT_Val _UINT32_(0x2) /* (CAN_TEST) Dominant (0) level at pin CAN_TX */ 439 #define CAN_TEST_TX_RECESSIVE_Val _UINT32_(0x3) /* (CAN_TEST) Recessive (1) level at pin CAN_TX */ 440 #define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX controlled by CAN core Position */ 441 #define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) TX monitoring sample point Position */ 442 #define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Dominant (0) level at pin CAN_TX Position */ 443 #define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) /* (CAN_TEST) Recessive (1) level at pin CAN_TX Position */ 444 #define CAN_TEST_RX_Pos _UINT32_(7) /* (CAN_TEST) Receive Pin Position */ 445 #define CAN_TEST_RX_Msk (_UINT32_(0x1) << CAN_TEST_RX_Pos) /* (CAN_TEST) Receive Pin Mask */ 446 #define CAN_TEST_RX(value) (CAN_TEST_RX_Msk & (_UINT32_(value) << CAN_TEST_RX_Pos)) /* Assignment of value for RX in the CAN_TEST register */ 447 #define CAN_TEST_Msk _UINT32_(0x000000F0) /* (CAN_TEST) Register Mask */ 448 449 450 /* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ 451 #define CAN_RWD_RESETVALUE _UINT32_(0x00) /* (CAN_RWD) RAM Watchdog Reset Value */ 452 453 #define CAN_RWD_WDC_Pos _UINT32_(0) /* (CAN_RWD) Watchdog Configuration Position */ 454 #define CAN_RWD_WDC_Msk (_UINT32_(0xFF) << CAN_RWD_WDC_Pos) /* (CAN_RWD) Watchdog Configuration Mask */ 455 #define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & (_UINT32_(value) << CAN_RWD_WDC_Pos)) /* Assignment of value for WDC in the CAN_RWD register */ 456 #define CAN_RWD_WDV_Pos _UINT32_(8) /* (CAN_RWD) Watchdog Value Position */ 457 #define CAN_RWD_WDV_Msk (_UINT32_(0xFF) << CAN_RWD_WDV_Pos) /* (CAN_RWD) Watchdog Value Mask */ 458 #define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & (_UINT32_(value) << CAN_RWD_WDV_Pos)) /* Assignment of value for WDV in the CAN_RWD register */ 459 #define CAN_RWD_Msk _UINT32_(0x0000FFFF) /* (CAN_RWD) Register Mask */ 460 461 462 /* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ 463 #define CAN_CCCR_RESETVALUE _UINT32_(0x01) /* (CAN_CCCR) CC Control Reset Value */ 464 465 #define CAN_CCCR_INIT_Pos _UINT32_(0) /* (CAN_CCCR) Initialization Position */ 466 #define CAN_CCCR_INIT_Msk (_UINT32_(0x1) << CAN_CCCR_INIT_Pos) /* (CAN_CCCR) Initialization Mask */ 467 #define CAN_CCCR_INIT(value) (CAN_CCCR_INIT_Msk & (_UINT32_(value) << CAN_CCCR_INIT_Pos)) /* Assignment of value for INIT in the CAN_CCCR register */ 468 #define CAN_CCCR_CCE_Pos _UINT32_(1) /* (CAN_CCCR) Configuration Change Enable Position */ 469 #define CAN_CCCR_CCE_Msk (_UINT32_(0x1) << CAN_CCCR_CCE_Pos) /* (CAN_CCCR) Configuration Change Enable Mask */ 470 #define CAN_CCCR_CCE(value) (CAN_CCCR_CCE_Msk & (_UINT32_(value) << CAN_CCCR_CCE_Pos)) /* Assignment of value for CCE in the CAN_CCCR register */ 471 #define CAN_CCCR_ASM_Pos _UINT32_(2) /* (CAN_CCCR) ASM Restricted Operation Mode Position */ 472 #define CAN_CCCR_ASM_Msk (_UINT32_(0x1) << CAN_CCCR_ASM_Pos) /* (CAN_CCCR) ASM Restricted Operation Mode Mask */ 473 #define CAN_CCCR_ASM(value) (CAN_CCCR_ASM_Msk & (_UINT32_(value) << CAN_CCCR_ASM_Pos)) /* Assignment of value for ASM in the CAN_CCCR register */ 474 #define CAN_CCCR_CSA_Pos _UINT32_(3) /* (CAN_CCCR) Clock Stop Acknowledge Position */ 475 #define CAN_CCCR_CSA_Msk (_UINT32_(0x1) << CAN_CCCR_CSA_Pos) /* (CAN_CCCR) Clock Stop Acknowledge Mask */ 476 #define CAN_CCCR_CSA(value) (CAN_CCCR_CSA_Msk & (_UINT32_(value) << CAN_CCCR_CSA_Pos)) /* Assignment of value for CSA in the CAN_CCCR register */ 477 #define CAN_CCCR_CSR_Pos _UINT32_(4) /* (CAN_CCCR) Clock Stop Request Position */ 478 #define CAN_CCCR_CSR_Msk (_UINT32_(0x1) << CAN_CCCR_CSR_Pos) /* (CAN_CCCR) Clock Stop Request Mask */ 479 #define CAN_CCCR_CSR(value) (CAN_CCCR_CSR_Msk & (_UINT32_(value) << CAN_CCCR_CSR_Pos)) /* Assignment of value for CSR in the CAN_CCCR register */ 480 #define CAN_CCCR_MON_Pos _UINT32_(5) /* (CAN_CCCR) Bus Monitoring Mode Position */ 481 #define CAN_CCCR_MON_Msk (_UINT32_(0x1) << CAN_CCCR_MON_Pos) /* (CAN_CCCR) Bus Monitoring Mode Mask */ 482 #define CAN_CCCR_MON(value) (CAN_CCCR_MON_Msk & (_UINT32_(value) << CAN_CCCR_MON_Pos)) /* Assignment of value for MON in the CAN_CCCR register */ 483 #define CAN_CCCR_DAR_Pos _UINT32_(6) /* (CAN_CCCR) Disable Automatic Retransmission Position */ 484 #define CAN_CCCR_DAR_Msk (_UINT32_(0x1) << CAN_CCCR_DAR_Pos) /* (CAN_CCCR) Disable Automatic Retransmission Mask */ 485 #define CAN_CCCR_DAR(value) (CAN_CCCR_DAR_Msk & (_UINT32_(value) << CAN_CCCR_DAR_Pos)) /* Assignment of value for DAR in the CAN_CCCR register */ 486 #define CAN_CCCR_TEST_Pos _UINT32_(7) /* (CAN_CCCR) Test Mode Enable Position */ 487 #define CAN_CCCR_TEST_Msk (_UINT32_(0x1) << CAN_CCCR_TEST_Pos) /* (CAN_CCCR) Test Mode Enable Mask */ 488 #define CAN_CCCR_TEST(value) (CAN_CCCR_TEST_Msk & (_UINT32_(value) << CAN_CCCR_TEST_Pos)) /* Assignment of value for TEST in the CAN_CCCR register */ 489 #define CAN_CCCR_FDOE_Pos _UINT32_(8) /* (CAN_CCCR) FD Operation Enable Position */ 490 #define CAN_CCCR_FDOE_Msk (_UINT32_(0x1) << CAN_CCCR_FDOE_Pos) /* (CAN_CCCR) FD Operation Enable Mask */ 491 #define CAN_CCCR_FDOE(value) (CAN_CCCR_FDOE_Msk & (_UINT32_(value) << CAN_CCCR_FDOE_Pos)) /* Assignment of value for FDOE in the CAN_CCCR register */ 492 #define CAN_CCCR_BRSE_Pos _UINT32_(9) /* (CAN_CCCR) Bit Rate Switch Enable Position */ 493 #define CAN_CCCR_BRSE_Msk (_UINT32_(0x1) << CAN_CCCR_BRSE_Pos) /* (CAN_CCCR) Bit Rate Switch Enable Mask */ 494 #define CAN_CCCR_BRSE(value) (CAN_CCCR_BRSE_Msk & (_UINT32_(value) << CAN_CCCR_BRSE_Pos)) /* Assignment of value for BRSE in the CAN_CCCR register */ 495 #define CAN_CCCR_PXHD_Pos _UINT32_(12) /* (CAN_CCCR) Protocol Exception Handling Disable Position */ 496 #define CAN_CCCR_PXHD_Msk (_UINT32_(0x1) << CAN_CCCR_PXHD_Pos) /* (CAN_CCCR) Protocol Exception Handling Disable Mask */ 497 #define CAN_CCCR_PXHD(value) (CAN_CCCR_PXHD_Msk & (_UINT32_(value) << CAN_CCCR_PXHD_Pos)) /* Assignment of value for PXHD in the CAN_CCCR register */ 498 #define CAN_CCCR_EFBI_Pos _UINT32_(13) /* (CAN_CCCR) Edge Filtering during Bus Integration Position */ 499 #define CAN_CCCR_EFBI_Msk (_UINT32_(0x1) << CAN_CCCR_EFBI_Pos) /* (CAN_CCCR) Edge Filtering during Bus Integration Mask */ 500 #define CAN_CCCR_EFBI(value) (CAN_CCCR_EFBI_Msk & (_UINT32_(value) << CAN_CCCR_EFBI_Pos)) /* Assignment of value for EFBI in the CAN_CCCR register */ 501 #define CAN_CCCR_TXP_Pos _UINT32_(14) /* (CAN_CCCR) Transmit Pause Position */ 502 #define CAN_CCCR_TXP_Msk (_UINT32_(0x1) << CAN_CCCR_TXP_Pos) /* (CAN_CCCR) Transmit Pause Mask */ 503 #define CAN_CCCR_TXP(value) (CAN_CCCR_TXP_Msk & (_UINT32_(value) << CAN_CCCR_TXP_Pos)) /* Assignment of value for TXP in the CAN_CCCR register */ 504 #define CAN_CCCR_Msk _UINT32_(0x000073FF) /* (CAN_CCCR) Register Mask */ 505 506 507 /* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ 508 #define CAN_NBTP_RESETVALUE _UINT32_(0x6000A03) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Reset Value */ 509 510 #define CAN_NBTP_NTSEG2_Pos _UINT32_(0) /* (CAN_NBTP) Nominal Time segment after sample point Position */ 511 #define CAN_NBTP_NTSEG2_Msk (_UINT32_(0x7F) << CAN_NBTP_NTSEG2_Pos) /* (CAN_NBTP) Nominal Time segment after sample point Mask */ 512 #define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG2_Pos)) /* Assignment of value for NTSEG2 in the CAN_NBTP register */ 513 #define CAN_NBTP_NTSEG1_Pos _UINT32_(8) /* (CAN_NBTP) Nominal Time segment before sample point Position */ 514 #define CAN_NBTP_NTSEG1_Msk (_UINT32_(0xFF) << CAN_NBTP_NTSEG1_Pos) /* (CAN_NBTP) Nominal Time segment before sample point Mask */ 515 #define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & (_UINT32_(value) << CAN_NBTP_NTSEG1_Pos)) /* Assignment of value for NTSEG1 in the CAN_NBTP register */ 516 #define CAN_NBTP_NBRP_Pos _UINT32_(16) /* (CAN_NBTP) Nominal Baud Rate Prescaler Position */ 517 #define CAN_NBTP_NBRP_Msk (_UINT32_(0x1FF) << CAN_NBTP_NBRP_Pos) /* (CAN_NBTP) Nominal Baud Rate Prescaler Mask */ 518 #define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & (_UINT32_(value) << CAN_NBTP_NBRP_Pos)) /* Assignment of value for NBRP in the CAN_NBTP register */ 519 #define CAN_NBTP_NSJW_Pos _UINT32_(25) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Position */ 520 #define CAN_NBTP_NSJW_Msk (_UINT32_(0x7F) << CAN_NBTP_NSJW_Pos) /* (CAN_NBTP) Nominal (Re)Synchronization Jump Width Mask */ 521 #define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & (_UINT32_(value) << CAN_NBTP_NSJW_Pos)) /* Assignment of value for NSJW in the CAN_NBTP register */ 522 #define CAN_NBTP_Msk _UINT32_(0xFFFFFF7F) /* (CAN_NBTP) Register Mask */ 523 524 525 /* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ 526 #define CAN_TSCC_RESETVALUE _UINT32_(0x00) /* (CAN_TSCC) Timestamp Counter Configuration Reset Value */ 527 528 #define CAN_TSCC_TSS_Pos _UINT32_(0) /* (CAN_TSCC) Timestamp Select Position */ 529 #define CAN_TSCC_TSS_Msk (_UINT32_(0x3) << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp Select Mask */ 530 #define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & (_UINT32_(value) << CAN_TSCC_TSS_Pos)) /* Assignment of value for TSS in the CAN_TSCC register */ 531 #define CAN_TSCC_TSS_ZERO_Val _UINT32_(0x0) /* (CAN_TSCC) Timestamp counter value always 0x0000 */ 532 #define CAN_TSCC_TSS_INC_Val _UINT32_(0x1) /* (CAN_TSCC) Timestamp counter value incremented by TCP */ 533 #define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value always 0x0000 Position */ 534 #define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) /* (CAN_TSCC) Timestamp counter value incremented by TCP Position */ 535 #define CAN_TSCC_TCP_Pos _UINT32_(16) /* (CAN_TSCC) Timestamp Counter Prescaler Position */ 536 #define CAN_TSCC_TCP_Msk (_UINT32_(0xF) << CAN_TSCC_TCP_Pos) /* (CAN_TSCC) Timestamp Counter Prescaler Mask */ 537 #define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & (_UINT32_(value) << CAN_TSCC_TCP_Pos)) /* Assignment of value for TCP in the CAN_TSCC register */ 538 #define CAN_TSCC_Msk _UINT32_(0x000F0003) /* (CAN_TSCC) Register Mask */ 539 540 541 /* -------- CAN_TSCV : (CAN Offset: 0x24) ( R/ 32) Timestamp Counter Value -------- */ 542 #define CAN_TSCV_RESETVALUE _UINT32_(0x00) /* (CAN_TSCV) Timestamp Counter Value Reset Value */ 543 544 #define CAN_TSCV_TSC_Pos _UINT32_(0) /* (CAN_TSCV) Timestamp Counter Position */ 545 #define CAN_TSCV_TSC_Msk (_UINT32_(0xFFFF) << CAN_TSCV_TSC_Pos) /* (CAN_TSCV) Timestamp Counter Mask */ 546 #define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & (_UINT32_(value) << CAN_TSCV_TSC_Pos)) /* Assignment of value for TSC in the CAN_TSCV register */ 547 #define CAN_TSCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TSCV) Register Mask */ 548 549 550 /* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ 551 #define CAN_TOCC_RESETVALUE _UINT32_(0xFFFF0000) /* (CAN_TOCC) Timeout Counter Configuration Reset Value */ 552 553 #define CAN_TOCC_ETOC_Pos _UINT32_(0) /* (CAN_TOCC) Enable Timeout Counter Position */ 554 #define CAN_TOCC_ETOC_Msk (_UINT32_(0x1) << CAN_TOCC_ETOC_Pos) /* (CAN_TOCC) Enable Timeout Counter Mask */ 555 #define CAN_TOCC_ETOC(value) (CAN_TOCC_ETOC_Msk & (_UINT32_(value) << CAN_TOCC_ETOC_Pos)) /* Assignment of value for ETOC in the CAN_TOCC register */ 556 #define CAN_TOCC_TOS_Pos _UINT32_(1) /* (CAN_TOCC) Timeout Select Position */ 557 #define CAN_TOCC_TOS_Msk (_UINT32_(0x3) << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout Select Mask */ 558 #define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & (_UINT32_(value) << CAN_TOCC_TOS_Pos)) /* Assignment of value for TOS in the CAN_TOCC register */ 559 #define CAN_TOCC_TOS_CONT_Val _UINT32_(0x0) /* (CAN_TOCC) Continuout operation */ 560 #define CAN_TOCC_TOS_TXEF_Val _UINT32_(0x1) /* (CAN_TOCC) Timeout controlled by TX Event FIFO */ 561 #define CAN_TOCC_TOS_RXF0_Val _UINT32_(0x2) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ 562 #define CAN_TOCC_TOS_RXF1_Val _UINT32_(0x3) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ 563 #define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Continuout operation Position */ 564 #define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by TX Event FIFO Position */ 565 #define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 0 Position */ 566 #define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) /* (CAN_TOCC) Timeout controlled by Rx FIFO 1 Position */ 567 #define CAN_TOCC_TOP_Pos _UINT32_(16) /* (CAN_TOCC) Timeout Period Position */ 568 #define CAN_TOCC_TOP_Msk (_UINT32_(0xFFFF) << CAN_TOCC_TOP_Pos) /* (CAN_TOCC) Timeout Period Mask */ 569 #define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & (_UINT32_(value) << CAN_TOCC_TOP_Pos)) /* Assignment of value for TOP in the CAN_TOCC register */ 570 #define CAN_TOCC_Msk _UINT32_(0xFFFF0007) /* (CAN_TOCC) Register Mask */ 571 572 573 /* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ 574 #define CAN_TOCV_RESETVALUE _UINT32_(0xFFFF) /* (CAN_TOCV) Timeout Counter Value Reset Value */ 575 576 #define CAN_TOCV_TOC_Pos _UINT32_(0) /* (CAN_TOCV) Timeout Counter Position */ 577 #define CAN_TOCV_TOC_Msk (_UINT32_(0xFFFF) << CAN_TOCV_TOC_Pos) /* (CAN_TOCV) Timeout Counter Mask */ 578 #define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & (_UINT32_(value) << CAN_TOCV_TOC_Pos)) /* Assignment of value for TOC in the CAN_TOCV register */ 579 #define CAN_TOCV_Msk _UINT32_(0x0000FFFF) /* (CAN_TOCV) Register Mask */ 580 581 582 /* -------- CAN_ECR : (CAN Offset: 0x40) ( R/ 32) Error Counter -------- */ 583 #define CAN_ECR_RESETVALUE _UINT32_(0x00) /* (CAN_ECR) Error Counter Reset Value */ 584 585 #define CAN_ECR_TEC_Pos _UINT32_(0) /* (CAN_ECR) Transmit Error Counter Position */ 586 #define CAN_ECR_TEC_Msk (_UINT32_(0xFF) << CAN_ECR_TEC_Pos) /* (CAN_ECR) Transmit Error Counter Mask */ 587 #define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & (_UINT32_(value) << CAN_ECR_TEC_Pos)) /* Assignment of value for TEC in the CAN_ECR register */ 588 #define CAN_ECR_REC_Pos _UINT32_(8) /* (CAN_ECR) Receive Error Counter Position */ 589 #define CAN_ECR_REC_Msk (_UINT32_(0x7F) << CAN_ECR_REC_Pos) /* (CAN_ECR) Receive Error Counter Mask */ 590 #define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & (_UINT32_(value) << CAN_ECR_REC_Pos)) /* Assignment of value for REC in the CAN_ECR register */ 591 #define CAN_ECR_RP_Pos _UINT32_(15) /* (CAN_ECR) Receive Error Passive Position */ 592 #define CAN_ECR_RP_Msk (_UINT32_(0x1) << CAN_ECR_RP_Pos) /* (CAN_ECR) Receive Error Passive Mask */ 593 #define CAN_ECR_RP(value) (CAN_ECR_RP_Msk & (_UINT32_(value) << CAN_ECR_RP_Pos)) /* Assignment of value for RP in the CAN_ECR register */ 594 #define CAN_ECR_CEL_Pos _UINT32_(16) /* (CAN_ECR) CAN Error Logging Position */ 595 #define CAN_ECR_CEL_Msk (_UINT32_(0xFF) << CAN_ECR_CEL_Pos) /* (CAN_ECR) CAN Error Logging Mask */ 596 #define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & (_UINT32_(value) << CAN_ECR_CEL_Pos)) /* Assignment of value for CEL in the CAN_ECR register */ 597 #define CAN_ECR_Msk _UINT32_(0x00FFFFFF) /* (CAN_ECR) Register Mask */ 598 599 600 /* -------- CAN_PSR : (CAN Offset: 0x44) ( R/ 32) Protocol Status -------- */ 601 #define CAN_PSR_RESETVALUE _UINT32_(0x707) /* (CAN_PSR) Protocol Status Reset Value */ 602 603 #define CAN_PSR_LEC_Pos _UINT32_(0) /* (CAN_PSR) Last Error Code Position */ 604 #define CAN_PSR_LEC_Msk (_UINT32_(0x7) << CAN_PSR_LEC_Pos) /* (CAN_PSR) Last Error Code Mask */ 605 #define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & (_UINT32_(value) << CAN_PSR_LEC_Pos)) /* Assignment of value for LEC in the CAN_PSR register */ 606 #define CAN_PSR_LEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ 607 #define CAN_PSR_LEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ 608 #define CAN_PSR_LEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ 609 #define CAN_PSR_LEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ 610 #define CAN_PSR_LEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ 611 #define CAN_PSR_LEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ 612 #define CAN_PSR_LEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ 613 #define CAN_PSR_LEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ 614 #define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Error Position */ 615 #define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Stuff Error Position */ 616 #define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Form Error Position */ 617 #define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Ack Error Position */ 618 #define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit1 Error Position */ 619 #define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) Bit0 Error Position */ 620 #define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) CRC Error Position */ 621 #define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) /* (CAN_PSR) No Change Position */ 622 #define CAN_PSR_ACT_Pos _UINT32_(3) /* (CAN_PSR) Activity Position */ 623 #define CAN_PSR_ACT_Msk (_UINT32_(0x3) << CAN_PSR_ACT_Pos) /* (CAN_PSR) Activity Mask */ 624 #define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & (_UINT32_(value) << CAN_PSR_ACT_Pos)) /* Assignment of value for ACT in the CAN_PSR register */ 625 #define CAN_PSR_ACT_SYNC_Val _UINT32_(0x0) /* (CAN_PSR) Node is synchronizing on CAN communication */ 626 #define CAN_PSR_ACT_IDLE_Val _UINT32_(0x1) /* (CAN_PSR) Node is neither receiver nor transmitter */ 627 #define CAN_PSR_ACT_RX_Val _UINT32_(0x2) /* (CAN_PSR) Node is operating as receiver */ 628 #define CAN_PSR_ACT_TX_Val _UINT32_(0x3) /* (CAN_PSR) Node is operating as transmitter */ 629 #define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is synchronizing on CAN communication Position */ 630 #define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is neither receiver nor transmitter Position */ 631 #define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as receiver Position */ 632 #define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) /* (CAN_PSR) Node is operating as transmitter Position */ 633 #define CAN_PSR_EP_Pos _UINT32_(5) /* (CAN_PSR) Error Passive Position */ 634 #define CAN_PSR_EP_Msk (_UINT32_(0x1) << CAN_PSR_EP_Pos) /* (CAN_PSR) Error Passive Mask */ 635 #define CAN_PSR_EP(value) (CAN_PSR_EP_Msk & (_UINT32_(value) << CAN_PSR_EP_Pos)) /* Assignment of value for EP in the CAN_PSR register */ 636 #define CAN_PSR_EW_Pos _UINT32_(6) /* (CAN_PSR) Warning Status Position */ 637 #define CAN_PSR_EW_Msk (_UINT32_(0x1) << CAN_PSR_EW_Pos) /* (CAN_PSR) Warning Status Mask */ 638 #define CAN_PSR_EW(value) (CAN_PSR_EW_Msk & (_UINT32_(value) << CAN_PSR_EW_Pos)) /* Assignment of value for EW in the CAN_PSR register */ 639 #define CAN_PSR_BO_Pos _UINT32_(7) /* (CAN_PSR) Bus_Off Status Position */ 640 #define CAN_PSR_BO_Msk (_UINT32_(0x1) << CAN_PSR_BO_Pos) /* (CAN_PSR) Bus_Off Status Mask */ 641 #define CAN_PSR_BO(value) (CAN_PSR_BO_Msk & (_UINT32_(value) << CAN_PSR_BO_Pos)) /* Assignment of value for BO in the CAN_PSR register */ 642 #define CAN_PSR_DLEC_Pos _UINT32_(8) /* (CAN_PSR) Data Phase Last Error Code Position */ 643 #define CAN_PSR_DLEC_Msk (_UINT32_(0x7) << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Data Phase Last Error Code Mask */ 644 #define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & (_UINT32_(value) << CAN_PSR_DLEC_Pos)) /* Assignment of value for DLEC in the CAN_PSR register */ 645 #define CAN_PSR_DLEC_NONE_Val _UINT32_(0x0) /* (CAN_PSR) No Error */ 646 #define CAN_PSR_DLEC_STUFF_Val _UINT32_(0x1) /* (CAN_PSR) Stuff Error */ 647 #define CAN_PSR_DLEC_FORM_Val _UINT32_(0x2) /* (CAN_PSR) Form Error */ 648 #define CAN_PSR_DLEC_ACK_Val _UINT32_(0x3) /* (CAN_PSR) Ack Error */ 649 #define CAN_PSR_DLEC_BIT1_Val _UINT32_(0x4) /* (CAN_PSR) Bit1 Error */ 650 #define CAN_PSR_DLEC_BIT0_Val _UINT32_(0x5) /* (CAN_PSR) Bit0 Error */ 651 #define CAN_PSR_DLEC_CRC_Val _UINT32_(0x6) /* (CAN_PSR) CRC Error */ 652 #define CAN_PSR_DLEC_NC_Val _UINT32_(0x7) /* (CAN_PSR) No Change */ 653 #define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Error Position */ 654 #define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Stuff Error Position */ 655 #define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Form Error Position */ 656 #define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Ack Error Position */ 657 #define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit1 Error Position */ 658 #define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) Bit0 Error Position */ 659 #define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) CRC Error Position */ 660 #define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) /* (CAN_PSR) No Change Position */ 661 #define CAN_PSR_RESI_Pos _UINT32_(11) /* (CAN_PSR) ESI flag of last received CAN FD Message Position */ 662 #define CAN_PSR_RESI_Msk (_UINT32_(0x1) << CAN_PSR_RESI_Pos) /* (CAN_PSR) ESI flag of last received CAN FD Message Mask */ 663 #define CAN_PSR_RESI(value) (CAN_PSR_RESI_Msk & (_UINT32_(value) << CAN_PSR_RESI_Pos)) /* Assignment of value for RESI in the CAN_PSR register */ 664 #define CAN_PSR_RBRS_Pos _UINT32_(12) /* (CAN_PSR) BRS flag of last received CAN FD Message Position */ 665 #define CAN_PSR_RBRS_Msk (_UINT32_(0x1) << CAN_PSR_RBRS_Pos) /* (CAN_PSR) BRS flag of last received CAN FD Message Mask */ 666 #define CAN_PSR_RBRS(value) (CAN_PSR_RBRS_Msk & (_UINT32_(value) << CAN_PSR_RBRS_Pos)) /* Assignment of value for RBRS in the CAN_PSR register */ 667 #define CAN_PSR_RFDF_Pos _UINT32_(13) /* (CAN_PSR) Received a CAN FD Message Position */ 668 #define CAN_PSR_RFDF_Msk (_UINT32_(0x1) << CAN_PSR_RFDF_Pos) /* (CAN_PSR) Received a CAN FD Message Mask */ 669 #define CAN_PSR_RFDF(value) (CAN_PSR_RFDF_Msk & (_UINT32_(value) << CAN_PSR_RFDF_Pos)) /* Assignment of value for RFDF in the CAN_PSR register */ 670 #define CAN_PSR_PXE_Pos _UINT32_(14) /* (CAN_PSR) Protocol Exception Event Position */ 671 #define CAN_PSR_PXE_Msk (_UINT32_(0x1) << CAN_PSR_PXE_Pos) /* (CAN_PSR) Protocol Exception Event Mask */ 672 #define CAN_PSR_PXE(value) (CAN_PSR_PXE_Msk & (_UINT32_(value) << CAN_PSR_PXE_Pos)) /* Assignment of value for PXE in the CAN_PSR register */ 673 #define CAN_PSR_TDCV_Pos _UINT32_(16) /* (CAN_PSR) Transmitter Delay Compensation Value Position */ 674 #define CAN_PSR_TDCV_Msk (_UINT32_(0x7F) << CAN_PSR_TDCV_Pos) /* (CAN_PSR) Transmitter Delay Compensation Value Mask */ 675 #define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & (_UINT32_(value) << CAN_PSR_TDCV_Pos)) /* Assignment of value for TDCV in the CAN_PSR register */ 676 #define CAN_PSR_Msk _UINT32_(0x007F7FFF) /* (CAN_PSR) Register Mask */ 677 678 679 /* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ 680 #define CAN_TDCR_RESETVALUE _UINT32_(0x00) /* (CAN_TDCR) Extended ID Filter Configuration Reset Value */ 681 682 #define CAN_TDCR_TDCF_Pos _UINT32_(0) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Position */ 683 #define CAN_TDCR_TDCF_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCF_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Filter Length Mask */ 684 #define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & (_UINT32_(value) << CAN_TDCR_TDCF_Pos)) /* Assignment of value for TDCF in the CAN_TDCR register */ 685 #define CAN_TDCR_TDCO_Pos _UINT32_(8) /* (CAN_TDCR) Transmitter Delay Compensation Offset Position */ 686 #define CAN_TDCR_TDCO_Msk (_UINT32_(0x7F) << CAN_TDCR_TDCO_Pos) /* (CAN_TDCR) Transmitter Delay Compensation Offset Mask */ 687 #define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & (_UINT32_(value) << CAN_TDCR_TDCO_Pos)) /* Assignment of value for TDCO in the CAN_TDCR register */ 688 #define CAN_TDCR_Msk _UINT32_(0x00007F7F) /* (CAN_TDCR) Register Mask */ 689 690 691 /* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ 692 #define CAN_IR_RESETVALUE _UINT32_(0x00) /* (CAN_IR) Interrupt Reset Value */ 693 694 #define CAN_IR_RF0N_Pos _UINT32_(0) /* (CAN_IR) Rx FIFO 0 New Message Position */ 695 #define CAN_IR_RF0N_Msk (_UINT32_(0x1) << CAN_IR_RF0N_Pos) /* (CAN_IR) Rx FIFO 0 New Message Mask */ 696 #define CAN_IR_RF0N(value) (CAN_IR_RF0N_Msk & (_UINT32_(value) << CAN_IR_RF0N_Pos)) /* Assignment of value for RF0N in the CAN_IR register */ 697 #define CAN_IR_RF0W_Pos _UINT32_(1) /* (CAN_IR) Rx FIFO 0 Watermark Reached Position */ 698 #define CAN_IR_RF0W_Msk (_UINT32_(0x1) << CAN_IR_RF0W_Pos) /* (CAN_IR) Rx FIFO 0 Watermark Reached Mask */ 699 #define CAN_IR_RF0W(value) (CAN_IR_RF0W_Msk & (_UINT32_(value) << CAN_IR_RF0W_Pos)) /* Assignment of value for RF0W in the CAN_IR register */ 700 #define CAN_IR_RF0F_Pos _UINT32_(2) /* (CAN_IR) Rx FIFO 0 Full Position */ 701 #define CAN_IR_RF0F_Msk (_UINT32_(0x1) << CAN_IR_RF0F_Pos) /* (CAN_IR) Rx FIFO 0 Full Mask */ 702 #define CAN_IR_RF0F(value) (CAN_IR_RF0F_Msk & (_UINT32_(value) << CAN_IR_RF0F_Pos)) /* Assignment of value for RF0F in the CAN_IR register */ 703 #define CAN_IR_RF0L_Pos _UINT32_(3) /* (CAN_IR) Rx FIFO 0 Message Lost Position */ 704 #define CAN_IR_RF0L_Msk (_UINT32_(0x1) << CAN_IR_RF0L_Pos) /* (CAN_IR) Rx FIFO 0 Message Lost Mask */ 705 #define CAN_IR_RF0L(value) (CAN_IR_RF0L_Msk & (_UINT32_(value) << CAN_IR_RF0L_Pos)) /* Assignment of value for RF0L in the CAN_IR register */ 706 #define CAN_IR_RF1N_Pos _UINT32_(4) /* (CAN_IR) Rx FIFO 1 New Message Position */ 707 #define CAN_IR_RF1N_Msk (_UINT32_(0x1) << CAN_IR_RF1N_Pos) /* (CAN_IR) Rx FIFO 1 New Message Mask */ 708 #define CAN_IR_RF1N(value) (CAN_IR_RF1N_Msk & (_UINT32_(value) << CAN_IR_RF1N_Pos)) /* Assignment of value for RF1N in the CAN_IR register */ 709 #define CAN_IR_RF1W_Pos _UINT32_(5) /* (CAN_IR) Rx FIFO 1 Watermark Reached Position */ 710 #define CAN_IR_RF1W_Msk (_UINT32_(0x1) << CAN_IR_RF1W_Pos) /* (CAN_IR) Rx FIFO 1 Watermark Reached Mask */ 711 #define CAN_IR_RF1W(value) (CAN_IR_RF1W_Msk & (_UINT32_(value) << CAN_IR_RF1W_Pos)) /* Assignment of value for RF1W in the CAN_IR register */ 712 #define CAN_IR_RF1F_Pos _UINT32_(6) /* (CAN_IR) Rx FIFO 1 FIFO Full Position */ 713 #define CAN_IR_RF1F_Msk (_UINT32_(0x1) << CAN_IR_RF1F_Pos) /* (CAN_IR) Rx FIFO 1 FIFO Full Mask */ 714 #define CAN_IR_RF1F(value) (CAN_IR_RF1F_Msk & (_UINT32_(value) << CAN_IR_RF1F_Pos)) /* Assignment of value for RF1F in the CAN_IR register */ 715 #define CAN_IR_RF1L_Pos _UINT32_(7) /* (CAN_IR) Rx FIFO 1 Message Lost Position */ 716 #define CAN_IR_RF1L_Msk (_UINT32_(0x1) << CAN_IR_RF1L_Pos) /* (CAN_IR) Rx FIFO 1 Message Lost Mask */ 717 #define CAN_IR_RF1L(value) (CAN_IR_RF1L_Msk & (_UINT32_(value) << CAN_IR_RF1L_Pos)) /* Assignment of value for RF1L in the CAN_IR register */ 718 #define CAN_IR_HPM_Pos _UINT32_(8) /* (CAN_IR) High Priority Message Position */ 719 #define CAN_IR_HPM_Msk (_UINT32_(0x1) << CAN_IR_HPM_Pos) /* (CAN_IR) High Priority Message Mask */ 720 #define CAN_IR_HPM(value) (CAN_IR_HPM_Msk & (_UINT32_(value) << CAN_IR_HPM_Pos)) /* Assignment of value for HPM in the CAN_IR register */ 721 #define CAN_IR_TC_Pos _UINT32_(9) /* (CAN_IR) Timestamp Completed Position */ 722 #define CAN_IR_TC_Msk (_UINT32_(0x1) << CAN_IR_TC_Pos) /* (CAN_IR) Timestamp Completed Mask */ 723 #define CAN_IR_TC(value) (CAN_IR_TC_Msk & (_UINT32_(value) << CAN_IR_TC_Pos)) /* Assignment of value for TC in the CAN_IR register */ 724 #define CAN_IR_TCF_Pos _UINT32_(10) /* (CAN_IR) Transmission Cancellation Finished Position */ 725 #define CAN_IR_TCF_Msk (_UINT32_(0x1) << CAN_IR_TCF_Pos) /* (CAN_IR) Transmission Cancellation Finished Mask */ 726 #define CAN_IR_TCF(value) (CAN_IR_TCF_Msk & (_UINT32_(value) << CAN_IR_TCF_Pos)) /* Assignment of value for TCF in the CAN_IR register */ 727 #define CAN_IR_TFE_Pos _UINT32_(11) /* (CAN_IR) Tx FIFO Empty Position */ 728 #define CAN_IR_TFE_Msk (_UINT32_(0x1) << CAN_IR_TFE_Pos) /* (CAN_IR) Tx FIFO Empty Mask */ 729 #define CAN_IR_TFE(value) (CAN_IR_TFE_Msk & (_UINT32_(value) << CAN_IR_TFE_Pos)) /* Assignment of value for TFE in the CAN_IR register */ 730 #define CAN_IR_TEFN_Pos _UINT32_(12) /* (CAN_IR) Tx Event FIFO New Entry Position */ 731 #define CAN_IR_TEFN_Msk (_UINT32_(0x1) << CAN_IR_TEFN_Pos) /* (CAN_IR) Tx Event FIFO New Entry Mask */ 732 #define CAN_IR_TEFN(value) (CAN_IR_TEFN_Msk & (_UINT32_(value) << CAN_IR_TEFN_Pos)) /* Assignment of value for TEFN in the CAN_IR register */ 733 #define CAN_IR_TEFW_Pos _UINT32_(13) /* (CAN_IR) Tx Event FIFO Watermark Reached Position */ 734 #define CAN_IR_TEFW_Msk (_UINT32_(0x1) << CAN_IR_TEFW_Pos) /* (CAN_IR) Tx Event FIFO Watermark Reached Mask */ 735 #define CAN_IR_TEFW(value) (CAN_IR_TEFW_Msk & (_UINT32_(value) << CAN_IR_TEFW_Pos)) /* Assignment of value for TEFW in the CAN_IR register */ 736 #define CAN_IR_TEFF_Pos _UINT32_(14) /* (CAN_IR) Tx Event FIFO Full Position */ 737 #define CAN_IR_TEFF_Msk (_UINT32_(0x1) << CAN_IR_TEFF_Pos) /* (CAN_IR) Tx Event FIFO Full Mask */ 738 #define CAN_IR_TEFF(value) (CAN_IR_TEFF_Msk & (_UINT32_(value) << CAN_IR_TEFF_Pos)) /* Assignment of value for TEFF in the CAN_IR register */ 739 #define CAN_IR_TEFL_Pos _UINT32_(15) /* (CAN_IR) Tx Event FIFO Element Lost Position */ 740 #define CAN_IR_TEFL_Msk (_UINT32_(0x1) << CAN_IR_TEFL_Pos) /* (CAN_IR) Tx Event FIFO Element Lost Mask */ 741 #define CAN_IR_TEFL(value) (CAN_IR_TEFL_Msk & (_UINT32_(value) << CAN_IR_TEFL_Pos)) /* Assignment of value for TEFL in the CAN_IR register */ 742 #define CAN_IR_TSW_Pos _UINT32_(16) /* (CAN_IR) Timestamp Wraparound Position */ 743 #define CAN_IR_TSW_Msk (_UINT32_(0x1) << CAN_IR_TSW_Pos) /* (CAN_IR) Timestamp Wraparound Mask */ 744 #define CAN_IR_TSW(value) (CAN_IR_TSW_Msk & (_UINT32_(value) << CAN_IR_TSW_Pos)) /* Assignment of value for TSW in the CAN_IR register */ 745 #define CAN_IR_MRAF_Pos _UINT32_(17) /* (CAN_IR) Message RAM Access Failure Position */ 746 #define CAN_IR_MRAF_Msk (_UINT32_(0x1) << CAN_IR_MRAF_Pos) /* (CAN_IR) Message RAM Access Failure Mask */ 747 #define CAN_IR_MRAF(value) (CAN_IR_MRAF_Msk & (_UINT32_(value) << CAN_IR_MRAF_Pos)) /* Assignment of value for MRAF in the CAN_IR register */ 748 #define CAN_IR_TOO_Pos _UINT32_(18) /* (CAN_IR) Timeout Occurred Position */ 749 #define CAN_IR_TOO_Msk (_UINT32_(0x1) << CAN_IR_TOO_Pos) /* (CAN_IR) Timeout Occurred Mask */ 750 #define CAN_IR_TOO(value) (CAN_IR_TOO_Msk & (_UINT32_(value) << CAN_IR_TOO_Pos)) /* Assignment of value for TOO in the CAN_IR register */ 751 #define CAN_IR_DRX_Pos _UINT32_(19) /* (CAN_IR) Message stored to Dedicated Rx Buffer Position */ 752 #define CAN_IR_DRX_Msk (_UINT32_(0x1) << CAN_IR_DRX_Pos) /* (CAN_IR) Message stored to Dedicated Rx Buffer Mask */ 753 #define CAN_IR_DRX(value) (CAN_IR_DRX_Msk & (_UINT32_(value) << CAN_IR_DRX_Pos)) /* Assignment of value for DRX in the CAN_IR register */ 754 #define CAN_IR_BEC_Pos _UINT32_(20) /* (CAN_IR) Bit Error Corrected Position */ 755 #define CAN_IR_BEC_Msk (_UINT32_(0x1) << CAN_IR_BEC_Pos) /* (CAN_IR) Bit Error Corrected Mask */ 756 #define CAN_IR_BEC(value) (CAN_IR_BEC_Msk & (_UINT32_(value) << CAN_IR_BEC_Pos)) /* Assignment of value for BEC in the CAN_IR register */ 757 #define CAN_IR_BEU_Pos _UINT32_(21) /* (CAN_IR) Bit Error Uncorrected Position */ 758 #define CAN_IR_BEU_Msk (_UINT32_(0x1) << CAN_IR_BEU_Pos) /* (CAN_IR) Bit Error Uncorrected Mask */ 759 #define CAN_IR_BEU(value) (CAN_IR_BEU_Msk & (_UINT32_(value) << CAN_IR_BEU_Pos)) /* Assignment of value for BEU in the CAN_IR register */ 760 #define CAN_IR_ELO_Pos _UINT32_(22) /* (CAN_IR) Error Logging Overflow Position */ 761 #define CAN_IR_ELO_Msk (_UINT32_(0x1) << CAN_IR_ELO_Pos) /* (CAN_IR) Error Logging Overflow Mask */ 762 #define CAN_IR_ELO(value) (CAN_IR_ELO_Msk & (_UINT32_(value) << CAN_IR_ELO_Pos)) /* Assignment of value for ELO in the CAN_IR register */ 763 #define CAN_IR_EP_Pos _UINT32_(23) /* (CAN_IR) Error Passive Position */ 764 #define CAN_IR_EP_Msk (_UINT32_(0x1) << CAN_IR_EP_Pos) /* (CAN_IR) Error Passive Mask */ 765 #define CAN_IR_EP(value) (CAN_IR_EP_Msk & (_UINT32_(value) << CAN_IR_EP_Pos)) /* Assignment of value for EP in the CAN_IR register */ 766 #define CAN_IR_EW_Pos _UINT32_(24) /* (CAN_IR) Warning Status Position */ 767 #define CAN_IR_EW_Msk (_UINT32_(0x1) << CAN_IR_EW_Pos) /* (CAN_IR) Warning Status Mask */ 768 #define CAN_IR_EW(value) (CAN_IR_EW_Msk & (_UINT32_(value) << CAN_IR_EW_Pos)) /* Assignment of value for EW in the CAN_IR register */ 769 #define CAN_IR_BO_Pos _UINT32_(25) /* (CAN_IR) Bus_Off Status Position */ 770 #define CAN_IR_BO_Msk (_UINT32_(0x1) << CAN_IR_BO_Pos) /* (CAN_IR) Bus_Off Status Mask */ 771 #define CAN_IR_BO(value) (CAN_IR_BO_Msk & (_UINT32_(value) << CAN_IR_BO_Pos)) /* Assignment of value for BO in the CAN_IR register */ 772 #define CAN_IR_WDI_Pos _UINT32_(26) /* (CAN_IR) Watchdog Interrupt Position */ 773 #define CAN_IR_WDI_Msk (_UINT32_(0x1) << CAN_IR_WDI_Pos) /* (CAN_IR) Watchdog Interrupt Mask */ 774 #define CAN_IR_WDI(value) (CAN_IR_WDI_Msk & (_UINT32_(value) << CAN_IR_WDI_Pos)) /* Assignment of value for WDI in the CAN_IR register */ 775 #define CAN_IR_PEA_Pos _UINT32_(27) /* (CAN_IR) Protocol Error in Arbitration Phase Position */ 776 #define CAN_IR_PEA_Msk (_UINT32_(0x1) << CAN_IR_PEA_Pos) /* (CAN_IR) Protocol Error in Arbitration Phase Mask */ 777 #define CAN_IR_PEA(value) (CAN_IR_PEA_Msk & (_UINT32_(value) << CAN_IR_PEA_Pos)) /* Assignment of value for PEA in the CAN_IR register */ 778 #define CAN_IR_PED_Pos _UINT32_(28) /* (CAN_IR) Protocol Error in Data Phase Position */ 779 #define CAN_IR_PED_Msk (_UINT32_(0x1) << CAN_IR_PED_Pos) /* (CAN_IR) Protocol Error in Data Phase Mask */ 780 #define CAN_IR_PED(value) (CAN_IR_PED_Msk & (_UINT32_(value) << CAN_IR_PED_Pos)) /* Assignment of value for PED in the CAN_IR register */ 781 #define CAN_IR_ARA_Pos _UINT32_(29) /* (CAN_IR) Access to Reserved Address Position */ 782 #define CAN_IR_ARA_Msk (_UINT32_(0x1) << CAN_IR_ARA_Pos) /* (CAN_IR) Access to Reserved Address Mask */ 783 #define CAN_IR_ARA(value) (CAN_IR_ARA_Msk & (_UINT32_(value) << CAN_IR_ARA_Pos)) /* Assignment of value for ARA in the CAN_IR register */ 784 #define CAN_IR_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IR) Register Mask */ 785 786 787 /* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ 788 #define CAN_IE_RESETVALUE _UINT32_(0x00) /* (CAN_IE) Interrupt Enable Reset Value */ 789 790 #define CAN_IE_RF0NE_Pos _UINT32_(0) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Position */ 791 #define CAN_IE_RF0NE_Msk (_UINT32_(0x1) << CAN_IE_RF0NE_Pos) /* (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Mask */ 792 #define CAN_IE_RF0NE(value) (CAN_IE_RF0NE_Msk & (_UINT32_(value) << CAN_IE_RF0NE_Pos)) /* Assignment of value for RF0NE in the CAN_IE register */ 793 #define CAN_IE_RF0WE_Pos _UINT32_(1) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Position */ 794 #define CAN_IE_RF0WE_Msk (_UINT32_(0x1) << CAN_IE_RF0WE_Pos) /* (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Mask */ 795 #define CAN_IE_RF0WE(value) (CAN_IE_RF0WE_Msk & (_UINT32_(value) << CAN_IE_RF0WE_Pos)) /* Assignment of value for RF0WE in the CAN_IE register */ 796 #define CAN_IE_RF0FE_Pos _UINT32_(2) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Position */ 797 #define CAN_IE_RF0FE_Msk (_UINT32_(0x1) << CAN_IE_RF0FE_Pos) /* (CAN_IE) Rx FIFO 0 Full Interrupt Enable Mask */ 798 #define CAN_IE_RF0FE(value) (CAN_IE_RF0FE_Msk & (_UINT32_(value) << CAN_IE_RF0FE_Pos)) /* Assignment of value for RF0FE in the CAN_IE register */ 799 #define CAN_IE_RF0LE_Pos _UINT32_(3) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Position */ 800 #define CAN_IE_RF0LE_Msk (_UINT32_(0x1) << CAN_IE_RF0LE_Pos) /* (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Mask */ 801 #define CAN_IE_RF0LE(value) (CAN_IE_RF0LE_Msk & (_UINT32_(value) << CAN_IE_RF0LE_Pos)) /* Assignment of value for RF0LE in the CAN_IE register */ 802 #define CAN_IE_RF1NE_Pos _UINT32_(4) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Position */ 803 #define CAN_IE_RF1NE_Msk (_UINT32_(0x1) << CAN_IE_RF1NE_Pos) /* (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Mask */ 804 #define CAN_IE_RF1NE(value) (CAN_IE_RF1NE_Msk & (_UINT32_(value) << CAN_IE_RF1NE_Pos)) /* Assignment of value for RF1NE in the CAN_IE register */ 805 #define CAN_IE_RF1WE_Pos _UINT32_(5) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Position */ 806 #define CAN_IE_RF1WE_Msk (_UINT32_(0x1) << CAN_IE_RF1WE_Pos) /* (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Mask */ 807 #define CAN_IE_RF1WE(value) (CAN_IE_RF1WE_Msk & (_UINT32_(value) << CAN_IE_RF1WE_Pos)) /* Assignment of value for RF1WE in the CAN_IE register */ 808 #define CAN_IE_RF1FE_Pos _UINT32_(6) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Position */ 809 #define CAN_IE_RF1FE_Msk (_UINT32_(0x1) << CAN_IE_RF1FE_Pos) /* (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Mask */ 810 #define CAN_IE_RF1FE(value) (CAN_IE_RF1FE_Msk & (_UINT32_(value) << CAN_IE_RF1FE_Pos)) /* Assignment of value for RF1FE in the CAN_IE register */ 811 #define CAN_IE_RF1LE_Pos _UINT32_(7) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Position */ 812 #define CAN_IE_RF1LE_Msk (_UINT32_(0x1) << CAN_IE_RF1LE_Pos) /* (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Mask */ 813 #define CAN_IE_RF1LE(value) (CAN_IE_RF1LE_Msk & (_UINT32_(value) << CAN_IE_RF1LE_Pos)) /* Assignment of value for RF1LE in the CAN_IE register */ 814 #define CAN_IE_HPME_Pos _UINT32_(8) /* (CAN_IE) High Priority Message Interrupt Enable Position */ 815 #define CAN_IE_HPME_Msk (_UINT32_(0x1) << CAN_IE_HPME_Pos) /* (CAN_IE) High Priority Message Interrupt Enable Mask */ 816 #define CAN_IE_HPME(value) (CAN_IE_HPME_Msk & (_UINT32_(value) << CAN_IE_HPME_Pos)) /* Assignment of value for HPME in the CAN_IE register */ 817 #define CAN_IE_TCE_Pos _UINT32_(9) /* (CAN_IE) Timestamp Completed Interrupt Enable Position */ 818 #define CAN_IE_TCE_Msk (_UINT32_(0x1) << CAN_IE_TCE_Pos) /* (CAN_IE) Timestamp Completed Interrupt Enable Mask */ 819 #define CAN_IE_TCE(value) (CAN_IE_TCE_Msk & (_UINT32_(value) << CAN_IE_TCE_Pos)) /* Assignment of value for TCE in the CAN_IE register */ 820 #define CAN_IE_TCFE_Pos _UINT32_(10) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ 821 #define CAN_IE_TCFE_Msk (_UINT32_(0x1) << CAN_IE_TCFE_Pos) /* (CAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ 822 #define CAN_IE_TCFE(value) (CAN_IE_TCFE_Msk & (_UINT32_(value) << CAN_IE_TCFE_Pos)) /* Assignment of value for TCFE in the CAN_IE register */ 823 #define CAN_IE_TFEE_Pos _UINT32_(11) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Position */ 824 #define CAN_IE_TFEE_Msk (_UINT32_(0x1) << CAN_IE_TFEE_Pos) /* (CAN_IE) Tx FIFO Empty Interrupt Enable Mask */ 825 #define CAN_IE_TFEE(value) (CAN_IE_TFEE_Msk & (_UINT32_(value) << CAN_IE_TFEE_Pos)) /* Assignment of value for TFEE in the CAN_IE register */ 826 #define CAN_IE_TEFNE_Pos _UINT32_(12) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ 827 #define CAN_IE_TEFNE_Msk (_UINT32_(0x1) << CAN_IE_TEFNE_Pos) /* (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ 828 #define CAN_IE_TEFNE(value) (CAN_IE_TEFNE_Msk & (_UINT32_(value) << CAN_IE_TEFNE_Pos)) /* Assignment of value for TEFNE in the CAN_IE register */ 829 #define CAN_IE_TEFWE_Pos _UINT32_(13) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ 830 #define CAN_IE_TEFWE_Msk (_UINT32_(0x1) << CAN_IE_TEFWE_Pos) /* (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ 831 #define CAN_IE_TEFWE(value) (CAN_IE_TEFWE_Msk & (_UINT32_(value) << CAN_IE_TEFWE_Pos)) /* Assignment of value for TEFWE in the CAN_IE register */ 832 #define CAN_IE_TEFFE_Pos _UINT32_(14) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Position */ 833 #define CAN_IE_TEFFE_Msk (_UINT32_(0x1) << CAN_IE_TEFFE_Pos) /* (CAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ 834 #define CAN_IE_TEFFE(value) (CAN_IE_TEFFE_Msk & (_UINT32_(value) << CAN_IE_TEFFE_Pos)) /* Assignment of value for TEFFE in the CAN_IE register */ 835 #define CAN_IE_TEFLE_Pos _UINT32_(15) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Position */ 836 #define CAN_IE_TEFLE_Msk (_UINT32_(0x1) << CAN_IE_TEFLE_Pos) /* (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Mask */ 837 #define CAN_IE_TEFLE(value) (CAN_IE_TEFLE_Msk & (_UINT32_(value) << CAN_IE_TEFLE_Pos)) /* Assignment of value for TEFLE in the CAN_IE register */ 838 #define CAN_IE_TSWE_Pos _UINT32_(16) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Position */ 839 #define CAN_IE_TSWE_Msk (_UINT32_(0x1) << CAN_IE_TSWE_Pos) /* (CAN_IE) Timestamp Wraparound Interrupt Enable Mask */ 840 #define CAN_IE_TSWE(value) (CAN_IE_TSWE_Msk & (_UINT32_(value) << CAN_IE_TSWE_Pos)) /* Assignment of value for TSWE in the CAN_IE register */ 841 #define CAN_IE_MRAFE_Pos _UINT32_(17) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Position */ 842 #define CAN_IE_MRAFE_Msk (_UINT32_(0x1) << CAN_IE_MRAFE_Pos) /* (CAN_IE) Message RAM Access Failure Interrupt Enable Mask */ 843 #define CAN_IE_MRAFE(value) (CAN_IE_MRAFE_Msk & (_UINT32_(value) << CAN_IE_MRAFE_Pos)) /* Assignment of value for MRAFE in the CAN_IE register */ 844 #define CAN_IE_TOOE_Pos _UINT32_(18) /* (CAN_IE) Timeout Occurred Interrupt Enable Position */ 845 #define CAN_IE_TOOE_Msk (_UINT32_(0x1) << CAN_IE_TOOE_Pos) /* (CAN_IE) Timeout Occurred Interrupt Enable Mask */ 846 #define CAN_IE_TOOE(value) (CAN_IE_TOOE_Msk & (_UINT32_(value) << CAN_IE_TOOE_Pos)) /* Assignment of value for TOOE in the CAN_IE register */ 847 #define CAN_IE_DRXE_Pos _UINT32_(19) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Position */ 848 #define CAN_IE_DRXE_Msk (_UINT32_(0x1) << CAN_IE_DRXE_Pos) /* (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Mask */ 849 #define CAN_IE_DRXE(value) (CAN_IE_DRXE_Msk & (_UINT32_(value) << CAN_IE_DRXE_Pos)) /* Assignment of value for DRXE in the CAN_IE register */ 850 #define CAN_IE_BECE_Pos _UINT32_(20) /* (CAN_IE) Bit Error Corrected Interrupt Enable Position */ 851 #define CAN_IE_BECE_Msk (_UINT32_(0x1) << CAN_IE_BECE_Pos) /* (CAN_IE) Bit Error Corrected Interrupt Enable Mask */ 852 #define CAN_IE_BECE(value) (CAN_IE_BECE_Msk & (_UINT32_(value) << CAN_IE_BECE_Pos)) /* Assignment of value for BECE in the CAN_IE register */ 853 #define CAN_IE_BEUE_Pos _UINT32_(21) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Position */ 854 #define CAN_IE_BEUE_Msk (_UINT32_(0x1) << CAN_IE_BEUE_Pos) /* (CAN_IE) Bit Error Uncorrected Interrupt Enable Mask */ 855 #define CAN_IE_BEUE(value) (CAN_IE_BEUE_Msk & (_UINT32_(value) << CAN_IE_BEUE_Pos)) /* Assignment of value for BEUE in the CAN_IE register */ 856 #define CAN_IE_ELOE_Pos _UINT32_(22) /* (CAN_IE) Error Logging Overflow Interrupt Enable Position */ 857 #define CAN_IE_ELOE_Msk (_UINT32_(0x1) << CAN_IE_ELOE_Pos) /* (CAN_IE) Error Logging Overflow Interrupt Enable Mask */ 858 #define CAN_IE_ELOE(value) (CAN_IE_ELOE_Msk & (_UINT32_(value) << CAN_IE_ELOE_Pos)) /* Assignment of value for ELOE in the CAN_IE register */ 859 #define CAN_IE_EPE_Pos _UINT32_(23) /* (CAN_IE) Error Passive Interrupt Enable Position */ 860 #define CAN_IE_EPE_Msk (_UINT32_(0x1) << CAN_IE_EPE_Pos) /* (CAN_IE) Error Passive Interrupt Enable Mask */ 861 #define CAN_IE_EPE(value) (CAN_IE_EPE_Msk & (_UINT32_(value) << CAN_IE_EPE_Pos)) /* Assignment of value for EPE in the CAN_IE register */ 862 #define CAN_IE_EWE_Pos _UINT32_(24) /* (CAN_IE) Warning Status Interrupt Enable Position */ 863 #define CAN_IE_EWE_Msk (_UINT32_(0x1) << CAN_IE_EWE_Pos) /* (CAN_IE) Warning Status Interrupt Enable Mask */ 864 #define CAN_IE_EWE(value) (CAN_IE_EWE_Msk & (_UINT32_(value) << CAN_IE_EWE_Pos)) /* Assignment of value for EWE in the CAN_IE register */ 865 #define CAN_IE_BOE_Pos _UINT32_(25) /* (CAN_IE) Bus_Off Status Interrupt Enable Position */ 866 #define CAN_IE_BOE_Msk (_UINT32_(0x1) << CAN_IE_BOE_Pos) /* (CAN_IE) Bus_Off Status Interrupt Enable Mask */ 867 #define CAN_IE_BOE(value) (CAN_IE_BOE_Msk & (_UINT32_(value) << CAN_IE_BOE_Pos)) /* Assignment of value for BOE in the CAN_IE register */ 868 #define CAN_IE_WDIE_Pos _UINT32_(26) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Position */ 869 #define CAN_IE_WDIE_Msk (_UINT32_(0x1) << CAN_IE_WDIE_Pos) /* (CAN_IE) Watchdog Interrupt Interrupt Enable Mask */ 870 #define CAN_IE_WDIE(value) (CAN_IE_WDIE_Msk & (_UINT32_(value) << CAN_IE_WDIE_Pos)) /* Assignment of value for WDIE in the CAN_IE register */ 871 #define CAN_IE_PEAE_Pos _UINT32_(27) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Position */ 872 #define CAN_IE_PEAE_Msk (_UINT32_(0x1) << CAN_IE_PEAE_Pos) /* (CAN_IE) Protocol Error in Arbitration Phase Enable Mask */ 873 #define CAN_IE_PEAE(value) (CAN_IE_PEAE_Msk & (_UINT32_(value) << CAN_IE_PEAE_Pos)) /* Assignment of value for PEAE in the CAN_IE register */ 874 #define CAN_IE_PEDE_Pos _UINT32_(28) /* (CAN_IE) Protocol Error in Data Phase Enable Position */ 875 #define CAN_IE_PEDE_Msk (_UINT32_(0x1) << CAN_IE_PEDE_Pos) /* (CAN_IE) Protocol Error in Data Phase Enable Mask */ 876 #define CAN_IE_PEDE(value) (CAN_IE_PEDE_Msk & (_UINT32_(value) << CAN_IE_PEDE_Pos)) /* Assignment of value for PEDE in the CAN_IE register */ 877 #define CAN_IE_ARAE_Pos _UINT32_(29) /* (CAN_IE) Access to Reserved Address Enable Position */ 878 #define CAN_IE_ARAE_Msk (_UINT32_(0x1) << CAN_IE_ARAE_Pos) /* (CAN_IE) Access to Reserved Address Enable Mask */ 879 #define CAN_IE_ARAE(value) (CAN_IE_ARAE_Msk & (_UINT32_(value) << CAN_IE_ARAE_Pos)) /* Assignment of value for ARAE in the CAN_IE register */ 880 #define CAN_IE_Msk _UINT32_(0x3FFFFFFF) /* (CAN_IE) Register Mask */ 881 882 883 /* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ 884 #define CAN_ILS_RESETVALUE _UINT32_(0x00) /* (CAN_ILS) Interrupt Line Select Reset Value */ 885 886 #define CAN_ILS_RF0NL_Pos _UINT32_(0) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Position */ 887 #define CAN_ILS_RF0NL_Msk (_UINT32_(0x1) << CAN_ILS_RF0NL_Pos) /* (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Mask */ 888 #define CAN_ILS_RF0NL(value) (CAN_ILS_RF0NL_Msk & (_UINT32_(value) << CAN_ILS_RF0NL_Pos)) /* Assignment of value for RF0NL in the CAN_ILS register */ 889 #define CAN_ILS_RF0WL_Pos _UINT32_(1) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Position */ 890 #define CAN_ILS_RF0WL_Msk (_UINT32_(0x1) << CAN_ILS_RF0WL_Pos) /* (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Mask */ 891 #define CAN_ILS_RF0WL(value) (CAN_ILS_RF0WL_Msk & (_UINT32_(value) << CAN_ILS_RF0WL_Pos)) /* Assignment of value for RF0WL in the CAN_ILS register */ 892 #define CAN_ILS_RF0FL_Pos _UINT32_(2) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Position */ 893 #define CAN_ILS_RF0FL_Msk (_UINT32_(0x1) << CAN_ILS_RF0FL_Pos) /* (CAN_ILS) Rx FIFO 0 Full Interrupt Line Mask */ 894 #define CAN_ILS_RF0FL(value) (CAN_ILS_RF0FL_Msk & (_UINT32_(value) << CAN_ILS_RF0FL_Pos)) /* Assignment of value for RF0FL in the CAN_ILS register */ 895 #define CAN_ILS_RF0LL_Pos _UINT32_(3) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Position */ 896 #define CAN_ILS_RF0LL_Msk (_UINT32_(0x1) << CAN_ILS_RF0LL_Pos) /* (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Mask */ 897 #define CAN_ILS_RF0LL(value) (CAN_ILS_RF0LL_Msk & (_UINT32_(value) << CAN_ILS_RF0LL_Pos)) /* Assignment of value for RF0LL in the CAN_ILS register */ 898 #define CAN_ILS_RF1NL_Pos _UINT32_(4) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Position */ 899 #define CAN_ILS_RF1NL_Msk (_UINT32_(0x1) << CAN_ILS_RF1NL_Pos) /* (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Mask */ 900 #define CAN_ILS_RF1NL(value) (CAN_ILS_RF1NL_Msk & (_UINT32_(value) << CAN_ILS_RF1NL_Pos)) /* Assignment of value for RF1NL in the CAN_ILS register */ 901 #define CAN_ILS_RF1WL_Pos _UINT32_(5) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Position */ 902 #define CAN_ILS_RF1WL_Msk (_UINT32_(0x1) << CAN_ILS_RF1WL_Pos) /* (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Mask */ 903 #define CAN_ILS_RF1WL(value) (CAN_ILS_RF1WL_Msk & (_UINT32_(value) << CAN_ILS_RF1WL_Pos)) /* Assignment of value for RF1WL in the CAN_ILS register */ 904 #define CAN_ILS_RF1FL_Pos _UINT32_(6) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Position */ 905 #define CAN_ILS_RF1FL_Msk (_UINT32_(0x1) << CAN_ILS_RF1FL_Pos) /* (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Mask */ 906 #define CAN_ILS_RF1FL(value) (CAN_ILS_RF1FL_Msk & (_UINT32_(value) << CAN_ILS_RF1FL_Pos)) /* Assignment of value for RF1FL in the CAN_ILS register */ 907 #define CAN_ILS_RF1LL_Pos _UINT32_(7) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Position */ 908 #define CAN_ILS_RF1LL_Msk (_UINT32_(0x1) << CAN_ILS_RF1LL_Pos) /* (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Mask */ 909 #define CAN_ILS_RF1LL(value) (CAN_ILS_RF1LL_Msk & (_UINT32_(value) << CAN_ILS_RF1LL_Pos)) /* Assignment of value for RF1LL in the CAN_ILS register */ 910 #define CAN_ILS_HPML_Pos _UINT32_(8) /* (CAN_ILS) High Priority Message Interrupt Line Position */ 911 #define CAN_ILS_HPML_Msk (_UINT32_(0x1) << CAN_ILS_HPML_Pos) /* (CAN_ILS) High Priority Message Interrupt Line Mask */ 912 #define CAN_ILS_HPML(value) (CAN_ILS_HPML_Msk & (_UINT32_(value) << CAN_ILS_HPML_Pos)) /* Assignment of value for HPML in the CAN_ILS register */ 913 #define CAN_ILS_TCL_Pos _UINT32_(9) /* (CAN_ILS) Timestamp Completed Interrupt Line Position */ 914 #define CAN_ILS_TCL_Msk (_UINT32_(0x1) << CAN_ILS_TCL_Pos) /* (CAN_ILS) Timestamp Completed Interrupt Line Mask */ 915 #define CAN_ILS_TCL(value) (CAN_ILS_TCL_Msk & (_UINT32_(value) << CAN_ILS_TCL_Pos)) /* Assignment of value for TCL in the CAN_ILS register */ 916 #define CAN_ILS_TCFL_Pos _UINT32_(10) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ 917 #define CAN_ILS_TCFL_Msk (_UINT32_(0x1) << CAN_ILS_TCFL_Pos) /* (CAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ 918 #define CAN_ILS_TCFL(value) (CAN_ILS_TCFL_Msk & (_UINT32_(value) << CAN_ILS_TCFL_Pos)) /* Assignment of value for TCFL in the CAN_ILS register */ 919 #define CAN_ILS_TFEL_Pos _UINT32_(11) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Position */ 920 #define CAN_ILS_TFEL_Msk (_UINT32_(0x1) << CAN_ILS_TFEL_Pos) /* (CAN_ILS) Tx FIFO Empty Interrupt Line Mask */ 921 #define CAN_ILS_TFEL(value) (CAN_ILS_TFEL_Msk & (_UINT32_(value) << CAN_ILS_TFEL_Pos)) /* Assignment of value for TFEL in the CAN_ILS register */ 922 #define CAN_ILS_TEFNL_Pos _UINT32_(12) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ 923 #define CAN_ILS_TEFNL_Msk (_UINT32_(0x1) << CAN_ILS_TEFNL_Pos) /* (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ 924 #define CAN_ILS_TEFNL(value) (CAN_ILS_TEFNL_Msk & (_UINT32_(value) << CAN_ILS_TEFNL_Pos)) /* Assignment of value for TEFNL in the CAN_ILS register */ 925 #define CAN_ILS_TEFWL_Pos _UINT32_(13) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ 926 #define CAN_ILS_TEFWL_Msk (_UINT32_(0x1) << CAN_ILS_TEFWL_Pos) /* (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ 927 #define CAN_ILS_TEFWL(value) (CAN_ILS_TEFWL_Msk & (_UINT32_(value) << CAN_ILS_TEFWL_Pos)) /* Assignment of value for TEFWL in the CAN_ILS register */ 928 #define CAN_ILS_TEFFL_Pos _UINT32_(14) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Position */ 929 #define CAN_ILS_TEFFL_Msk (_UINT32_(0x1) << CAN_ILS_TEFFL_Pos) /* (CAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ 930 #define CAN_ILS_TEFFL(value) (CAN_ILS_TEFFL_Msk & (_UINT32_(value) << CAN_ILS_TEFFL_Pos)) /* Assignment of value for TEFFL in the CAN_ILS register */ 931 #define CAN_ILS_TEFLL_Pos _UINT32_(15) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Position */ 932 #define CAN_ILS_TEFLL_Msk (_UINT32_(0x1) << CAN_ILS_TEFLL_Pos) /* (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Mask */ 933 #define CAN_ILS_TEFLL(value) (CAN_ILS_TEFLL_Msk & (_UINT32_(value) << CAN_ILS_TEFLL_Pos)) /* Assignment of value for TEFLL in the CAN_ILS register */ 934 #define CAN_ILS_TSWL_Pos _UINT32_(16) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Position */ 935 #define CAN_ILS_TSWL_Msk (_UINT32_(0x1) << CAN_ILS_TSWL_Pos) /* (CAN_ILS) Timestamp Wraparound Interrupt Line Mask */ 936 #define CAN_ILS_TSWL(value) (CAN_ILS_TSWL_Msk & (_UINT32_(value) << CAN_ILS_TSWL_Pos)) /* Assignment of value for TSWL in the CAN_ILS register */ 937 #define CAN_ILS_MRAFL_Pos _UINT32_(17) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Position */ 938 #define CAN_ILS_MRAFL_Msk (_UINT32_(0x1) << CAN_ILS_MRAFL_Pos) /* (CAN_ILS) Message RAM Access Failure Interrupt Line Mask */ 939 #define CAN_ILS_MRAFL(value) (CAN_ILS_MRAFL_Msk & (_UINT32_(value) << CAN_ILS_MRAFL_Pos)) /* Assignment of value for MRAFL in the CAN_ILS register */ 940 #define CAN_ILS_TOOL_Pos _UINT32_(18) /* (CAN_ILS) Timeout Occurred Interrupt Line Position */ 941 #define CAN_ILS_TOOL_Msk (_UINT32_(0x1) << CAN_ILS_TOOL_Pos) /* (CAN_ILS) Timeout Occurred Interrupt Line Mask */ 942 #define CAN_ILS_TOOL(value) (CAN_ILS_TOOL_Msk & (_UINT32_(value) << CAN_ILS_TOOL_Pos)) /* Assignment of value for TOOL in the CAN_ILS register */ 943 #define CAN_ILS_DRXL_Pos _UINT32_(19) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Position */ 944 #define CAN_ILS_DRXL_Msk (_UINT32_(0x1) << CAN_ILS_DRXL_Pos) /* (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Mask */ 945 #define CAN_ILS_DRXL(value) (CAN_ILS_DRXL_Msk & (_UINT32_(value) << CAN_ILS_DRXL_Pos)) /* Assignment of value for DRXL in the CAN_ILS register */ 946 #define CAN_ILS_BECL_Pos _UINT32_(20) /* (CAN_ILS) Bit Error Corrected Interrupt Line Position */ 947 #define CAN_ILS_BECL_Msk (_UINT32_(0x1) << CAN_ILS_BECL_Pos) /* (CAN_ILS) Bit Error Corrected Interrupt Line Mask */ 948 #define CAN_ILS_BECL(value) (CAN_ILS_BECL_Msk & (_UINT32_(value) << CAN_ILS_BECL_Pos)) /* Assignment of value for BECL in the CAN_ILS register */ 949 #define CAN_ILS_BEUL_Pos _UINT32_(21) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Position */ 950 #define CAN_ILS_BEUL_Msk (_UINT32_(0x1) << CAN_ILS_BEUL_Pos) /* (CAN_ILS) Bit Error Uncorrected Interrupt Line Mask */ 951 #define CAN_ILS_BEUL(value) (CAN_ILS_BEUL_Msk & (_UINT32_(value) << CAN_ILS_BEUL_Pos)) /* Assignment of value for BEUL in the CAN_ILS register */ 952 #define CAN_ILS_ELOL_Pos _UINT32_(22) /* (CAN_ILS) Error Logging Overflow Interrupt Line Position */ 953 #define CAN_ILS_ELOL_Msk (_UINT32_(0x1) << CAN_ILS_ELOL_Pos) /* (CAN_ILS) Error Logging Overflow Interrupt Line Mask */ 954 #define CAN_ILS_ELOL(value) (CAN_ILS_ELOL_Msk & (_UINT32_(value) << CAN_ILS_ELOL_Pos)) /* Assignment of value for ELOL in the CAN_ILS register */ 955 #define CAN_ILS_EPL_Pos _UINT32_(23) /* (CAN_ILS) Error Passive Interrupt Line Position */ 956 #define CAN_ILS_EPL_Msk (_UINT32_(0x1) << CAN_ILS_EPL_Pos) /* (CAN_ILS) Error Passive Interrupt Line Mask */ 957 #define CAN_ILS_EPL(value) (CAN_ILS_EPL_Msk & (_UINT32_(value) << CAN_ILS_EPL_Pos)) /* Assignment of value for EPL in the CAN_ILS register */ 958 #define CAN_ILS_EWL_Pos _UINT32_(24) /* (CAN_ILS) Warning Status Interrupt Line Position */ 959 #define CAN_ILS_EWL_Msk (_UINT32_(0x1) << CAN_ILS_EWL_Pos) /* (CAN_ILS) Warning Status Interrupt Line Mask */ 960 #define CAN_ILS_EWL(value) (CAN_ILS_EWL_Msk & (_UINT32_(value) << CAN_ILS_EWL_Pos)) /* Assignment of value for EWL in the CAN_ILS register */ 961 #define CAN_ILS_BOL_Pos _UINT32_(25) /* (CAN_ILS) Bus_Off Status Interrupt Line Position */ 962 #define CAN_ILS_BOL_Msk (_UINT32_(0x1) << CAN_ILS_BOL_Pos) /* (CAN_ILS) Bus_Off Status Interrupt Line Mask */ 963 #define CAN_ILS_BOL(value) (CAN_ILS_BOL_Msk & (_UINT32_(value) << CAN_ILS_BOL_Pos)) /* Assignment of value for BOL in the CAN_ILS register */ 964 #define CAN_ILS_WDIL_Pos _UINT32_(26) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Position */ 965 #define CAN_ILS_WDIL_Msk (_UINT32_(0x1) << CAN_ILS_WDIL_Pos) /* (CAN_ILS) Watchdog Interrupt Interrupt Line Mask */ 966 #define CAN_ILS_WDIL(value) (CAN_ILS_WDIL_Msk & (_UINT32_(value) << CAN_ILS_WDIL_Pos)) /* Assignment of value for WDIL in the CAN_ILS register */ 967 #define CAN_ILS_PEAL_Pos _UINT32_(27) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Position */ 968 #define CAN_ILS_PEAL_Msk (_UINT32_(0x1) << CAN_ILS_PEAL_Pos) /* (CAN_ILS) Protocol Error in Arbitration Phase Line Mask */ 969 #define CAN_ILS_PEAL(value) (CAN_ILS_PEAL_Msk & (_UINT32_(value) << CAN_ILS_PEAL_Pos)) /* Assignment of value for PEAL in the CAN_ILS register */ 970 #define CAN_ILS_PEDL_Pos _UINT32_(28) /* (CAN_ILS) Protocol Error in Data Phase Line Position */ 971 #define CAN_ILS_PEDL_Msk (_UINT32_(0x1) << CAN_ILS_PEDL_Pos) /* (CAN_ILS) Protocol Error in Data Phase Line Mask */ 972 #define CAN_ILS_PEDL(value) (CAN_ILS_PEDL_Msk & (_UINT32_(value) << CAN_ILS_PEDL_Pos)) /* Assignment of value for PEDL in the CAN_ILS register */ 973 #define CAN_ILS_ARAL_Pos _UINT32_(29) /* (CAN_ILS) Access to Reserved Address Line Position */ 974 #define CAN_ILS_ARAL_Msk (_UINT32_(0x1) << CAN_ILS_ARAL_Pos) /* (CAN_ILS) Access to Reserved Address Line Mask */ 975 #define CAN_ILS_ARAL(value) (CAN_ILS_ARAL_Msk & (_UINT32_(value) << CAN_ILS_ARAL_Pos)) /* Assignment of value for ARAL in the CAN_ILS register */ 976 #define CAN_ILS_Msk _UINT32_(0x3FFFFFFF) /* (CAN_ILS) Register Mask */ 977 978 979 /* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ 980 #define CAN_ILE_RESETVALUE _UINT32_(0x00) /* (CAN_ILE) Interrupt Line Enable Reset Value */ 981 982 #define CAN_ILE_EINT0_Pos _UINT32_(0) /* (CAN_ILE) Enable Interrupt Line 0 Position */ 983 #define CAN_ILE_EINT0_Msk (_UINT32_(0x1) << CAN_ILE_EINT0_Pos) /* (CAN_ILE) Enable Interrupt Line 0 Mask */ 984 #define CAN_ILE_EINT0(value) (CAN_ILE_EINT0_Msk & (_UINT32_(value) << CAN_ILE_EINT0_Pos)) /* Assignment of value for EINT0 in the CAN_ILE register */ 985 #define CAN_ILE_EINT1_Pos _UINT32_(1) /* (CAN_ILE) Enable Interrupt Line 1 Position */ 986 #define CAN_ILE_EINT1_Msk (_UINT32_(0x1) << CAN_ILE_EINT1_Pos) /* (CAN_ILE) Enable Interrupt Line 1 Mask */ 987 #define CAN_ILE_EINT1(value) (CAN_ILE_EINT1_Msk & (_UINT32_(value) << CAN_ILE_EINT1_Pos)) /* Assignment of value for EINT1 in the CAN_ILE register */ 988 #define CAN_ILE_Msk _UINT32_(0x00000003) /* (CAN_ILE) Register Mask */ 989 990 #define CAN_ILE_EINT_Pos _UINT32_(0) /* (CAN_ILE Position) Enable Interrupt Line x */ 991 #define CAN_ILE_EINT_Msk (_UINT32_(0x3) << CAN_ILE_EINT_Pos) /* (CAN_ILE Mask) EINT */ 992 #define CAN_ILE_EINT(value) (CAN_ILE_EINT_Msk & (_UINT32_(value) << CAN_ILE_EINT_Pos)) 993 994 /* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ 995 #define CAN_GFC_RESETVALUE _UINT32_(0x00) /* (CAN_GFC) Global Filter Configuration Reset Value */ 996 997 #define CAN_GFC_RRFE_Pos _UINT32_(0) /* (CAN_GFC) Reject Remote Frames Extended Position */ 998 #define CAN_GFC_RRFE_Msk (_UINT32_(0x1) << CAN_GFC_RRFE_Pos) /* (CAN_GFC) Reject Remote Frames Extended Mask */ 999 #define CAN_GFC_RRFE(value) (CAN_GFC_RRFE_Msk & (_UINT32_(value) << CAN_GFC_RRFE_Pos)) /* Assignment of value for RRFE in the CAN_GFC register */ 1000 #define CAN_GFC_RRFS_Pos _UINT32_(1) /* (CAN_GFC) Reject Remote Frames Standard Position */ 1001 #define CAN_GFC_RRFS_Msk (_UINT32_(0x1) << CAN_GFC_RRFS_Pos) /* (CAN_GFC) Reject Remote Frames Standard Mask */ 1002 #define CAN_GFC_RRFS(value) (CAN_GFC_RRFS_Msk & (_UINT32_(value) << CAN_GFC_RRFS_Pos)) /* Assignment of value for RRFS in the CAN_GFC register */ 1003 #define CAN_GFC_ANFE_Pos _UINT32_(2) /* (CAN_GFC) Accept Non-matching Frames Extended Position */ 1004 #define CAN_GFC_ANFE_Msk (_UINT32_(0x3) << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept Non-matching Frames Extended Mask */ 1005 #define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & (_UINT32_(value) << CAN_GFC_ANFE_Pos)) /* Assignment of value for ANFE in the CAN_GFC register */ 1006 #define CAN_GFC_ANFE_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ 1007 #define CAN_GFC_ANFE_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ 1008 #define CAN_GFC_ANFE_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ 1009 #define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ 1010 #define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ 1011 #define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) /* (CAN_GFC) Reject Position */ 1012 #define CAN_GFC_ANFS_Pos _UINT32_(4) /* (CAN_GFC) Accept Non-matching Frames Standard Position */ 1013 #define CAN_GFC_ANFS_Msk (_UINT32_(0x3) << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept Non-matching Frames Standard Mask */ 1014 #define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & (_UINT32_(value) << CAN_GFC_ANFS_Pos)) /* Assignment of value for ANFS in the CAN_GFC register */ 1015 #define CAN_GFC_ANFS_RXF0_Val _UINT32_(0x0) /* (CAN_GFC) Accept in Rx FIFO 0 */ 1016 #define CAN_GFC_ANFS_RXF1_Val _UINT32_(0x1) /* (CAN_GFC) Accept in Rx FIFO 1 */ 1017 #define CAN_GFC_ANFS_REJECT_Val _UINT32_(0x2) /* (CAN_GFC) Reject */ 1018 #define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 0 Position */ 1019 #define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Accept in Rx FIFO 1 Position */ 1020 #define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) /* (CAN_GFC) Reject Position */ 1021 #define CAN_GFC_Msk _UINT32_(0x0000003F) /* (CAN_GFC) Register Mask */ 1022 1023 1024 /* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ 1025 #define CAN_SIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_SIDFC) Standard ID Filter Configuration Reset Value */ 1026 1027 #define CAN_SIDFC_FLSSA_Pos _UINT32_(0) /* (CAN_SIDFC) Filter List Standard Start Address Position */ 1028 #define CAN_SIDFC_FLSSA_Msk (_UINT32_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) /* (CAN_SIDFC) Filter List Standard Start Address Mask */ 1029 #define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & (_UINT32_(value) << CAN_SIDFC_FLSSA_Pos)) /* Assignment of value for FLSSA in the CAN_SIDFC register */ 1030 #define CAN_SIDFC_LSS_Pos _UINT32_(16) /* (CAN_SIDFC) List Size Standard Position */ 1031 #define CAN_SIDFC_LSS_Msk (_UINT32_(0xFF) << CAN_SIDFC_LSS_Pos) /* (CAN_SIDFC) List Size Standard Mask */ 1032 #define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & (_UINT32_(value) << CAN_SIDFC_LSS_Pos)) /* Assignment of value for LSS in the CAN_SIDFC register */ 1033 #define CAN_SIDFC_Msk _UINT32_(0x00FFFFFF) /* (CAN_SIDFC) Register Mask */ 1034 1035 1036 /* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ 1037 #define CAN_XIDFC_RESETVALUE _UINT32_(0x00) /* (CAN_XIDFC) Extended ID Filter Configuration Reset Value */ 1038 1039 #define CAN_XIDFC_FLESA_Pos _UINT32_(0) /* (CAN_XIDFC) Filter List Extended Start Address Position */ 1040 #define CAN_XIDFC_FLESA_Msk (_UINT32_(0xFFFF) << CAN_XIDFC_FLESA_Pos) /* (CAN_XIDFC) Filter List Extended Start Address Mask */ 1041 #define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & (_UINT32_(value) << CAN_XIDFC_FLESA_Pos)) /* Assignment of value for FLESA in the CAN_XIDFC register */ 1042 #define CAN_XIDFC_LSE_Pos _UINT32_(16) /* (CAN_XIDFC) List Size Extended Position */ 1043 #define CAN_XIDFC_LSE_Msk (_UINT32_(0x7F) << CAN_XIDFC_LSE_Pos) /* (CAN_XIDFC) List Size Extended Mask */ 1044 #define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & (_UINT32_(value) << CAN_XIDFC_LSE_Pos)) /* Assignment of value for LSE in the CAN_XIDFC register */ 1045 #define CAN_XIDFC_Msk _UINT32_(0x007FFFFF) /* (CAN_XIDFC) Register Mask */ 1046 1047 1048 /* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ 1049 #define CAN_XIDAM_RESETVALUE _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Extended ID AND Mask Reset Value */ 1050 1051 #define CAN_XIDAM_EIDM_Pos _UINT32_(0) /* (CAN_XIDAM) Extended ID Mask Position */ 1052 #define CAN_XIDAM_EIDM_Msk (_UINT32_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) /* (CAN_XIDAM) Extended ID Mask Mask */ 1053 #define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & (_UINT32_(value) << CAN_XIDAM_EIDM_Pos)) /* Assignment of value for EIDM in the CAN_XIDAM register */ 1054 #define CAN_XIDAM_Msk _UINT32_(0x1FFFFFFF) /* (CAN_XIDAM) Register Mask */ 1055 1056 1057 /* -------- CAN_HPMS : (CAN Offset: 0x94) ( R/ 32) High Priority Message Status -------- */ 1058 #define CAN_HPMS_RESETVALUE _UINT32_(0x00) /* (CAN_HPMS) High Priority Message Status Reset Value */ 1059 1060 #define CAN_HPMS_BIDX_Pos _UINT32_(0) /* (CAN_HPMS) Buffer Index Position */ 1061 #define CAN_HPMS_BIDX_Msk (_UINT32_(0x3F) << CAN_HPMS_BIDX_Pos) /* (CAN_HPMS) Buffer Index Mask */ 1062 #define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & (_UINT32_(value) << CAN_HPMS_BIDX_Pos)) /* Assignment of value for BIDX in the CAN_HPMS register */ 1063 #define CAN_HPMS_MSI_Pos _UINT32_(6) /* (CAN_HPMS) Message Storage Indicator Position */ 1064 #define CAN_HPMS_MSI_Msk (_UINT32_(0x3) << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message Storage Indicator Mask */ 1065 #define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & (_UINT32_(value) << CAN_HPMS_MSI_Pos)) /* Assignment of value for MSI in the CAN_HPMS register */ 1066 #define CAN_HPMS_MSI_NONE_Val _UINT32_(0x0) /* (CAN_HPMS) No FIFO selected */ 1067 #define CAN_HPMS_MSI_LOST_Val _UINT32_(0x1) /* (CAN_HPMS) FIFO message lost */ 1068 #define CAN_HPMS_MSI_FIFO0_Val _UINT32_(0x2) /* (CAN_HPMS) Message stored in FIFO 0 */ 1069 #define CAN_HPMS_MSI_FIFO1_Val _UINT32_(0x3) /* (CAN_HPMS) Message stored in FIFO 1 */ 1070 #define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) No FIFO selected Position */ 1071 #define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) FIFO message lost Position */ 1072 #define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 0 Position */ 1073 #define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) /* (CAN_HPMS) Message stored in FIFO 1 Position */ 1074 #define CAN_HPMS_FIDX_Pos _UINT32_(8) /* (CAN_HPMS) Filter Index Position */ 1075 #define CAN_HPMS_FIDX_Msk (_UINT32_(0x7F) << CAN_HPMS_FIDX_Pos) /* (CAN_HPMS) Filter Index Mask */ 1076 #define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & (_UINT32_(value) << CAN_HPMS_FIDX_Pos)) /* Assignment of value for FIDX in the CAN_HPMS register */ 1077 #define CAN_HPMS_FLST_Pos _UINT32_(15) /* (CAN_HPMS) Filter List Position */ 1078 #define CAN_HPMS_FLST_Msk (_UINT32_(0x1) << CAN_HPMS_FLST_Pos) /* (CAN_HPMS) Filter List Mask */ 1079 #define CAN_HPMS_FLST(value) (CAN_HPMS_FLST_Msk & (_UINT32_(value) << CAN_HPMS_FLST_Pos)) /* Assignment of value for FLST in the CAN_HPMS register */ 1080 #define CAN_HPMS_Msk _UINT32_(0x0000FFFF) /* (CAN_HPMS) Register Mask */ 1081 1082 1083 /* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ 1084 #define CAN_NDAT1_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT1) New Data 1 Reset Value */ 1085 1086 #define CAN_NDAT1_ND0_Pos _UINT32_(0) /* (CAN_NDAT1) New Data 0 Position */ 1087 #define CAN_NDAT1_ND0_Msk (_UINT32_(0x1) << CAN_NDAT1_ND0_Pos) /* (CAN_NDAT1) New Data 0 Mask */ 1088 #define CAN_NDAT1_ND0(value) (CAN_NDAT1_ND0_Msk & (_UINT32_(value) << CAN_NDAT1_ND0_Pos)) /* Assignment of value for ND0 in the CAN_NDAT1 register */ 1089 #define CAN_NDAT1_ND1_Pos _UINT32_(1) /* (CAN_NDAT1) New Data 1 Position */ 1090 #define CAN_NDAT1_ND1_Msk (_UINT32_(0x1) << CAN_NDAT1_ND1_Pos) /* (CAN_NDAT1) New Data 1 Mask */ 1091 #define CAN_NDAT1_ND1(value) (CAN_NDAT1_ND1_Msk & (_UINT32_(value) << CAN_NDAT1_ND1_Pos)) /* Assignment of value for ND1 in the CAN_NDAT1 register */ 1092 #define CAN_NDAT1_ND2_Pos _UINT32_(2) /* (CAN_NDAT1) New Data 2 Position */ 1093 #define CAN_NDAT1_ND2_Msk (_UINT32_(0x1) << CAN_NDAT1_ND2_Pos) /* (CAN_NDAT1) New Data 2 Mask */ 1094 #define CAN_NDAT1_ND2(value) (CAN_NDAT1_ND2_Msk & (_UINT32_(value) << CAN_NDAT1_ND2_Pos)) /* Assignment of value for ND2 in the CAN_NDAT1 register */ 1095 #define CAN_NDAT1_ND3_Pos _UINT32_(3) /* (CAN_NDAT1) New Data 3 Position */ 1096 #define CAN_NDAT1_ND3_Msk (_UINT32_(0x1) << CAN_NDAT1_ND3_Pos) /* (CAN_NDAT1) New Data 3 Mask */ 1097 #define CAN_NDAT1_ND3(value) (CAN_NDAT1_ND3_Msk & (_UINT32_(value) << CAN_NDAT1_ND3_Pos)) /* Assignment of value for ND3 in the CAN_NDAT1 register */ 1098 #define CAN_NDAT1_ND4_Pos _UINT32_(4) /* (CAN_NDAT1) New Data 4 Position */ 1099 #define CAN_NDAT1_ND4_Msk (_UINT32_(0x1) << CAN_NDAT1_ND4_Pos) /* (CAN_NDAT1) New Data 4 Mask */ 1100 #define CAN_NDAT1_ND4(value) (CAN_NDAT1_ND4_Msk & (_UINT32_(value) << CAN_NDAT1_ND4_Pos)) /* Assignment of value for ND4 in the CAN_NDAT1 register */ 1101 #define CAN_NDAT1_ND5_Pos _UINT32_(5) /* (CAN_NDAT1) New Data 5 Position */ 1102 #define CAN_NDAT1_ND5_Msk (_UINT32_(0x1) << CAN_NDAT1_ND5_Pos) /* (CAN_NDAT1) New Data 5 Mask */ 1103 #define CAN_NDAT1_ND5(value) (CAN_NDAT1_ND5_Msk & (_UINT32_(value) << CAN_NDAT1_ND5_Pos)) /* Assignment of value for ND5 in the CAN_NDAT1 register */ 1104 #define CAN_NDAT1_ND6_Pos _UINT32_(6) /* (CAN_NDAT1) New Data 6 Position */ 1105 #define CAN_NDAT1_ND6_Msk (_UINT32_(0x1) << CAN_NDAT1_ND6_Pos) /* (CAN_NDAT1) New Data 6 Mask */ 1106 #define CAN_NDAT1_ND6(value) (CAN_NDAT1_ND6_Msk & (_UINT32_(value) << CAN_NDAT1_ND6_Pos)) /* Assignment of value for ND6 in the CAN_NDAT1 register */ 1107 #define CAN_NDAT1_ND7_Pos _UINT32_(7) /* (CAN_NDAT1) New Data 7 Position */ 1108 #define CAN_NDAT1_ND7_Msk (_UINT32_(0x1) << CAN_NDAT1_ND7_Pos) /* (CAN_NDAT1) New Data 7 Mask */ 1109 #define CAN_NDAT1_ND7(value) (CAN_NDAT1_ND7_Msk & (_UINT32_(value) << CAN_NDAT1_ND7_Pos)) /* Assignment of value for ND7 in the CAN_NDAT1 register */ 1110 #define CAN_NDAT1_ND8_Pos _UINT32_(8) /* (CAN_NDAT1) New Data 8 Position */ 1111 #define CAN_NDAT1_ND8_Msk (_UINT32_(0x1) << CAN_NDAT1_ND8_Pos) /* (CAN_NDAT1) New Data 8 Mask */ 1112 #define CAN_NDAT1_ND8(value) (CAN_NDAT1_ND8_Msk & (_UINT32_(value) << CAN_NDAT1_ND8_Pos)) /* Assignment of value for ND8 in the CAN_NDAT1 register */ 1113 #define CAN_NDAT1_ND9_Pos _UINT32_(9) /* (CAN_NDAT1) New Data 9 Position */ 1114 #define CAN_NDAT1_ND9_Msk (_UINT32_(0x1) << CAN_NDAT1_ND9_Pos) /* (CAN_NDAT1) New Data 9 Mask */ 1115 #define CAN_NDAT1_ND9(value) (CAN_NDAT1_ND9_Msk & (_UINT32_(value) << CAN_NDAT1_ND9_Pos)) /* Assignment of value for ND9 in the CAN_NDAT1 register */ 1116 #define CAN_NDAT1_ND10_Pos _UINT32_(10) /* (CAN_NDAT1) New Data 10 Position */ 1117 #define CAN_NDAT1_ND10_Msk (_UINT32_(0x1) << CAN_NDAT1_ND10_Pos) /* (CAN_NDAT1) New Data 10 Mask */ 1118 #define CAN_NDAT1_ND10(value) (CAN_NDAT1_ND10_Msk & (_UINT32_(value) << CAN_NDAT1_ND10_Pos)) /* Assignment of value for ND10 in the CAN_NDAT1 register */ 1119 #define CAN_NDAT1_ND11_Pos _UINT32_(11) /* (CAN_NDAT1) New Data 11 Position */ 1120 #define CAN_NDAT1_ND11_Msk (_UINT32_(0x1) << CAN_NDAT1_ND11_Pos) /* (CAN_NDAT1) New Data 11 Mask */ 1121 #define CAN_NDAT1_ND11(value) (CAN_NDAT1_ND11_Msk & (_UINT32_(value) << CAN_NDAT1_ND11_Pos)) /* Assignment of value for ND11 in the CAN_NDAT1 register */ 1122 #define CAN_NDAT1_ND12_Pos _UINT32_(12) /* (CAN_NDAT1) New Data 12 Position */ 1123 #define CAN_NDAT1_ND12_Msk (_UINT32_(0x1) << CAN_NDAT1_ND12_Pos) /* (CAN_NDAT1) New Data 12 Mask */ 1124 #define CAN_NDAT1_ND12(value) (CAN_NDAT1_ND12_Msk & (_UINT32_(value) << CAN_NDAT1_ND12_Pos)) /* Assignment of value for ND12 in the CAN_NDAT1 register */ 1125 #define CAN_NDAT1_ND13_Pos _UINT32_(13) /* (CAN_NDAT1) New Data 13 Position */ 1126 #define CAN_NDAT1_ND13_Msk (_UINT32_(0x1) << CAN_NDAT1_ND13_Pos) /* (CAN_NDAT1) New Data 13 Mask */ 1127 #define CAN_NDAT1_ND13(value) (CAN_NDAT1_ND13_Msk & (_UINT32_(value) << CAN_NDAT1_ND13_Pos)) /* Assignment of value for ND13 in the CAN_NDAT1 register */ 1128 #define CAN_NDAT1_ND14_Pos _UINT32_(14) /* (CAN_NDAT1) New Data 14 Position */ 1129 #define CAN_NDAT1_ND14_Msk (_UINT32_(0x1) << CAN_NDAT1_ND14_Pos) /* (CAN_NDAT1) New Data 14 Mask */ 1130 #define CAN_NDAT1_ND14(value) (CAN_NDAT1_ND14_Msk & (_UINT32_(value) << CAN_NDAT1_ND14_Pos)) /* Assignment of value for ND14 in the CAN_NDAT1 register */ 1131 #define CAN_NDAT1_ND15_Pos _UINT32_(15) /* (CAN_NDAT1) New Data 15 Position */ 1132 #define CAN_NDAT1_ND15_Msk (_UINT32_(0x1) << CAN_NDAT1_ND15_Pos) /* (CAN_NDAT1) New Data 15 Mask */ 1133 #define CAN_NDAT1_ND15(value) (CAN_NDAT1_ND15_Msk & (_UINT32_(value) << CAN_NDAT1_ND15_Pos)) /* Assignment of value for ND15 in the CAN_NDAT1 register */ 1134 #define CAN_NDAT1_ND16_Pos _UINT32_(16) /* (CAN_NDAT1) New Data 16 Position */ 1135 #define CAN_NDAT1_ND16_Msk (_UINT32_(0x1) << CAN_NDAT1_ND16_Pos) /* (CAN_NDAT1) New Data 16 Mask */ 1136 #define CAN_NDAT1_ND16(value) (CAN_NDAT1_ND16_Msk & (_UINT32_(value) << CAN_NDAT1_ND16_Pos)) /* Assignment of value for ND16 in the CAN_NDAT1 register */ 1137 #define CAN_NDAT1_ND17_Pos _UINT32_(17) /* (CAN_NDAT1) New Data 17 Position */ 1138 #define CAN_NDAT1_ND17_Msk (_UINT32_(0x1) << CAN_NDAT1_ND17_Pos) /* (CAN_NDAT1) New Data 17 Mask */ 1139 #define CAN_NDAT1_ND17(value) (CAN_NDAT1_ND17_Msk & (_UINT32_(value) << CAN_NDAT1_ND17_Pos)) /* Assignment of value for ND17 in the CAN_NDAT1 register */ 1140 #define CAN_NDAT1_ND18_Pos _UINT32_(18) /* (CAN_NDAT1) New Data 18 Position */ 1141 #define CAN_NDAT1_ND18_Msk (_UINT32_(0x1) << CAN_NDAT1_ND18_Pos) /* (CAN_NDAT1) New Data 18 Mask */ 1142 #define CAN_NDAT1_ND18(value) (CAN_NDAT1_ND18_Msk & (_UINT32_(value) << CAN_NDAT1_ND18_Pos)) /* Assignment of value for ND18 in the CAN_NDAT1 register */ 1143 #define CAN_NDAT1_ND19_Pos _UINT32_(19) /* (CAN_NDAT1) New Data 19 Position */ 1144 #define CAN_NDAT1_ND19_Msk (_UINT32_(0x1) << CAN_NDAT1_ND19_Pos) /* (CAN_NDAT1) New Data 19 Mask */ 1145 #define CAN_NDAT1_ND19(value) (CAN_NDAT1_ND19_Msk & (_UINT32_(value) << CAN_NDAT1_ND19_Pos)) /* Assignment of value for ND19 in the CAN_NDAT1 register */ 1146 #define CAN_NDAT1_ND20_Pos _UINT32_(20) /* (CAN_NDAT1) New Data 20 Position */ 1147 #define CAN_NDAT1_ND20_Msk (_UINT32_(0x1) << CAN_NDAT1_ND20_Pos) /* (CAN_NDAT1) New Data 20 Mask */ 1148 #define CAN_NDAT1_ND20(value) (CAN_NDAT1_ND20_Msk & (_UINT32_(value) << CAN_NDAT1_ND20_Pos)) /* Assignment of value for ND20 in the CAN_NDAT1 register */ 1149 #define CAN_NDAT1_ND21_Pos _UINT32_(21) /* (CAN_NDAT1) New Data 21 Position */ 1150 #define CAN_NDAT1_ND21_Msk (_UINT32_(0x1) << CAN_NDAT1_ND21_Pos) /* (CAN_NDAT1) New Data 21 Mask */ 1151 #define CAN_NDAT1_ND21(value) (CAN_NDAT1_ND21_Msk & (_UINT32_(value) << CAN_NDAT1_ND21_Pos)) /* Assignment of value for ND21 in the CAN_NDAT1 register */ 1152 #define CAN_NDAT1_ND22_Pos _UINT32_(22) /* (CAN_NDAT1) New Data 22 Position */ 1153 #define CAN_NDAT1_ND22_Msk (_UINT32_(0x1) << CAN_NDAT1_ND22_Pos) /* (CAN_NDAT1) New Data 22 Mask */ 1154 #define CAN_NDAT1_ND22(value) (CAN_NDAT1_ND22_Msk & (_UINT32_(value) << CAN_NDAT1_ND22_Pos)) /* Assignment of value for ND22 in the CAN_NDAT1 register */ 1155 #define CAN_NDAT1_ND23_Pos _UINT32_(23) /* (CAN_NDAT1) New Data 23 Position */ 1156 #define CAN_NDAT1_ND23_Msk (_UINT32_(0x1) << CAN_NDAT1_ND23_Pos) /* (CAN_NDAT1) New Data 23 Mask */ 1157 #define CAN_NDAT1_ND23(value) (CAN_NDAT1_ND23_Msk & (_UINT32_(value) << CAN_NDAT1_ND23_Pos)) /* Assignment of value for ND23 in the CAN_NDAT1 register */ 1158 #define CAN_NDAT1_ND24_Pos _UINT32_(24) /* (CAN_NDAT1) New Data 24 Position */ 1159 #define CAN_NDAT1_ND24_Msk (_UINT32_(0x1) << CAN_NDAT1_ND24_Pos) /* (CAN_NDAT1) New Data 24 Mask */ 1160 #define CAN_NDAT1_ND24(value) (CAN_NDAT1_ND24_Msk & (_UINT32_(value) << CAN_NDAT1_ND24_Pos)) /* Assignment of value for ND24 in the CAN_NDAT1 register */ 1161 #define CAN_NDAT1_ND25_Pos _UINT32_(25) /* (CAN_NDAT1) New Data 25 Position */ 1162 #define CAN_NDAT1_ND25_Msk (_UINT32_(0x1) << CAN_NDAT1_ND25_Pos) /* (CAN_NDAT1) New Data 25 Mask */ 1163 #define CAN_NDAT1_ND25(value) (CAN_NDAT1_ND25_Msk & (_UINT32_(value) << CAN_NDAT1_ND25_Pos)) /* Assignment of value for ND25 in the CAN_NDAT1 register */ 1164 #define CAN_NDAT1_ND26_Pos _UINT32_(26) /* (CAN_NDAT1) New Data 26 Position */ 1165 #define CAN_NDAT1_ND26_Msk (_UINT32_(0x1) << CAN_NDAT1_ND26_Pos) /* (CAN_NDAT1) New Data 26 Mask */ 1166 #define CAN_NDAT1_ND26(value) (CAN_NDAT1_ND26_Msk & (_UINT32_(value) << CAN_NDAT1_ND26_Pos)) /* Assignment of value for ND26 in the CAN_NDAT1 register */ 1167 #define CAN_NDAT1_ND27_Pos _UINT32_(27) /* (CAN_NDAT1) New Data 27 Position */ 1168 #define CAN_NDAT1_ND27_Msk (_UINT32_(0x1) << CAN_NDAT1_ND27_Pos) /* (CAN_NDAT1) New Data 27 Mask */ 1169 #define CAN_NDAT1_ND27(value) (CAN_NDAT1_ND27_Msk & (_UINT32_(value) << CAN_NDAT1_ND27_Pos)) /* Assignment of value for ND27 in the CAN_NDAT1 register */ 1170 #define CAN_NDAT1_ND28_Pos _UINT32_(28) /* (CAN_NDAT1) New Data 28 Position */ 1171 #define CAN_NDAT1_ND28_Msk (_UINT32_(0x1) << CAN_NDAT1_ND28_Pos) /* (CAN_NDAT1) New Data 28 Mask */ 1172 #define CAN_NDAT1_ND28(value) (CAN_NDAT1_ND28_Msk & (_UINT32_(value) << CAN_NDAT1_ND28_Pos)) /* Assignment of value for ND28 in the CAN_NDAT1 register */ 1173 #define CAN_NDAT1_ND29_Pos _UINT32_(29) /* (CAN_NDAT1) New Data 29 Position */ 1174 #define CAN_NDAT1_ND29_Msk (_UINT32_(0x1) << CAN_NDAT1_ND29_Pos) /* (CAN_NDAT1) New Data 29 Mask */ 1175 #define CAN_NDAT1_ND29(value) (CAN_NDAT1_ND29_Msk & (_UINT32_(value) << CAN_NDAT1_ND29_Pos)) /* Assignment of value for ND29 in the CAN_NDAT1 register */ 1176 #define CAN_NDAT1_ND30_Pos _UINT32_(30) /* (CAN_NDAT1) New Data 30 Position */ 1177 #define CAN_NDAT1_ND30_Msk (_UINT32_(0x1) << CAN_NDAT1_ND30_Pos) /* (CAN_NDAT1) New Data 30 Mask */ 1178 #define CAN_NDAT1_ND30(value) (CAN_NDAT1_ND30_Msk & (_UINT32_(value) << CAN_NDAT1_ND30_Pos)) /* Assignment of value for ND30 in the CAN_NDAT1 register */ 1179 #define CAN_NDAT1_ND31_Pos _UINT32_(31) /* (CAN_NDAT1) New Data 31 Position */ 1180 #define CAN_NDAT1_ND31_Msk (_UINT32_(0x1) << CAN_NDAT1_ND31_Pos) /* (CAN_NDAT1) New Data 31 Mask */ 1181 #define CAN_NDAT1_ND31(value) (CAN_NDAT1_ND31_Msk & (_UINT32_(value) << CAN_NDAT1_ND31_Pos)) /* Assignment of value for ND31 in the CAN_NDAT1 register */ 1182 #define CAN_NDAT1_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT1) Register Mask */ 1183 1184 #define CAN_NDAT1_ND_Pos _UINT32_(0) /* (CAN_NDAT1 Position) New Data 3x */ 1185 #define CAN_NDAT1_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT1_ND_Pos) /* (CAN_NDAT1 Mask) ND */ 1186 #define CAN_NDAT1_ND(value) (CAN_NDAT1_ND_Msk & (_UINT32_(value) << CAN_NDAT1_ND_Pos)) 1187 1188 /* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ 1189 #define CAN_NDAT2_RESETVALUE _UINT32_(0x00) /* (CAN_NDAT2) New Data 2 Reset Value */ 1190 1191 #define CAN_NDAT2_ND32_Pos _UINT32_(0) /* (CAN_NDAT2) New Data 32 Position */ 1192 #define CAN_NDAT2_ND32_Msk (_UINT32_(0x1) << CAN_NDAT2_ND32_Pos) /* (CAN_NDAT2) New Data 32 Mask */ 1193 #define CAN_NDAT2_ND32(value) (CAN_NDAT2_ND32_Msk & (_UINT32_(value) << CAN_NDAT2_ND32_Pos)) /* Assignment of value for ND32 in the CAN_NDAT2 register */ 1194 #define CAN_NDAT2_ND33_Pos _UINT32_(1) /* (CAN_NDAT2) New Data 33 Position */ 1195 #define CAN_NDAT2_ND33_Msk (_UINT32_(0x1) << CAN_NDAT2_ND33_Pos) /* (CAN_NDAT2) New Data 33 Mask */ 1196 #define CAN_NDAT2_ND33(value) (CAN_NDAT2_ND33_Msk & (_UINT32_(value) << CAN_NDAT2_ND33_Pos)) /* Assignment of value for ND33 in the CAN_NDAT2 register */ 1197 #define CAN_NDAT2_ND34_Pos _UINT32_(2) /* (CAN_NDAT2) New Data 34 Position */ 1198 #define CAN_NDAT2_ND34_Msk (_UINT32_(0x1) << CAN_NDAT2_ND34_Pos) /* (CAN_NDAT2) New Data 34 Mask */ 1199 #define CAN_NDAT2_ND34(value) (CAN_NDAT2_ND34_Msk & (_UINT32_(value) << CAN_NDAT2_ND34_Pos)) /* Assignment of value for ND34 in the CAN_NDAT2 register */ 1200 #define CAN_NDAT2_ND35_Pos _UINT32_(3) /* (CAN_NDAT2) New Data 35 Position */ 1201 #define CAN_NDAT2_ND35_Msk (_UINT32_(0x1) << CAN_NDAT2_ND35_Pos) /* (CAN_NDAT2) New Data 35 Mask */ 1202 #define CAN_NDAT2_ND35(value) (CAN_NDAT2_ND35_Msk & (_UINT32_(value) << CAN_NDAT2_ND35_Pos)) /* Assignment of value for ND35 in the CAN_NDAT2 register */ 1203 #define CAN_NDAT2_ND36_Pos _UINT32_(4) /* (CAN_NDAT2) New Data 36 Position */ 1204 #define CAN_NDAT2_ND36_Msk (_UINT32_(0x1) << CAN_NDAT2_ND36_Pos) /* (CAN_NDAT2) New Data 36 Mask */ 1205 #define CAN_NDAT2_ND36(value) (CAN_NDAT2_ND36_Msk & (_UINT32_(value) << CAN_NDAT2_ND36_Pos)) /* Assignment of value for ND36 in the CAN_NDAT2 register */ 1206 #define CAN_NDAT2_ND37_Pos _UINT32_(5) /* (CAN_NDAT2) New Data 37 Position */ 1207 #define CAN_NDAT2_ND37_Msk (_UINT32_(0x1) << CAN_NDAT2_ND37_Pos) /* (CAN_NDAT2) New Data 37 Mask */ 1208 #define CAN_NDAT2_ND37(value) (CAN_NDAT2_ND37_Msk & (_UINT32_(value) << CAN_NDAT2_ND37_Pos)) /* Assignment of value for ND37 in the CAN_NDAT2 register */ 1209 #define CAN_NDAT2_ND38_Pos _UINT32_(6) /* (CAN_NDAT2) New Data 38 Position */ 1210 #define CAN_NDAT2_ND38_Msk (_UINT32_(0x1) << CAN_NDAT2_ND38_Pos) /* (CAN_NDAT2) New Data 38 Mask */ 1211 #define CAN_NDAT2_ND38(value) (CAN_NDAT2_ND38_Msk & (_UINT32_(value) << CAN_NDAT2_ND38_Pos)) /* Assignment of value for ND38 in the CAN_NDAT2 register */ 1212 #define CAN_NDAT2_ND39_Pos _UINT32_(7) /* (CAN_NDAT2) New Data 39 Position */ 1213 #define CAN_NDAT2_ND39_Msk (_UINT32_(0x1) << CAN_NDAT2_ND39_Pos) /* (CAN_NDAT2) New Data 39 Mask */ 1214 #define CAN_NDAT2_ND39(value) (CAN_NDAT2_ND39_Msk & (_UINT32_(value) << CAN_NDAT2_ND39_Pos)) /* Assignment of value for ND39 in the CAN_NDAT2 register */ 1215 #define CAN_NDAT2_ND40_Pos _UINT32_(8) /* (CAN_NDAT2) New Data 40 Position */ 1216 #define CAN_NDAT2_ND40_Msk (_UINT32_(0x1) << CAN_NDAT2_ND40_Pos) /* (CAN_NDAT2) New Data 40 Mask */ 1217 #define CAN_NDAT2_ND40(value) (CAN_NDAT2_ND40_Msk & (_UINT32_(value) << CAN_NDAT2_ND40_Pos)) /* Assignment of value for ND40 in the CAN_NDAT2 register */ 1218 #define CAN_NDAT2_ND41_Pos _UINT32_(9) /* (CAN_NDAT2) New Data 41 Position */ 1219 #define CAN_NDAT2_ND41_Msk (_UINT32_(0x1) << CAN_NDAT2_ND41_Pos) /* (CAN_NDAT2) New Data 41 Mask */ 1220 #define CAN_NDAT2_ND41(value) (CAN_NDAT2_ND41_Msk & (_UINT32_(value) << CAN_NDAT2_ND41_Pos)) /* Assignment of value for ND41 in the CAN_NDAT2 register */ 1221 #define CAN_NDAT2_ND42_Pos _UINT32_(10) /* (CAN_NDAT2) New Data 42 Position */ 1222 #define CAN_NDAT2_ND42_Msk (_UINT32_(0x1) << CAN_NDAT2_ND42_Pos) /* (CAN_NDAT2) New Data 42 Mask */ 1223 #define CAN_NDAT2_ND42(value) (CAN_NDAT2_ND42_Msk & (_UINT32_(value) << CAN_NDAT2_ND42_Pos)) /* Assignment of value for ND42 in the CAN_NDAT2 register */ 1224 #define CAN_NDAT2_ND43_Pos _UINT32_(11) /* (CAN_NDAT2) New Data 43 Position */ 1225 #define CAN_NDAT2_ND43_Msk (_UINT32_(0x1) << CAN_NDAT2_ND43_Pos) /* (CAN_NDAT2) New Data 43 Mask */ 1226 #define CAN_NDAT2_ND43(value) (CAN_NDAT2_ND43_Msk & (_UINT32_(value) << CAN_NDAT2_ND43_Pos)) /* Assignment of value for ND43 in the CAN_NDAT2 register */ 1227 #define CAN_NDAT2_ND44_Pos _UINT32_(12) /* (CAN_NDAT2) New Data 44 Position */ 1228 #define CAN_NDAT2_ND44_Msk (_UINT32_(0x1) << CAN_NDAT2_ND44_Pos) /* (CAN_NDAT2) New Data 44 Mask */ 1229 #define CAN_NDAT2_ND44(value) (CAN_NDAT2_ND44_Msk & (_UINT32_(value) << CAN_NDAT2_ND44_Pos)) /* Assignment of value for ND44 in the CAN_NDAT2 register */ 1230 #define CAN_NDAT2_ND45_Pos _UINT32_(13) /* (CAN_NDAT2) New Data 45 Position */ 1231 #define CAN_NDAT2_ND45_Msk (_UINT32_(0x1) << CAN_NDAT2_ND45_Pos) /* (CAN_NDAT2) New Data 45 Mask */ 1232 #define CAN_NDAT2_ND45(value) (CAN_NDAT2_ND45_Msk & (_UINT32_(value) << CAN_NDAT2_ND45_Pos)) /* Assignment of value for ND45 in the CAN_NDAT2 register */ 1233 #define CAN_NDAT2_ND46_Pos _UINT32_(14) /* (CAN_NDAT2) New Data 46 Position */ 1234 #define CAN_NDAT2_ND46_Msk (_UINT32_(0x1) << CAN_NDAT2_ND46_Pos) /* (CAN_NDAT2) New Data 46 Mask */ 1235 #define CAN_NDAT2_ND46(value) (CAN_NDAT2_ND46_Msk & (_UINT32_(value) << CAN_NDAT2_ND46_Pos)) /* Assignment of value for ND46 in the CAN_NDAT2 register */ 1236 #define CAN_NDAT2_ND47_Pos _UINT32_(15) /* (CAN_NDAT2) New Data 47 Position */ 1237 #define CAN_NDAT2_ND47_Msk (_UINT32_(0x1) << CAN_NDAT2_ND47_Pos) /* (CAN_NDAT2) New Data 47 Mask */ 1238 #define CAN_NDAT2_ND47(value) (CAN_NDAT2_ND47_Msk & (_UINT32_(value) << CAN_NDAT2_ND47_Pos)) /* Assignment of value for ND47 in the CAN_NDAT2 register */ 1239 #define CAN_NDAT2_ND48_Pos _UINT32_(16) /* (CAN_NDAT2) New Data 48 Position */ 1240 #define CAN_NDAT2_ND48_Msk (_UINT32_(0x1) << CAN_NDAT2_ND48_Pos) /* (CAN_NDAT2) New Data 48 Mask */ 1241 #define CAN_NDAT2_ND48(value) (CAN_NDAT2_ND48_Msk & (_UINT32_(value) << CAN_NDAT2_ND48_Pos)) /* Assignment of value for ND48 in the CAN_NDAT2 register */ 1242 #define CAN_NDAT2_ND49_Pos _UINT32_(17) /* (CAN_NDAT2) New Data 49 Position */ 1243 #define CAN_NDAT2_ND49_Msk (_UINT32_(0x1) << CAN_NDAT2_ND49_Pos) /* (CAN_NDAT2) New Data 49 Mask */ 1244 #define CAN_NDAT2_ND49(value) (CAN_NDAT2_ND49_Msk & (_UINT32_(value) << CAN_NDAT2_ND49_Pos)) /* Assignment of value for ND49 in the CAN_NDAT2 register */ 1245 #define CAN_NDAT2_ND50_Pos _UINT32_(18) /* (CAN_NDAT2) New Data 50 Position */ 1246 #define CAN_NDAT2_ND50_Msk (_UINT32_(0x1) << CAN_NDAT2_ND50_Pos) /* (CAN_NDAT2) New Data 50 Mask */ 1247 #define CAN_NDAT2_ND50(value) (CAN_NDAT2_ND50_Msk & (_UINT32_(value) << CAN_NDAT2_ND50_Pos)) /* Assignment of value for ND50 in the CAN_NDAT2 register */ 1248 #define CAN_NDAT2_ND51_Pos _UINT32_(19) /* (CAN_NDAT2) New Data 51 Position */ 1249 #define CAN_NDAT2_ND51_Msk (_UINT32_(0x1) << CAN_NDAT2_ND51_Pos) /* (CAN_NDAT2) New Data 51 Mask */ 1250 #define CAN_NDAT2_ND51(value) (CAN_NDAT2_ND51_Msk & (_UINT32_(value) << CAN_NDAT2_ND51_Pos)) /* Assignment of value for ND51 in the CAN_NDAT2 register */ 1251 #define CAN_NDAT2_ND52_Pos _UINT32_(20) /* (CAN_NDAT2) New Data 52 Position */ 1252 #define CAN_NDAT2_ND52_Msk (_UINT32_(0x1) << CAN_NDAT2_ND52_Pos) /* (CAN_NDAT2) New Data 52 Mask */ 1253 #define CAN_NDAT2_ND52(value) (CAN_NDAT2_ND52_Msk & (_UINT32_(value) << CAN_NDAT2_ND52_Pos)) /* Assignment of value for ND52 in the CAN_NDAT2 register */ 1254 #define CAN_NDAT2_ND53_Pos _UINT32_(21) /* (CAN_NDAT2) New Data 53 Position */ 1255 #define CAN_NDAT2_ND53_Msk (_UINT32_(0x1) << CAN_NDAT2_ND53_Pos) /* (CAN_NDAT2) New Data 53 Mask */ 1256 #define CAN_NDAT2_ND53(value) (CAN_NDAT2_ND53_Msk & (_UINT32_(value) << CAN_NDAT2_ND53_Pos)) /* Assignment of value for ND53 in the CAN_NDAT2 register */ 1257 #define CAN_NDAT2_ND54_Pos _UINT32_(22) /* (CAN_NDAT2) New Data 54 Position */ 1258 #define CAN_NDAT2_ND54_Msk (_UINT32_(0x1) << CAN_NDAT2_ND54_Pos) /* (CAN_NDAT2) New Data 54 Mask */ 1259 #define CAN_NDAT2_ND54(value) (CAN_NDAT2_ND54_Msk & (_UINT32_(value) << CAN_NDAT2_ND54_Pos)) /* Assignment of value for ND54 in the CAN_NDAT2 register */ 1260 #define CAN_NDAT2_ND55_Pos _UINT32_(23) /* (CAN_NDAT2) New Data 55 Position */ 1261 #define CAN_NDAT2_ND55_Msk (_UINT32_(0x1) << CAN_NDAT2_ND55_Pos) /* (CAN_NDAT2) New Data 55 Mask */ 1262 #define CAN_NDAT2_ND55(value) (CAN_NDAT2_ND55_Msk & (_UINT32_(value) << CAN_NDAT2_ND55_Pos)) /* Assignment of value for ND55 in the CAN_NDAT2 register */ 1263 #define CAN_NDAT2_ND56_Pos _UINT32_(24) /* (CAN_NDAT2) New Data 56 Position */ 1264 #define CAN_NDAT2_ND56_Msk (_UINT32_(0x1) << CAN_NDAT2_ND56_Pos) /* (CAN_NDAT2) New Data 56 Mask */ 1265 #define CAN_NDAT2_ND56(value) (CAN_NDAT2_ND56_Msk & (_UINT32_(value) << CAN_NDAT2_ND56_Pos)) /* Assignment of value for ND56 in the CAN_NDAT2 register */ 1266 #define CAN_NDAT2_ND57_Pos _UINT32_(25) /* (CAN_NDAT2) New Data 57 Position */ 1267 #define CAN_NDAT2_ND57_Msk (_UINT32_(0x1) << CAN_NDAT2_ND57_Pos) /* (CAN_NDAT2) New Data 57 Mask */ 1268 #define CAN_NDAT2_ND57(value) (CAN_NDAT2_ND57_Msk & (_UINT32_(value) << CAN_NDAT2_ND57_Pos)) /* Assignment of value for ND57 in the CAN_NDAT2 register */ 1269 #define CAN_NDAT2_ND58_Pos _UINT32_(26) /* (CAN_NDAT2) New Data 58 Position */ 1270 #define CAN_NDAT2_ND58_Msk (_UINT32_(0x1) << CAN_NDAT2_ND58_Pos) /* (CAN_NDAT2) New Data 58 Mask */ 1271 #define CAN_NDAT2_ND58(value) (CAN_NDAT2_ND58_Msk & (_UINT32_(value) << CAN_NDAT2_ND58_Pos)) /* Assignment of value for ND58 in the CAN_NDAT2 register */ 1272 #define CAN_NDAT2_ND59_Pos _UINT32_(27) /* (CAN_NDAT2) New Data 59 Position */ 1273 #define CAN_NDAT2_ND59_Msk (_UINT32_(0x1) << CAN_NDAT2_ND59_Pos) /* (CAN_NDAT2) New Data 59 Mask */ 1274 #define CAN_NDAT2_ND59(value) (CAN_NDAT2_ND59_Msk & (_UINT32_(value) << CAN_NDAT2_ND59_Pos)) /* Assignment of value for ND59 in the CAN_NDAT2 register */ 1275 #define CAN_NDAT2_ND60_Pos _UINT32_(28) /* (CAN_NDAT2) New Data 60 Position */ 1276 #define CAN_NDAT2_ND60_Msk (_UINT32_(0x1) << CAN_NDAT2_ND60_Pos) /* (CAN_NDAT2) New Data 60 Mask */ 1277 #define CAN_NDAT2_ND60(value) (CAN_NDAT2_ND60_Msk & (_UINT32_(value) << CAN_NDAT2_ND60_Pos)) /* Assignment of value for ND60 in the CAN_NDAT2 register */ 1278 #define CAN_NDAT2_ND61_Pos _UINT32_(29) /* (CAN_NDAT2) New Data 61 Position */ 1279 #define CAN_NDAT2_ND61_Msk (_UINT32_(0x1) << CAN_NDAT2_ND61_Pos) /* (CAN_NDAT2) New Data 61 Mask */ 1280 #define CAN_NDAT2_ND61(value) (CAN_NDAT2_ND61_Msk & (_UINT32_(value) << CAN_NDAT2_ND61_Pos)) /* Assignment of value for ND61 in the CAN_NDAT2 register */ 1281 #define CAN_NDAT2_ND62_Pos _UINT32_(30) /* (CAN_NDAT2) New Data 62 Position */ 1282 #define CAN_NDAT2_ND62_Msk (_UINT32_(0x1) << CAN_NDAT2_ND62_Pos) /* (CAN_NDAT2) New Data 62 Mask */ 1283 #define CAN_NDAT2_ND62(value) (CAN_NDAT2_ND62_Msk & (_UINT32_(value) << CAN_NDAT2_ND62_Pos)) /* Assignment of value for ND62 in the CAN_NDAT2 register */ 1284 #define CAN_NDAT2_ND63_Pos _UINT32_(31) /* (CAN_NDAT2) New Data 63 Position */ 1285 #define CAN_NDAT2_ND63_Msk (_UINT32_(0x1) << CAN_NDAT2_ND63_Pos) /* (CAN_NDAT2) New Data 63 Mask */ 1286 #define CAN_NDAT2_ND63(value) (CAN_NDAT2_ND63_Msk & (_UINT32_(value) << CAN_NDAT2_ND63_Pos)) /* Assignment of value for ND63 in the CAN_NDAT2 register */ 1287 #define CAN_NDAT2_Msk _UINT32_(0xFFFFFFFF) /* (CAN_NDAT2) Register Mask */ 1288 1289 #define CAN_NDAT2_ND_Pos _UINT32_(0) /* (CAN_NDAT2 Position) New Data 63 */ 1290 #define CAN_NDAT2_ND_Msk (_UINT32_(0xFFFFFFFF) << CAN_NDAT2_ND_Pos) /* (CAN_NDAT2 Mask) ND */ 1291 #define CAN_NDAT2_ND(value) (CAN_NDAT2_ND_Msk & (_UINT32_(value) << CAN_NDAT2_ND_Pos)) 1292 1293 /* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ 1294 #define CAN_RXF0C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0C) Rx FIFO 0 Configuration Reset Value */ 1295 1296 #define CAN_RXF0C_F0SA_Pos _UINT32_(0) /* (CAN_RXF0C) Rx FIFO 0 Start Address Position */ 1297 #define CAN_RXF0C_F0SA_Msk (_UINT32_(0xFFFF) << CAN_RXF0C_F0SA_Pos) /* (CAN_RXF0C) Rx FIFO 0 Start Address Mask */ 1298 #define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & (_UINT32_(value) << CAN_RXF0C_F0SA_Pos)) /* Assignment of value for F0SA in the CAN_RXF0C register */ 1299 #define CAN_RXF0C_F0S_Pos _UINT32_(16) /* (CAN_RXF0C) Rx FIFO 0 Size Position */ 1300 #define CAN_RXF0C_F0S_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0S_Pos) /* (CAN_RXF0C) Rx FIFO 0 Size Mask */ 1301 #define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & (_UINT32_(value) << CAN_RXF0C_F0S_Pos)) /* Assignment of value for F0S in the CAN_RXF0C register */ 1302 #define CAN_RXF0C_F0WM_Pos _UINT32_(24) /* (CAN_RXF0C) Rx FIFO 0 Watermark Position */ 1303 #define CAN_RXF0C_F0WM_Msk (_UINT32_(0x7F) << CAN_RXF0C_F0WM_Pos) /* (CAN_RXF0C) Rx FIFO 0 Watermark Mask */ 1304 #define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & (_UINT32_(value) << CAN_RXF0C_F0WM_Pos)) /* Assignment of value for F0WM in the CAN_RXF0C register */ 1305 #define CAN_RXF0C_F0OM_Pos _UINT32_(31) /* (CAN_RXF0C) FIFO 0 Operation Mode Position */ 1306 #define CAN_RXF0C_F0OM_Msk (_UINT32_(0x1) << CAN_RXF0C_F0OM_Pos) /* (CAN_RXF0C) FIFO 0 Operation Mode Mask */ 1307 #define CAN_RXF0C_F0OM(value) (CAN_RXF0C_F0OM_Msk & (_UINT32_(value) << CAN_RXF0C_F0OM_Pos)) /* Assignment of value for F0OM in the CAN_RXF0C register */ 1308 #define CAN_RXF0C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF0C) Register Mask */ 1309 1310 1311 /* -------- CAN_RXF0S : (CAN Offset: 0xA4) ( R/ 32) Rx FIFO 0 Status -------- */ 1312 #define CAN_RXF0S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0S) Rx FIFO 0 Status Reset Value */ 1313 1314 #define CAN_RXF0S_F0FL_Pos _UINT32_(0) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Position */ 1315 #define CAN_RXF0S_F0FL_Msk (_UINT32_(0x7F) << CAN_RXF0S_F0FL_Pos) /* (CAN_RXF0S) Rx FIFO 0 Fill Level Mask */ 1316 #define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & (_UINT32_(value) << CAN_RXF0S_F0FL_Pos)) /* Assignment of value for F0FL in the CAN_RXF0S register */ 1317 #define CAN_RXF0S_F0GI_Pos _UINT32_(8) /* (CAN_RXF0S) Rx FIFO 0 Get Index Position */ 1318 #define CAN_RXF0S_F0GI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0GI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Get Index Mask */ 1319 #define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & (_UINT32_(value) << CAN_RXF0S_F0GI_Pos)) /* Assignment of value for F0GI in the CAN_RXF0S register */ 1320 #define CAN_RXF0S_F0PI_Pos _UINT32_(16) /* (CAN_RXF0S) Rx FIFO 0 Put Index Position */ 1321 #define CAN_RXF0S_F0PI_Msk (_UINT32_(0x3F) << CAN_RXF0S_F0PI_Pos) /* (CAN_RXF0S) Rx FIFO 0 Put Index Mask */ 1322 #define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & (_UINT32_(value) << CAN_RXF0S_F0PI_Pos)) /* Assignment of value for F0PI in the CAN_RXF0S register */ 1323 #define CAN_RXF0S_F0F_Pos _UINT32_(24) /* (CAN_RXF0S) Rx FIFO 0 Full Position */ 1324 #define CAN_RXF0S_F0F_Msk (_UINT32_(0x1) << CAN_RXF0S_F0F_Pos) /* (CAN_RXF0S) Rx FIFO 0 Full Mask */ 1325 #define CAN_RXF0S_F0F(value) (CAN_RXF0S_F0F_Msk & (_UINT32_(value) << CAN_RXF0S_F0F_Pos)) /* Assignment of value for F0F in the CAN_RXF0S register */ 1326 #define CAN_RXF0S_RF0L_Pos _UINT32_(25) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Position */ 1327 #define CAN_RXF0S_RF0L_Msk (_UINT32_(0x1) << CAN_RXF0S_RF0L_Pos) /* (CAN_RXF0S) Rx FIFO 0 Message Lost Mask */ 1328 #define CAN_RXF0S_RF0L(value) (CAN_RXF0S_RF0L_Msk & (_UINT32_(value) << CAN_RXF0S_RF0L_Pos)) /* Assignment of value for RF0L in the CAN_RXF0S register */ 1329 #define CAN_RXF0S_Msk _UINT32_(0x033F3F7F) /* (CAN_RXF0S) Register Mask */ 1330 1331 1332 /* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ 1333 #define CAN_RXF0A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Reset Value */ 1334 1335 #define CAN_RXF0A_F0AI_Pos _UINT32_(0) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Position */ 1336 #define CAN_RXF0A_F0AI_Msk (_UINT32_(0x3F) << CAN_RXF0A_F0AI_Pos) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Mask */ 1337 #define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & (_UINT32_(value) << CAN_RXF0A_F0AI_Pos)) /* Assignment of value for F0AI in the CAN_RXF0A register */ 1338 #define CAN_RXF0A_Msk _UINT32_(0x0000003F) /* (CAN_RXF0A) Register Mask */ 1339 1340 1341 /* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ 1342 #define CAN_RXBC_RESETVALUE _UINT32_(0x00) /* (CAN_RXBC) Rx Buffer Configuration Reset Value */ 1343 1344 #define CAN_RXBC_RBSA_Pos _UINT32_(0) /* (CAN_RXBC) Rx Buffer Start Address Position */ 1345 #define CAN_RXBC_RBSA_Msk (_UINT32_(0xFFFF) << CAN_RXBC_RBSA_Pos) /* (CAN_RXBC) Rx Buffer Start Address Mask */ 1346 #define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & (_UINT32_(value) << CAN_RXBC_RBSA_Pos)) /* Assignment of value for RBSA in the CAN_RXBC register */ 1347 #define CAN_RXBC_Msk _UINT32_(0x0000FFFF) /* (CAN_RXBC) Register Mask */ 1348 1349 1350 /* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ 1351 #define CAN_RXF1C_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1C) Rx FIFO 1 Configuration Reset Value */ 1352 1353 #define CAN_RXF1C_F1SA_Pos _UINT32_(0) /* (CAN_RXF1C) Rx FIFO 1 Start Address Position */ 1354 #define CAN_RXF1C_F1SA_Msk (_UINT32_(0xFFFF) << CAN_RXF1C_F1SA_Pos) /* (CAN_RXF1C) Rx FIFO 1 Start Address Mask */ 1355 #define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & (_UINT32_(value) << CAN_RXF1C_F1SA_Pos)) /* Assignment of value for F1SA in the CAN_RXF1C register */ 1356 #define CAN_RXF1C_F1S_Pos _UINT32_(16) /* (CAN_RXF1C) Rx FIFO 1 Size Position */ 1357 #define CAN_RXF1C_F1S_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1S_Pos) /* (CAN_RXF1C) Rx FIFO 1 Size Mask */ 1358 #define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & (_UINT32_(value) << CAN_RXF1C_F1S_Pos)) /* Assignment of value for F1S in the CAN_RXF1C register */ 1359 #define CAN_RXF1C_F1WM_Pos _UINT32_(24) /* (CAN_RXF1C) Rx FIFO 1 Watermark Position */ 1360 #define CAN_RXF1C_F1WM_Msk (_UINT32_(0x7F) << CAN_RXF1C_F1WM_Pos) /* (CAN_RXF1C) Rx FIFO 1 Watermark Mask */ 1361 #define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & (_UINT32_(value) << CAN_RXF1C_F1WM_Pos)) /* Assignment of value for F1WM in the CAN_RXF1C register */ 1362 #define CAN_RXF1C_F1OM_Pos _UINT32_(31) /* (CAN_RXF1C) FIFO 1 Operation Mode Position */ 1363 #define CAN_RXF1C_F1OM_Msk (_UINT32_(0x1) << CAN_RXF1C_F1OM_Pos) /* (CAN_RXF1C) FIFO 1 Operation Mode Mask */ 1364 #define CAN_RXF1C_F1OM(value) (CAN_RXF1C_F1OM_Msk & (_UINT32_(value) << CAN_RXF1C_F1OM_Pos)) /* Assignment of value for F1OM in the CAN_RXF1C register */ 1365 #define CAN_RXF1C_Msk _UINT32_(0xFF7FFFFF) /* (CAN_RXF1C) Register Mask */ 1366 1367 1368 /* -------- CAN_RXF1S : (CAN Offset: 0xB4) ( R/ 32) Rx FIFO 1 Status -------- */ 1369 #define CAN_RXF1S_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1S) Rx FIFO 1 Status Reset Value */ 1370 1371 #define CAN_RXF1S_F1FL_Pos _UINT32_(0) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Position */ 1372 #define CAN_RXF1S_F1FL_Msk (_UINT32_(0x7F) << CAN_RXF1S_F1FL_Pos) /* (CAN_RXF1S) Rx FIFO 1 Fill Level Mask */ 1373 #define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & (_UINT32_(value) << CAN_RXF1S_F1FL_Pos)) /* Assignment of value for F1FL in the CAN_RXF1S register */ 1374 #define CAN_RXF1S_F1GI_Pos _UINT32_(8) /* (CAN_RXF1S) Rx FIFO 1 Get Index Position */ 1375 #define CAN_RXF1S_F1GI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1GI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Get Index Mask */ 1376 #define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & (_UINT32_(value) << CAN_RXF1S_F1GI_Pos)) /* Assignment of value for F1GI in the CAN_RXF1S register */ 1377 #define CAN_RXF1S_F1PI_Pos _UINT32_(16) /* (CAN_RXF1S) Rx FIFO 1 Put Index Position */ 1378 #define CAN_RXF1S_F1PI_Msk (_UINT32_(0x3F) << CAN_RXF1S_F1PI_Pos) /* (CAN_RXF1S) Rx FIFO 1 Put Index Mask */ 1379 #define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & (_UINT32_(value) << CAN_RXF1S_F1PI_Pos)) /* Assignment of value for F1PI in the CAN_RXF1S register */ 1380 #define CAN_RXF1S_F1F_Pos _UINT32_(24) /* (CAN_RXF1S) Rx FIFO 1 Full Position */ 1381 #define CAN_RXF1S_F1F_Msk (_UINT32_(0x1) << CAN_RXF1S_F1F_Pos) /* (CAN_RXF1S) Rx FIFO 1 Full Mask */ 1382 #define CAN_RXF1S_F1F(value) (CAN_RXF1S_F1F_Msk & (_UINT32_(value) << CAN_RXF1S_F1F_Pos)) /* Assignment of value for F1F in the CAN_RXF1S register */ 1383 #define CAN_RXF1S_RF1L_Pos _UINT32_(25) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Position */ 1384 #define CAN_RXF1S_RF1L_Msk (_UINT32_(0x1) << CAN_RXF1S_RF1L_Pos) /* (CAN_RXF1S) Rx FIFO 1 Message Lost Mask */ 1385 #define CAN_RXF1S_RF1L(value) (CAN_RXF1S_RF1L_Msk & (_UINT32_(value) << CAN_RXF1S_RF1L_Pos)) /* Assignment of value for RF1L in the CAN_RXF1S register */ 1386 #define CAN_RXF1S_DMS_Pos _UINT32_(30) /* (CAN_RXF1S) Debug Message Status Position */ 1387 #define CAN_RXF1S_DMS_Msk (_UINT32_(0x3) << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug Message Status Mask */ 1388 #define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & (_UINT32_(value) << CAN_RXF1S_DMS_Pos)) /* Assignment of value for DMS in the CAN_RXF1S register */ 1389 #define CAN_RXF1S_DMS_IDLE_Val _UINT32_(0x0) /* (CAN_RXF1S) Idle state */ 1390 #define CAN_RXF1S_DMS_DBGA_Val _UINT32_(0x1) /* (CAN_RXF1S) Debug message A received */ 1391 #define CAN_RXF1S_DMS_DBGB_Val _UINT32_(0x2) /* (CAN_RXF1S) Debug message A/B received */ 1392 #define CAN_RXF1S_DMS_DBGC_Val _UINT32_(0x3) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set */ 1393 #define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Idle state Position */ 1394 #define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A received Position */ 1395 #define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B received Position */ 1396 #define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) /* (CAN_RXF1S) Debug message A/B/C received, DMA request set Position */ 1397 #define CAN_RXF1S_Msk _UINT32_(0xC33F3F7F) /* (CAN_RXF1S) Register Mask */ 1398 1399 1400 /* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ 1401 #define CAN_RXF1A_RESETVALUE _UINT32_(0x00) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Reset Value */ 1402 1403 #define CAN_RXF1A_F1AI_Pos _UINT32_(0) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Position */ 1404 #define CAN_RXF1A_F1AI_Msk (_UINT32_(0x3F) << CAN_RXF1A_F1AI_Pos) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Mask */ 1405 #define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & (_UINT32_(value) << CAN_RXF1A_F1AI_Pos)) /* Assignment of value for F1AI in the CAN_RXF1A register */ 1406 #define CAN_RXF1A_Msk _UINT32_(0x0000003F) /* (CAN_RXF1A) Register Mask */ 1407 1408 1409 /* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ 1410 #define CAN_RXESC_RESETVALUE _UINT32_(0x00) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Reset Value */ 1411 1412 #define CAN_RXESC_F0DS_Pos _UINT32_(0) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Position */ 1413 #define CAN_RXESC_F0DS_Msk (_UINT32_(0x7) << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) Rx FIFO 0 Data Field Size Mask */ 1414 #define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & (_UINT32_(value) << CAN_RXESC_F0DS_Pos)) /* Assignment of value for F0DS in the CAN_RXESC register */ 1415 #define CAN_RXESC_F0DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ 1416 #define CAN_RXESC_F0DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ 1417 #define CAN_RXESC_F0DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ 1418 #define CAN_RXESC_F0DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ 1419 #define CAN_RXESC_F0DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ 1420 #define CAN_RXESC_F0DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ 1421 #define CAN_RXESC_F0DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ 1422 #define CAN_RXESC_F0DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ 1423 #define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ 1424 #define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ 1425 #define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ 1426 #define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ 1427 #define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ 1428 #define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ 1429 #define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ 1430 #define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ 1431 #define CAN_RXESC_F1DS_Pos _UINT32_(4) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Position */ 1432 #define CAN_RXESC_F1DS_Msk (_UINT32_(0x7) << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) Rx FIFO 1 Data Field Size Mask */ 1433 #define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & (_UINT32_(value) << CAN_RXESC_F1DS_Pos)) /* Assignment of value for F1DS in the CAN_RXESC register */ 1434 #define CAN_RXESC_F1DS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ 1435 #define CAN_RXESC_F1DS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ 1436 #define CAN_RXESC_F1DS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ 1437 #define CAN_RXESC_F1DS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ 1438 #define CAN_RXESC_F1DS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ 1439 #define CAN_RXESC_F1DS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ 1440 #define CAN_RXESC_F1DS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ 1441 #define CAN_RXESC_F1DS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ 1442 #define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 8 byte data field Position */ 1443 #define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 12 byte data field Position */ 1444 #define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 16 byte data field Position */ 1445 #define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 20 byte data field Position */ 1446 #define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 24 byte data field Position */ 1447 #define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 32 byte data field Position */ 1448 #define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 48 byte data field Position */ 1449 #define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) /* (CAN_RXESC) 64 byte data field Position */ 1450 #define CAN_RXESC_RBDS_Pos _UINT32_(8) /* (CAN_RXESC) Rx Buffer Data Field Size Position */ 1451 #define CAN_RXESC_RBDS_Msk (_UINT32_(0x7) << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) Rx Buffer Data Field Size Mask */ 1452 #define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & (_UINT32_(value) << CAN_RXESC_RBDS_Pos)) /* Assignment of value for RBDS in the CAN_RXESC register */ 1453 #define CAN_RXESC_RBDS_DATA8_Val _UINT32_(0x0) /* (CAN_RXESC) 8 byte data field */ 1454 #define CAN_RXESC_RBDS_DATA12_Val _UINT32_(0x1) /* (CAN_RXESC) 12 byte data field */ 1455 #define CAN_RXESC_RBDS_DATA16_Val _UINT32_(0x2) /* (CAN_RXESC) 16 byte data field */ 1456 #define CAN_RXESC_RBDS_DATA20_Val _UINT32_(0x3) /* (CAN_RXESC) 20 byte data field */ 1457 #define CAN_RXESC_RBDS_DATA24_Val _UINT32_(0x4) /* (CAN_RXESC) 24 byte data field */ 1458 #define CAN_RXESC_RBDS_DATA32_Val _UINT32_(0x5) /* (CAN_RXESC) 32 byte data field */ 1459 #define CAN_RXESC_RBDS_DATA48_Val _UINT32_(0x6) /* (CAN_RXESC) 48 byte data field */ 1460 #define CAN_RXESC_RBDS_DATA64_Val _UINT32_(0x7) /* (CAN_RXESC) 64 byte data field */ 1461 #define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 8 byte data field Position */ 1462 #define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 12 byte data field Position */ 1463 #define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 16 byte data field Position */ 1464 #define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 20 byte data field Position */ 1465 #define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 24 byte data field Position */ 1466 #define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 32 byte data field Position */ 1467 #define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 48 byte data field Position */ 1468 #define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) /* (CAN_RXESC) 64 byte data field Position */ 1469 #define CAN_RXESC_Msk _UINT32_(0x00000777) /* (CAN_RXESC) Register Mask */ 1470 1471 1472 /* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ 1473 #define CAN_TXBC_RESETVALUE _UINT32_(0x00) /* (CAN_TXBC) Tx Buffer Configuration Reset Value */ 1474 1475 #define CAN_TXBC_TBSA_Pos _UINT32_(0) /* (CAN_TXBC) Tx Buffers Start Address Position */ 1476 #define CAN_TXBC_TBSA_Msk (_UINT32_(0xFFFF) << CAN_TXBC_TBSA_Pos) /* (CAN_TXBC) Tx Buffers Start Address Mask */ 1477 #define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & (_UINT32_(value) << CAN_TXBC_TBSA_Pos)) /* Assignment of value for TBSA in the CAN_TXBC register */ 1478 #define CAN_TXBC_NDTB_Pos _UINT32_(16) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Position */ 1479 #define CAN_TXBC_NDTB_Msk (_UINT32_(0x3F) << CAN_TXBC_NDTB_Pos) /* (CAN_TXBC) Number of Dedicated Transmit Buffers Mask */ 1480 #define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & (_UINT32_(value) << CAN_TXBC_NDTB_Pos)) /* Assignment of value for NDTB in the CAN_TXBC register */ 1481 #define CAN_TXBC_TFQS_Pos _UINT32_(24) /* (CAN_TXBC) Transmit FIFO/Queue Size Position */ 1482 #define CAN_TXBC_TFQS_Msk (_UINT32_(0x3F) << CAN_TXBC_TFQS_Pos) /* (CAN_TXBC) Transmit FIFO/Queue Size Mask */ 1483 #define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & (_UINT32_(value) << CAN_TXBC_TFQS_Pos)) /* Assignment of value for TFQS in the CAN_TXBC register */ 1484 #define CAN_TXBC_TFQM_Pos _UINT32_(30) /* (CAN_TXBC) Tx FIFO/Queue Mode Position */ 1485 #define CAN_TXBC_TFQM_Msk (_UINT32_(0x1) << CAN_TXBC_TFQM_Pos) /* (CAN_TXBC) Tx FIFO/Queue Mode Mask */ 1486 #define CAN_TXBC_TFQM(value) (CAN_TXBC_TFQM_Msk & (_UINT32_(value) << CAN_TXBC_TFQM_Pos)) /* Assignment of value for TFQM in the CAN_TXBC register */ 1487 #define CAN_TXBC_Msk _UINT32_(0x7F3FFFFF) /* (CAN_TXBC) Register Mask */ 1488 1489 1490 /* -------- CAN_TXFQS : (CAN Offset: 0xC4) ( R/ 32) Tx FIFO / Queue Status -------- */ 1491 #define CAN_TXFQS_RESETVALUE _UINT32_(0x00) /* (CAN_TXFQS) Tx FIFO / Queue Status Reset Value */ 1492 1493 #define CAN_TXFQS_TFFL_Pos _UINT32_(0) /* (CAN_TXFQS) Tx FIFO Free Level Position */ 1494 #define CAN_TXFQS_TFFL_Msk (_UINT32_(0x3F) << CAN_TXFQS_TFFL_Pos) /* (CAN_TXFQS) Tx FIFO Free Level Mask */ 1495 #define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & (_UINT32_(value) << CAN_TXFQS_TFFL_Pos)) /* Assignment of value for TFFL in the CAN_TXFQS register */ 1496 #define CAN_TXFQS_TFGI_Pos _UINT32_(8) /* (CAN_TXFQS) Tx FIFO Get Index Position */ 1497 #define CAN_TXFQS_TFGI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFGI_Pos) /* (CAN_TXFQS) Tx FIFO Get Index Mask */ 1498 #define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & (_UINT32_(value) << CAN_TXFQS_TFGI_Pos)) /* Assignment of value for TFGI in the CAN_TXFQS register */ 1499 #define CAN_TXFQS_TFQPI_Pos _UINT32_(16) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Position */ 1500 #define CAN_TXFQS_TFQPI_Msk (_UINT32_(0x1F) << CAN_TXFQS_TFQPI_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Put Index Mask */ 1501 #define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & (_UINT32_(value) << CAN_TXFQS_TFQPI_Pos)) /* Assignment of value for TFQPI in the CAN_TXFQS register */ 1502 #define CAN_TXFQS_TFQF_Pos _UINT32_(21) /* (CAN_TXFQS) Tx FIFO/Queue Full Position */ 1503 #define CAN_TXFQS_TFQF_Msk (_UINT32_(0x1) << CAN_TXFQS_TFQF_Pos) /* (CAN_TXFQS) Tx FIFO/Queue Full Mask */ 1504 #define CAN_TXFQS_TFQF(value) (CAN_TXFQS_TFQF_Msk & (_UINT32_(value) << CAN_TXFQS_TFQF_Pos)) /* Assignment of value for TFQF in the CAN_TXFQS register */ 1505 #define CAN_TXFQS_Msk _UINT32_(0x003F1F3F) /* (CAN_TXFQS) Register Mask */ 1506 1507 1508 /* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ 1509 #define CAN_TXESC_RESETVALUE _UINT32_(0x00) /* (CAN_TXESC) Tx Buffer Element Size Configuration Reset Value */ 1510 1511 #define CAN_TXESC_TBDS_Pos _UINT32_(0) /* (CAN_TXESC) Tx Buffer Data Field Size Position */ 1512 #define CAN_TXESC_TBDS_Msk (_UINT32_(0x7) << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) Tx Buffer Data Field Size Mask */ 1513 #define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & (_UINT32_(value) << CAN_TXESC_TBDS_Pos)) /* Assignment of value for TBDS in the CAN_TXESC register */ 1514 #define CAN_TXESC_TBDS_DATA8_Val _UINT32_(0x0) /* (CAN_TXESC) 8 byte data field */ 1515 #define CAN_TXESC_TBDS_DATA12_Val _UINT32_(0x1) /* (CAN_TXESC) 12 byte data field */ 1516 #define CAN_TXESC_TBDS_DATA16_Val _UINT32_(0x2) /* (CAN_TXESC) 16 byte data field */ 1517 #define CAN_TXESC_TBDS_DATA20_Val _UINT32_(0x3) /* (CAN_TXESC) 20 byte data field */ 1518 #define CAN_TXESC_TBDS_DATA24_Val _UINT32_(0x4) /* (CAN_TXESC) 24 byte data field */ 1519 #define CAN_TXESC_TBDS_DATA32_Val _UINT32_(0x5) /* (CAN_TXESC) 32 byte data field */ 1520 #define CAN_TXESC_TBDS_DATA48_Val _UINT32_(0x6) /* (CAN_TXESC) 48 byte data field */ 1521 #define CAN_TXESC_TBDS_DATA64_Val _UINT32_(0x7) /* (CAN_TXESC) 64 byte data field */ 1522 #define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 8 byte data field Position */ 1523 #define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 12 byte data field Position */ 1524 #define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 16 byte data field Position */ 1525 #define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 20 byte data field Position */ 1526 #define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 24 byte data field Position */ 1527 #define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 32 byte data field Position */ 1528 #define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 48 byte data field Position */ 1529 #define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) /* (CAN_TXESC) 64 byte data field Position */ 1530 #define CAN_TXESC_Msk _UINT32_(0x00000007) /* (CAN_TXESC) Register Mask */ 1531 1532 1533 /* -------- CAN_TXBRP : (CAN Offset: 0xCC) ( R/ 32) Tx Buffer Request Pending -------- */ 1534 #define CAN_TXBRP_RESETVALUE _UINT32_(0x00) /* (CAN_TXBRP) Tx Buffer Request Pending Reset Value */ 1535 1536 #define CAN_TXBRP_TRP0_Pos _UINT32_(0) /* (CAN_TXBRP) Transmission Request Pending 0 Position */ 1537 #define CAN_TXBRP_TRP0_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP0_Pos) /* (CAN_TXBRP) Transmission Request Pending 0 Mask */ 1538 #define CAN_TXBRP_TRP0(value) (CAN_TXBRP_TRP0_Msk & (_UINT32_(value) << CAN_TXBRP_TRP0_Pos)) /* Assignment of value for TRP0 in the CAN_TXBRP register */ 1539 #define CAN_TXBRP_TRP1_Pos _UINT32_(1) /* (CAN_TXBRP) Transmission Request Pending 1 Position */ 1540 #define CAN_TXBRP_TRP1_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP1_Pos) /* (CAN_TXBRP) Transmission Request Pending 1 Mask */ 1541 #define CAN_TXBRP_TRP1(value) (CAN_TXBRP_TRP1_Msk & (_UINT32_(value) << CAN_TXBRP_TRP1_Pos)) /* Assignment of value for TRP1 in the CAN_TXBRP register */ 1542 #define CAN_TXBRP_TRP2_Pos _UINT32_(2) /* (CAN_TXBRP) Transmission Request Pending 2 Position */ 1543 #define CAN_TXBRP_TRP2_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP2_Pos) /* (CAN_TXBRP) Transmission Request Pending 2 Mask */ 1544 #define CAN_TXBRP_TRP2(value) (CAN_TXBRP_TRP2_Msk & (_UINT32_(value) << CAN_TXBRP_TRP2_Pos)) /* Assignment of value for TRP2 in the CAN_TXBRP register */ 1545 #define CAN_TXBRP_TRP3_Pos _UINT32_(3) /* (CAN_TXBRP) Transmission Request Pending 3 Position */ 1546 #define CAN_TXBRP_TRP3_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP3_Pos) /* (CAN_TXBRP) Transmission Request Pending 3 Mask */ 1547 #define CAN_TXBRP_TRP3(value) (CAN_TXBRP_TRP3_Msk & (_UINT32_(value) << CAN_TXBRP_TRP3_Pos)) /* Assignment of value for TRP3 in the CAN_TXBRP register */ 1548 #define CAN_TXBRP_TRP4_Pos _UINT32_(4) /* (CAN_TXBRP) Transmission Request Pending 4 Position */ 1549 #define CAN_TXBRP_TRP4_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP4_Pos) /* (CAN_TXBRP) Transmission Request Pending 4 Mask */ 1550 #define CAN_TXBRP_TRP4(value) (CAN_TXBRP_TRP4_Msk & (_UINT32_(value) << CAN_TXBRP_TRP4_Pos)) /* Assignment of value for TRP4 in the CAN_TXBRP register */ 1551 #define CAN_TXBRP_TRP5_Pos _UINT32_(5) /* (CAN_TXBRP) Transmission Request Pending 5 Position */ 1552 #define CAN_TXBRP_TRP5_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP5_Pos) /* (CAN_TXBRP) Transmission Request Pending 5 Mask */ 1553 #define CAN_TXBRP_TRP5(value) (CAN_TXBRP_TRP5_Msk & (_UINT32_(value) << CAN_TXBRP_TRP5_Pos)) /* Assignment of value for TRP5 in the CAN_TXBRP register */ 1554 #define CAN_TXBRP_TRP6_Pos _UINT32_(6) /* (CAN_TXBRP) Transmission Request Pending 6 Position */ 1555 #define CAN_TXBRP_TRP6_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP6_Pos) /* (CAN_TXBRP) Transmission Request Pending 6 Mask */ 1556 #define CAN_TXBRP_TRP6(value) (CAN_TXBRP_TRP6_Msk & (_UINT32_(value) << CAN_TXBRP_TRP6_Pos)) /* Assignment of value for TRP6 in the CAN_TXBRP register */ 1557 #define CAN_TXBRP_TRP7_Pos _UINT32_(7) /* (CAN_TXBRP) Transmission Request Pending 7 Position */ 1558 #define CAN_TXBRP_TRP7_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP7_Pos) /* (CAN_TXBRP) Transmission Request Pending 7 Mask */ 1559 #define CAN_TXBRP_TRP7(value) (CAN_TXBRP_TRP7_Msk & (_UINT32_(value) << CAN_TXBRP_TRP7_Pos)) /* Assignment of value for TRP7 in the CAN_TXBRP register */ 1560 #define CAN_TXBRP_TRP8_Pos _UINT32_(8) /* (CAN_TXBRP) Transmission Request Pending 8 Position */ 1561 #define CAN_TXBRP_TRP8_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP8_Pos) /* (CAN_TXBRP) Transmission Request Pending 8 Mask */ 1562 #define CAN_TXBRP_TRP8(value) (CAN_TXBRP_TRP8_Msk & (_UINT32_(value) << CAN_TXBRP_TRP8_Pos)) /* Assignment of value for TRP8 in the CAN_TXBRP register */ 1563 #define CAN_TXBRP_TRP9_Pos _UINT32_(9) /* (CAN_TXBRP) Transmission Request Pending 9 Position */ 1564 #define CAN_TXBRP_TRP9_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP9_Pos) /* (CAN_TXBRP) Transmission Request Pending 9 Mask */ 1565 #define CAN_TXBRP_TRP9(value) (CAN_TXBRP_TRP9_Msk & (_UINT32_(value) << CAN_TXBRP_TRP9_Pos)) /* Assignment of value for TRP9 in the CAN_TXBRP register */ 1566 #define CAN_TXBRP_TRP10_Pos _UINT32_(10) /* (CAN_TXBRP) Transmission Request Pending 10 Position */ 1567 #define CAN_TXBRP_TRP10_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP10_Pos) /* (CAN_TXBRP) Transmission Request Pending 10 Mask */ 1568 #define CAN_TXBRP_TRP10(value) (CAN_TXBRP_TRP10_Msk & (_UINT32_(value) << CAN_TXBRP_TRP10_Pos)) /* Assignment of value for TRP10 in the CAN_TXBRP register */ 1569 #define CAN_TXBRP_TRP11_Pos _UINT32_(11) /* (CAN_TXBRP) Transmission Request Pending 11 Position */ 1570 #define CAN_TXBRP_TRP11_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP11_Pos) /* (CAN_TXBRP) Transmission Request Pending 11 Mask */ 1571 #define CAN_TXBRP_TRP11(value) (CAN_TXBRP_TRP11_Msk & (_UINT32_(value) << CAN_TXBRP_TRP11_Pos)) /* Assignment of value for TRP11 in the CAN_TXBRP register */ 1572 #define CAN_TXBRP_TRP12_Pos _UINT32_(12) /* (CAN_TXBRP) Transmission Request Pending 12 Position */ 1573 #define CAN_TXBRP_TRP12_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP12_Pos) /* (CAN_TXBRP) Transmission Request Pending 12 Mask */ 1574 #define CAN_TXBRP_TRP12(value) (CAN_TXBRP_TRP12_Msk & (_UINT32_(value) << CAN_TXBRP_TRP12_Pos)) /* Assignment of value for TRP12 in the CAN_TXBRP register */ 1575 #define CAN_TXBRP_TRP13_Pos _UINT32_(13) /* (CAN_TXBRP) Transmission Request Pending 13 Position */ 1576 #define CAN_TXBRP_TRP13_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP13_Pos) /* (CAN_TXBRP) Transmission Request Pending 13 Mask */ 1577 #define CAN_TXBRP_TRP13(value) (CAN_TXBRP_TRP13_Msk & (_UINT32_(value) << CAN_TXBRP_TRP13_Pos)) /* Assignment of value for TRP13 in the CAN_TXBRP register */ 1578 #define CAN_TXBRP_TRP14_Pos _UINT32_(14) /* (CAN_TXBRP) Transmission Request Pending 14 Position */ 1579 #define CAN_TXBRP_TRP14_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP14_Pos) /* (CAN_TXBRP) Transmission Request Pending 14 Mask */ 1580 #define CAN_TXBRP_TRP14(value) (CAN_TXBRP_TRP14_Msk & (_UINT32_(value) << CAN_TXBRP_TRP14_Pos)) /* Assignment of value for TRP14 in the CAN_TXBRP register */ 1581 #define CAN_TXBRP_TRP15_Pos _UINT32_(15) /* (CAN_TXBRP) Transmission Request Pending 15 Position */ 1582 #define CAN_TXBRP_TRP15_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP15_Pos) /* (CAN_TXBRP) Transmission Request Pending 15 Mask */ 1583 #define CAN_TXBRP_TRP15(value) (CAN_TXBRP_TRP15_Msk & (_UINT32_(value) << CAN_TXBRP_TRP15_Pos)) /* Assignment of value for TRP15 in the CAN_TXBRP register */ 1584 #define CAN_TXBRP_TRP16_Pos _UINT32_(16) /* (CAN_TXBRP) Transmission Request Pending 16 Position */ 1585 #define CAN_TXBRP_TRP16_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP16_Pos) /* (CAN_TXBRP) Transmission Request Pending 16 Mask */ 1586 #define CAN_TXBRP_TRP16(value) (CAN_TXBRP_TRP16_Msk & (_UINT32_(value) << CAN_TXBRP_TRP16_Pos)) /* Assignment of value for TRP16 in the CAN_TXBRP register */ 1587 #define CAN_TXBRP_TRP17_Pos _UINT32_(17) /* (CAN_TXBRP) Transmission Request Pending 17 Position */ 1588 #define CAN_TXBRP_TRP17_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP17_Pos) /* (CAN_TXBRP) Transmission Request Pending 17 Mask */ 1589 #define CAN_TXBRP_TRP17(value) (CAN_TXBRP_TRP17_Msk & (_UINT32_(value) << CAN_TXBRP_TRP17_Pos)) /* Assignment of value for TRP17 in the CAN_TXBRP register */ 1590 #define CAN_TXBRP_TRP18_Pos _UINT32_(18) /* (CAN_TXBRP) Transmission Request Pending 18 Position */ 1591 #define CAN_TXBRP_TRP18_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP18_Pos) /* (CAN_TXBRP) Transmission Request Pending 18 Mask */ 1592 #define CAN_TXBRP_TRP18(value) (CAN_TXBRP_TRP18_Msk & (_UINT32_(value) << CAN_TXBRP_TRP18_Pos)) /* Assignment of value for TRP18 in the CAN_TXBRP register */ 1593 #define CAN_TXBRP_TRP19_Pos _UINT32_(19) /* (CAN_TXBRP) Transmission Request Pending 19 Position */ 1594 #define CAN_TXBRP_TRP19_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP19_Pos) /* (CAN_TXBRP) Transmission Request Pending 19 Mask */ 1595 #define CAN_TXBRP_TRP19(value) (CAN_TXBRP_TRP19_Msk & (_UINT32_(value) << CAN_TXBRP_TRP19_Pos)) /* Assignment of value for TRP19 in the CAN_TXBRP register */ 1596 #define CAN_TXBRP_TRP20_Pos _UINT32_(20) /* (CAN_TXBRP) Transmission Request Pending 20 Position */ 1597 #define CAN_TXBRP_TRP20_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP20_Pos) /* (CAN_TXBRP) Transmission Request Pending 20 Mask */ 1598 #define CAN_TXBRP_TRP20(value) (CAN_TXBRP_TRP20_Msk & (_UINT32_(value) << CAN_TXBRP_TRP20_Pos)) /* Assignment of value for TRP20 in the CAN_TXBRP register */ 1599 #define CAN_TXBRP_TRP21_Pos _UINT32_(21) /* (CAN_TXBRP) Transmission Request Pending 21 Position */ 1600 #define CAN_TXBRP_TRP21_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP21_Pos) /* (CAN_TXBRP) Transmission Request Pending 21 Mask */ 1601 #define CAN_TXBRP_TRP21(value) (CAN_TXBRP_TRP21_Msk & (_UINT32_(value) << CAN_TXBRP_TRP21_Pos)) /* Assignment of value for TRP21 in the CAN_TXBRP register */ 1602 #define CAN_TXBRP_TRP22_Pos _UINT32_(22) /* (CAN_TXBRP) Transmission Request Pending 22 Position */ 1603 #define CAN_TXBRP_TRP22_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP22_Pos) /* (CAN_TXBRP) Transmission Request Pending 22 Mask */ 1604 #define CAN_TXBRP_TRP22(value) (CAN_TXBRP_TRP22_Msk & (_UINT32_(value) << CAN_TXBRP_TRP22_Pos)) /* Assignment of value for TRP22 in the CAN_TXBRP register */ 1605 #define CAN_TXBRP_TRP23_Pos _UINT32_(23) /* (CAN_TXBRP) Transmission Request Pending 23 Position */ 1606 #define CAN_TXBRP_TRP23_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP23_Pos) /* (CAN_TXBRP) Transmission Request Pending 23 Mask */ 1607 #define CAN_TXBRP_TRP23(value) (CAN_TXBRP_TRP23_Msk & (_UINT32_(value) << CAN_TXBRP_TRP23_Pos)) /* Assignment of value for TRP23 in the CAN_TXBRP register */ 1608 #define CAN_TXBRP_TRP24_Pos _UINT32_(24) /* (CAN_TXBRP) Transmission Request Pending 24 Position */ 1609 #define CAN_TXBRP_TRP24_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP24_Pos) /* (CAN_TXBRP) Transmission Request Pending 24 Mask */ 1610 #define CAN_TXBRP_TRP24(value) (CAN_TXBRP_TRP24_Msk & (_UINT32_(value) << CAN_TXBRP_TRP24_Pos)) /* Assignment of value for TRP24 in the CAN_TXBRP register */ 1611 #define CAN_TXBRP_TRP25_Pos _UINT32_(25) /* (CAN_TXBRP) Transmission Request Pending 25 Position */ 1612 #define CAN_TXBRP_TRP25_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP25_Pos) /* (CAN_TXBRP) Transmission Request Pending 25 Mask */ 1613 #define CAN_TXBRP_TRP25(value) (CAN_TXBRP_TRP25_Msk & (_UINT32_(value) << CAN_TXBRP_TRP25_Pos)) /* Assignment of value for TRP25 in the CAN_TXBRP register */ 1614 #define CAN_TXBRP_TRP26_Pos _UINT32_(26) /* (CAN_TXBRP) Transmission Request Pending 26 Position */ 1615 #define CAN_TXBRP_TRP26_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP26_Pos) /* (CAN_TXBRP) Transmission Request Pending 26 Mask */ 1616 #define CAN_TXBRP_TRP26(value) (CAN_TXBRP_TRP26_Msk & (_UINT32_(value) << CAN_TXBRP_TRP26_Pos)) /* Assignment of value for TRP26 in the CAN_TXBRP register */ 1617 #define CAN_TXBRP_TRP27_Pos _UINT32_(27) /* (CAN_TXBRP) Transmission Request Pending 27 Position */ 1618 #define CAN_TXBRP_TRP27_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP27_Pos) /* (CAN_TXBRP) Transmission Request Pending 27 Mask */ 1619 #define CAN_TXBRP_TRP27(value) (CAN_TXBRP_TRP27_Msk & (_UINT32_(value) << CAN_TXBRP_TRP27_Pos)) /* Assignment of value for TRP27 in the CAN_TXBRP register */ 1620 #define CAN_TXBRP_TRP28_Pos _UINT32_(28) /* (CAN_TXBRP) Transmission Request Pending 28 Position */ 1621 #define CAN_TXBRP_TRP28_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP28_Pos) /* (CAN_TXBRP) Transmission Request Pending 28 Mask */ 1622 #define CAN_TXBRP_TRP28(value) (CAN_TXBRP_TRP28_Msk & (_UINT32_(value) << CAN_TXBRP_TRP28_Pos)) /* Assignment of value for TRP28 in the CAN_TXBRP register */ 1623 #define CAN_TXBRP_TRP29_Pos _UINT32_(29) /* (CAN_TXBRP) Transmission Request Pending 29 Position */ 1624 #define CAN_TXBRP_TRP29_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP29_Pos) /* (CAN_TXBRP) Transmission Request Pending 29 Mask */ 1625 #define CAN_TXBRP_TRP29(value) (CAN_TXBRP_TRP29_Msk & (_UINT32_(value) << CAN_TXBRP_TRP29_Pos)) /* Assignment of value for TRP29 in the CAN_TXBRP register */ 1626 #define CAN_TXBRP_TRP30_Pos _UINT32_(30) /* (CAN_TXBRP) Transmission Request Pending 30 Position */ 1627 #define CAN_TXBRP_TRP30_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP30_Pos) /* (CAN_TXBRP) Transmission Request Pending 30 Mask */ 1628 #define CAN_TXBRP_TRP30(value) (CAN_TXBRP_TRP30_Msk & (_UINT32_(value) << CAN_TXBRP_TRP30_Pos)) /* Assignment of value for TRP30 in the CAN_TXBRP register */ 1629 #define CAN_TXBRP_TRP31_Pos _UINT32_(31) /* (CAN_TXBRP) Transmission Request Pending 31 Position */ 1630 #define CAN_TXBRP_TRP31_Msk (_UINT32_(0x1) << CAN_TXBRP_TRP31_Pos) /* (CAN_TXBRP) Transmission Request Pending 31 Mask */ 1631 #define CAN_TXBRP_TRP31(value) (CAN_TXBRP_TRP31_Msk & (_UINT32_(value) << CAN_TXBRP_TRP31_Pos)) /* Assignment of value for TRP31 in the CAN_TXBRP register */ 1632 #define CAN_TXBRP_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBRP) Register Mask */ 1633 1634 #define CAN_TXBRP_TRP_Pos _UINT32_(0) /* (CAN_TXBRP Position) Transmission Request Pending 3x */ 1635 #define CAN_TXBRP_TRP_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBRP_TRP_Pos) /* (CAN_TXBRP Mask) TRP */ 1636 #define CAN_TXBRP_TRP(value) (CAN_TXBRP_TRP_Msk & (_UINT32_(value) << CAN_TXBRP_TRP_Pos)) 1637 1638 /* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ 1639 #define CAN_TXBAR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBAR) Tx Buffer Add Request Reset Value */ 1640 1641 #define CAN_TXBAR_AR0_Pos _UINT32_(0) /* (CAN_TXBAR) Add Request 0 Position */ 1642 #define CAN_TXBAR_AR0_Msk (_UINT32_(0x1) << CAN_TXBAR_AR0_Pos) /* (CAN_TXBAR) Add Request 0 Mask */ 1643 #define CAN_TXBAR_AR0(value) (CAN_TXBAR_AR0_Msk & (_UINT32_(value) << CAN_TXBAR_AR0_Pos)) /* Assignment of value for AR0 in the CAN_TXBAR register */ 1644 #define CAN_TXBAR_AR1_Pos _UINT32_(1) /* (CAN_TXBAR) Add Request 1 Position */ 1645 #define CAN_TXBAR_AR1_Msk (_UINT32_(0x1) << CAN_TXBAR_AR1_Pos) /* (CAN_TXBAR) Add Request 1 Mask */ 1646 #define CAN_TXBAR_AR1(value) (CAN_TXBAR_AR1_Msk & (_UINT32_(value) << CAN_TXBAR_AR1_Pos)) /* Assignment of value for AR1 in the CAN_TXBAR register */ 1647 #define CAN_TXBAR_AR2_Pos _UINT32_(2) /* (CAN_TXBAR) Add Request 2 Position */ 1648 #define CAN_TXBAR_AR2_Msk (_UINT32_(0x1) << CAN_TXBAR_AR2_Pos) /* (CAN_TXBAR) Add Request 2 Mask */ 1649 #define CAN_TXBAR_AR2(value) (CAN_TXBAR_AR2_Msk & (_UINT32_(value) << CAN_TXBAR_AR2_Pos)) /* Assignment of value for AR2 in the CAN_TXBAR register */ 1650 #define CAN_TXBAR_AR3_Pos _UINT32_(3) /* (CAN_TXBAR) Add Request 3 Position */ 1651 #define CAN_TXBAR_AR3_Msk (_UINT32_(0x1) << CAN_TXBAR_AR3_Pos) /* (CAN_TXBAR) Add Request 3 Mask */ 1652 #define CAN_TXBAR_AR3(value) (CAN_TXBAR_AR3_Msk & (_UINT32_(value) << CAN_TXBAR_AR3_Pos)) /* Assignment of value for AR3 in the CAN_TXBAR register */ 1653 #define CAN_TXBAR_AR4_Pos _UINT32_(4) /* (CAN_TXBAR) Add Request 4 Position */ 1654 #define CAN_TXBAR_AR4_Msk (_UINT32_(0x1) << CAN_TXBAR_AR4_Pos) /* (CAN_TXBAR) Add Request 4 Mask */ 1655 #define CAN_TXBAR_AR4(value) (CAN_TXBAR_AR4_Msk & (_UINT32_(value) << CAN_TXBAR_AR4_Pos)) /* Assignment of value for AR4 in the CAN_TXBAR register */ 1656 #define CAN_TXBAR_AR5_Pos _UINT32_(5) /* (CAN_TXBAR) Add Request 5 Position */ 1657 #define CAN_TXBAR_AR5_Msk (_UINT32_(0x1) << CAN_TXBAR_AR5_Pos) /* (CAN_TXBAR) Add Request 5 Mask */ 1658 #define CAN_TXBAR_AR5(value) (CAN_TXBAR_AR5_Msk & (_UINT32_(value) << CAN_TXBAR_AR5_Pos)) /* Assignment of value for AR5 in the CAN_TXBAR register */ 1659 #define CAN_TXBAR_AR6_Pos _UINT32_(6) /* (CAN_TXBAR) Add Request 6 Position */ 1660 #define CAN_TXBAR_AR6_Msk (_UINT32_(0x1) << CAN_TXBAR_AR6_Pos) /* (CAN_TXBAR) Add Request 6 Mask */ 1661 #define CAN_TXBAR_AR6(value) (CAN_TXBAR_AR6_Msk & (_UINT32_(value) << CAN_TXBAR_AR6_Pos)) /* Assignment of value for AR6 in the CAN_TXBAR register */ 1662 #define CAN_TXBAR_AR7_Pos _UINT32_(7) /* (CAN_TXBAR) Add Request 7 Position */ 1663 #define CAN_TXBAR_AR7_Msk (_UINT32_(0x1) << CAN_TXBAR_AR7_Pos) /* (CAN_TXBAR) Add Request 7 Mask */ 1664 #define CAN_TXBAR_AR7(value) (CAN_TXBAR_AR7_Msk & (_UINT32_(value) << CAN_TXBAR_AR7_Pos)) /* Assignment of value for AR7 in the CAN_TXBAR register */ 1665 #define CAN_TXBAR_AR8_Pos _UINT32_(8) /* (CAN_TXBAR) Add Request 8 Position */ 1666 #define CAN_TXBAR_AR8_Msk (_UINT32_(0x1) << CAN_TXBAR_AR8_Pos) /* (CAN_TXBAR) Add Request 8 Mask */ 1667 #define CAN_TXBAR_AR8(value) (CAN_TXBAR_AR8_Msk & (_UINT32_(value) << CAN_TXBAR_AR8_Pos)) /* Assignment of value for AR8 in the CAN_TXBAR register */ 1668 #define CAN_TXBAR_AR9_Pos _UINT32_(9) /* (CAN_TXBAR) Add Request 9 Position */ 1669 #define CAN_TXBAR_AR9_Msk (_UINT32_(0x1) << CAN_TXBAR_AR9_Pos) /* (CAN_TXBAR) Add Request 9 Mask */ 1670 #define CAN_TXBAR_AR9(value) (CAN_TXBAR_AR9_Msk & (_UINT32_(value) << CAN_TXBAR_AR9_Pos)) /* Assignment of value for AR9 in the CAN_TXBAR register */ 1671 #define CAN_TXBAR_AR10_Pos _UINT32_(10) /* (CAN_TXBAR) Add Request 10 Position */ 1672 #define CAN_TXBAR_AR10_Msk (_UINT32_(0x1) << CAN_TXBAR_AR10_Pos) /* (CAN_TXBAR) Add Request 10 Mask */ 1673 #define CAN_TXBAR_AR10(value) (CAN_TXBAR_AR10_Msk & (_UINT32_(value) << CAN_TXBAR_AR10_Pos)) /* Assignment of value for AR10 in the CAN_TXBAR register */ 1674 #define CAN_TXBAR_AR11_Pos _UINT32_(11) /* (CAN_TXBAR) Add Request 11 Position */ 1675 #define CAN_TXBAR_AR11_Msk (_UINT32_(0x1) << CAN_TXBAR_AR11_Pos) /* (CAN_TXBAR) Add Request 11 Mask */ 1676 #define CAN_TXBAR_AR11(value) (CAN_TXBAR_AR11_Msk & (_UINT32_(value) << CAN_TXBAR_AR11_Pos)) /* Assignment of value for AR11 in the CAN_TXBAR register */ 1677 #define CAN_TXBAR_AR12_Pos _UINT32_(12) /* (CAN_TXBAR) Add Request 12 Position */ 1678 #define CAN_TXBAR_AR12_Msk (_UINT32_(0x1) << CAN_TXBAR_AR12_Pos) /* (CAN_TXBAR) Add Request 12 Mask */ 1679 #define CAN_TXBAR_AR12(value) (CAN_TXBAR_AR12_Msk & (_UINT32_(value) << CAN_TXBAR_AR12_Pos)) /* Assignment of value for AR12 in the CAN_TXBAR register */ 1680 #define CAN_TXBAR_AR13_Pos _UINT32_(13) /* (CAN_TXBAR) Add Request 13 Position */ 1681 #define CAN_TXBAR_AR13_Msk (_UINT32_(0x1) << CAN_TXBAR_AR13_Pos) /* (CAN_TXBAR) Add Request 13 Mask */ 1682 #define CAN_TXBAR_AR13(value) (CAN_TXBAR_AR13_Msk & (_UINT32_(value) << CAN_TXBAR_AR13_Pos)) /* Assignment of value for AR13 in the CAN_TXBAR register */ 1683 #define CAN_TXBAR_AR14_Pos _UINT32_(14) /* (CAN_TXBAR) Add Request 14 Position */ 1684 #define CAN_TXBAR_AR14_Msk (_UINT32_(0x1) << CAN_TXBAR_AR14_Pos) /* (CAN_TXBAR) Add Request 14 Mask */ 1685 #define CAN_TXBAR_AR14(value) (CAN_TXBAR_AR14_Msk & (_UINT32_(value) << CAN_TXBAR_AR14_Pos)) /* Assignment of value for AR14 in the CAN_TXBAR register */ 1686 #define CAN_TXBAR_AR15_Pos _UINT32_(15) /* (CAN_TXBAR) Add Request 15 Position */ 1687 #define CAN_TXBAR_AR15_Msk (_UINT32_(0x1) << CAN_TXBAR_AR15_Pos) /* (CAN_TXBAR) Add Request 15 Mask */ 1688 #define CAN_TXBAR_AR15(value) (CAN_TXBAR_AR15_Msk & (_UINT32_(value) << CAN_TXBAR_AR15_Pos)) /* Assignment of value for AR15 in the CAN_TXBAR register */ 1689 #define CAN_TXBAR_AR16_Pos _UINT32_(16) /* (CAN_TXBAR) Add Request 16 Position */ 1690 #define CAN_TXBAR_AR16_Msk (_UINT32_(0x1) << CAN_TXBAR_AR16_Pos) /* (CAN_TXBAR) Add Request 16 Mask */ 1691 #define CAN_TXBAR_AR16(value) (CAN_TXBAR_AR16_Msk & (_UINT32_(value) << CAN_TXBAR_AR16_Pos)) /* Assignment of value for AR16 in the CAN_TXBAR register */ 1692 #define CAN_TXBAR_AR17_Pos _UINT32_(17) /* (CAN_TXBAR) Add Request 17 Position */ 1693 #define CAN_TXBAR_AR17_Msk (_UINT32_(0x1) << CAN_TXBAR_AR17_Pos) /* (CAN_TXBAR) Add Request 17 Mask */ 1694 #define CAN_TXBAR_AR17(value) (CAN_TXBAR_AR17_Msk & (_UINT32_(value) << CAN_TXBAR_AR17_Pos)) /* Assignment of value for AR17 in the CAN_TXBAR register */ 1695 #define CAN_TXBAR_AR18_Pos _UINT32_(18) /* (CAN_TXBAR) Add Request 18 Position */ 1696 #define CAN_TXBAR_AR18_Msk (_UINT32_(0x1) << CAN_TXBAR_AR18_Pos) /* (CAN_TXBAR) Add Request 18 Mask */ 1697 #define CAN_TXBAR_AR18(value) (CAN_TXBAR_AR18_Msk & (_UINT32_(value) << CAN_TXBAR_AR18_Pos)) /* Assignment of value for AR18 in the CAN_TXBAR register */ 1698 #define CAN_TXBAR_AR19_Pos _UINT32_(19) /* (CAN_TXBAR) Add Request 19 Position */ 1699 #define CAN_TXBAR_AR19_Msk (_UINT32_(0x1) << CAN_TXBAR_AR19_Pos) /* (CAN_TXBAR) Add Request 19 Mask */ 1700 #define CAN_TXBAR_AR19(value) (CAN_TXBAR_AR19_Msk & (_UINT32_(value) << CAN_TXBAR_AR19_Pos)) /* Assignment of value for AR19 in the CAN_TXBAR register */ 1701 #define CAN_TXBAR_AR20_Pos _UINT32_(20) /* (CAN_TXBAR) Add Request 20 Position */ 1702 #define CAN_TXBAR_AR20_Msk (_UINT32_(0x1) << CAN_TXBAR_AR20_Pos) /* (CAN_TXBAR) Add Request 20 Mask */ 1703 #define CAN_TXBAR_AR20(value) (CAN_TXBAR_AR20_Msk & (_UINT32_(value) << CAN_TXBAR_AR20_Pos)) /* Assignment of value for AR20 in the CAN_TXBAR register */ 1704 #define CAN_TXBAR_AR21_Pos _UINT32_(21) /* (CAN_TXBAR) Add Request 21 Position */ 1705 #define CAN_TXBAR_AR21_Msk (_UINT32_(0x1) << CAN_TXBAR_AR21_Pos) /* (CAN_TXBAR) Add Request 21 Mask */ 1706 #define CAN_TXBAR_AR21(value) (CAN_TXBAR_AR21_Msk & (_UINT32_(value) << CAN_TXBAR_AR21_Pos)) /* Assignment of value for AR21 in the CAN_TXBAR register */ 1707 #define CAN_TXBAR_AR22_Pos _UINT32_(22) /* (CAN_TXBAR) Add Request 22 Position */ 1708 #define CAN_TXBAR_AR22_Msk (_UINT32_(0x1) << CAN_TXBAR_AR22_Pos) /* (CAN_TXBAR) Add Request 22 Mask */ 1709 #define CAN_TXBAR_AR22(value) (CAN_TXBAR_AR22_Msk & (_UINT32_(value) << CAN_TXBAR_AR22_Pos)) /* Assignment of value for AR22 in the CAN_TXBAR register */ 1710 #define CAN_TXBAR_AR23_Pos _UINT32_(23) /* (CAN_TXBAR) Add Request 23 Position */ 1711 #define CAN_TXBAR_AR23_Msk (_UINT32_(0x1) << CAN_TXBAR_AR23_Pos) /* (CAN_TXBAR) Add Request 23 Mask */ 1712 #define CAN_TXBAR_AR23(value) (CAN_TXBAR_AR23_Msk & (_UINT32_(value) << CAN_TXBAR_AR23_Pos)) /* Assignment of value for AR23 in the CAN_TXBAR register */ 1713 #define CAN_TXBAR_AR24_Pos _UINT32_(24) /* (CAN_TXBAR) Add Request 24 Position */ 1714 #define CAN_TXBAR_AR24_Msk (_UINT32_(0x1) << CAN_TXBAR_AR24_Pos) /* (CAN_TXBAR) Add Request 24 Mask */ 1715 #define CAN_TXBAR_AR24(value) (CAN_TXBAR_AR24_Msk & (_UINT32_(value) << CAN_TXBAR_AR24_Pos)) /* Assignment of value for AR24 in the CAN_TXBAR register */ 1716 #define CAN_TXBAR_AR25_Pos _UINT32_(25) /* (CAN_TXBAR) Add Request 25 Position */ 1717 #define CAN_TXBAR_AR25_Msk (_UINT32_(0x1) << CAN_TXBAR_AR25_Pos) /* (CAN_TXBAR) Add Request 25 Mask */ 1718 #define CAN_TXBAR_AR25(value) (CAN_TXBAR_AR25_Msk & (_UINT32_(value) << CAN_TXBAR_AR25_Pos)) /* Assignment of value for AR25 in the CAN_TXBAR register */ 1719 #define CAN_TXBAR_AR26_Pos _UINT32_(26) /* (CAN_TXBAR) Add Request 26 Position */ 1720 #define CAN_TXBAR_AR26_Msk (_UINT32_(0x1) << CAN_TXBAR_AR26_Pos) /* (CAN_TXBAR) Add Request 26 Mask */ 1721 #define CAN_TXBAR_AR26(value) (CAN_TXBAR_AR26_Msk & (_UINT32_(value) << CAN_TXBAR_AR26_Pos)) /* Assignment of value for AR26 in the CAN_TXBAR register */ 1722 #define CAN_TXBAR_AR27_Pos _UINT32_(27) /* (CAN_TXBAR) Add Request 27 Position */ 1723 #define CAN_TXBAR_AR27_Msk (_UINT32_(0x1) << CAN_TXBAR_AR27_Pos) /* (CAN_TXBAR) Add Request 27 Mask */ 1724 #define CAN_TXBAR_AR27(value) (CAN_TXBAR_AR27_Msk & (_UINT32_(value) << CAN_TXBAR_AR27_Pos)) /* Assignment of value for AR27 in the CAN_TXBAR register */ 1725 #define CAN_TXBAR_AR28_Pos _UINT32_(28) /* (CAN_TXBAR) Add Request 28 Position */ 1726 #define CAN_TXBAR_AR28_Msk (_UINT32_(0x1) << CAN_TXBAR_AR28_Pos) /* (CAN_TXBAR) Add Request 28 Mask */ 1727 #define CAN_TXBAR_AR28(value) (CAN_TXBAR_AR28_Msk & (_UINT32_(value) << CAN_TXBAR_AR28_Pos)) /* Assignment of value for AR28 in the CAN_TXBAR register */ 1728 #define CAN_TXBAR_AR29_Pos _UINT32_(29) /* (CAN_TXBAR) Add Request 29 Position */ 1729 #define CAN_TXBAR_AR29_Msk (_UINT32_(0x1) << CAN_TXBAR_AR29_Pos) /* (CAN_TXBAR) Add Request 29 Mask */ 1730 #define CAN_TXBAR_AR29(value) (CAN_TXBAR_AR29_Msk & (_UINT32_(value) << CAN_TXBAR_AR29_Pos)) /* Assignment of value for AR29 in the CAN_TXBAR register */ 1731 #define CAN_TXBAR_AR30_Pos _UINT32_(30) /* (CAN_TXBAR) Add Request 30 Position */ 1732 #define CAN_TXBAR_AR30_Msk (_UINT32_(0x1) << CAN_TXBAR_AR30_Pos) /* (CAN_TXBAR) Add Request 30 Mask */ 1733 #define CAN_TXBAR_AR30(value) (CAN_TXBAR_AR30_Msk & (_UINT32_(value) << CAN_TXBAR_AR30_Pos)) /* Assignment of value for AR30 in the CAN_TXBAR register */ 1734 #define CAN_TXBAR_AR31_Pos _UINT32_(31) /* (CAN_TXBAR) Add Request 31 Position */ 1735 #define CAN_TXBAR_AR31_Msk (_UINT32_(0x1) << CAN_TXBAR_AR31_Pos) /* (CAN_TXBAR) Add Request 31 Mask */ 1736 #define CAN_TXBAR_AR31(value) (CAN_TXBAR_AR31_Msk & (_UINT32_(value) << CAN_TXBAR_AR31_Pos)) /* Assignment of value for AR31 in the CAN_TXBAR register */ 1737 #define CAN_TXBAR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBAR) Register Mask */ 1738 1739 #define CAN_TXBAR_AR_Pos _UINT32_(0) /* (CAN_TXBAR Position) Add Request 3x */ 1740 #define CAN_TXBAR_AR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBAR_AR_Pos) /* (CAN_TXBAR Mask) AR */ 1741 #define CAN_TXBAR_AR(value) (CAN_TXBAR_AR_Msk & (_UINT32_(value) << CAN_TXBAR_AR_Pos)) 1742 1743 /* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ 1744 #define CAN_TXBCR_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCR) Tx Buffer Cancellation Request Reset Value */ 1745 1746 #define CAN_TXBCR_CR0_Pos _UINT32_(0) /* (CAN_TXBCR) Cancellation Request 0 Position */ 1747 #define CAN_TXBCR_CR0_Msk (_UINT32_(0x1) << CAN_TXBCR_CR0_Pos) /* (CAN_TXBCR) Cancellation Request 0 Mask */ 1748 #define CAN_TXBCR_CR0(value) (CAN_TXBCR_CR0_Msk & (_UINT32_(value) << CAN_TXBCR_CR0_Pos)) /* Assignment of value for CR0 in the CAN_TXBCR register */ 1749 #define CAN_TXBCR_CR1_Pos _UINT32_(1) /* (CAN_TXBCR) Cancellation Request 1 Position */ 1750 #define CAN_TXBCR_CR1_Msk (_UINT32_(0x1) << CAN_TXBCR_CR1_Pos) /* (CAN_TXBCR) Cancellation Request 1 Mask */ 1751 #define CAN_TXBCR_CR1(value) (CAN_TXBCR_CR1_Msk & (_UINT32_(value) << CAN_TXBCR_CR1_Pos)) /* Assignment of value for CR1 in the CAN_TXBCR register */ 1752 #define CAN_TXBCR_CR2_Pos _UINT32_(2) /* (CAN_TXBCR) Cancellation Request 2 Position */ 1753 #define CAN_TXBCR_CR2_Msk (_UINT32_(0x1) << CAN_TXBCR_CR2_Pos) /* (CAN_TXBCR) Cancellation Request 2 Mask */ 1754 #define CAN_TXBCR_CR2(value) (CAN_TXBCR_CR2_Msk & (_UINT32_(value) << CAN_TXBCR_CR2_Pos)) /* Assignment of value for CR2 in the CAN_TXBCR register */ 1755 #define CAN_TXBCR_CR3_Pos _UINT32_(3) /* (CAN_TXBCR) Cancellation Request 3 Position */ 1756 #define CAN_TXBCR_CR3_Msk (_UINT32_(0x1) << CAN_TXBCR_CR3_Pos) /* (CAN_TXBCR) Cancellation Request 3 Mask */ 1757 #define CAN_TXBCR_CR3(value) (CAN_TXBCR_CR3_Msk & (_UINT32_(value) << CAN_TXBCR_CR3_Pos)) /* Assignment of value for CR3 in the CAN_TXBCR register */ 1758 #define CAN_TXBCR_CR4_Pos _UINT32_(4) /* (CAN_TXBCR) Cancellation Request 4 Position */ 1759 #define CAN_TXBCR_CR4_Msk (_UINT32_(0x1) << CAN_TXBCR_CR4_Pos) /* (CAN_TXBCR) Cancellation Request 4 Mask */ 1760 #define CAN_TXBCR_CR4(value) (CAN_TXBCR_CR4_Msk & (_UINT32_(value) << CAN_TXBCR_CR4_Pos)) /* Assignment of value for CR4 in the CAN_TXBCR register */ 1761 #define CAN_TXBCR_CR5_Pos _UINT32_(5) /* (CAN_TXBCR) Cancellation Request 5 Position */ 1762 #define CAN_TXBCR_CR5_Msk (_UINT32_(0x1) << CAN_TXBCR_CR5_Pos) /* (CAN_TXBCR) Cancellation Request 5 Mask */ 1763 #define CAN_TXBCR_CR5(value) (CAN_TXBCR_CR5_Msk & (_UINT32_(value) << CAN_TXBCR_CR5_Pos)) /* Assignment of value for CR5 in the CAN_TXBCR register */ 1764 #define CAN_TXBCR_CR6_Pos _UINT32_(6) /* (CAN_TXBCR) Cancellation Request 6 Position */ 1765 #define CAN_TXBCR_CR6_Msk (_UINT32_(0x1) << CAN_TXBCR_CR6_Pos) /* (CAN_TXBCR) Cancellation Request 6 Mask */ 1766 #define CAN_TXBCR_CR6(value) (CAN_TXBCR_CR6_Msk & (_UINT32_(value) << CAN_TXBCR_CR6_Pos)) /* Assignment of value for CR6 in the CAN_TXBCR register */ 1767 #define CAN_TXBCR_CR7_Pos _UINT32_(7) /* (CAN_TXBCR) Cancellation Request 7 Position */ 1768 #define CAN_TXBCR_CR7_Msk (_UINT32_(0x1) << CAN_TXBCR_CR7_Pos) /* (CAN_TXBCR) Cancellation Request 7 Mask */ 1769 #define CAN_TXBCR_CR7(value) (CAN_TXBCR_CR7_Msk & (_UINT32_(value) << CAN_TXBCR_CR7_Pos)) /* Assignment of value for CR7 in the CAN_TXBCR register */ 1770 #define CAN_TXBCR_CR8_Pos _UINT32_(8) /* (CAN_TXBCR) Cancellation Request 8 Position */ 1771 #define CAN_TXBCR_CR8_Msk (_UINT32_(0x1) << CAN_TXBCR_CR8_Pos) /* (CAN_TXBCR) Cancellation Request 8 Mask */ 1772 #define CAN_TXBCR_CR8(value) (CAN_TXBCR_CR8_Msk & (_UINT32_(value) << CAN_TXBCR_CR8_Pos)) /* Assignment of value for CR8 in the CAN_TXBCR register */ 1773 #define CAN_TXBCR_CR9_Pos _UINT32_(9) /* (CAN_TXBCR) Cancellation Request 9 Position */ 1774 #define CAN_TXBCR_CR9_Msk (_UINT32_(0x1) << CAN_TXBCR_CR9_Pos) /* (CAN_TXBCR) Cancellation Request 9 Mask */ 1775 #define CAN_TXBCR_CR9(value) (CAN_TXBCR_CR9_Msk & (_UINT32_(value) << CAN_TXBCR_CR9_Pos)) /* Assignment of value for CR9 in the CAN_TXBCR register */ 1776 #define CAN_TXBCR_CR10_Pos _UINT32_(10) /* (CAN_TXBCR) Cancellation Request 10 Position */ 1777 #define CAN_TXBCR_CR10_Msk (_UINT32_(0x1) << CAN_TXBCR_CR10_Pos) /* (CAN_TXBCR) Cancellation Request 10 Mask */ 1778 #define CAN_TXBCR_CR10(value) (CAN_TXBCR_CR10_Msk & (_UINT32_(value) << CAN_TXBCR_CR10_Pos)) /* Assignment of value for CR10 in the CAN_TXBCR register */ 1779 #define CAN_TXBCR_CR11_Pos _UINT32_(11) /* (CAN_TXBCR) Cancellation Request 11 Position */ 1780 #define CAN_TXBCR_CR11_Msk (_UINT32_(0x1) << CAN_TXBCR_CR11_Pos) /* (CAN_TXBCR) Cancellation Request 11 Mask */ 1781 #define CAN_TXBCR_CR11(value) (CAN_TXBCR_CR11_Msk & (_UINT32_(value) << CAN_TXBCR_CR11_Pos)) /* Assignment of value for CR11 in the CAN_TXBCR register */ 1782 #define CAN_TXBCR_CR12_Pos _UINT32_(12) /* (CAN_TXBCR) Cancellation Request 12 Position */ 1783 #define CAN_TXBCR_CR12_Msk (_UINT32_(0x1) << CAN_TXBCR_CR12_Pos) /* (CAN_TXBCR) Cancellation Request 12 Mask */ 1784 #define CAN_TXBCR_CR12(value) (CAN_TXBCR_CR12_Msk & (_UINT32_(value) << CAN_TXBCR_CR12_Pos)) /* Assignment of value for CR12 in the CAN_TXBCR register */ 1785 #define CAN_TXBCR_CR13_Pos _UINT32_(13) /* (CAN_TXBCR) Cancellation Request 13 Position */ 1786 #define CAN_TXBCR_CR13_Msk (_UINT32_(0x1) << CAN_TXBCR_CR13_Pos) /* (CAN_TXBCR) Cancellation Request 13 Mask */ 1787 #define CAN_TXBCR_CR13(value) (CAN_TXBCR_CR13_Msk & (_UINT32_(value) << CAN_TXBCR_CR13_Pos)) /* Assignment of value for CR13 in the CAN_TXBCR register */ 1788 #define CAN_TXBCR_CR14_Pos _UINT32_(14) /* (CAN_TXBCR) Cancellation Request 14 Position */ 1789 #define CAN_TXBCR_CR14_Msk (_UINT32_(0x1) << CAN_TXBCR_CR14_Pos) /* (CAN_TXBCR) Cancellation Request 14 Mask */ 1790 #define CAN_TXBCR_CR14(value) (CAN_TXBCR_CR14_Msk & (_UINT32_(value) << CAN_TXBCR_CR14_Pos)) /* Assignment of value for CR14 in the CAN_TXBCR register */ 1791 #define CAN_TXBCR_CR15_Pos _UINT32_(15) /* (CAN_TXBCR) Cancellation Request 15 Position */ 1792 #define CAN_TXBCR_CR15_Msk (_UINT32_(0x1) << CAN_TXBCR_CR15_Pos) /* (CAN_TXBCR) Cancellation Request 15 Mask */ 1793 #define CAN_TXBCR_CR15(value) (CAN_TXBCR_CR15_Msk & (_UINT32_(value) << CAN_TXBCR_CR15_Pos)) /* Assignment of value for CR15 in the CAN_TXBCR register */ 1794 #define CAN_TXBCR_CR16_Pos _UINT32_(16) /* (CAN_TXBCR) Cancellation Request 16 Position */ 1795 #define CAN_TXBCR_CR16_Msk (_UINT32_(0x1) << CAN_TXBCR_CR16_Pos) /* (CAN_TXBCR) Cancellation Request 16 Mask */ 1796 #define CAN_TXBCR_CR16(value) (CAN_TXBCR_CR16_Msk & (_UINT32_(value) << CAN_TXBCR_CR16_Pos)) /* Assignment of value for CR16 in the CAN_TXBCR register */ 1797 #define CAN_TXBCR_CR17_Pos _UINT32_(17) /* (CAN_TXBCR) Cancellation Request 17 Position */ 1798 #define CAN_TXBCR_CR17_Msk (_UINT32_(0x1) << CAN_TXBCR_CR17_Pos) /* (CAN_TXBCR) Cancellation Request 17 Mask */ 1799 #define CAN_TXBCR_CR17(value) (CAN_TXBCR_CR17_Msk & (_UINT32_(value) << CAN_TXBCR_CR17_Pos)) /* Assignment of value for CR17 in the CAN_TXBCR register */ 1800 #define CAN_TXBCR_CR18_Pos _UINT32_(18) /* (CAN_TXBCR) Cancellation Request 18 Position */ 1801 #define CAN_TXBCR_CR18_Msk (_UINT32_(0x1) << CAN_TXBCR_CR18_Pos) /* (CAN_TXBCR) Cancellation Request 18 Mask */ 1802 #define CAN_TXBCR_CR18(value) (CAN_TXBCR_CR18_Msk & (_UINT32_(value) << CAN_TXBCR_CR18_Pos)) /* Assignment of value for CR18 in the CAN_TXBCR register */ 1803 #define CAN_TXBCR_CR19_Pos _UINT32_(19) /* (CAN_TXBCR) Cancellation Request 19 Position */ 1804 #define CAN_TXBCR_CR19_Msk (_UINT32_(0x1) << CAN_TXBCR_CR19_Pos) /* (CAN_TXBCR) Cancellation Request 19 Mask */ 1805 #define CAN_TXBCR_CR19(value) (CAN_TXBCR_CR19_Msk & (_UINT32_(value) << CAN_TXBCR_CR19_Pos)) /* Assignment of value for CR19 in the CAN_TXBCR register */ 1806 #define CAN_TXBCR_CR20_Pos _UINT32_(20) /* (CAN_TXBCR) Cancellation Request 20 Position */ 1807 #define CAN_TXBCR_CR20_Msk (_UINT32_(0x1) << CAN_TXBCR_CR20_Pos) /* (CAN_TXBCR) Cancellation Request 20 Mask */ 1808 #define CAN_TXBCR_CR20(value) (CAN_TXBCR_CR20_Msk & (_UINT32_(value) << CAN_TXBCR_CR20_Pos)) /* Assignment of value for CR20 in the CAN_TXBCR register */ 1809 #define CAN_TXBCR_CR21_Pos _UINT32_(21) /* (CAN_TXBCR) Cancellation Request 21 Position */ 1810 #define CAN_TXBCR_CR21_Msk (_UINT32_(0x1) << CAN_TXBCR_CR21_Pos) /* (CAN_TXBCR) Cancellation Request 21 Mask */ 1811 #define CAN_TXBCR_CR21(value) (CAN_TXBCR_CR21_Msk & (_UINT32_(value) << CAN_TXBCR_CR21_Pos)) /* Assignment of value for CR21 in the CAN_TXBCR register */ 1812 #define CAN_TXBCR_CR22_Pos _UINT32_(22) /* (CAN_TXBCR) Cancellation Request 22 Position */ 1813 #define CAN_TXBCR_CR22_Msk (_UINT32_(0x1) << CAN_TXBCR_CR22_Pos) /* (CAN_TXBCR) Cancellation Request 22 Mask */ 1814 #define CAN_TXBCR_CR22(value) (CAN_TXBCR_CR22_Msk & (_UINT32_(value) << CAN_TXBCR_CR22_Pos)) /* Assignment of value for CR22 in the CAN_TXBCR register */ 1815 #define CAN_TXBCR_CR23_Pos _UINT32_(23) /* (CAN_TXBCR) Cancellation Request 23 Position */ 1816 #define CAN_TXBCR_CR23_Msk (_UINT32_(0x1) << CAN_TXBCR_CR23_Pos) /* (CAN_TXBCR) Cancellation Request 23 Mask */ 1817 #define CAN_TXBCR_CR23(value) (CAN_TXBCR_CR23_Msk & (_UINT32_(value) << CAN_TXBCR_CR23_Pos)) /* Assignment of value for CR23 in the CAN_TXBCR register */ 1818 #define CAN_TXBCR_CR24_Pos _UINT32_(24) /* (CAN_TXBCR) Cancellation Request 24 Position */ 1819 #define CAN_TXBCR_CR24_Msk (_UINT32_(0x1) << CAN_TXBCR_CR24_Pos) /* (CAN_TXBCR) Cancellation Request 24 Mask */ 1820 #define CAN_TXBCR_CR24(value) (CAN_TXBCR_CR24_Msk & (_UINT32_(value) << CAN_TXBCR_CR24_Pos)) /* Assignment of value for CR24 in the CAN_TXBCR register */ 1821 #define CAN_TXBCR_CR25_Pos _UINT32_(25) /* (CAN_TXBCR) Cancellation Request 25 Position */ 1822 #define CAN_TXBCR_CR25_Msk (_UINT32_(0x1) << CAN_TXBCR_CR25_Pos) /* (CAN_TXBCR) Cancellation Request 25 Mask */ 1823 #define CAN_TXBCR_CR25(value) (CAN_TXBCR_CR25_Msk & (_UINT32_(value) << CAN_TXBCR_CR25_Pos)) /* Assignment of value for CR25 in the CAN_TXBCR register */ 1824 #define CAN_TXBCR_CR26_Pos _UINT32_(26) /* (CAN_TXBCR) Cancellation Request 26 Position */ 1825 #define CAN_TXBCR_CR26_Msk (_UINT32_(0x1) << CAN_TXBCR_CR26_Pos) /* (CAN_TXBCR) Cancellation Request 26 Mask */ 1826 #define CAN_TXBCR_CR26(value) (CAN_TXBCR_CR26_Msk & (_UINT32_(value) << CAN_TXBCR_CR26_Pos)) /* Assignment of value for CR26 in the CAN_TXBCR register */ 1827 #define CAN_TXBCR_CR27_Pos _UINT32_(27) /* (CAN_TXBCR) Cancellation Request 27 Position */ 1828 #define CAN_TXBCR_CR27_Msk (_UINT32_(0x1) << CAN_TXBCR_CR27_Pos) /* (CAN_TXBCR) Cancellation Request 27 Mask */ 1829 #define CAN_TXBCR_CR27(value) (CAN_TXBCR_CR27_Msk & (_UINT32_(value) << CAN_TXBCR_CR27_Pos)) /* Assignment of value for CR27 in the CAN_TXBCR register */ 1830 #define CAN_TXBCR_CR28_Pos _UINT32_(28) /* (CAN_TXBCR) Cancellation Request 28 Position */ 1831 #define CAN_TXBCR_CR28_Msk (_UINT32_(0x1) << CAN_TXBCR_CR28_Pos) /* (CAN_TXBCR) Cancellation Request 28 Mask */ 1832 #define CAN_TXBCR_CR28(value) (CAN_TXBCR_CR28_Msk & (_UINT32_(value) << CAN_TXBCR_CR28_Pos)) /* Assignment of value for CR28 in the CAN_TXBCR register */ 1833 #define CAN_TXBCR_CR29_Pos _UINT32_(29) /* (CAN_TXBCR) Cancellation Request 29 Position */ 1834 #define CAN_TXBCR_CR29_Msk (_UINT32_(0x1) << CAN_TXBCR_CR29_Pos) /* (CAN_TXBCR) Cancellation Request 29 Mask */ 1835 #define CAN_TXBCR_CR29(value) (CAN_TXBCR_CR29_Msk & (_UINT32_(value) << CAN_TXBCR_CR29_Pos)) /* Assignment of value for CR29 in the CAN_TXBCR register */ 1836 #define CAN_TXBCR_CR30_Pos _UINT32_(30) /* (CAN_TXBCR) Cancellation Request 30 Position */ 1837 #define CAN_TXBCR_CR30_Msk (_UINT32_(0x1) << CAN_TXBCR_CR30_Pos) /* (CAN_TXBCR) Cancellation Request 30 Mask */ 1838 #define CAN_TXBCR_CR30(value) (CAN_TXBCR_CR30_Msk & (_UINT32_(value) << CAN_TXBCR_CR30_Pos)) /* Assignment of value for CR30 in the CAN_TXBCR register */ 1839 #define CAN_TXBCR_CR31_Pos _UINT32_(31) /* (CAN_TXBCR) Cancellation Request 31 Position */ 1840 #define CAN_TXBCR_CR31_Msk (_UINT32_(0x1) << CAN_TXBCR_CR31_Pos) /* (CAN_TXBCR) Cancellation Request 31 Mask */ 1841 #define CAN_TXBCR_CR31(value) (CAN_TXBCR_CR31_Msk & (_UINT32_(value) << CAN_TXBCR_CR31_Pos)) /* Assignment of value for CR31 in the CAN_TXBCR register */ 1842 #define CAN_TXBCR_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCR) Register Mask */ 1843 1844 #define CAN_TXBCR_CR_Pos _UINT32_(0) /* (CAN_TXBCR Position) Cancellation Request 3x */ 1845 #define CAN_TXBCR_CR_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCR_CR_Pos) /* (CAN_TXBCR Mask) CR */ 1846 #define CAN_TXBCR_CR(value) (CAN_TXBCR_CR_Msk & (_UINT32_(value) << CAN_TXBCR_CR_Pos)) 1847 1848 /* -------- CAN_TXBTO : (CAN Offset: 0xD8) ( R/ 32) Tx Buffer Transmission Occurred -------- */ 1849 #define CAN_TXBTO_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Reset Value */ 1850 1851 #define CAN_TXBTO_TO0_Pos _UINT32_(0) /* (CAN_TXBTO) Transmission Occurred 0 Position */ 1852 #define CAN_TXBTO_TO0_Msk (_UINT32_(0x1) << CAN_TXBTO_TO0_Pos) /* (CAN_TXBTO) Transmission Occurred 0 Mask */ 1853 #define CAN_TXBTO_TO0(value) (CAN_TXBTO_TO0_Msk & (_UINT32_(value) << CAN_TXBTO_TO0_Pos)) /* Assignment of value for TO0 in the CAN_TXBTO register */ 1854 #define CAN_TXBTO_TO1_Pos _UINT32_(1) /* (CAN_TXBTO) Transmission Occurred 1 Position */ 1855 #define CAN_TXBTO_TO1_Msk (_UINT32_(0x1) << CAN_TXBTO_TO1_Pos) /* (CAN_TXBTO) Transmission Occurred 1 Mask */ 1856 #define CAN_TXBTO_TO1(value) (CAN_TXBTO_TO1_Msk & (_UINT32_(value) << CAN_TXBTO_TO1_Pos)) /* Assignment of value for TO1 in the CAN_TXBTO register */ 1857 #define CAN_TXBTO_TO2_Pos _UINT32_(2) /* (CAN_TXBTO) Transmission Occurred 2 Position */ 1858 #define CAN_TXBTO_TO2_Msk (_UINT32_(0x1) << CAN_TXBTO_TO2_Pos) /* (CAN_TXBTO) Transmission Occurred 2 Mask */ 1859 #define CAN_TXBTO_TO2(value) (CAN_TXBTO_TO2_Msk & (_UINT32_(value) << CAN_TXBTO_TO2_Pos)) /* Assignment of value for TO2 in the CAN_TXBTO register */ 1860 #define CAN_TXBTO_TO3_Pos _UINT32_(3) /* (CAN_TXBTO) Transmission Occurred 3 Position */ 1861 #define CAN_TXBTO_TO3_Msk (_UINT32_(0x1) << CAN_TXBTO_TO3_Pos) /* (CAN_TXBTO) Transmission Occurred 3 Mask */ 1862 #define CAN_TXBTO_TO3(value) (CAN_TXBTO_TO3_Msk & (_UINT32_(value) << CAN_TXBTO_TO3_Pos)) /* Assignment of value for TO3 in the CAN_TXBTO register */ 1863 #define CAN_TXBTO_TO4_Pos _UINT32_(4) /* (CAN_TXBTO) Transmission Occurred 4 Position */ 1864 #define CAN_TXBTO_TO4_Msk (_UINT32_(0x1) << CAN_TXBTO_TO4_Pos) /* (CAN_TXBTO) Transmission Occurred 4 Mask */ 1865 #define CAN_TXBTO_TO4(value) (CAN_TXBTO_TO4_Msk & (_UINT32_(value) << CAN_TXBTO_TO4_Pos)) /* Assignment of value for TO4 in the CAN_TXBTO register */ 1866 #define CAN_TXBTO_TO5_Pos _UINT32_(5) /* (CAN_TXBTO) Transmission Occurred 5 Position */ 1867 #define CAN_TXBTO_TO5_Msk (_UINT32_(0x1) << CAN_TXBTO_TO5_Pos) /* (CAN_TXBTO) Transmission Occurred 5 Mask */ 1868 #define CAN_TXBTO_TO5(value) (CAN_TXBTO_TO5_Msk & (_UINT32_(value) << CAN_TXBTO_TO5_Pos)) /* Assignment of value for TO5 in the CAN_TXBTO register */ 1869 #define CAN_TXBTO_TO6_Pos _UINT32_(6) /* (CAN_TXBTO) Transmission Occurred 6 Position */ 1870 #define CAN_TXBTO_TO6_Msk (_UINT32_(0x1) << CAN_TXBTO_TO6_Pos) /* (CAN_TXBTO) Transmission Occurred 6 Mask */ 1871 #define CAN_TXBTO_TO6(value) (CAN_TXBTO_TO6_Msk & (_UINT32_(value) << CAN_TXBTO_TO6_Pos)) /* Assignment of value for TO6 in the CAN_TXBTO register */ 1872 #define CAN_TXBTO_TO7_Pos _UINT32_(7) /* (CAN_TXBTO) Transmission Occurred 7 Position */ 1873 #define CAN_TXBTO_TO7_Msk (_UINT32_(0x1) << CAN_TXBTO_TO7_Pos) /* (CAN_TXBTO) Transmission Occurred 7 Mask */ 1874 #define CAN_TXBTO_TO7(value) (CAN_TXBTO_TO7_Msk & (_UINT32_(value) << CAN_TXBTO_TO7_Pos)) /* Assignment of value for TO7 in the CAN_TXBTO register */ 1875 #define CAN_TXBTO_TO8_Pos _UINT32_(8) /* (CAN_TXBTO) Transmission Occurred 8 Position */ 1876 #define CAN_TXBTO_TO8_Msk (_UINT32_(0x1) << CAN_TXBTO_TO8_Pos) /* (CAN_TXBTO) Transmission Occurred 8 Mask */ 1877 #define CAN_TXBTO_TO8(value) (CAN_TXBTO_TO8_Msk & (_UINT32_(value) << CAN_TXBTO_TO8_Pos)) /* Assignment of value for TO8 in the CAN_TXBTO register */ 1878 #define CAN_TXBTO_TO9_Pos _UINT32_(9) /* (CAN_TXBTO) Transmission Occurred 9 Position */ 1879 #define CAN_TXBTO_TO9_Msk (_UINT32_(0x1) << CAN_TXBTO_TO9_Pos) /* (CAN_TXBTO) Transmission Occurred 9 Mask */ 1880 #define CAN_TXBTO_TO9(value) (CAN_TXBTO_TO9_Msk & (_UINT32_(value) << CAN_TXBTO_TO9_Pos)) /* Assignment of value for TO9 in the CAN_TXBTO register */ 1881 #define CAN_TXBTO_TO10_Pos _UINT32_(10) /* (CAN_TXBTO) Transmission Occurred 10 Position */ 1882 #define CAN_TXBTO_TO10_Msk (_UINT32_(0x1) << CAN_TXBTO_TO10_Pos) /* (CAN_TXBTO) Transmission Occurred 10 Mask */ 1883 #define CAN_TXBTO_TO10(value) (CAN_TXBTO_TO10_Msk & (_UINT32_(value) << CAN_TXBTO_TO10_Pos)) /* Assignment of value for TO10 in the CAN_TXBTO register */ 1884 #define CAN_TXBTO_TO11_Pos _UINT32_(11) /* (CAN_TXBTO) Transmission Occurred 11 Position */ 1885 #define CAN_TXBTO_TO11_Msk (_UINT32_(0x1) << CAN_TXBTO_TO11_Pos) /* (CAN_TXBTO) Transmission Occurred 11 Mask */ 1886 #define CAN_TXBTO_TO11(value) (CAN_TXBTO_TO11_Msk & (_UINT32_(value) << CAN_TXBTO_TO11_Pos)) /* Assignment of value for TO11 in the CAN_TXBTO register */ 1887 #define CAN_TXBTO_TO12_Pos _UINT32_(12) /* (CAN_TXBTO) Transmission Occurred 12 Position */ 1888 #define CAN_TXBTO_TO12_Msk (_UINT32_(0x1) << CAN_TXBTO_TO12_Pos) /* (CAN_TXBTO) Transmission Occurred 12 Mask */ 1889 #define CAN_TXBTO_TO12(value) (CAN_TXBTO_TO12_Msk & (_UINT32_(value) << CAN_TXBTO_TO12_Pos)) /* Assignment of value for TO12 in the CAN_TXBTO register */ 1890 #define CAN_TXBTO_TO13_Pos _UINT32_(13) /* (CAN_TXBTO) Transmission Occurred 13 Position */ 1891 #define CAN_TXBTO_TO13_Msk (_UINT32_(0x1) << CAN_TXBTO_TO13_Pos) /* (CAN_TXBTO) Transmission Occurred 13 Mask */ 1892 #define CAN_TXBTO_TO13(value) (CAN_TXBTO_TO13_Msk & (_UINT32_(value) << CAN_TXBTO_TO13_Pos)) /* Assignment of value for TO13 in the CAN_TXBTO register */ 1893 #define CAN_TXBTO_TO14_Pos _UINT32_(14) /* (CAN_TXBTO) Transmission Occurred 14 Position */ 1894 #define CAN_TXBTO_TO14_Msk (_UINT32_(0x1) << CAN_TXBTO_TO14_Pos) /* (CAN_TXBTO) Transmission Occurred 14 Mask */ 1895 #define CAN_TXBTO_TO14(value) (CAN_TXBTO_TO14_Msk & (_UINT32_(value) << CAN_TXBTO_TO14_Pos)) /* Assignment of value for TO14 in the CAN_TXBTO register */ 1896 #define CAN_TXBTO_TO15_Pos _UINT32_(15) /* (CAN_TXBTO) Transmission Occurred 15 Position */ 1897 #define CAN_TXBTO_TO15_Msk (_UINT32_(0x1) << CAN_TXBTO_TO15_Pos) /* (CAN_TXBTO) Transmission Occurred 15 Mask */ 1898 #define CAN_TXBTO_TO15(value) (CAN_TXBTO_TO15_Msk & (_UINT32_(value) << CAN_TXBTO_TO15_Pos)) /* Assignment of value for TO15 in the CAN_TXBTO register */ 1899 #define CAN_TXBTO_TO16_Pos _UINT32_(16) /* (CAN_TXBTO) Transmission Occurred 16 Position */ 1900 #define CAN_TXBTO_TO16_Msk (_UINT32_(0x1) << CAN_TXBTO_TO16_Pos) /* (CAN_TXBTO) Transmission Occurred 16 Mask */ 1901 #define CAN_TXBTO_TO16(value) (CAN_TXBTO_TO16_Msk & (_UINT32_(value) << CAN_TXBTO_TO16_Pos)) /* Assignment of value for TO16 in the CAN_TXBTO register */ 1902 #define CAN_TXBTO_TO17_Pos _UINT32_(17) /* (CAN_TXBTO) Transmission Occurred 17 Position */ 1903 #define CAN_TXBTO_TO17_Msk (_UINT32_(0x1) << CAN_TXBTO_TO17_Pos) /* (CAN_TXBTO) Transmission Occurred 17 Mask */ 1904 #define CAN_TXBTO_TO17(value) (CAN_TXBTO_TO17_Msk & (_UINT32_(value) << CAN_TXBTO_TO17_Pos)) /* Assignment of value for TO17 in the CAN_TXBTO register */ 1905 #define CAN_TXBTO_TO18_Pos _UINT32_(18) /* (CAN_TXBTO) Transmission Occurred 18 Position */ 1906 #define CAN_TXBTO_TO18_Msk (_UINT32_(0x1) << CAN_TXBTO_TO18_Pos) /* (CAN_TXBTO) Transmission Occurred 18 Mask */ 1907 #define CAN_TXBTO_TO18(value) (CAN_TXBTO_TO18_Msk & (_UINT32_(value) << CAN_TXBTO_TO18_Pos)) /* Assignment of value for TO18 in the CAN_TXBTO register */ 1908 #define CAN_TXBTO_TO19_Pos _UINT32_(19) /* (CAN_TXBTO) Transmission Occurred 19 Position */ 1909 #define CAN_TXBTO_TO19_Msk (_UINT32_(0x1) << CAN_TXBTO_TO19_Pos) /* (CAN_TXBTO) Transmission Occurred 19 Mask */ 1910 #define CAN_TXBTO_TO19(value) (CAN_TXBTO_TO19_Msk & (_UINT32_(value) << CAN_TXBTO_TO19_Pos)) /* Assignment of value for TO19 in the CAN_TXBTO register */ 1911 #define CAN_TXBTO_TO20_Pos _UINT32_(20) /* (CAN_TXBTO) Transmission Occurred 20 Position */ 1912 #define CAN_TXBTO_TO20_Msk (_UINT32_(0x1) << CAN_TXBTO_TO20_Pos) /* (CAN_TXBTO) Transmission Occurred 20 Mask */ 1913 #define CAN_TXBTO_TO20(value) (CAN_TXBTO_TO20_Msk & (_UINT32_(value) << CAN_TXBTO_TO20_Pos)) /* Assignment of value for TO20 in the CAN_TXBTO register */ 1914 #define CAN_TXBTO_TO21_Pos _UINT32_(21) /* (CAN_TXBTO) Transmission Occurred 21 Position */ 1915 #define CAN_TXBTO_TO21_Msk (_UINT32_(0x1) << CAN_TXBTO_TO21_Pos) /* (CAN_TXBTO) Transmission Occurred 21 Mask */ 1916 #define CAN_TXBTO_TO21(value) (CAN_TXBTO_TO21_Msk & (_UINT32_(value) << CAN_TXBTO_TO21_Pos)) /* Assignment of value for TO21 in the CAN_TXBTO register */ 1917 #define CAN_TXBTO_TO22_Pos _UINT32_(22) /* (CAN_TXBTO) Transmission Occurred 22 Position */ 1918 #define CAN_TXBTO_TO22_Msk (_UINT32_(0x1) << CAN_TXBTO_TO22_Pos) /* (CAN_TXBTO) Transmission Occurred 22 Mask */ 1919 #define CAN_TXBTO_TO22(value) (CAN_TXBTO_TO22_Msk & (_UINT32_(value) << CAN_TXBTO_TO22_Pos)) /* Assignment of value for TO22 in the CAN_TXBTO register */ 1920 #define CAN_TXBTO_TO23_Pos _UINT32_(23) /* (CAN_TXBTO) Transmission Occurred 23 Position */ 1921 #define CAN_TXBTO_TO23_Msk (_UINT32_(0x1) << CAN_TXBTO_TO23_Pos) /* (CAN_TXBTO) Transmission Occurred 23 Mask */ 1922 #define CAN_TXBTO_TO23(value) (CAN_TXBTO_TO23_Msk & (_UINT32_(value) << CAN_TXBTO_TO23_Pos)) /* Assignment of value for TO23 in the CAN_TXBTO register */ 1923 #define CAN_TXBTO_TO24_Pos _UINT32_(24) /* (CAN_TXBTO) Transmission Occurred 24 Position */ 1924 #define CAN_TXBTO_TO24_Msk (_UINT32_(0x1) << CAN_TXBTO_TO24_Pos) /* (CAN_TXBTO) Transmission Occurred 24 Mask */ 1925 #define CAN_TXBTO_TO24(value) (CAN_TXBTO_TO24_Msk & (_UINT32_(value) << CAN_TXBTO_TO24_Pos)) /* Assignment of value for TO24 in the CAN_TXBTO register */ 1926 #define CAN_TXBTO_TO25_Pos _UINT32_(25) /* (CAN_TXBTO) Transmission Occurred 25 Position */ 1927 #define CAN_TXBTO_TO25_Msk (_UINT32_(0x1) << CAN_TXBTO_TO25_Pos) /* (CAN_TXBTO) Transmission Occurred 25 Mask */ 1928 #define CAN_TXBTO_TO25(value) (CAN_TXBTO_TO25_Msk & (_UINT32_(value) << CAN_TXBTO_TO25_Pos)) /* Assignment of value for TO25 in the CAN_TXBTO register */ 1929 #define CAN_TXBTO_TO26_Pos _UINT32_(26) /* (CAN_TXBTO) Transmission Occurred 26 Position */ 1930 #define CAN_TXBTO_TO26_Msk (_UINT32_(0x1) << CAN_TXBTO_TO26_Pos) /* (CAN_TXBTO) Transmission Occurred 26 Mask */ 1931 #define CAN_TXBTO_TO26(value) (CAN_TXBTO_TO26_Msk & (_UINT32_(value) << CAN_TXBTO_TO26_Pos)) /* Assignment of value for TO26 in the CAN_TXBTO register */ 1932 #define CAN_TXBTO_TO27_Pos _UINT32_(27) /* (CAN_TXBTO) Transmission Occurred 27 Position */ 1933 #define CAN_TXBTO_TO27_Msk (_UINT32_(0x1) << CAN_TXBTO_TO27_Pos) /* (CAN_TXBTO) Transmission Occurred 27 Mask */ 1934 #define CAN_TXBTO_TO27(value) (CAN_TXBTO_TO27_Msk & (_UINT32_(value) << CAN_TXBTO_TO27_Pos)) /* Assignment of value for TO27 in the CAN_TXBTO register */ 1935 #define CAN_TXBTO_TO28_Pos _UINT32_(28) /* (CAN_TXBTO) Transmission Occurred 28 Position */ 1936 #define CAN_TXBTO_TO28_Msk (_UINT32_(0x1) << CAN_TXBTO_TO28_Pos) /* (CAN_TXBTO) Transmission Occurred 28 Mask */ 1937 #define CAN_TXBTO_TO28(value) (CAN_TXBTO_TO28_Msk & (_UINT32_(value) << CAN_TXBTO_TO28_Pos)) /* Assignment of value for TO28 in the CAN_TXBTO register */ 1938 #define CAN_TXBTO_TO29_Pos _UINT32_(29) /* (CAN_TXBTO) Transmission Occurred 29 Position */ 1939 #define CAN_TXBTO_TO29_Msk (_UINT32_(0x1) << CAN_TXBTO_TO29_Pos) /* (CAN_TXBTO) Transmission Occurred 29 Mask */ 1940 #define CAN_TXBTO_TO29(value) (CAN_TXBTO_TO29_Msk & (_UINT32_(value) << CAN_TXBTO_TO29_Pos)) /* Assignment of value for TO29 in the CAN_TXBTO register */ 1941 #define CAN_TXBTO_TO30_Pos _UINT32_(30) /* (CAN_TXBTO) Transmission Occurred 30 Position */ 1942 #define CAN_TXBTO_TO30_Msk (_UINT32_(0x1) << CAN_TXBTO_TO30_Pos) /* (CAN_TXBTO) Transmission Occurred 30 Mask */ 1943 #define CAN_TXBTO_TO30(value) (CAN_TXBTO_TO30_Msk & (_UINT32_(value) << CAN_TXBTO_TO30_Pos)) /* Assignment of value for TO30 in the CAN_TXBTO register */ 1944 #define CAN_TXBTO_TO31_Pos _UINT32_(31) /* (CAN_TXBTO) Transmission Occurred 31 Position */ 1945 #define CAN_TXBTO_TO31_Msk (_UINT32_(0x1) << CAN_TXBTO_TO31_Pos) /* (CAN_TXBTO) Transmission Occurred 31 Mask */ 1946 #define CAN_TXBTO_TO31(value) (CAN_TXBTO_TO31_Msk & (_UINT32_(value) << CAN_TXBTO_TO31_Pos)) /* Assignment of value for TO31 in the CAN_TXBTO register */ 1947 #define CAN_TXBTO_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTO) Register Mask */ 1948 1949 #define CAN_TXBTO_TO_Pos _UINT32_(0) /* (CAN_TXBTO Position) Transmission Occurred 3x */ 1950 #define CAN_TXBTO_TO_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTO_TO_Pos) /* (CAN_TXBTO Mask) TO */ 1951 #define CAN_TXBTO_TO(value) (CAN_TXBTO_TO_Msk & (_UINT32_(value) << CAN_TXBTO_TO_Pos)) 1952 1953 /* -------- CAN_TXBCF : (CAN Offset: 0xDC) ( R/ 32) Tx Buffer Cancellation Finished -------- */ 1954 #define CAN_TXBCF_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Reset Value */ 1955 1956 #define CAN_TXBCF_CF0_Pos _UINT32_(0) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Position */ 1957 #define CAN_TXBCF_CF0_Msk (_UINT32_(0x1) << CAN_TXBCF_CF0_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Mask */ 1958 #define CAN_TXBCF_CF0(value) (CAN_TXBCF_CF0_Msk & (_UINT32_(value) << CAN_TXBCF_CF0_Pos)) /* Assignment of value for CF0 in the CAN_TXBCF register */ 1959 #define CAN_TXBCF_CF1_Pos _UINT32_(1) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Position */ 1960 #define CAN_TXBCF_CF1_Msk (_UINT32_(0x1) << CAN_TXBCF_CF1_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Mask */ 1961 #define CAN_TXBCF_CF1(value) (CAN_TXBCF_CF1_Msk & (_UINT32_(value) << CAN_TXBCF_CF1_Pos)) /* Assignment of value for CF1 in the CAN_TXBCF register */ 1962 #define CAN_TXBCF_CF2_Pos _UINT32_(2) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Position */ 1963 #define CAN_TXBCF_CF2_Msk (_UINT32_(0x1) << CAN_TXBCF_CF2_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Mask */ 1964 #define CAN_TXBCF_CF2(value) (CAN_TXBCF_CF2_Msk & (_UINT32_(value) << CAN_TXBCF_CF2_Pos)) /* Assignment of value for CF2 in the CAN_TXBCF register */ 1965 #define CAN_TXBCF_CF3_Pos _UINT32_(3) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Position */ 1966 #define CAN_TXBCF_CF3_Msk (_UINT32_(0x1) << CAN_TXBCF_CF3_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Mask */ 1967 #define CAN_TXBCF_CF3(value) (CAN_TXBCF_CF3_Msk & (_UINT32_(value) << CAN_TXBCF_CF3_Pos)) /* Assignment of value for CF3 in the CAN_TXBCF register */ 1968 #define CAN_TXBCF_CF4_Pos _UINT32_(4) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Position */ 1969 #define CAN_TXBCF_CF4_Msk (_UINT32_(0x1) << CAN_TXBCF_CF4_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Mask */ 1970 #define CAN_TXBCF_CF4(value) (CAN_TXBCF_CF4_Msk & (_UINT32_(value) << CAN_TXBCF_CF4_Pos)) /* Assignment of value for CF4 in the CAN_TXBCF register */ 1971 #define CAN_TXBCF_CF5_Pos _UINT32_(5) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Position */ 1972 #define CAN_TXBCF_CF5_Msk (_UINT32_(0x1) << CAN_TXBCF_CF5_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Mask */ 1973 #define CAN_TXBCF_CF5(value) (CAN_TXBCF_CF5_Msk & (_UINT32_(value) << CAN_TXBCF_CF5_Pos)) /* Assignment of value for CF5 in the CAN_TXBCF register */ 1974 #define CAN_TXBCF_CF6_Pos _UINT32_(6) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Position */ 1975 #define CAN_TXBCF_CF6_Msk (_UINT32_(0x1) << CAN_TXBCF_CF6_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Mask */ 1976 #define CAN_TXBCF_CF6(value) (CAN_TXBCF_CF6_Msk & (_UINT32_(value) << CAN_TXBCF_CF6_Pos)) /* Assignment of value for CF6 in the CAN_TXBCF register */ 1977 #define CAN_TXBCF_CF7_Pos _UINT32_(7) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Position */ 1978 #define CAN_TXBCF_CF7_Msk (_UINT32_(0x1) << CAN_TXBCF_CF7_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Mask */ 1979 #define CAN_TXBCF_CF7(value) (CAN_TXBCF_CF7_Msk & (_UINT32_(value) << CAN_TXBCF_CF7_Pos)) /* Assignment of value for CF7 in the CAN_TXBCF register */ 1980 #define CAN_TXBCF_CF8_Pos _UINT32_(8) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Position */ 1981 #define CAN_TXBCF_CF8_Msk (_UINT32_(0x1) << CAN_TXBCF_CF8_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Mask */ 1982 #define CAN_TXBCF_CF8(value) (CAN_TXBCF_CF8_Msk & (_UINT32_(value) << CAN_TXBCF_CF8_Pos)) /* Assignment of value for CF8 in the CAN_TXBCF register */ 1983 #define CAN_TXBCF_CF9_Pos _UINT32_(9) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Position */ 1984 #define CAN_TXBCF_CF9_Msk (_UINT32_(0x1) << CAN_TXBCF_CF9_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Mask */ 1985 #define CAN_TXBCF_CF9(value) (CAN_TXBCF_CF9_Msk & (_UINT32_(value) << CAN_TXBCF_CF9_Pos)) /* Assignment of value for CF9 in the CAN_TXBCF register */ 1986 #define CAN_TXBCF_CF10_Pos _UINT32_(10) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Position */ 1987 #define CAN_TXBCF_CF10_Msk (_UINT32_(0x1) << CAN_TXBCF_CF10_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Mask */ 1988 #define CAN_TXBCF_CF10(value) (CAN_TXBCF_CF10_Msk & (_UINT32_(value) << CAN_TXBCF_CF10_Pos)) /* Assignment of value for CF10 in the CAN_TXBCF register */ 1989 #define CAN_TXBCF_CF11_Pos _UINT32_(11) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Position */ 1990 #define CAN_TXBCF_CF11_Msk (_UINT32_(0x1) << CAN_TXBCF_CF11_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Mask */ 1991 #define CAN_TXBCF_CF11(value) (CAN_TXBCF_CF11_Msk & (_UINT32_(value) << CAN_TXBCF_CF11_Pos)) /* Assignment of value for CF11 in the CAN_TXBCF register */ 1992 #define CAN_TXBCF_CF12_Pos _UINT32_(12) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Position */ 1993 #define CAN_TXBCF_CF12_Msk (_UINT32_(0x1) << CAN_TXBCF_CF12_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Mask */ 1994 #define CAN_TXBCF_CF12(value) (CAN_TXBCF_CF12_Msk & (_UINT32_(value) << CAN_TXBCF_CF12_Pos)) /* Assignment of value for CF12 in the CAN_TXBCF register */ 1995 #define CAN_TXBCF_CF13_Pos _UINT32_(13) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Position */ 1996 #define CAN_TXBCF_CF13_Msk (_UINT32_(0x1) << CAN_TXBCF_CF13_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Mask */ 1997 #define CAN_TXBCF_CF13(value) (CAN_TXBCF_CF13_Msk & (_UINT32_(value) << CAN_TXBCF_CF13_Pos)) /* Assignment of value for CF13 in the CAN_TXBCF register */ 1998 #define CAN_TXBCF_CF14_Pos _UINT32_(14) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Position */ 1999 #define CAN_TXBCF_CF14_Msk (_UINT32_(0x1) << CAN_TXBCF_CF14_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Mask */ 2000 #define CAN_TXBCF_CF14(value) (CAN_TXBCF_CF14_Msk & (_UINT32_(value) << CAN_TXBCF_CF14_Pos)) /* Assignment of value for CF14 in the CAN_TXBCF register */ 2001 #define CAN_TXBCF_CF15_Pos _UINT32_(15) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Position */ 2002 #define CAN_TXBCF_CF15_Msk (_UINT32_(0x1) << CAN_TXBCF_CF15_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Mask */ 2003 #define CAN_TXBCF_CF15(value) (CAN_TXBCF_CF15_Msk & (_UINT32_(value) << CAN_TXBCF_CF15_Pos)) /* Assignment of value for CF15 in the CAN_TXBCF register */ 2004 #define CAN_TXBCF_CF16_Pos _UINT32_(16) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Position */ 2005 #define CAN_TXBCF_CF16_Msk (_UINT32_(0x1) << CAN_TXBCF_CF16_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Mask */ 2006 #define CAN_TXBCF_CF16(value) (CAN_TXBCF_CF16_Msk & (_UINT32_(value) << CAN_TXBCF_CF16_Pos)) /* Assignment of value for CF16 in the CAN_TXBCF register */ 2007 #define CAN_TXBCF_CF17_Pos _UINT32_(17) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Position */ 2008 #define CAN_TXBCF_CF17_Msk (_UINT32_(0x1) << CAN_TXBCF_CF17_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Mask */ 2009 #define CAN_TXBCF_CF17(value) (CAN_TXBCF_CF17_Msk & (_UINT32_(value) << CAN_TXBCF_CF17_Pos)) /* Assignment of value for CF17 in the CAN_TXBCF register */ 2010 #define CAN_TXBCF_CF18_Pos _UINT32_(18) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Position */ 2011 #define CAN_TXBCF_CF18_Msk (_UINT32_(0x1) << CAN_TXBCF_CF18_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Mask */ 2012 #define CAN_TXBCF_CF18(value) (CAN_TXBCF_CF18_Msk & (_UINT32_(value) << CAN_TXBCF_CF18_Pos)) /* Assignment of value for CF18 in the CAN_TXBCF register */ 2013 #define CAN_TXBCF_CF19_Pos _UINT32_(19) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Position */ 2014 #define CAN_TXBCF_CF19_Msk (_UINT32_(0x1) << CAN_TXBCF_CF19_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Mask */ 2015 #define CAN_TXBCF_CF19(value) (CAN_TXBCF_CF19_Msk & (_UINT32_(value) << CAN_TXBCF_CF19_Pos)) /* Assignment of value for CF19 in the CAN_TXBCF register */ 2016 #define CAN_TXBCF_CF20_Pos _UINT32_(20) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Position */ 2017 #define CAN_TXBCF_CF20_Msk (_UINT32_(0x1) << CAN_TXBCF_CF20_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Mask */ 2018 #define CAN_TXBCF_CF20(value) (CAN_TXBCF_CF20_Msk & (_UINT32_(value) << CAN_TXBCF_CF20_Pos)) /* Assignment of value for CF20 in the CAN_TXBCF register */ 2019 #define CAN_TXBCF_CF21_Pos _UINT32_(21) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Position */ 2020 #define CAN_TXBCF_CF21_Msk (_UINT32_(0x1) << CAN_TXBCF_CF21_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Mask */ 2021 #define CAN_TXBCF_CF21(value) (CAN_TXBCF_CF21_Msk & (_UINT32_(value) << CAN_TXBCF_CF21_Pos)) /* Assignment of value for CF21 in the CAN_TXBCF register */ 2022 #define CAN_TXBCF_CF22_Pos _UINT32_(22) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Position */ 2023 #define CAN_TXBCF_CF22_Msk (_UINT32_(0x1) << CAN_TXBCF_CF22_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Mask */ 2024 #define CAN_TXBCF_CF22(value) (CAN_TXBCF_CF22_Msk & (_UINT32_(value) << CAN_TXBCF_CF22_Pos)) /* Assignment of value for CF22 in the CAN_TXBCF register */ 2025 #define CAN_TXBCF_CF23_Pos _UINT32_(23) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Position */ 2026 #define CAN_TXBCF_CF23_Msk (_UINT32_(0x1) << CAN_TXBCF_CF23_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Mask */ 2027 #define CAN_TXBCF_CF23(value) (CAN_TXBCF_CF23_Msk & (_UINT32_(value) << CAN_TXBCF_CF23_Pos)) /* Assignment of value for CF23 in the CAN_TXBCF register */ 2028 #define CAN_TXBCF_CF24_Pos _UINT32_(24) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Position */ 2029 #define CAN_TXBCF_CF24_Msk (_UINT32_(0x1) << CAN_TXBCF_CF24_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Mask */ 2030 #define CAN_TXBCF_CF24(value) (CAN_TXBCF_CF24_Msk & (_UINT32_(value) << CAN_TXBCF_CF24_Pos)) /* Assignment of value for CF24 in the CAN_TXBCF register */ 2031 #define CAN_TXBCF_CF25_Pos _UINT32_(25) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Position */ 2032 #define CAN_TXBCF_CF25_Msk (_UINT32_(0x1) << CAN_TXBCF_CF25_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Mask */ 2033 #define CAN_TXBCF_CF25(value) (CAN_TXBCF_CF25_Msk & (_UINT32_(value) << CAN_TXBCF_CF25_Pos)) /* Assignment of value for CF25 in the CAN_TXBCF register */ 2034 #define CAN_TXBCF_CF26_Pos _UINT32_(26) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Position */ 2035 #define CAN_TXBCF_CF26_Msk (_UINT32_(0x1) << CAN_TXBCF_CF26_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Mask */ 2036 #define CAN_TXBCF_CF26(value) (CAN_TXBCF_CF26_Msk & (_UINT32_(value) << CAN_TXBCF_CF26_Pos)) /* Assignment of value for CF26 in the CAN_TXBCF register */ 2037 #define CAN_TXBCF_CF27_Pos _UINT32_(27) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Position */ 2038 #define CAN_TXBCF_CF27_Msk (_UINT32_(0x1) << CAN_TXBCF_CF27_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Mask */ 2039 #define CAN_TXBCF_CF27(value) (CAN_TXBCF_CF27_Msk & (_UINT32_(value) << CAN_TXBCF_CF27_Pos)) /* Assignment of value for CF27 in the CAN_TXBCF register */ 2040 #define CAN_TXBCF_CF28_Pos _UINT32_(28) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Position */ 2041 #define CAN_TXBCF_CF28_Msk (_UINT32_(0x1) << CAN_TXBCF_CF28_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Mask */ 2042 #define CAN_TXBCF_CF28(value) (CAN_TXBCF_CF28_Msk & (_UINT32_(value) << CAN_TXBCF_CF28_Pos)) /* Assignment of value for CF28 in the CAN_TXBCF register */ 2043 #define CAN_TXBCF_CF29_Pos _UINT32_(29) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Position */ 2044 #define CAN_TXBCF_CF29_Msk (_UINT32_(0x1) << CAN_TXBCF_CF29_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Mask */ 2045 #define CAN_TXBCF_CF29(value) (CAN_TXBCF_CF29_Msk & (_UINT32_(value) << CAN_TXBCF_CF29_Pos)) /* Assignment of value for CF29 in the CAN_TXBCF register */ 2046 #define CAN_TXBCF_CF30_Pos _UINT32_(30) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Position */ 2047 #define CAN_TXBCF_CF30_Msk (_UINT32_(0x1) << CAN_TXBCF_CF30_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Mask */ 2048 #define CAN_TXBCF_CF30(value) (CAN_TXBCF_CF30_Msk & (_UINT32_(value) << CAN_TXBCF_CF30_Pos)) /* Assignment of value for CF30 in the CAN_TXBCF register */ 2049 #define CAN_TXBCF_CF31_Pos _UINT32_(31) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Position */ 2050 #define CAN_TXBCF_CF31_Msk (_UINT32_(0x1) << CAN_TXBCF_CF31_Pos) /* (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Mask */ 2051 #define CAN_TXBCF_CF31(value) (CAN_TXBCF_CF31_Msk & (_UINT32_(value) << CAN_TXBCF_CF31_Pos)) /* Assignment of value for CF31 in the CAN_TXBCF register */ 2052 #define CAN_TXBCF_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCF) Register Mask */ 2053 2054 #define CAN_TXBCF_CF_Pos _UINT32_(0) /* (CAN_TXBCF Position) Tx Buffer Cancellation Finished 3x */ 2055 #define CAN_TXBCF_CF_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCF_CF_Pos) /* (CAN_TXBCF Mask) CF */ 2056 #define CAN_TXBCF_CF(value) (CAN_TXBCF_CF_Msk & (_UINT32_(value) << CAN_TXBCF_CF_Pos)) 2057 2058 /* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ 2059 #define CAN_TXBTIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Reset Value */ 2060 2061 #define CAN_TXBTIE_TIE0_Pos _UINT32_(0) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Position */ 2062 #define CAN_TXBTIE_TIE0_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE0_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 0 Mask */ 2063 #define CAN_TXBTIE_TIE0(value) (CAN_TXBTIE_TIE0_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE0_Pos)) /* Assignment of value for TIE0 in the CAN_TXBTIE register */ 2064 #define CAN_TXBTIE_TIE1_Pos _UINT32_(1) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Position */ 2065 #define CAN_TXBTIE_TIE1_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE1_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 1 Mask */ 2066 #define CAN_TXBTIE_TIE1(value) (CAN_TXBTIE_TIE1_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE1_Pos)) /* Assignment of value for TIE1 in the CAN_TXBTIE register */ 2067 #define CAN_TXBTIE_TIE2_Pos _UINT32_(2) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Position */ 2068 #define CAN_TXBTIE_TIE2_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE2_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 2 Mask */ 2069 #define CAN_TXBTIE_TIE2(value) (CAN_TXBTIE_TIE2_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE2_Pos)) /* Assignment of value for TIE2 in the CAN_TXBTIE register */ 2070 #define CAN_TXBTIE_TIE3_Pos _UINT32_(3) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Position */ 2071 #define CAN_TXBTIE_TIE3_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE3_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 3 Mask */ 2072 #define CAN_TXBTIE_TIE3(value) (CAN_TXBTIE_TIE3_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE3_Pos)) /* Assignment of value for TIE3 in the CAN_TXBTIE register */ 2073 #define CAN_TXBTIE_TIE4_Pos _UINT32_(4) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Position */ 2074 #define CAN_TXBTIE_TIE4_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE4_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 4 Mask */ 2075 #define CAN_TXBTIE_TIE4(value) (CAN_TXBTIE_TIE4_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE4_Pos)) /* Assignment of value for TIE4 in the CAN_TXBTIE register */ 2076 #define CAN_TXBTIE_TIE5_Pos _UINT32_(5) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Position */ 2077 #define CAN_TXBTIE_TIE5_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE5_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 5 Mask */ 2078 #define CAN_TXBTIE_TIE5(value) (CAN_TXBTIE_TIE5_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE5_Pos)) /* Assignment of value for TIE5 in the CAN_TXBTIE register */ 2079 #define CAN_TXBTIE_TIE6_Pos _UINT32_(6) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Position */ 2080 #define CAN_TXBTIE_TIE6_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE6_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 6 Mask */ 2081 #define CAN_TXBTIE_TIE6(value) (CAN_TXBTIE_TIE6_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE6_Pos)) /* Assignment of value for TIE6 in the CAN_TXBTIE register */ 2082 #define CAN_TXBTIE_TIE7_Pos _UINT32_(7) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Position */ 2083 #define CAN_TXBTIE_TIE7_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE7_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 7 Mask */ 2084 #define CAN_TXBTIE_TIE7(value) (CAN_TXBTIE_TIE7_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE7_Pos)) /* Assignment of value for TIE7 in the CAN_TXBTIE register */ 2085 #define CAN_TXBTIE_TIE8_Pos _UINT32_(8) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Position */ 2086 #define CAN_TXBTIE_TIE8_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE8_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 8 Mask */ 2087 #define CAN_TXBTIE_TIE8(value) (CAN_TXBTIE_TIE8_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE8_Pos)) /* Assignment of value for TIE8 in the CAN_TXBTIE register */ 2088 #define CAN_TXBTIE_TIE9_Pos _UINT32_(9) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Position */ 2089 #define CAN_TXBTIE_TIE9_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE9_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 9 Mask */ 2090 #define CAN_TXBTIE_TIE9(value) (CAN_TXBTIE_TIE9_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE9_Pos)) /* Assignment of value for TIE9 in the CAN_TXBTIE register */ 2091 #define CAN_TXBTIE_TIE10_Pos _UINT32_(10) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Position */ 2092 #define CAN_TXBTIE_TIE10_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE10_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 10 Mask */ 2093 #define CAN_TXBTIE_TIE10(value) (CAN_TXBTIE_TIE10_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE10_Pos)) /* Assignment of value for TIE10 in the CAN_TXBTIE register */ 2094 #define CAN_TXBTIE_TIE11_Pos _UINT32_(11) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Position */ 2095 #define CAN_TXBTIE_TIE11_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE11_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 11 Mask */ 2096 #define CAN_TXBTIE_TIE11(value) (CAN_TXBTIE_TIE11_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE11_Pos)) /* Assignment of value for TIE11 in the CAN_TXBTIE register */ 2097 #define CAN_TXBTIE_TIE12_Pos _UINT32_(12) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Position */ 2098 #define CAN_TXBTIE_TIE12_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE12_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 12 Mask */ 2099 #define CAN_TXBTIE_TIE12(value) (CAN_TXBTIE_TIE12_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE12_Pos)) /* Assignment of value for TIE12 in the CAN_TXBTIE register */ 2100 #define CAN_TXBTIE_TIE13_Pos _UINT32_(13) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Position */ 2101 #define CAN_TXBTIE_TIE13_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE13_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 13 Mask */ 2102 #define CAN_TXBTIE_TIE13(value) (CAN_TXBTIE_TIE13_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE13_Pos)) /* Assignment of value for TIE13 in the CAN_TXBTIE register */ 2103 #define CAN_TXBTIE_TIE14_Pos _UINT32_(14) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Position */ 2104 #define CAN_TXBTIE_TIE14_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE14_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 14 Mask */ 2105 #define CAN_TXBTIE_TIE14(value) (CAN_TXBTIE_TIE14_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE14_Pos)) /* Assignment of value for TIE14 in the CAN_TXBTIE register */ 2106 #define CAN_TXBTIE_TIE15_Pos _UINT32_(15) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Position */ 2107 #define CAN_TXBTIE_TIE15_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE15_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 15 Mask */ 2108 #define CAN_TXBTIE_TIE15(value) (CAN_TXBTIE_TIE15_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE15_Pos)) /* Assignment of value for TIE15 in the CAN_TXBTIE register */ 2109 #define CAN_TXBTIE_TIE16_Pos _UINT32_(16) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Position */ 2110 #define CAN_TXBTIE_TIE16_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE16_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 16 Mask */ 2111 #define CAN_TXBTIE_TIE16(value) (CAN_TXBTIE_TIE16_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE16_Pos)) /* Assignment of value for TIE16 in the CAN_TXBTIE register */ 2112 #define CAN_TXBTIE_TIE17_Pos _UINT32_(17) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Position */ 2113 #define CAN_TXBTIE_TIE17_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE17_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 17 Mask */ 2114 #define CAN_TXBTIE_TIE17(value) (CAN_TXBTIE_TIE17_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE17_Pos)) /* Assignment of value for TIE17 in the CAN_TXBTIE register */ 2115 #define CAN_TXBTIE_TIE18_Pos _UINT32_(18) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Position */ 2116 #define CAN_TXBTIE_TIE18_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE18_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 18 Mask */ 2117 #define CAN_TXBTIE_TIE18(value) (CAN_TXBTIE_TIE18_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE18_Pos)) /* Assignment of value for TIE18 in the CAN_TXBTIE register */ 2118 #define CAN_TXBTIE_TIE19_Pos _UINT32_(19) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Position */ 2119 #define CAN_TXBTIE_TIE19_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE19_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 19 Mask */ 2120 #define CAN_TXBTIE_TIE19(value) (CAN_TXBTIE_TIE19_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE19_Pos)) /* Assignment of value for TIE19 in the CAN_TXBTIE register */ 2121 #define CAN_TXBTIE_TIE20_Pos _UINT32_(20) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Position */ 2122 #define CAN_TXBTIE_TIE20_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE20_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 20 Mask */ 2123 #define CAN_TXBTIE_TIE20(value) (CAN_TXBTIE_TIE20_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE20_Pos)) /* Assignment of value for TIE20 in the CAN_TXBTIE register */ 2124 #define CAN_TXBTIE_TIE21_Pos _UINT32_(21) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Position */ 2125 #define CAN_TXBTIE_TIE21_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE21_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 21 Mask */ 2126 #define CAN_TXBTIE_TIE21(value) (CAN_TXBTIE_TIE21_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE21_Pos)) /* Assignment of value for TIE21 in the CAN_TXBTIE register */ 2127 #define CAN_TXBTIE_TIE22_Pos _UINT32_(22) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Position */ 2128 #define CAN_TXBTIE_TIE22_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE22_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 22 Mask */ 2129 #define CAN_TXBTIE_TIE22(value) (CAN_TXBTIE_TIE22_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE22_Pos)) /* Assignment of value for TIE22 in the CAN_TXBTIE register */ 2130 #define CAN_TXBTIE_TIE23_Pos _UINT32_(23) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Position */ 2131 #define CAN_TXBTIE_TIE23_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE23_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 23 Mask */ 2132 #define CAN_TXBTIE_TIE23(value) (CAN_TXBTIE_TIE23_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE23_Pos)) /* Assignment of value for TIE23 in the CAN_TXBTIE register */ 2133 #define CAN_TXBTIE_TIE24_Pos _UINT32_(24) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Position */ 2134 #define CAN_TXBTIE_TIE24_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE24_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 24 Mask */ 2135 #define CAN_TXBTIE_TIE24(value) (CAN_TXBTIE_TIE24_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE24_Pos)) /* Assignment of value for TIE24 in the CAN_TXBTIE register */ 2136 #define CAN_TXBTIE_TIE25_Pos _UINT32_(25) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Position */ 2137 #define CAN_TXBTIE_TIE25_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE25_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 25 Mask */ 2138 #define CAN_TXBTIE_TIE25(value) (CAN_TXBTIE_TIE25_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE25_Pos)) /* Assignment of value for TIE25 in the CAN_TXBTIE register */ 2139 #define CAN_TXBTIE_TIE26_Pos _UINT32_(26) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Position */ 2140 #define CAN_TXBTIE_TIE26_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE26_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 26 Mask */ 2141 #define CAN_TXBTIE_TIE26(value) (CAN_TXBTIE_TIE26_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE26_Pos)) /* Assignment of value for TIE26 in the CAN_TXBTIE register */ 2142 #define CAN_TXBTIE_TIE27_Pos _UINT32_(27) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Position */ 2143 #define CAN_TXBTIE_TIE27_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE27_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 27 Mask */ 2144 #define CAN_TXBTIE_TIE27(value) (CAN_TXBTIE_TIE27_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE27_Pos)) /* Assignment of value for TIE27 in the CAN_TXBTIE register */ 2145 #define CAN_TXBTIE_TIE28_Pos _UINT32_(28) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Position */ 2146 #define CAN_TXBTIE_TIE28_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE28_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 28 Mask */ 2147 #define CAN_TXBTIE_TIE28(value) (CAN_TXBTIE_TIE28_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE28_Pos)) /* Assignment of value for TIE28 in the CAN_TXBTIE register */ 2148 #define CAN_TXBTIE_TIE29_Pos _UINT32_(29) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Position */ 2149 #define CAN_TXBTIE_TIE29_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE29_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 29 Mask */ 2150 #define CAN_TXBTIE_TIE29(value) (CAN_TXBTIE_TIE29_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE29_Pos)) /* Assignment of value for TIE29 in the CAN_TXBTIE register */ 2151 #define CAN_TXBTIE_TIE30_Pos _UINT32_(30) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Position */ 2152 #define CAN_TXBTIE_TIE30_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE30_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 30 Mask */ 2153 #define CAN_TXBTIE_TIE30(value) (CAN_TXBTIE_TIE30_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE30_Pos)) /* Assignment of value for TIE30 in the CAN_TXBTIE register */ 2154 #define CAN_TXBTIE_TIE31_Pos _UINT32_(31) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Position */ 2155 #define CAN_TXBTIE_TIE31_Msk (_UINT32_(0x1) << CAN_TXBTIE_TIE31_Pos) /* (CAN_TXBTIE) Transmission Interrupt Enable 31 Mask */ 2156 #define CAN_TXBTIE_TIE31(value) (CAN_TXBTIE_TIE31_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE31_Pos)) /* Assignment of value for TIE31 in the CAN_TXBTIE register */ 2157 #define CAN_TXBTIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBTIE) Register Mask */ 2158 2159 #define CAN_TXBTIE_TIE_Pos _UINT32_(0) /* (CAN_TXBTIE Position) Transmission Interrupt Enable 3x */ 2160 #define CAN_TXBTIE_TIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBTIE_TIE_Pos) /* (CAN_TXBTIE Mask) TIE */ 2161 #define CAN_TXBTIE_TIE(value) (CAN_TXBTIE_TIE_Msk & (_UINT32_(value) << CAN_TXBTIE_TIE_Pos)) 2162 2163 /* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ 2164 #define CAN_TXBCIE_RESETVALUE _UINT32_(0x00) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Reset Value */ 2165 2166 #define CAN_TXBCIE_CFIE0_Pos _UINT32_(0) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Position */ 2167 #define CAN_TXBCIE_CFIE0_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE0_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Mask */ 2168 #define CAN_TXBCIE_CFIE0(value) (CAN_TXBCIE_CFIE0_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE0_Pos)) /* Assignment of value for CFIE0 in the CAN_TXBCIE register */ 2169 #define CAN_TXBCIE_CFIE1_Pos _UINT32_(1) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Position */ 2170 #define CAN_TXBCIE_CFIE1_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE1_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Mask */ 2171 #define CAN_TXBCIE_CFIE1(value) (CAN_TXBCIE_CFIE1_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE1_Pos)) /* Assignment of value for CFIE1 in the CAN_TXBCIE register */ 2172 #define CAN_TXBCIE_CFIE2_Pos _UINT32_(2) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Position */ 2173 #define CAN_TXBCIE_CFIE2_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE2_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Mask */ 2174 #define CAN_TXBCIE_CFIE2(value) (CAN_TXBCIE_CFIE2_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE2_Pos)) /* Assignment of value for CFIE2 in the CAN_TXBCIE register */ 2175 #define CAN_TXBCIE_CFIE3_Pos _UINT32_(3) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Position */ 2176 #define CAN_TXBCIE_CFIE3_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE3_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Mask */ 2177 #define CAN_TXBCIE_CFIE3(value) (CAN_TXBCIE_CFIE3_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE3_Pos)) /* Assignment of value for CFIE3 in the CAN_TXBCIE register */ 2178 #define CAN_TXBCIE_CFIE4_Pos _UINT32_(4) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Position */ 2179 #define CAN_TXBCIE_CFIE4_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE4_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Mask */ 2180 #define CAN_TXBCIE_CFIE4(value) (CAN_TXBCIE_CFIE4_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE4_Pos)) /* Assignment of value for CFIE4 in the CAN_TXBCIE register */ 2181 #define CAN_TXBCIE_CFIE5_Pos _UINT32_(5) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Position */ 2182 #define CAN_TXBCIE_CFIE5_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE5_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Mask */ 2183 #define CAN_TXBCIE_CFIE5(value) (CAN_TXBCIE_CFIE5_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE5_Pos)) /* Assignment of value for CFIE5 in the CAN_TXBCIE register */ 2184 #define CAN_TXBCIE_CFIE6_Pos _UINT32_(6) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Position */ 2185 #define CAN_TXBCIE_CFIE6_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE6_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Mask */ 2186 #define CAN_TXBCIE_CFIE6(value) (CAN_TXBCIE_CFIE6_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE6_Pos)) /* Assignment of value for CFIE6 in the CAN_TXBCIE register */ 2187 #define CAN_TXBCIE_CFIE7_Pos _UINT32_(7) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Position */ 2188 #define CAN_TXBCIE_CFIE7_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE7_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Mask */ 2189 #define CAN_TXBCIE_CFIE7(value) (CAN_TXBCIE_CFIE7_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE7_Pos)) /* Assignment of value for CFIE7 in the CAN_TXBCIE register */ 2190 #define CAN_TXBCIE_CFIE8_Pos _UINT32_(8) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Position */ 2191 #define CAN_TXBCIE_CFIE8_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE8_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Mask */ 2192 #define CAN_TXBCIE_CFIE8(value) (CAN_TXBCIE_CFIE8_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE8_Pos)) /* Assignment of value for CFIE8 in the CAN_TXBCIE register */ 2193 #define CAN_TXBCIE_CFIE9_Pos _UINT32_(9) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Position */ 2194 #define CAN_TXBCIE_CFIE9_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE9_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Mask */ 2195 #define CAN_TXBCIE_CFIE9(value) (CAN_TXBCIE_CFIE9_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE9_Pos)) /* Assignment of value for CFIE9 in the CAN_TXBCIE register */ 2196 #define CAN_TXBCIE_CFIE10_Pos _UINT32_(10) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Position */ 2197 #define CAN_TXBCIE_CFIE10_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE10_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Mask */ 2198 #define CAN_TXBCIE_CFIE10(value) (CAN_TXBCIE_CFIE10_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE10_Pos)) /* Assignment of value for CFIE10 in the CAN_TXBCIE register */ 2199 #define CAN_TXBCIE_CFIE11_Pos _UINT32_(11) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Position */ 2200 #define CAN_TXBCIE_CFIE11_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE11_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Mask */ 2201 #define CAN_TXBCIE_CFIE11(value) (CAN_TXBCIE_CFIE11_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE11_Pos)) /* Assignment of value for CFIE11 in the CAN_TXBCIE register */ 2202 #define CAN_TXBCIE_CFIE12_Pos _UINT32_(12) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Position */ 2203 #define CAN_TXBCIE_CFIE12_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE12_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Mask */ 2204 #define CAN_TXBCIE_CFIE12(value) (CAN_TXBCIE_CFIE12_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE12_Pos)) /* Assignment of value for CFIE12 in the CAN_TXBCIE register */ 2205 #define CAN_TXBCIE_CFIE13_Pos _UINT32_(13) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Position */ 2206 #define CAN_TXBCIE_CFIE13_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE13_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Mask */ 2207 #define CAN_TXBCIE_CFIE13(value) (CAN_TXBCIE_CFIE13_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE13_Pos)) /* Assignment of value for CFIE13 in the CAN_TXBCIE register */ 2208 #define CAN_TXBCIE_CFIE14_Pos _UINT32_(14) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Position */ 2209 #define CAN_TXBCIE_CFIE14_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE14_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Mask */ 2210 #define CAN_TXBCIE_CFIE14(value) (CAN_TXBCIE_CFIE14_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE14_Pos)) /* Assignment of value for CFIE14 in the CAN_TXBCIE register */ 2211 #define CAN_TXBCIE_CFIE15_Pos _UINT32_(15) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Position */ 2212 #define CAN_TXBCIE_CFIE15_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE15_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Mask */ 2213 #define CAN_TXBCIE_CFIE15(value) (CAN_TXBCIE_CFIE15_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE15_Pos)) /* Assignment of value for CFIE15 in the CAN_TXBCIE register */ 2214 #define CAN_TXBCIE_CFIE16_Pos _UINT32_(16) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Position */ 2215 #define CAN_TXBCIE_CFIE16_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE16_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Mask */ 2216 #define CAN_TXBCIE_CFIE16(value) (CAN_TXBCIE_CFIE16_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE16_Pos)) /* Assignment of value for CFIE16 in the CAN_TXBCIE register */ 2217 #define CAN_TXBCIE_CFIE17_Pos _UINT32_(17) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Position */ 2218 #define CAN_TXBCIE_CFIE17_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE17_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Mask */ 2219 #define CAN_TXBCIE_CFIE17(value) (CAN_TXBCIE_CFIE17_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE17_Pos)) /* Assignment of value for CFIE17 in the CAN_TXBCIE register */ 2220 #define CAN_TXBCIE_CFIE18_Pos _UINT32_(18) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Position */ 2221 #define CAN_TXBCIE_CFIE18_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE18_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Mask */ 2222 #define CAN_TXBCIE_CFIE18(value) (CAN_TXBCIE_CFIE18_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE18_Pos)) /* Assignment of value for CFIE18 in the CAN_TXBCIE register */ 2223 #define CAN_TXBCIE_CFIE19_Pos _UINT32_(19) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Position */ 2224 #define CAN_TXBCIE_CFIE19_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE19_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Mask */ 2225 #define CAN_TXBCIE_CFIE19(value) (CAN_TXBCIE_CFIE19_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE19_Pos)) /* Assignment of value for CFIE19 in the CAN_TXBCIE register */ 2226 #define CAN_TXBCIE_CFIE20_Pos _UINT32_(20) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Position */ 2227 #define CAN_TXBCIE_CFIE20_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE20_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Mask */ 2228 #define CAN_TXBCIE_CFIE20(value) (CAN_TXBCIE_CFIE20_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE20_Pos)) /* Assignment of value for CFIE20 in the CAN_TXBCIE register */ 2229 #define CAN_TXBCIE_CFIE21_Pos _UINT32_(21) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Position */ 2230 #define CAN_TXBCIE_CFIE21_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE21_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Mask */ 2231 #define CAN_TXBCIE_CFIE21(value) (CAN_TXBCIE_CFIE21_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE21_Pos)) /* Assignment of value for CFIE21 in the CAN_TXBCIE register */ 2232 #define CAN_TXBCIE_CFIE22_Pos _UINT32_(22) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Position */ 2233 #define CAN_TXBCIE_CFIE22_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE22_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Mask */ 2234 #define CAN_TXBCIE_CFIE22(value) (CAN_TXBCIE_CFIE22_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE22_Pos)) /* Assignment of value for CFIE22 in the CAN_TXBCIE register */ 2235 #define CAN_TXBCIE_CFIE23_Pos _UINT32_(23) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Position */ 2236 #define CAN_TXBCIE_CFIE23_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE23_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Mask */ 2237 #define CAN_TXBCIE_CFIE23(value) (CAN_TXBCIE_CFIE23_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE23_Pos)) /* Assignment of value for CFIE23 in the CAN_TXBCIE register */ 2238 #define CAN_TXBCIE_CFIE24_Pos _UINT32_(24) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Position */ 2239 #define CAN_TXBCIE_CFIE24_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE24_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Mask */ 2240 #define CAN_TXBCIE_CFIE24(value) (CAN_TXBCIE_CFIE24_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE24_Pos)) /* Assignment of value for CFIE24 in the CAN_TXBCIE register */ 2241 #define CAN_TXBCIE_CFIE25_Pos _UINT32_(25) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Position */ 2242 #define CAN_TXBCIE_CFIE25_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE25_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Mask */ 2243 #define CAN_TXBCIE_CFIE25(value) (CAN_TXBCIE_CFIE25_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE25_Pos)) /* Assignment of value for CFIE25 in the CAN_TXBCIE register */ 2244 #define CAN_TXBCIE_CFIE26_Pos _UINT32_(26) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Position */ 2245 #define CAN_TXBCIE_CFIE26_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE26_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Mask */ 2246 #define CAN_TXBCIE_CFIE26(value) (CAN_TXBCIE_CFIE26_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE26_Pos)) /* Assignment of value for CFIE26 in the CAN_TXBCIE register */ 2247 #define CAN_TXBCIE_CFIE27_Pos _UINT32_(27) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Position */ 2248 #define CAN_TXBCIE_CFIE27_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE27_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Mask */ 2249 #define CAN_TXBCIE_CFIE27(value) (CAN_TXBCIE_CFIE27_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE27_Pos)) /* Assignment of value for CFIE27 in the CAN_TXBCIE register */ 2250 #define CAN_TXBCIE_CFIE28_Pos _UINT32_(28) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Position */ 2251 #define CAN_TXBCIE_CFIE28_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE28_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Mask */ 2252 #define CAN_TXBCIE_CFIE28(value) (CAN_TXBCIE_CFIE28_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE28_Pos)) /* Assignment of value for CFIE28 in the CAN_TXBCIE register */ 2253 #define CAN_TXBCIE_CFIE29_Pos _UINT32_(29) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Position */ 2254 #define CAN_TXBCIE_CFIE29_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE29_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Mask */ 2255 #define CAN_TXBCIE_CFIE29(value) (CAN_TXBCIE_CFIE29_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE29_Pos)) /* Assignment of value for CFIE29 in the CAN_TXBCIE register */ 2256 #define CAN_TXBCIE_CFIE30_Pos _UINT32_(30) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Position */ 2257 #define CAN_TXBCIE_CFIE30_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE30_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Mask */ 2258 #define CAN_TXBCIE_CFIE30(value) (CAN_TXBCIE_CFIE30_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE30_Pos)) /* Assignment of value for CFIE30 in the CAN_TXBCIE register */ 2259 #define CAN_TXBCIE_CFIE31_Pos _UINT32_(31) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Position */ 2260 #define CAN_TXBCIE_CFIE31_Msk (_UINT32_(0x1) << CAN_TXBCIE_CFIE31_Pos) /* (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Mask */ 2261 #define CAN_TXBCIE_CFIE31(value) (CAN_TXBCIE_CFIE31_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE31_Pos)) /* Assignment of value for CFIE31 in the CAN_TXBCIE register */ 2262 #define CAN_TXBCIE_Msk _UINT32_(0xFFFFFFFF) /* (CAN_TXBCIE) Register Mask */ 2263 2264 #define CAN_TXBCIE_CFIE_Pos _UINT32_(0) /* (CAN_TXBCIE Position) Cancellation Finished Interrupt Enable 3x */ 2265 #define CAN_TXBCIE_CFIE_Msk (_UINT32_(0xFFFFFFFF) << CAN_TXBCIE_CFIE_Pos) /* (CAN_TXBCIE Mask) CFIE */ 2266 #define CAN_TXBCIE_CFIE(value) (CAN_TXBCIE_CFIE_Msk & (_UINT32_(value) << CAN_TXBCIE_CFIE_Pos)) 2267 2268 /* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ 2269 #define CAN_TXEFC_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFC) Tx Event FIFO Configuration Reset Value */ 2270 2271 #define CAN_TXEFC_EFSA_Pos _UINT32_(0) /* (CAN_TXEFC) Event FIFO Start Address Position */ 2272 #define CAN_TXEFC_EFSA_Msk (_UINT32_(0xFFFF) << CAN_TXEFC_EFSA_Pos) /* (CAN_TXEFC) Event FIFO Start Address Mask */ 2273 #define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & (_UINT32_(value) << CAN_TXEFC_EFSA_Pos)) /* Assignment of value for EFSA in the CAN_TXEFC register */ 2274 #define CAN_TXEFC_EFS_Pos _UINT32_(16) /* (CAN_TXEFC) Event FIFO Size Position */ 2275 #define CAN_TXEFC_EFS_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFS_Pos) /* (CAN_TXEFC) Event FIFO Size Mask */ 2276 #define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & (_UINT32_(value) << CAN_TXEFC_EFS_Pos)) /* Assignment of value for EFS in the CAN_TXEFC register */ 2277 #define CAN_TXEFC_EFWM_Pos _UINT32_(24) /* (CAN_TXEFC) Event FIFO Watermark Position */ 2278 #define CAN_TXEFC_EFWM_Msk (_UINT32_(0x3F) << CAN_TXEFC_EFWM_Pos) /* (CAN_TXEFC) Event FIFO Watermark Mask */ 2279 #define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & (_UINT32_(value) << CAN_TXEFC_EFWM_Pos)) /* Assignment of value for EFWM in the CAN_TXEFC register */ 2280 #define CAN_TXEFC_Msk _UINT32_(0x3F3FFFFF) /* (CAN_TXEFC) Register Mask */ 2281 2282 2283 /* -------- CAN_TXEFS : (CAN Offset: 0xF4) ( R/ 32) Tx Event FIFO Status -------- */ 2284 #define CAN_TXEFS_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFS) Tx Event FIFO Status Reset Value */ 2285 2286 #define CAN_TXEFS_EFFL_Pos _UINT32_(0) /* (CAN_TXEFS) Event FIFO Fill Level Position */ 2287 #define CAN_TXEFS_EFFL_Msk (_UINT32_(0x3F) << CAN_TXEFS_EFFL_Pos) /* (CAN_TXEFS) Event FIFO Fill Level Mask */ 2288 #define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & (_UINT32_(value) << CAN_TXEFS_EFFL_Pos)) /* Assignment of value for EFFL in the CAN_TXEFS register */ 2289 #define CAN_TXEFS_EFGI_Pos _UINT32_(8) /* (CAN_TXEFS) Event FIFO Get Index Position */ 2290 #define CAN_TXEFS_EFGI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFGI_Pos) /* (CAN_TXEFS) Event FIFO Get Index Mask */ 2291 #define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & (_UINT32_(value) << CAN_TXEFS_EFGI_Pos)) /* Assignment of value for EFGI in the CAN_TXEFS register */ 2292 #define CAN_TXEFS_EFPI_Pos _UINT32_(16) /* (CAN_TXEFS) Event FIFO Put Index Position */ 2293 #define CAN_TXEFS_EFPI_Msk (_UINT32_(0x1F) << CAN_TXEFS_EFPI_Pos) /* (CAN_TXEFS) Event FIFO Put Index Mask */ 2294 #define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & (_UINT32_(value) << CAN_TXEFS_EFPI_Pos)) /* Assignment of value for EFPI in the CAN_TXEFS register */ 2295 #define CAN_TXEFS_EFF_Pos _UINT32_(24) /* (CAN_TXEFS) Event FIFO Full Position */ 2296 #define CAN_TXEFS_EFF_Msk (_UINT32_(0x1) << CAN_TXEFS_EFF_Pos) /* (CAN_TXEFS) Event FIFO Full Mask */ 2297 #define CAN_TXEFS_EFF(value) (CAN_TXEFS_EFF_Msk & (_UINT32_(value) << CAN_TXEFS_EFF_Pos)) /* Assignment of value for EFF in the CAN_TXEFS register */ 2298 #define CAN_TXEFS_TEFL_Pos _UINT32_(25) /* (CAN_TXEFS) Tx Event FIFO Element Lost Position */ 2299 #define CAN_TXEFS_TEFL_Msk (_UINT32_(0x1) << CAN_TXEFS_TEFL_Pos) /* (CAN_TXEFS) Tx Event FIFO Element Lost Mask */ 2300 #define CAN_TXEFS_TEFL(value) (CAN_TXEFS_TEFL_Msk & (_UINT32_(value) << CAN_TXEFS_TEFL_Pos)) /* Assignment of value for TEFL in the CAN_TXEFS register */ 2301 #define CAN_TXEFS_Msk _UINT32_(0x031F1F3F) /* (CAN_TXEFS) Register Mask */ 2302 2303 2304 /* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ 2305 #define CAN_TXEFA_RESETVALUE _UINT32_(0x00) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Reset Value */ 2306 2307 #define CAN_TXEFA_EFAI_Pos _UINT32_(0) /* (CAN_TXEFA) Event FIFO Acknowledge Index Position */ 2308 #define CAN_TXEFA_EFAI_Msk (_UINT32_(0x1F) << CAN_TXEFA_EFAI_Pos) /* (CAN_TXEFA) Event FIFO Acknowledge Index Mask */ 2309 #define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & (_UINT32_(value) << CAN_TXEFA_EFAI_Pos)) /* Assignment of value for EFAI in the CAN_TXEFA register */ 2310 #define CAN_TXEFA_Msk _UINT32_(0x0000001F) /* (CAN_TXEFA) Register Mask */ 2311 2312 2313 /* CAN register offsets definitions */ 2314 #define CAN_RXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_RXBE_0) Rx Buffer Element 0 Offset */ 2315 #define CAN_RXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_RXBE_1) Rx Buffer Element 1 Offset */ 2316 #define CAN_RXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXBE_DATA) Rx Buffer Element Data Offset */ 2317 #define CAN_RXF0E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ 2318 #define CAN_RXF0E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ 2319 #define CAN_RXF0E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ 2320 #define CAN_RXF1E_0_REG_OFST _UINT32_(0x00) /* (CAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ 2321 #define CAN_RXF1E_1_REG_OFST _UINT32_(0x04) /* (CAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ 2322 #define CAN_RXF1E_DATA_REG_OFST _UINT32_(0x08) /* (CAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ 2323 #define CAN_TXBE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXBE_0) Tx Buffer Element 0 Offset */ 2324 #define CAN_TXBE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXBE_1) Tx Buffer Element 1 Offset */ 2325 #define CAN_TXBE_DATA_REG_OFST _UINT32_(0x08) /* (CAN_TXBE_DATA) Tx Buffer Element Data Offset */ 2326 #define CAN_TXEFE_0_REG_OFST _UINT32_(0x00) /* (CAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ 2327 #define CAN_TXEFE_1_REG_OFST _UINT32_(0x04) /* (CAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ 2328 #define CAN_SIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ 2329 #define CAN_XIDFE_0_REG_OFST _UINT32_(0x00) /* (CAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ 2330 #define CAN_XIDFE_1_REG_OFST _UINT32_(0x04) /* (CAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ 2331 #define CAN_CREL_REG_OFST _UINT32_(0x00) /* (CAN_CREL) Core Release Offset */ 2332 #define CAN_ENDN_REG_OFST _UINT32_(0x04) /* (CAN_ENDN) Endian Offset */ 2333 #define CAN_MRCFG_REG_OFST _UINT32_(0x08) /* (CAN_MRCFG) Message RAM Configuration Offset */ 2334 #define CAN_DBTP_REG_OFST _UINT32_(0x0C) /* (CAN_DBTP) Fast Bit Timing and Prescaler Offset */ 2335 #define CAN_TEST_REG_OFST _UINT32_(0x10) /* (CAN_TEST) Test Offset */ 2336 #define CAN_RWD_REG_OFST _UINT32_(0x14) /* (CAN_RWD) RAM Watchdog Offset */ 2337 #define CAN_CCCR_REG_OFST _UINT32_(0x18) /* (CAN_CCCR) CC Control Offset */ 2338 #define CAN_NBTP_REG_OFST _UINT32_(0x1C) /* (CAN_NBTP) Nominal Bit Timing and Prescaler Offset */ 2339 #define CAN_TSCC_REG_OFST _UINT32_(0x20) /* (CAN_TSCC) Timestamp Counter Configuration Offset */ 2340 #define CAN_TSCV_REG_OFST _UINT32_(0x24) /* (CAN_TSCV) Timestamp Counter Value Offset */ 2341 #define CAN_TOCC_REG_OFST _UINT32_(0x28) /* (CAN_TOCC) Timeout Counter Configuration Offset */ 2342 #define CAN_TOCV_REG_OFST _UINT32_(0x2C) /* (CAN_TOCV) Timeout Counter Value Offset */ 2343 #define CAN_ECR_REG_OFST _UINT32_(0x40) /* (CAN_ECR) Error Counter Offset */ 2344 #define CAN_PSR_REG_OFST _UINT32_(0x44) /* (CAN_PSR) Protocol Status Offset */ 2345 #define CAN_TDCR_REG_OFST _UINT32_(0x48) /* (CAN_TDCR) Extended ID Filter Configuration Offset */ 2346 #define CAN_IR_REG_OFST _UINT32_(0x50) /* (CAN_IR) Interrupt Offset */ 2347 #define CAN_IE_REG_OFST _UINT32_(0x54) /* (CAN_IE) Interrupt Enable Offset */ 2348 #define CAN_ILS_REG_OFST _UINT32_(0x58) /* (CAN_ILS) Interrupt Line Select Offset */ 2349 #define CAN_ILE_REG_OFST _UINT32_(0x5C) /* (CAN_ILE) Interrupt Line Enable Offset */ 2350 #define CAN_GFC_REG_OFST _UINT32_(0x80) /* (CAN_GFC) Global Filter Configuration Offset */ 2351 #define CAN_SIDFC_REG_OFST _UINT32_(0x84) /* (CAN_SIDFC) Standard ID Filter Configuration Offset */ 2352 #define CAN_XIDFC_REG_OFST _UINT32_(0x88) /* (CAN_XIDFC) Extended ID Filter Configuration Offset */ 2353 #define CAN_XIDAM_REG_OFST _UINT32_(0x90) /* (CAN_XIDAM) Extended ID AND Mask Offset */ 2354 #define CAN_HPMS_REG_OFST _UINT32_(0x94) /* (CAN_HPMS) High Priority Message Status Offset */ 2355 #define CAN_NDAT1_REG_OFST _UINT32_(0x98) /* (CAN_NDAT1) New Data 1 Offset */ 2356 #define CAN_NDAT2_REG_OFST _UINT32_(0x9C) /* (CAN_NDAT2) New Data 2 Offset */ 2357 #define CAN_RXF0C_REG_OFST _UINT32_(0xA0) /* (CAN_RXF0C) Rx FIFO 0 Configuration Offset */ 2358 #define CAN_RXF0S_REG_OFST _UINT32_(0xA4) /* (CAN_RXF0S) Rx FIFO 0 Status Offset */ 2359 #define CAN_RXF0A_REG_OFST _UINT32_(0xA8) /* (CAN_RXF0A) Rx FIFO 0 Acknowledge Offset */ 2360 #define CAN_RXBC_REG_OFST _UINT32_(0xAC) /* (CAN_RXBC) Rx Buffer Configuration Offset */ 2361 #define CAN_RXF1C_REG_OFST _UINT32_(0xB0) /* (CAN_RXF1C) Rx FIFO 1 Configuration Offset */ 2362 #define CAN_RXF1S_REG_OFST _UINT32_(0xB4) /* (CAN_RXF1S) Rx FIFO 1 Status Offset */ 2363 #define CAN_RXF1A_REG_OFST _UINT32_(0xB8) /* (CAN_RXF1A) Rx FIFO 1 Acknowledge Offset */ 2364 #define CAN_RXESC_REG_OFST _UINT32_(0xBC) /* (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Offset */ 2365 #define CAN_TXBC_REG_OFST _UINT32_(0xC0) /* (CAN_TXBC) Tx Buffer Configuration Offset */ 2366 #define CAN_TXFQS_REG_OFST _UINT32_(0xC4) /* (CAN_TXFQS) Tx FIFO / Queue Status Offset */ 2367 #define CAN_TXESC_REG_OFST _UINT32_(0xC8) /* (CAN_TXESC) Tx Buffer Element Size Configuration Offset */ 2368 #define CAN_TXBRP_REG_OFST _UINT32_(0xCC) /* (CAN_TXBRP) Tx Buffer Request Pending Offset */ 2369 #define CAN_TXBAR_REG_OFST _UINT32_(0xD0) /* (CAN_TXBAR) Tx Buffer Add Request Offset */ 2370 #define CAN_TXBCR_REG_OFST _UINT32_(0xD4) /* (CAN_TXBCR) Tx Buffer Cancellation Request Offset */ 2371 #define CAN_TXBTO_REG_OFST _UINT32_(0xD8) /* (CAN_TXBTO) Tx Buffer Transmission Occurred Offset */ 2372 #define CAN_TXBCF_REG_OFST _UINT32_(0xDC) /* (CAN_TXBCF) Tx Buffer Cancellation Finished Offset */ 2373 #define CAN_TXBTIE_REG_OFST _UINT32_(0xE0) /* (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Offset */ 2374 #define CAN_TXBCIE_REG_OFST _UINT32_(0xE4) /* (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Offset */ 2375 #define CAN_TXEFC_REG_OFST _UINT32_(0xF0) /* (CAN_TXEFC) Tx Event FIFO Configuration Offset */ 2376 #define CAN_TXEFS_REG_OFST _UINT32_(0xF4) /* (CAN_TXEFS) Tx Event FIFO Status Offset */ 2377 #define CAN_TXEFA_REG_OFST _UINT32_(0xF8) /* (CAN_TXEFA) Tx Event FIFO Acknowledge Offset */ 2378 2379 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2380 /* CAN_RXBE register API structure */ 2381 typedef struct 2382 { /* Rx Buffer Element */ 2383 __IO uint32_t CAN_RXBE_0; /* Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ 2384 __IO uint32_t CAN_RXBE_1; /* Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ 2385 __IO uint32_t CAN_RXBE_DATA; /* Offset: 0x08 (R/W 32) Rx Buffer Element Data */ 2386 } can_rxbe_registers_t 2387 #ifdef __GNUC__ 2388 __attribute__ ((aligned (4))) 2389 #endif 2390 ; 2391 2392 /* CAN_RXF0E register API structure */ 2393 typedef struct 2394 { /* Rx FIFO 0 Element */ 2395 __IO uint32_t CAN_RXF0E_0; /* Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ 2396 __IO uint32_t CAN_RXF0E_1; /* Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ 2397 __IO uint32_t CAN_RXF0E_DATA; /* Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ 2398 } can_rxf0e_registers_t 2399 #ifdef __GNUC__ 2400 __attribute__ ((aligned (4))) 2401 #endif 2402 ; 2403 2404 /* CAN_RXF1E register API structure */ 2405 typedef struct 2406 { /* Rx FIFO 1 Element */ 2407 __IO uint32_t CAN_RXF1E_0; /* Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ 2408 __IO uint32_t CAN_RXF1E_1; /* Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ 2409 __IO uint32_t CAN_RXF1E_DATA; /* Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ 2410 } can_rxf1e_registers_t 2411 #ifdef __GNUC__ 2412 __attribute__ ((aligned (4))) 2413 #endif 2414 ; 2415 2416 /* CAN_TXBE register API structure */ 2417 typedef struct 2418 { /* Tx Buffer Element */ 2419 __IO uint32_t CAN_TXBE_0; /* Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ 2420 __IO uint32_t CAN_TXBE_1; /* Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ 2421 __IO uint32_t CAN_TXBE_DATA; /* Offset: 0x08 (R/W 32) Tx Buffer Element Data */ 2422 } can_txbe_registers_t 2423 #ifdef __GNUC__ 2424 __attribute__ ((aligned (4))) 2425 #endif 2426 ; 2427 2428 /* CAN_TXEFE register API structure */ 2429 typedef struct 2430 { /* Tx Event FIFO Element */ 2431 __IO uint32_t CAN_TXEFE_0; /* Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ 2432 __IO uint32_t CAN_TXEFE_1; /* Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ 2433 } can_txefe_registers_t 2434 #ifdef __GNUC__ 2435 __attribute__ ((aligned (4))) 2436 #endif 2437 ; 2438 2439 /* CAN_SIDFE register API structure */ 2440 typedef struct 2441 { /* Standard Message ID Filter Element */ 2442 __IO uint32_t CAN_SIDFE_0; /* Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ 2443 } can_sidfe_registers_t 2444 #ifdef __GNUC__ 2445 __attribute__ ((aligned (4))) 2446 #endif 2447 ; 2448 2449 /* CAN_XIDFE register API structure */ 2450 typedef struct 2451 { /* Extended Message ID Filter Element */ 2452 __IO uint32_t CAN_XIDFE_0; /* Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ 2453 __IO uint32_t CAN_XIDFE_1; /* Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ 2454 } can_xidfe_registers_t 2455 #ifdef __GNUC__ 2456 __attribute__ ((aligned (4))) 2457 #endif 2458 ; 2459 2460 /* CAN register API structure */ 2461 typedef struct 2462 { /* Control Area Network */ 2463 __I uint32_t CAN_CREL; /* Offset: 0x00 (R/ 32) Core Release */ 2464 __I uint32_t CAN_ENDN; /* Offset: 0x04 (R/ 32) Endian */ 2465 __IO uint32_t CAN_MRCFG; /* Offset: 0x08 (R/W 32) Message RAM Configuration */ 2466 __IO uint32_t CAN_DBTP; /* Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ 2467 __IO uint32_t CAN_TEST; /* Offset: 0x10 (R/W 32) Test */ 2468 __IO uint32_t CAN_RWD; /* Offset: 0x14 (R/W 32) RAM Watchdog */ 2469 __IO uint32_t CAN_CCCR; /* Offset: 0x18 (R/W 32) CC Control */ 2470 __IO uint32_t CAN_NBTP; /* Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ 2471 __IO uint32_t CAN_TSCC; /* Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ 2472 __I uint32_t CAN_TSCV; /* Offset: 0x24 (R/ 32) Timestamp Counter Value */ 2473 __IO uint32_t CAN_TOCC; /* Offset: 0x28 (R/W 32) Timeout Counter Configuration */ 2474 __IO uint32_t CAN_TOCV; /* Offset: 0x2C (R/W 32) Timeout Counter Value */ 2475 __I uint8_t Reserved1[0x10]; 2476 __I uint32_t CAN_ECR; /* Offset: 0x40 (R/ 32) Error Counter */ 2477 __I uint32_t CAN_PSR; /* Offset: 0x44 (R/ 32) Protocol Status */ 2478 __IO uint32_t CAN_TDCR; /* Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ 2479 __I uint8_t Reserved2[0x04]; 2480 __IO uint32_t CAN_IR; /* Offset: 0x50 (R/W 32) Interrupt */ 2481 __IO uint32_t CAN_IE; /* Offset: 0x54 (R/W 32) Interrupt Enable */ 2482 __IO uint32_t CAN_ILS; /* Offset: 0x58 (R/W 32) Interrupt Line Select */ 2483 __IO uint32_t CAN_ILE; /* Offset: 0x5C (R/W 32) Interrupt Line Enable */ 2484 __I uint8_t Reserved3[0x20]; 2485 __IO uint32_t CAN_GFC; /* Offset: 0x80 (R/W 32) Global Filter Configuration */ 2486 __IO uint32_t CAN_SIDFC; /* Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ 2487 __IO uint32_t CAN_XIDFC; /* Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ 2488 __I uint8_t Reserved4[0x04]; 2489 __IO uint32_t CAN_XIDAM; /* Offset: 0x90 (R/W 32) Extended ID AND Mask */ 2490 __I uint32_t CAN_HPMS; /* Offset: 0x94 (R/ 32) High Priority Message Status */ 2491 __IO uint32_t CAN_NDAT1; /* Offset: 0x98 (R/W 32) New Data 1 */ 2492 __IO uint32_t CAN_NDAT2; /* Offset: 0x9C (R/W 32) New Data 2 */ 2493 __IO uint32_t CAN_RXF0C; /* Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ 2494 __I uint32_t CAN_RXF0S; /* Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ 2495 __IO uint32_t CAN_RXF0A; /* Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ 2496 __IO uint32_t CAN_RXBC; /* Offset: 0xAC (R/W 32) Rx Buffer Configuration */ 2497 __IO uint32_t CAN_RXF1C; /* Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ 2498 __I uint32_t CAN_RXF1S; /* Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ 2499 __IO uint32_t CAN_RXF1A; /* Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ 2500 __IO uint32_t CAN_RXESC; /* Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ 2501 __IO uint32_t CAN_TXBC; /* Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ 2502 __I uint32_t CAN_TXFQS; /* Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ 2503 __IO uint32_t CAN_TXESC; /* Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ 2504 __I uint32_t CAN_TXBRP; /* Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ 2505 __IO uint32_t CAN_TXBAR; /* Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ 2506 __IO uint32_t CAN_TXBCR; /* Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ 2507 __I uint32_t CAN_TXBTO; /* Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ 2508 __I uint32_t CAN_TXBCF; /* Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ 2509 __IO uint32_t CAN_TXBTIE; /* Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ 2510 __IO uint32_t CAN_TXBCIE; /* Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ 2511 __I uint8_t Reserved5[0x08]; 2512 __IO uint32_t CAN_TXEFC; /* Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ 2513 __I uint32_t CAN_TXEFS; /* Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ 2514 __IO uint32_t CAN_TXEFA; /* Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ 2515 } can_registers_t; 2516 2517 2518 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2519 #endif /* _PIC32CXSG41_CAN_COMPONENT_H_ */ 2520
