1 /* 2 * Component description for QSPI 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_QSPI_COMPONENT_H_ 22 #define _PIC32CXSG61_QSPI_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR QSPI */ 26 /* ************************************************************************** */ 27 28 /* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */ 29 #define QSPI_CTRLA_RESETVALUE _UINT32_(0x00) /* (QSPI_CTRLA) Control A Reset Value */ 30 31 #define QSPI_CTRLA_SWRST_Pos _UINT32_(0) /* (QSPI_CTRLA) Software Reset Position */ 32 #define QSPI_CTRLA_SWRST_Msk (_UINT32_(0x1) << QSPI_CTRLA_SWRST_Pos) /* (QSPI_CTRLA) Software Reset Mask */ 33 #define QSPI_CTRLA_SWRST(value) (QSPI_CTRLA_SWRST_Msk & (_UINT32_(value) << QSPI_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the QSPI_CTRLA register */ 34 #define QSPI_CTRLA_ENABLE_Pos _UINT32_(1) /* (QSPI_CTRLA) Enable Position */ 35 #define QSPI_CTRLA_ENABLE_Msk (_UINT32_(0x1) << QSPI_CTRLA_ENABLE_Pos) /* (QSPI_CTRLA) Enable Mask */ 36 #define QSPI_CTRLA_ENABLE(value) (QSPI_CTRLA_ENABLE_Msk & (_UINT32_(value) << QSPI_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the QSPI_CTRLA register */ 37 #define QSPI_CTRLA_LASTXFER_Pos _UINT32_(24) /* (QSPI_CTRLA) Last Transfer Position */ 38 #define QSPI_CTRLA_LASTXFER_Msk (_UINT32_(0x1) << QSPI_CTRLA_LASTXFER_Pos) /* (QSPI_CTRLA) Last Transfer Mask */ 39 #define QSPI_CTRLA_LASTXFER(value) (QSPI_CTRLA_LASTXFER_Msk & (_UINT32_(value) << QSPI_CTRLA_LASTXFER_Pos)) /* Assigment of value for LASTXFER in the QSPI_CTRLA register */ 40 #define QSPI_CTRLA_Msk _UINT32_(0x01000003) /* (QSPI_CTRLA) Register Mask */ 41 42 43 /* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */ 44 #define QSPI_CTRLB_RESETVALUE _UINT32_(0x00) /* (QSPI_CTRLB) Control B Reset Value */ 45 46 #define QSPI_CTRLB_MODE_Pos _UINT32_(0) /* (QSPI_CTRLB) Serial Memory Mode Position */ 47 #define QSPI_CTRLB_MODE_Msk (_UINT32_(0x1) << QSPI_CTRLB_MODE_Pos) /* (QSPI_CTRLB) Serial Memory Mode Mask */ 48 #define QSPI_CTRLB_MODE(value) (QSPI_CTRLB_MODE_Msk & (_UINT32_(value) << QSPI_CTRLB_MODE_Pos)) /* Assigment of value for MODE in the QSPI_CTRLB register */ 49 #define QSPI_CTRLB_MODE_SPI_Val _UINT32_(0x0) /* (QSPI_CTRLB) SPI operating mode */ 50 #define QSPI_CTRLB_MODE_MEMORY_Val _UINT32_(0x1) /* (QSPI_CTRLB) Serial Memory operating mode */ 51 #define QSPI_CTRLB_MODE_SPI (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos) /* (QSPI_CTRLB) SPI operating mode Position */ 52 #define QSPI_CTRLB_MODE_MEMORY (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos) /* (QSPI_CTRLB) Serial Memory operating mode Position */ 53 #define QSPI_CTRLB_LOOPEN_Pos _UINT32_(1) /* (QSPI_CTRLB) Local Loopback Enable Position */ 54 #define QSPI_CTRLB_LOOPEN_Msk (_UINT32_(0x1) << QSPI_CTRLB_LOOPEN_Pos) /* (QSPI_CTRLB) Local Loopback Enable Mask */ 55 #define QSPI_CTRLB_LOOPEN(value) (QSPI_CTRLB_LOOPEN_Msk & (_UINT32_(value) << QSPI_CTRLB_LOOPEN_Pos)) /* Assigment of value for LOOPEN in the QSPI_CTRLB register */ 56 #define QSPI_CTRLB_LOOPEN_DISABLED_Val _UINT32_(0x0) /* (QSPI_CTRLB) Local Loopback is disabled */ 57 #define QSPI_CTRLB_LOOPEN_ENABLED_Val _UINT32_(0x1) /* (QSPI_CTRLB) Local Loopback is enabled */ 58 #define QSPI_CTRLB_LOOPEN_DISABLED (QSPI_CTRLB_LOOPEN_DISABLED_Val << QSPI_CTRLB_LOOPEN_Pos) /* (QSPI_CTRLB) Local Loopback is disabled Position */ 59 #define QSPI_CTRLB_LOOPEN_ENABLED (QSPI_CTRLB_LOOPEN_ENABLED_Val << QSPI_CTRLB_LOOPEN_Pos) /* (QSPI_CTRLB) Local Loopback is enabled Position */ 60 #define QSPI_CTRLB_WDRBT_Pos _UINT32_(2) /* (QSPI_CTRLB) Wait Data Read Before Transfer Position */ 61 #define QSPI_CTRLB_WDRBT_Msk (_UINT32_(0x1) << QSPI_CTRLB_WDRBT_Pos) /* (QSPI_CTRLB) Wait Data Read Before Transfer Mask */ 62 #define QSPI_CTRLB_WDRBT(value) (QSPI_CTRLB_WDRBT_Msk & (_UINT32_(value) << QSPI_CTRLB_WDRBT_Pos)) /* Assigment of value for WDRBT in the QSPI_CTRLB register */ 63 #define QSPI_CTRLB_SMEMREG_Pos _UINT32_(3) /* (QSPI_CTRLB) Serial Memory reg Position */ 64 #define QSPI_CTRLB_SMEMREG_Msk (_UINT32_(0x1) << QSPI_CTRLB_SMEMREG_Pos) /* (QSPI_CTRLB) Serial Memory reg Mask */ 65 #define QSPI_CTRLB_SMEMREG(value) (QSPI_CTRLB_SMEMREG_Msk & (_UINT32_(value) << QSPI_CTRLB_SMEMREG_Pos)) /* Assigment of value for SMEMREG in the QSPI_CTRLB register */ 66 #define QSPI_CTRLB_CSMODE_Pos _UINT32_(4) /* (QSPI_CTRLB) Chip Select Mode Position */ 67 #define QSPI_CTRLB_CSMODE_Msk (_UINT32_(0x3) << QSPI_CTRLB_CSMODE_Pos) /* (QSPI_CTRLB) Chip Select Mode Mask */ 68 #define QSPI_CTRLB_CSMODE(value) (QSPI_CTRLB_CSMODE_Msk & (_UINT32_(value) << QSPI_CTRLB_CSMODE_Pos)) /* Assigment of value for CSMODE in the QSPI_CTRLB register */ 69 #define QSPI_CTRLB_CSMODE_NORELOAD_Val _UINT32_(0x0) /* (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */ 70 #define QSPI_CTRLB_CSMODE_LASTXFER_Val _UINT32_(0x1) /* (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */ 71 #define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _UINT32_(0x2) /* (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. */ 72 #define QSPI_CTRLB_CSMODE_NORELOAD (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos) /* (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. Position */ 73 #define QSPI_CTRLB_CSMODE_LASTXFER (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos) /* (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. Position */ 74 #define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos) /* (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. Position */ 75 #define QSPI_CTRLB_DATALEN_Pos _UINT32_(8) /* (QSPI_CTRLB) Data Length Position */ 76 #define QSPI_CTRLB_DATALEN_Msk (_UINT32_(0xF) << QSPI_CTRLB_DATALEN_Pos) /* (QSPI_CTRLB) Data Length Mask */ 77 #define QSPI_CTRLB_DATALEN(value) (QSPI_CTRLB_DATALEN_Msk & (_UINT32_(value) << QSPI_CTRLB_DATALEN_Pos)) /* Assigment of value for DATALEN in the QSPI_CTRLB register */ 78 #define QSPI_CTRLB_DATALEN_8BITS_Val _UINT32_(0x0) /* (QSPI_CTRLB) 8-bits transfer */ 79 #define QSPI_CTRLB_DATALEN_9BITS_Val _UINT32_(0x1) /* (QSPI_CTRLB) 9 bits transfer */ 80 #define QSPI_CTRLB_DATALEN_10BITS_Val _UINT32_(0x2) /* (QSPI_CTRLB) 10-bits transfer */ 81 #define QSPI_CTRLB_DATALEN_11BITS_Val _UINT32_(0x3) /* (QSPI_CTRLB) 11-bits transfer */ 82 #define QSPI_CTRLB_DATALEN_12BITS_Val _UINT32_(0x4) /* (QSPI_CTRLB) 12-bits transfer */ 83 #define QSPI_CTRLB_DATALEN_13BITS_Val _UINT32_(0x5) /* (QSPI_CTRLB) 13-bits transfer */ 84 #define QSPI_CTRLB_DATALEN_14BITS_Val _UINT32_(0x6) /* (QSPI_CTRLB) 14-bits transfer */ 85 #define QSPI_CTRLB_DATALEN_15BITS_Val _UINT32_(0x7) /* (QSPI_CTRLB) 15-bits transfer */ 86 #define QSPI_CTRLB_DATALEN_16BITS_Val _UINT32_(0x8) /* (QSPI_CTRLB) 16-bits transfer */ 87 #define QSPI_CTRLB_DATALEN_8BITS (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos) /* (QSPI_CTRLB) 8-bits transfer Position */ 88 #define QSPI_CTRLB_DATALEN_9BITS (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos) /* (QSPI_CTRLB) 9 bits transfer Position */ 89 #define QSPI_CTRLB_DATALEN_10BITS (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos) /* (QSPI_CTRLB) 10-bits transfer Position */ 90 #define QSPI_CTRLB_DATALEN_11BITS (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos) /* (QSPI_CTRLB) 11-bits transfer Position */ 91 #define QSPI_CTRLB_DATALEN_12BITS (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos) /* (QSPI_CTRLB) 12-bits transfer Position */ 92 #define QSPI_CTRLB_DATALEN_13BITS (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos) /* (QSPI_CTRLB) 13-bits transfer Position */ 93 #define QSPI_CTRLB_DATALEN_14BITS (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos) /* (QSPI_CTRLB) 14-bits transfer Position */ 94 #define QSPI_CTRLB_DATALEN_15BITS (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos) /* (QSPI_CTRLB) 15-bits transfer Position */ 95 #define QSPI_CTRLB_DATALEN_16BITS (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos) /* (QSPI_CTRLB) 16-bits transfer Position */ 96 #define QSPI_CTRLB_DLYBCT_Pos _UINT32_(16) /* (QSPI_CTRLB) Delay Between Consecutive Transfers Position */ 97 #define QSPI_CTRLB_DLYBCT_Msk (_UINT32_(0xFF) << QSPI_CTRLB_DLYBCT_Pos) /* (QSPI_CTRLB) Delay Between Consecutive Transfers Mask */ 98 #define QSPI_CTRLB_DLYBCT(value) (QSPI_CTRLB_DLYBCT_Msk & (_UINT32_(value) << QSPI_CTRLB_DLYBCT_Pos)) /* Assigment of value for DLYBCT in the QSPI_CTRLB register */ 99 #define QSPI_CTRLB_DLYCS_Pos _UINT32_(24) /* (QSPI_CTRLB) Minimum Inactive CS Delay Position */ 100 #define QSPI_CTRLB_DLYCS_Msk (_UINT32_(0xFF) << QSPI_CTRLB_DLYCS_Pos) /* (QSPI_CTRLB) Minimum Inactive CS Delay Mask */ 101 #define QSPI_CTRLB_DLYCS(value) (QSPI_CTRLB_DLYCS_Msk & (_UINT32_(value) << QSPI_CTRLB_DLYCS_Pos)) /* Assigment of value for DLYCS in the QSPI_CTRLB register */ 102 #define QSPI_CTRLB_Msk _UINT32_(0xFFFF0F3F) /* (QSPI_CTRLB) Register Mask */ 103 104 105 /* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */ 106 #define QSPI_BAUD_RESETVALUE _UINT32_(0x00) /* (QSPI_BAUD) Baud Rate Reset Value */ 107 108 #define QSPI_BAUD_CPOL_Pos _UINT32_(0) /* (QSPI_BAUD) Clock Polarity Position */ 109 #define QSPI_BAUD_CPOL_Msk (_UINT32_(0x1) << QSPI_BAUD_CPOL_Pos) /* (QSPI_BAUD) Clock Polarity Mask */ 110 #define QSPI_BAUD_CPOL(value) (QSPI_BAUD_CPOL_Msk & (_UINT32_(value) << QSPI_BAUD_CPOL_Pos)) /* Assigment of value for CPOL in the QSPI_BAUD register */ 111 #define QSPI_BAUD_CPHA_Pos _UINT32_(1) /* (QSPI_BAUD) Clock Phase Position */ 112 #define QSPI_BAUD_CPHA_Msk (_UINT32_(0x1) << QSPI_BAUD_CPHA_Pos) /* (QSPI_BAUD) Clock Phase Mask */ 113 #define QSPI_BAUD_CPHA(value) (QSPI_BAUD_CPHA_Msk & (_UINT32_(value) << QSPI_BAUD_CPHA_Pos)) /* Assigment of value for CPHA in the QSPI_BAUD register */ 114 #define QSPI_BAUD_BAUD_Pos _UINT32_(8) /* (QSPI_BAUD) Serial Clock Baud Rate Position */ 115 #define QSPI_BAUD_BAUD_Msk (_UINT32_(0xFF) << QSPI_BAUD_BAUD_Pos) /* (QSPI_BAUD) Serial Clock Baud Rate Mask */ 116 #define QSPI_BAUD_BAUD(value) (QSPI_BAUD_BAUD_Msk & (_UINT32_(value) << QSPI_BAUD_BAUD_Pos)) /* Assigment of value for BAUD in the QSPI_BAUD register */ 117 #define QSPI_BAUD_DLYBS_Pos _UINT32_(16) /* (QSPI_BAUD) Delay Before SCK Position */ 118 #define QSPI_BAUD_DLYBS_Msk (_UINT32_(0xFF) << QSPI_BAUD_DLYBS_Pos) /* (QSPI_BAUD) Delay Before SCK Mask */ 119 #define QSPI_BAUD_DLYBS(value) (QSPI_BAUD_DLYBS_Msk & (_UINT32_(value) << QSPI_BAUD_DLYBS_Pos)) /* Assigment of value for DLYBS in the QSPI_BAUD register */ 120 #define QSPI_BAUD_Msk _UINT32_(0x00FFFF03) /* (QSPI_BAUD) Register Mask */ 121 122 123 /* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) ( R/ 32) Receive Data -------- */ 124 #define QSPI_RXDATA_RESETVALUE _UINT32_(0x00) /* (QSPI_RXDATA) Receive Data Reset Value */ 125 126 #define QSPI_RXDATA_DATA_Pos _UINT32_(0) /* (QSPI_RXDATA) Receive Data Position */ 127 #define QSPI_RXDATA_DATA_Msk (_UINT32_(0xFFFF) << QSPI_RXDATA_DATA_Pos) /* (QSPI_RXDATA) Receive Data Mask */ 128 #define QSPI_RXDATA_DATA(value) (QSPI_RXDATA_DATA_Msk & (_UINT32_(value) << QSPI_RXDATA_DATA_Pos)) /* Assigment of value for DATA in the QSPI_RXDATA register */ 129 #define QSPI_RXDATA_Msk _UINT32_(0x0000FFFF) /* (QSPI_RXDATA) Register Mask */ 130 131 132 /* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */ 133 #define QSPI_TXDATA_RESETVALUE _UINT32_(0x00) /* (QSPI_TXDATA) Transmit Data Reset Value */ 134 135 #define QSPI_TXDATA_DATA_Pos _UINT32_(0) /* (QSPI_TXDATA) Transmit Data Position */ 136 #define QSPI_TXDATA_DATA_Msk (_UINT32_(0xFFFF) << QSPI_TXDATA_DATA_Pos) /* (QSPI_TXDATA) Transmit Data Mask */ 137 #define QSPI_TXDATA_DATA(value) (QSPI_TXDATA_DATA_Msk & (_UINT32_(value) << QSPI_TXDATA_DATA_Pos)) /* Assigment of value for DATA in the QSPI_TXDATA register */ 138 #define QSPI_TXDATA_Msk _UINT32_(0x0000FFFF) /* (QSPI_TXDATA) Register Mask */ 139 140 141 /* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */ 142 #define QSPI_INTENCLR_RESETVALUE _UINT32_(0x00) /* (QSPI_INTENCLR) Interrupt Enable Clear Reset Value */ 143 144 #define QSPI_INTENCLR_RXC_Pos _UINT32_(0) /* (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable Position */ 145 #define QSPI_INTENCLR_RXC_Msk (_UINT32_(0x1) << QSPI_INTENCLR_RXC_Pos) /* (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable Mask */ 146 #define QSPI_INTENCLR_RXC(value) (QSPI_INTENCLR_RXC_Msk & (_UINT32_(value) << QSPI_INTENCLR_RXC_Pos)) /* Assigment of value for RXC in the QSPI_INTENCLR register */ 147 #define QSPI_INTENCLR_DRE_Pos _UINT32_(1) /* (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable Position */ 148 #define QSPI_INTENCLR_DRE_Msk (_UINT32_(0x1) << QSPI_INTENCLR_DRE_Pos) /* (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable Mask */ 149 #define QSPI_INTENCLR_DRE(value) (QSPI_INTENCLR_DRE_Msk & (_UINT32_(value) << QSPI_INTENCLR_DRE_Pos)) /* Assigment of value for DRE in the QSPI_INTENCLR register */ 150 #define QSPI_INTENCLR_TXC_Pos _UINT32_(2) /* (QSPI_INTENCLR) Transmission Complete Interrupt Disable Position */ 151 #define QSPI_INTENCLR_TXC_Msk (_UINT32_(0x1) << QSPI_INTENCLR_TXC_Pos) /* (QSPI_INTENCLR) Transmission Complete Interrupt Disable Mask */ 152 #define QSPI_INTENCLR_TXC(value) (QSPI_INTENCLR_TXC_Msk & (_UINT32_(value) << QSPI_INTENCLR_TXC_Pos)) /* Assigment of value for TXC in the QSPI_INTENCLR register */ 153 #define QSPI_INTENCLR_ERROR_Pos _UINT32_(3) /* (QSPI_INTENCLR) Overrun Error Interrupt Disable Position */ 154 #define QSPI_INTENCLR_ERROR_Msk (_UINT32_(0x1) << QSPI_INTENCLR_ERROR_Pos) /* (QSPI_INTENCLR) Overrun Error Interrupt Disable Mask */ 155 #define QSPI_INTENCLR_ERROR(value) (QSPI_INTENCLR_ERROR_Msk & (_UINT32_(value) << QSPI_INTENCLR_ERROR_Pos)) /* Assigment of value for ERROR in the QSPI_INTENCLR register */ 156 #define QSPI_INTENCLR_CSRISE_Pos _UINT32_(8) /* (QSPI_INTENCLR) Chip Select Rise Interrupt Disable Position */ 157 #define QSPI_INTENCLR_CSRISE_Msk (_UINT32_(0x1) << QSPI_INTENCLR_CSRISE_Pos) /* (QSPI_INTENCLR) Chip Select Rise Interrupt Disable Mask */ 158 #define QSPI_INTENCLR_CSRISE(value) (QSPI_INTENCLR_CSRISE_Msk & (_UINT32_(value) << QSPI_INTENCLR_CSRISE_Pos)) /* Assigment of value for CSRISE in the QSPI_INTENCLR register */ 159 #define QSPI_INTENCLR_INSTREND_Pos _UINT32_(10) /* (QSPI_INTENCLR) Instruction End Interrupt Disable Position */ 160 #define QSPI_INTENCLR_INSTREND_Msk (_UINT32_(0x1) << QSPI_INTENCLR_INSTREND_Pos) /* (QSPI_INTENCLR) Instruction End Interrupt Disable Mask */ 161 #define QSPI_INTENCLR_INSTREND(value) (QSPI_INTENCLR_INSTREND_Msk & (_UINT32_(value) << QSPI_INTENCLR_INSTREND_Pos)) /* Assigment of value for INSTREND in the QSPI_INTENCLR register */ 162 #define QSPI_INTENCLR_Msk _UINT32_(0x0000050F) /* (QSPI_INTENCLR) Register Mask */ 163 164 165 /* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */ 166 #define QSPI_INTENSET_RESETVALUE _UINT32_(0x00) /* (QSPI_INTENSET) Interrupt Enable Set Reset Value */ 167 168 #define QSPI_INTENSET_RXC_Pos _UINT32_(0) /* (QSPI_INTENSET) Receive Data Register Full Interrupt Enable Position */ 169 #define QSPI_INTENSET_RXC_Msk (_UINT32_(0x1) << QSPI_INTENSET_RXC_Pos) /* (QSPI_INTENSET) Receive Data Register Full Interrupt Enable Mask */ 170 #define QSPI_INTENSET_RXC(value) (QSPI_INTENSET_RXC_Msk & (_UINT32_(value) << QSPI_INTENSET_RXC_Pos)) /* Assigment of value for RXC in the QSPI_INTENSET register */ 171 #define QSPI_INTENSET_DRE_Pos _UINT32_(1) /* (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable Position */ 172 #define QSPI_INTENSET_DRE_Msk (_UINT32_(0x1) << QSPI_INTENSET_DRE_Pos) /* (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable Mask */ 173 #define QSPI_INTENSET_DRE(value) (QSPI_INTENSET_DRE_Msk & (_UINT32_(value) << QSPI_INTENSET_DRE_Pos)) /* Assigment of value for DRE in the QSPI_INTENSET register */ 174 #define QSPI_INTENSET_TXC_Pos _UINT32_(2) /* (QSPI_INTENSET) Transmission Complete Interrupt Enable Position */ 175 #define QSPI_INTENSET_TXC_Msk (_UINT32_(0x1) << QSPI_INTENSET_TXC_Pos) /* (QSPI_INTENSET) Transmission Complete Interrupt Enable Mask */ 176 #define QSPI_INTENSET_TXC(value) (QSPI_INTENSET_TXC_Msk & (_UINT32_(value) << QSPI_INTENSET_TXC_Pos)) /* Assigment of value for TXC in the QSPI_INTENSET register */ 177 #define QSPI_INTENSET_ERROR_Pos _UINT32_(3) /* (QSPI_INTENSET) Overrun Error Interrupt Enable Position */ 178 #define QSPI_INTENSET_ERROR_Msk (_UINT32_(0x1) << QSPI_INTENSET_ERROR_Pos) /* (QSPI_INTENSET) Overrun Error Interrupt Enable Mask */ 179 #define QSPI_INTENSET_ERROR(value) (QSPI_INTENSET_ERROR_Msk & (_UINT32_(value) << QSPI_INTENSET_ERROR_Pos)) /* Assigment of value for ERROR in the QSPI_INTENSET register */ 180 #define QSPI_INTENSET_CSRISE_Pos _UINT32_(8) /* (QSPI_INTENSET) Chip Select Rise Interrupt Enable Position */ 181 #define QSPI_INTENSET_CSRISE_Msk (_UINT32_(0x1) << QSPI_INTENSET_CSRISE_Pos) /* (QSPI_INTENSET) Chip Select Rise Interrupt Enable Mask */ 182 #define QSPI_INTENSET_CSRISE(value) (QSPI_INTENSET_CSRISE_Msk & (_UINT32_(value) << QSPI_INTENSET_CSRISE_Pos)) /* Assigment of value for CSRISE in the QSPI_INTENSET register */ 183 #define QSPI_INTENSET_INSTREND_Pos _UINT32_(10) /* (QSPI_INTENSET) Instruction End Interrupt Enable Position */ 184 #define QSPI_INTENSET_INSTREND_Msk (_UINT32_(0x1) << QSPI_INTENSET_INSTREND_Pos) /* (QSPI_INTENSET) Instruction End Interrupt Enable Mask */ 185 #define QSPI_INTENSET_INSTREND(value) (QSPI_INTENSET_INSTREND_Msk & (_UINT32_(value) << QSPI_INTENSET_INSTREND_Pos)) /* Assigment of value for INSTREND in the QSPI_INTENSET register */ 186 #define QSPI_INTENSET_Msk _UINT32_(0x0000050F) /* (QSPI_INTENSET) Register Mask */ 187 188 189 /* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */ 190 #define QSPI_INTFLAG_RESETVALUE _UINT32_(0x00) /* (QSPI_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 191 192 #define QSPI_INTFLAG_RXC_Pos _UINT32_(0) /* (QSPI_INTFLAG) Receive Data Register Full Position */ 193 #define QSPI_INTFLAG_RXC_Msk (_UINT32_(0x1) << QSPI_INTFLAG_RXC_Pos) /* (QSPI_INTFLAG) Receive Data Register Full Mask */ 194 #define QSPI_INTFLAG_RXC(value) (QSPI_INTFLAG_RXC_Msk & (_UINT32_(value) << QSPI_INTFLAG_RXC_Pos)) /* Assigment of value for RXC in the QSPI_INTFLAG register */ 195 #define QSPI_INTFLAG_DRE_Pos _UINT32_(1) /* (QSPI_INTFLAG) Transmit Data Register Empty Position */ 196 #define QSPI_INTFLAG_DRE_Msk (_UINT32_(0x1) << QSPI_INTFLAG_DRE_Pos) /* (QSPI_INTFLAG) Transmit Data Register Empty Mask */ 197 #define QSPI_INTFLAG_DRE(value) (QSPI_INTFLAG_DRE_Msk & (_UINT32_(value) << QSPI_INTFLAG_DRE_Pos)) /* Assigment of value for DRE in the QSPI_INTFLAG register */ 198 #define QSPI_INTFLAG_TXC_Pos _UINT32_(2) /* (QSPI_INTFLAG) Transmission Complete Position */ 199 #define QSPI_INTFLAG_TXC_Msk (_UINT32_(0x1) << QSPI_INTFLAG_TXC_Pos) /* (QSPI_INTFLAG) Transmission Complete Mask */ 200 #define QSPI_INTFLAG_TXC(value) (QSPI_INTFLAG_TXC_Msk & (_UINT32_(value) << QSPI_INTFLAG_TXC_Pos)) /* Assigment of value for TXC in the QSPI_INTFLAG register */ 201 #define QSPI_INTFLAG_ERROR_Pos _UINT32_(3) /* (QSPI_INTFLAG) Overrun Error Position */ 202 #define QSPI_INTFLAG_ERROR_Msk (_UINT32_(0x1) << QSPI_INTFLAG_ERROR_Pos) /* (QSPI_INTFLAG) Overrun Error Mask */ 203 #define QSPI_INTFLAG_ERROR(value) (QSPI_INTFLAG_ERROR_Msk & (_UINT32_(value) << QSPI_INTFLAG_ERROR_Pos)) /* Assigment of value for ERROR in the QSPI_INTFLAG register */ 204 #define QSPI_INTFLAG_CSRISE_Pos _UINT32_(8) /* (QSPI_INTFLAG) Chip Select Rise Position */ 205 #define QSPI_INTFLAG_CSRISE_Msk (_UINT32_(0x1) << QSPI_INTFLAG_CSRISE_Pos) /* (QSPI_INTFLAG) Chip Select Rise Mask */ 206 #define QSPI_INTFLAG_CSRISE(value) (QSPI_INTFLAG_CSRISE_Msk & (_UINT32_(value) << QSPI_INTFLAG_CSRISE_Pos)) /* Assigment of value for CSRISE in the QSPI_INTFLAG register */ 207 #define QSPI_INTFLAG_INSTREND_Pos _UINT32_(10) /* (QSPI_INTFLAG) Instruction End Position */ 208 #define QSPI_INTFLAG_INSTREND_Msk (_UINT32_(0x1) << QSPI_INTFLAG_INSTREND_Pos) /* (QSPI_INTFLAG) Instruction End Mask */ 209 #define QSPI_INTFLAG_INSTREND(value) (QSPI_INTFLAG_INSTREND_Msk & (_UINT32_(value) << QSPI_INTFLAG_INSTREND_Pos)) /* Assigment of value for INSTREND in the QSPI_INTFLAG register */ 210 #define QSPI_INTFLAG_Msk _UINT32_(0x0000050F) /* (QSPI_INTFLAG) Register Mask */ 211 212 213 /* -------- QSPI_STATUS : (QSPI Offset: 0x20) ( R/ 32) Status Register -------- */ 214 #define QSPI_STATUS_RESETVALUE _UINT32_(0x200) /* (QSPI_STATUS) Status Register Reset Value */ 215 216 #define QSPI_STATUS_ENABLE_Pos _UINT32_(1) /* (QSPI_STATUS) Enable Position */ 217 #define QSPI_STATUS_ENABLE_Msk (_UINT32_(0x1) << QSPI_STATUS_ENABLE_Pos) /* (QSPI_STATUS) Enable Mask */ 218 #define QSPI_STATUS_ENABLE(value) (QSPI_STATUS_ENABLE_Msk & (_UINT32_(value) << QSPI_STATUS_ENABLE_Pos)) /* Assigment of value for ENABLE in the QSPI_STATUS register */ 219 #define QSPI_STATUS_CSSTATUS_Pos _UINT32_(9) /* (QSPI_STATUS) Chip Select Position */ 220 #define QSPI_STATUS_CSSTATUS_Msk (_UINT32_(0x1) << QSPI_STATUS_CSSTATUS_Pos) /* (QSPI_STATUS) Chip Select Mask */ 221 #define QSPI_STATUS_CSSTATUS(value) (QSPI_STATUS_CSSTATUS_Msk & (_UINT32_(value) << QSPI_STATUS_CSSTATUS_Pos)) /* Assigment of value for CSSTATUS in the QSPI_STATUS register */ 222 #define QSPI_STATUS_Msk _UINT32_(0x00000202) /* (QSPI_STATUS) Register Mask */ 223 224 225 /* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */ 226 #define QSPI_INSTRADDR_RESETVALUE _UINT32_(0x00) /* (QSPI_INSTRADDR) Instruction Address Reset Value */ 227 228 #define QSPI_INSTRADDR_ADDR_Pos _UINT32_(0) /* (QSPI_INSTRADDR) Instruction Address Position */ 229 #define QSPI_INSTRADDR_ADDR_Msk (_UINT32_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos) /* (QSPI_INSTRADDR) Instruction Address Mask */ 230 #define QSPI_INSTRADDR_ADDR(value) (QSPI_INSTRADDR_ADDR_Msk & (_UINT32_(value) << QSPI_INSTRADDR_ADDR_Pos)) /* Assigment of value for ADDR in the QSPI_INSTRADDR register */ 231 #define QSPI_INSTRADDR_Msk _UINT32_(0xFFFFFFFF) /* (QSPI_INSTRADDR) Register Mask */ 232 233 234 /* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */ 235 #define QSPI_INSTRCTRL_RESETVALUE _UINT32_(0x00) /* (QSPI_INSTRCTRL) Instruction Code Reset Value */ 236 237 #define QSPI_INSTRCTRL_INSTR_Pos _UINT32_(0) /* (QSPI_INSTRCTRL) Instruction Code Position */ 238 #define QSPI_INSTRCTRL_INSTR_Msk (_UINT32_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos) /* (QSPI_INSTRCTRL) Instruction Code Mask */ 239 #define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & (_UINT32_(value) << QSPI_INSTRCTRL_INSTR_Pos)) /* Assigment of value for INSTR in the QSPI_INSTRCTRL register */ 240 #define QSPI_INSTRCTRL_OPTCODE_Pos _UINT32_(16) /* (QSPI_INSTRCTRL) Option Code Position */ 241 #define QSPI_INSTRCTRL_OPTCODE_Msk (_UINT32_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos) /* (QSPI_INSTRCTRL) Option Code Mask */ 242 #define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & (_UINT32_(value) << QSPI_INSTRCTRL_OPTCODE_Pos)) /* Assigment of value for OPTCODE in the QSPI_INSTRCTRL register */ 243 #define QSPI_INSTRCTRL_Msk _UINT32_(0x00FF00FF) /* (QSPI_INSTRCTRL) Register Mask */ 244 245 246 /* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */ 247 #define QSPI_INSTRFRAME_RESETVALUE _UINT32_(0x00) /* (QSPI_INSTRFRAME) Instruction Frame Reset Value */ 248 249 #define QSPI_INSTRFRAME_WIDTH_Pos _UINT32_(0) /* (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width Position */ 250 #define QSPI_INSTRFRAME_WIDTH_Msk (_UINT32_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos) /* (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width Mask */ 251 #define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_WIDTH_Pos)) /* Assigment of value for WIDTH in the QSPI_INSTRFRAME register */ 252 #define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _UINT32_(0x0) /* (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ 253 #define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _UINT32_(0x1) /* (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ 254 #define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _UINT32_(0x2) /* (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ 255 #define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _UINT32_(0x3) /* (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ 256 #define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _UINT32_(0x4) /* (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ 257 #define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _UINT32_(0x5) /* (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ 258 #define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _UINT32_(0x6) /* (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ 259 #define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos) /* (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI Position */ 260 #define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos) /* (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI Position */ 261 #define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos) /* (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI Position */ 262 #define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos) /* (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI Position */ 263 #define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos) /* (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI Position */ 264 #define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos) /* (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI Position */ 265 #define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos) /* (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI Position */ 266 #define QSPI_INSTRFRAME_INSTREN_Pos _UINT32_(4) /* (QSPI_INSTRFRAME) Instruction Enable Position */ 267 #define QSPI_INSTRFRAME_INSTREN_Msk (_UINT32_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos) /* (QSPI_INSTRFRAME) Instruction Enable Mask */ 268 #define QSPI_INSTRFRAME_INSTREN(value) (QSPI_INSTRFRAME_INSTREN_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_INSTREN_Pos)) /* Assigment of value for INSTREN in the QSPI_INSTRFRAME register */ 269 #define QSPI_INSTRFRAME_ADDREN_Pos _UINT32_(5) /* (QSPI_INSTRFRAME) Address Enable Position */ 270 #define QSPI_INSTRFRAME_ADDREN_Msk (_UINT32_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos) /* (QSPI_INSTRFRAME) Address Enable Mask */ 271 #define QSPI_INSTRFRAME_ADDREN(value) (QSPI_INSTRFRAME_ADDREN_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_ADDREN_Pos)) /* Assigment of value for ADDREN in the QSPI_INSTRFRAME register */ 272 #define QSPI_INSTRFRAME_OPTCODEEN_Pos _UINT32_(6) /* (QSPI_INSTRFRAME) Option Enable Position */ 273 #define QSPI_INSTRFRAME_OPTCODEEN_Msk (_UINT32_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos) /* (QSPI_INSTRFRAME) Option Enable Mask */ 274 #define QSPI_INSTRFRAME_OPTCODEEN(value) (QSPI_INSTRFRAME_OPTCODEEN_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_OPTCODEEN_Pos)) /* Assigment of value for OPTCODEEN in the QSPI_INSTRFRAME register */ 275 #define QSPI_INSTRFRAME_DATAEN_Pos _UINT32_(7) /* (QSPI_INSTRFRAME) Data Enable Position */ 276 #define QSPI_INSTRFRAME_DATAEN_Msk (_UINT32_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos) /* (QSPI_INSTRFRAME) Data Enable Mask */ 277 #define QSPI_INSTRFRAME_DATAEN(value) (QSPI_INSTRFRAME_DATAEN_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_DATAEN_Pos)) /* Assigment of value for DATAEN in the QSPI_INSTRFRAME register */ 278 #define QSPI_INSTRFRAME_OPTCODELEN_Pos _UINT32_(8) /* (QSPI_INSTRFRAME) Option Code Length Position */ 279 #define QSPI_INSTRFRAME_OPTCODELEN_Msk (_UINT32_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos) /* (QSPI_INSTRFRAME) Option Code Length Mask */ 280 #define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_OPTCODELEN_Pos)) /* Assigment of value for OPTCODELEN in the QSPI_INSTRFRAME register */ 281 #define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _UINT32_(0x0) /* (QSPI_INSTRFRAME) 1-bit length option code */ 282 #define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _UINT32_(0x1) /* (QSPI_INSTRFRAME) 2-bits length option code */ 283 #define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _UINT32_(0x2) /* (QSPI_INSTRFRAME) 4-bits length option code */ 284 #define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _UINT32_(0x3) /* (QSPI_INSTRFRAME) 8-bits length option code */ 285 #define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos) /* (QSPI_INSTRFRAME) 1-bit length option code Position */ 286 #define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos) /* (QSPI_INSTRFRAME) 2-bits length option code Position */ 287 #define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos) /* (QSPI_INSTRFRAME) 4-bits length option code Position */ 288 #define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos) /* (QSPI_INSTRFRAME) 8-bits length option code Position */ 289 #define QSPI_INSTRFRAME_ADDRLEN_Pos _UINT32_(10) /* (QSPI_INSTRFRAME) Address Length Position */ 290 #define QSPI_INSTRFRAME_ADDRLEN_Msk (_UINT32_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos) /* (QSPI_INSTRFRAME) Address Length Mask */ 291 #define QSPI_INSTRFRAME_ADDRLEN(value) (QSPI_INSTRFRAME_ADDRLEN_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_ADDRLEN_Pos)) /* Assigment of value for ADDRLEN in the QSPI_INSTRFRAME register */ 292 #define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _UINT32_(0x0) /* (QSPI_INSTRFRAME) 24-bits address length */ 293 #define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _UINT32_(0x1) /* (QSPI_INSTRFRAME) 32-bits address length */ 294 #define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos) /* (QSPI_INSTRFRAME) 24-bits address length Position */ 295 #define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos) /* (QSPI_INSTRFRAME) 32-bits address length Position */ 296 #define QSPI_INSTRFRAME_TFRTYPE_Pos _UINT32_(12) /* (QSPI_INSTRFRAME) Data Transfer Type Position */ 297 #define QSPI_INSTRFRAME_TFRTYPE_Msk (_UINT32_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos) /* (QSPI_INSTRFRAME) Data Transfer Type Mask */ 298 #define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_TFRTYPE_Pos)) /* Assigment of value for TFRTYPE in the QSPI_INSTRFRAME register */ 299 #define QSPI_INSTRFRAME_TFRTYPE_READ_Val _UINT32_(0x0) /* (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. */ 300 #define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _UINT32_(0x1) /* (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. */ 301 #define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _UINT32_(0x2) /* (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. */ 302 #define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _UINT32_(0x3) /* (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. */ 303 #define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos) /* (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. Position */ 304 #define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos) /* (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. Position */ 305 #define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos) /* (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. Position */ 306 #define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos) /* (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. Position */ 307 #define QSPI_INSTRFRAME_CRMODE_Pos _UINT32_(14) /* (QSPI_INSTRFRAME) Continuous Read Mode Position */ 308 #define QSPI_INSTRFRAME_CRMODE_Msk (_UINT32_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos) /* (QSPI_INSTRFRAME) Continuous Read Mode Mask */ 309 #define QSPI_INSTRFRAME_CRMODE(value) (QSPI_INSTRFRAME_CRMODE_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_CRMODE_Pos)) /* Assigment of value for CRMODE in the QSPI_INSTRFRAME register */ 310 #define QSPI_INSTRFRAME_DDREN_Pos _UINT32_(15) /* (QSPI_INSTRFRAME) Double Data Rate Enable Position */ 311 #define QSPI_INSTRFRAME_DDREN_Msk (_UINT32_(0x1) << QSPI_INSTRFRAME_DDREN_Pos) /* (QSPI_INSTRFRAME) Double Data Rate Enable Mask */ 312 #define QSPI_INSTRFRAME_DDREN(value) (QSPI_INSTRFRAME_DDREN_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_DDREN_Pos)) /* Assigment of value for DDREN in the QSPI_INSTRFRAME register */ 313 #define QSPI_INSTRFRAME_DUMMYLEN_Pos _UINT32_(16) /* (QSPI_INSTRFRAME) Dummy Cycles Length Position */ 314 #define QSPI_INSTRFRAME_DUMMYLEN_Msk (_UINT32_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos) /* (QSPI_INSTRFRAME) Dummy Cycles Length Mask */ 315 #define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & (_UINT32_(value) << QSPI_INSTRFRAME_DUMMYLEN_Pos)) /* Assigment of value for DUMMYLEN in the QSPI_INSTRFRAME register */ 316 #define QSPI_INSTRFRAME_Msk _UINT32_(0x001FF7F7) /* (QSPI_INSTRFRAME) Register Mask */ 317 318 319 /* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */ 320 #define QSPI_SCRAMBCTRL_RESETVALUE _UINT32_(0x00) /* (QSPI_SCRAMBCTRL) Scrambling Mode Reset Value */ 321 322 #define QSPI_SCRAMBCTRL_ENABLE_Pos _UINT32_(0) /* (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable Position */ 323 #define QSPI_SCRAMBCTRL_ENABLE_Msk (_UINT32_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos) /* (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable Mask */ 324 #define QSPI_SCRAMBCTRL_ENABLE(value) (QSPI_SCRAMBCTRL_ENABLE_Msk & (_UINT32_(value) << QSPI_SCRAMBCTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the QSPI_SCRAMBCTRL register */ 325 #define QSPI_SCRAMBCTRL_RANDOMDIS_Pos _UINT32_(1) /* (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable Position */ 326 #define QSPI_SCRAMBCTRL_RANDOMDIS_Msk (_UINT32_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos) /* (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable Mask */ 327 #define QSPI_SCRAMBCTRL_RANDOMDIS(value) (QSPI_SCRAMBCTRL_RANDOMDIS_Msk & (_UINT32_(value) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)) /* Assigment of value for RANDOMDIS in the QSPI_SCRAMBCTRL register */ 328 #define QSPI_SCRAMBCTRL_Msk _UINT32_(0x00000003) /* (QSPI_SCRAMBCTRL) Register Mask */ 329 330 331 /* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */ 332 #define QSPI_SCRAMBKEY_RESETVALUE _UINT32_(0x00) /* (QSPI_SCRAMBKEY) Scrambling Key Reset Value */ 333 334 #define QSPI_SCRAMBKEY_KEY_Pos _UINT32_(0) /* (QSPI_SCRAMBKEY) Scrambling User Key Position */ 335 #define QSPI_SCRAMBKEY_KEY_Msk (_UINT32_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos) /* (QSPI_SCRAMBKEY) Scrambling User Key Mask */ 336 #define QSPI_SCRAMBKEY_KEY(value) (QSPI_SCRAMBKEY_KEY_Msk & (_UINT32_(value) << QSPI_SCRAMBKEY_KEY_Pos)) /* Assigment of value for KEY in the QSPI_SCRAMBKEY register */ 337 #define QSPI_SCRAMBKEY_Msk _UINT32_(0xFFFFFFFF) /* (QSPI_SCRAMBKEY) Register Mask */ 338 339 340 /** \brief QSPI register offsets definitions */ 341 #define QSPI_CTRLA_REG_OFST _UINT32_(0x00) /* (QSPI_CTRLA) Control A Offset */ 342 #define QSPI_CTRLB_REG_OFST _UINT32_(0x04) /* (QSPI_CTRLB) Control B Offset */ 343 #define QSPI_BAUD_REG_OFST _UINT32_(0x08) /* (QSPI_BAUD) Baud Rate Offset */ 344 #define QSPI_RXDATA_REG_OFST _UINT32_(0x0C) /* (QSPI_RXDATA) Receive Data Offset */ 345 #define QSPI_TXDATA_REG_OFST _UINT32_(0x10) /* (QSPI_TXDATA) Transmit Data Offset */ 346 #define QSPI_INTENCLR_REG_OFST _UINT32_(0x14) /* (QSPI_INTENCLR) Interrupt Enable Clear Offset */ 347 #define QSPI_INTENSET_REG_OFST _UINT32_(0x18) /* (QSPI_INTENSET) Interrupt Enable Set Offset */ 348 #define QSPI_INTFLAG_REG_OFST _UINT32_(0x1C) /* (QSPI_INTFLAG) Interrupt Flag Status and Clear Offset */ 349 #define QSPI_STATUS_REG_OFST _UINT32_(0x20) /* (QSPI_STATUS) Status Register Offset */ 350 #define QSPI_INSTRADDR_REG_OFST _UINT32_(0x30) /* (QSPI_INSTRADDR) Instruction Address Offset */ 351 #define QSPI_INSTRCTRL_REG_OFST _UINT32_(0x34) /* (QSPI_INSTRCTRL) Instruction Code Offset */ 352 #define QSPI_INSTRFRAME_REG_OFST _UINT32_(0x38) /* (QSPI_INSTRFRAME) Instruction Frame Offset */ 353 #define QSPI_SCRAMBCTRL_REG_OFST _UINT32_(0x40) /* (QSPI_SCRAMBCTRL) Scrambling Mode Offset */ 354 #define QSPI_SCRAMBKEY_REG_OFST _UINT32_(0x44) /* (QSPI_SCRAMBKEY) Scrambling Key Offset */ 355 356 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 357 /** \brief QSPI register API structure */ 358 typedef struct 359 { /* Quad SPI interface */ 360 __IO uint32_t QSPI_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ 361 __IO uint32_t QSPI_CTRLB; /**< Offset: 0x04 (R/W 32) Control B */ 362 __IO uint32_t QSPI_BAUD; /**< Offset: 0x08 (R/W 32) Baud Rate */ 363 __I uint32_t QSPI_RXDATA; /**< Offset: 0x0C (R/ 32) Receive Data */ 364 __O uint32_t QSPI_TXDATA; /**< Offset: 0x10 ( /W 32) Transmit Data */ 365 __IO uint32_t QSPI_INTENCLR; /**< Offset: 0x14 (R/W 32) Interrupt Enable Clear */ 366 __IO uint32_t QSPI_INTENSET; /**< Offset: 0x18 (R/W 32) Interrupt Enable Set */ 367 __IO uint32_t QSPI_INTFLAG; /**< Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear */ 368 __I uint32_t QSPI_STATUS; /**< Offset: 0x20 (R/ 32) Status Register */ 369 __I uint8_t Reserved1[0x0C]; 370 __IO uint32_t QSPI_INSTRADDR; /**< Offset: 0x30 (R/W 32) Instruction Address */ 371 __IO uint32_t QSPI_INSTRCTRL; /**< Offset: 0x34 (R/W 32) Instruction Code */ 372 __IO uint32_t QSPI_INSTRFRAME; /**< Offset: 0x38 (R/W 32) Instruction Frame */ 373 __I uint8_t Reserved2[0x04]; 374 __IO uint32_t QSPI_SCRAMBCTRL; /**< Offset: 0x40 (R/W 32) Scrambling Mode */ 375 __O uint32_t QSPI_SCRAMBKEY; /**< Offset: 0x44 ( /W 32) Scrambling Key */ 376 } qspi_registers_t; 377 378 379 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 380 #endif /* _PIC32CXSG61_QSPI_COMPONENT_H_ */ 381
