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Searched refs:pcc (Results 1 – 25 of 30) sorted by relevance

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/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_clock.h20 #define NPCX_CLK_CTRL_NODE DT_NODELABEL(pcc)
36 #define OFMCLK DT_PROP(DT_NODELABEL(pcc), clock_frequency)
38 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
40 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
42 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
44 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
46 #if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
48 #define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
56 #define NPCX_PWDWN_CTL_INIT DT_FOREACH_PROP_ELEM(DT_NODELABEL(pcc), \
72 #define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler))
/Zephyr-latest/dts/arm/nuvoton/
Dm46x.dtsi60 pcc: peripheral-clock-controller { label
61 compatible = "nuvoton,numaker-pcc";
92 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC
102 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC
112 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC
122 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC
132 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC
142 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC
152 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC
162 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC
[all …]
Dm2l31x.dtsi54 pcc: peripheral-clock-controller { label
55 compatible = "nuvoton,numaker-pcc";
84 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC
94 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC
104 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC
114 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC
124 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC
134 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC
144 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC
154 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx.dtsi66 pcc: clock-controller@4000d000 { label
67 compatible = "nuvoton,npcx-pcc";
255 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 0>;
264 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 1>;
273 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 2>;
282 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 3>;
291 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 4>;
300 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 5>;
309 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>;
318 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 7>;
[all …]
Dnpcx4.dtsi100 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0
101 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
111 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4
112 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 0>;
122 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>;
133 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4
134 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 2>;
145 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3
146 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 3>;
152 pcc: clock-controller@4000d000 { label
[all …]
Dnpcx9.dtsi98 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0
99 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
109 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4
110 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 0>;
121 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6
122 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 1>;
133 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4
134 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 2>;
145 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3
146 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 3>;
[all …]
Dnpcx7.dtsi97 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 3
98 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>;
106 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL1 4>;
115 clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 6>;
121 pcc: clock-controller@4000d000 { label
274 clocks = <&pcc NPCX_CLOCK_BUS_FIU NPCX_PWDWN_CTL1 2>;
281 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>;
/Zephyr-latest/dts/arm/nxp/
Dnxp_ke1xz.dtsi121 pcc: pcc@40065000 { label
122 compatible = "nxp,kinetis-pcc";
148 clocks = <&pcc 0xec KINETIS_PCC_SRC_SIRC_ASYNC>;
159 clocks = <&pcc 0x1a8 KINETIS_PCC_SRC_FIRC_ASYNC>;
167 clocks = <&pcc 0x1ac KINETIS_PCC_SRC_FIRC_ASYNC>;
175 clocks = <&pcc 0x1b0 KINETIS_PCC_SRC_FIRC_ASYNC>;
192 clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>;
198 clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>;
204 clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>;
210 clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>;
[all …]
Dnxp_ke1xf.dtsi261 pcc: pcc@40065000 { label
262 compatible = "nxp,kinetis-pcc";
332 clocks = <&pcc 0x1a8 KINETIS_PCC_SRC_FIRC_ASYNC>;
343 clocks = <&pcc 0x1ac KINETIS_PCC_SRC_FIRC_ASYNC>;
354 clocks = <&pcc 0x1b0 KINETIS_PCC_SRC_FIRC_ASYNC>;
367 clocks = <&pcc 0x198 KINETIS_PCC_SRC_FIRC_ASYNC>;
378 clocks = <&pcc 0x19c KINETIS_PCC_SRC_FIRC_ASYNC>;
386 clocks = <&pcc 0xb0 KINETIS_PCC_SRC_FIRC_ASYNC>;
396 clocks = <&pcc 0xb4 KINETIS_PCC_SRC_FIRC_ASYNC>;
427 clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>;
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_numaker_scc.c33 CLK_EnableModuleClock(scc_subsys->pcc.clk_modidx); in numaker_scc_on()
50 CLK_DisableModuleClock(scc_subsys->pcc.clk_modidx); in numaker_scc_off()
87 CLK_SetModuleClock(scc_subsys->pcc.clk_modidx, scc_subsys->pcc.clk_src, in numaker_scc_configure()
88 scc_subsys->pcc.clk_div); in numaker_scc_configure()
Dclock_control_npcm.c89 #define OFMCLK DT_PROP(DT_NODELABEL(pcc), clock_frequency)
91 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
93 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
95 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
97 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
99 #define AHB6DIV_VAL (DT_PROP(DT_NODELABEL(pcc), ahb6_prescaler) - 1)
101 #define FIUDIV_VAL (DT_PROP(DT_NODELABEL(pcc), fiu_prescaler) - 1)
103 #define I3CDIV_VAL (DT_PROP(DT_NODELABEL(pcc), i3c_prescaler) - 1)
106 #define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler))
/Zephyr-latest/dts/arm/nuvoton/npcm/
Dnpcm.dtsi38 pcc: clock-controller@4000d000 { label
39 compatible = "nuvoton,npcm-pcc";
Dnpcm4.dtsi26 pcc: clock-controller@4000d000 { label
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dclock_control_numaker.h37 } pcc; member
/Zephyr-latest/drivers/watchdog/
Dwdt_wwdt_numaker.c260 scc_subsys.pcc.clk_modidx = cfg->clk_modidx; in wwdt_numaker_init()
261 scc_subsys.pcc.clk_src = cfg->clk_src; in wwdt_numaker_init()
262 scc_subsys.pcc.clk_div = cfg->clk_div; in wwdt_numaker_init()
/Zephyr-latest/drivers/can/
Dcan_numaker.c89 scc_subsys.pcc.clk_modidx = config->clk_modidx; in can_numaker_init_unlocked()
90 scc_subsys.pcc.clk_src = config->clk_src; in can_numaker_init_unlocked()
91 scc_subsys.pcc.clk_div = config->clk_div; in can_numaker_init_unlocked()
/Zephyr-latest/drivers/spi/
Dspi_numaker.c304 scc_subsys.pcc.clk_modidx = dev_cfg->clk_modidx; in spi_numaker_init()
305 scc_subsys.pcc.clk_src = dev_cfg->clk_src; in spi_numaker_init()
306 scc_subsys.pcc.clk_div = dev_cfg->clk_div; in spi_numaker_init()
/Zephyr-latest/drivers/adc/
Dadc_numaker.c332 scc_subsys.pcc.clk_modidx = cfg->clk_modidx; in adc_numaker_init()
333 scc_subsys.pcc.clk_src = cfg->clk_src; in adc_numaker_init()
334 scc_subsys.pcc.clk_div = cfg->clk_div; in adc_numaker_init()
/Zephyr-latest/drivers/serial/
Duart_numaker.c199 scc_subsys.pcc.clk_modidx = config->clk_modidx; in uart_numaker_init()
200 scc_subsys.pcc.clk_src = config->clk_src; in uart_numaker_init()
201 scc_subsys.pcc.clk_div = config->clk_div; in uart_numaker_init()
/Zephyr-latest/dts/xtensa/nxp/
Dnxp_imx8ulp.dtsi46 compatible = "nxp,kinetis-pcc";
/Zephyr-latest/drivers/pwm/
Dpwm_numaker.c481 scc_subsys.pcc.clk_modidx = cfg->clk_modidx; in pwm_numaker_init()
482 scc_subsys.pcc.clk_src = cfg->clk_src; in pwm_numaker_init()
483 scc_subsys.pcc.clk_div = cfg->clk_div; in pwm_numaker_init()
/Zephyr-latest/drivers/ethernet/
Deth_numaker.c723 scc_subsys.pcc.clk_modidx = cfg->clk_modidx; in eth_numaker_init()
724 scc_subsys.pcc.clk_src = cfg->clk_src; in eth_numaker_init()
725 scc_subsys.pcc.clk_div = cfg->clk_div; in eth_numaker_init()
/Zephyr-latest/drivers/i2c/
Di2c_numaker.c696 scc_subsys.pcc.clk_modidx = config->clk_modidx; in i2c_numaker_init()
697 scc_subsys.pcc.clk_src = config->clk_src; in i2c_numaker_init()
698 scc_subsys.pcc.clk_div = config->clk_div; in i2c_numaker_init()
/Zephyr-latest/drivers/gpio/
Dgpio_numaker.c259 scc_subsys.pcc.clk_modidx = config->clk_modidx; \
/Zephyr-latest/dts/riscv/openisa/
Drv32m1.dtsi61 compatible = "openisa,rv32m1-pcc";
67 compatible = "openisa,rv32m1-pcc";

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