Searched refs:core_clk (Results 1 – 25 of 25) sorted by relevance
| /Zephyr-latest/soc/nxp/kinetis/ke1xf/ |
| D | soc.c | 39 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(spll_clk))
41 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(core_clk), 1, 4,
44 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(core_clk), 1, 16,
50 .divCore = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(core_clk)),
51 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sosc_clk))
53 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sirc_clk))
55 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(firc_clk))
57 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(spll_clk))
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| /Zephyr-latest/soc/nxp/kinetis/ke1xz/ |
| D | soc.c | 36 ASSERT_WITHIN_RANGE(SCG_CLOCK_DIV(core_clk), 1, 16,
41 .divCore = TO_SYS_CLK_DIV(SCG_CLOCK_DIV(core_clk)),
42 #if DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sirc_clk))
44 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(firc_clk))
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_rcar.c | 56 struct rcar_cpg_clk core_clk; member
236 ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->core_clk, in pwm_rcar_init()
260 .core_clk.module = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
261 .core_clk.domain = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
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| /Zephyr-latest/soc/nxp/kinetis/kwx/ |
| D | soc_kw4xz.c | 40 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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| D | soc_kw2xd.c | 67 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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| /Zephyr-latest/tests/drivers/pwm/pwm_loopback/boards/ |
| D | frdm_ke17z.overlay | 57 core_clk {
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| D | frdm_ke17z512.overlay | 57 core_clk {
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| /Zephyr-latest/soc/nxp/kinetis/k2x/ |
| D | soc.c | 67 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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| /Zephyr-latest/soc/nxp/kinetis/kl2x/ |
| D | soc.c | 39 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) | in clock_init()
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| /Zephyr-latest/soc/nxp/kinetis/kv5x/ |
| D | soc.c | 60 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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| /Zephyr-latest/soc/nxp/kinetis/k8x/ |
| D | soc.c | 63 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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| /Zephyr-latest/soc/nxp/kinetis/k6x/ |
| D | soc.c | 70 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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| /Zephyr-latest/soc/nxp/mcx/mcxc/ |
| D | soc.c | 65 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_ke1xf.dtsi | 165 core_clk: core_clk { label
174 clocks = <&core_clk>;
181 clocks = <&core_clk>;
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| D | nxp_ke1xz.dtsi | 92 core_clk: core_clk { label
101 clocks = <&core_clk>;
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| D | nxp_kl25z.dtsi | 89 core_clk {
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| D | nxp_kw40z.dtsi | 63 core_clk {
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| D | nxp_kw41z.dtsi | 70 core_clk {
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| D | nxp_kv5x.dtsi | 48 core_clk {
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| D | nxp_kw2xd.dtsi | 86 core_clk {
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| D | nxp_mcxc_common.dtsi | 94 core_clk {
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| D | nxp_k2x.dtsi | 87 core_clk {
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| D | nxp_k8x.dtsi | 53 core_clk {
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| D | nxp_k6x.dtsi | 117 core_clk {
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| /Zephyr-latest/boards/nxp/twr_ke18f/ |
| D | twr_ke18f.dts | 169 core_clk {
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