1/*
2 * Copyright (c) 2018 Prevas A/S
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/kinetis_sim.h>
11#include <zephyr/dt-bindings/clock/kinetis_mcg.h>
12#include <zephyr/dt-bindings/gpio/gpio.h>
13#include <zephyr/dt-bindings/i2c/i2c.h>
14
15/ {
16	chosen {
17		zephyr,entropy = &rnga;
18		zephyr,flash-controller = &ftfe;
19	};
20
21	aliases {
22		watchdog0 = &wdog;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu@0 {
30			device_type = "cpu";
31			compatible = "arm,cortex-m4f";
32			reg = <0>;
33		};
34	};
35
36	/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
37	 * contiguous block in the memory map, however misaligned accesses
38	 * across the 0x2000_0000 boundary are not supported in the Arm
39	 * Cortex-M4 architecture. For clarity and to avoid the temptation for
40	 * someone to extend sram0 without solving this issue, we define two
41	 * separate memory nodes here and only use the upper one for now. A
42	 * potential solution has been proposed in binutils:
43	 * https://sourceware.org/ml/binutils/2017-02/msg00250.html
44	 */
45	sram_l: memory@1fff0000 {
46		compatible = "zephyr,memory-region", "mmio-sram";
47		reg = <0x1fff0000 DT_SIZE_K(64)>;
48		zephyr,memory-region = "SRAML";
49	};
50
51	sram0: memory@20000000 {
52		compatible = "mmio-sram";
53		reg = <0x20000000 DT_SIZE_K(64)>;
54	};
55
56	/* Dummy pinctrl node, filled with pin mux options at board level */
57	pinctrl: pinctrl {
58		compatible = "nxp,port-pinctrl";
59		status = "okay";
60	};
61
62	soc {
63		mcg: clock-controller@40064000 {
64			compatible = "nxp,kinetis-mcg";
65			reg = <0x40064000 0xd>;
66			#clock-cells = <1>;
67		};
68
69		osc: clock-controller@40065000 {
70			compatible = "nxp,k22f-osc";
71			reg = <0x40065000 0x4>;
72
73			enable-external-reference;
74		};
75
76		rtc: rtc@4003d000 {
77			compatible = "nxp,k22f-rtc";
78			reg = <0x4003d000 0x808>;
79			clock-frequency = <32768>;
80		};
81
82		sim: sim@40047000 {
83			compatible = "nxp,kinetis-sim";
84			reg = <0x40047000 0x1060>;
85			#clock-cells = <3>;
86
87			core_clk {
88				compatible = "fixed-factor-clock";
89				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
90				clock-div = <1>;
91				#clock-cells = <0>;
92			};
93
94			bus_clk {
95				compatible = "fixed-factor-clock";
96				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
97				clock-div = <2>;
98				#clock-cells = <0>;
99			};
100
101			flexbus_clk {
102				compatible = "fixed-factor-clock";
103				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
104				clock-div = <3>;
105				#clock-cells = <0>;
106			};
107
108			flash_clk {
109				compatible = "fixed-factor-clock";
110				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
111				clock-div = <3>;
112				#clock-cells = <0>;
113			};
114		};
115
116		ftfe: flash-controller@40020000 {
117			compatible = "nxp,kinetis-ftfe";
118			reg = <0x40020000 0x18>;
119			interrupts = <18 0>, <19 0>;
120			interrupt-names = "command-complete", "read-collision";
121			status = "okay";
122
123			#address-cells = <1>;
124			#size-cells = <1>;
125
126			flash0: flash@0 {
127				compatible = "soc-nv-flash";
128				reg = <0 DT_SIZE_M(1)>;
129				erase-block-size = <2048>;
130				write-block-size = <8>;
131			};
132		};
133
134		i2c0: i2c@40066000 {
135			compatible = "nxp,kinetis-i2c";
136			clock-frequency = <I2C_BITRATE_STANDARD>;
137			#address-cells = <1>;
138			#size-cells = <0>;
139			reg = <0x40066000 0x1000>;
140			interrupts = <24 0>;
141			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
142			status = "disabled";
143		};
144
145		i2c1: i2c@40067000 {
146			compatible = "nxp,kinetis-i2c";
147			clock-frequency = <I2C_BITRATE_STANDARD>;
148			#address-cells = <1>;
149			#size-cells = <0>;
150			reg = <0x40067000 0x1000>;
151			interrupts = <25 0>;
152			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
153			status = "disabled";
154		};
155
156		uart0: uart@4006a000 {
157			compatible = "nxp,kinetis-uart";
158			reg = <0x4006a000 0x1000>;
159			interrupts = <31 0>, <32 0>;
160			interrupt-names = "status", "error";
161			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
162
163			status = "disabled";
164		};
165
166		uart1: uart@4006b000 {
167			compatible = "nxp,kinetis-uart";
168			reg = <0x4006b000 0x1000>;
169			interrupts = <33 0>, <34 0>;
170			interrupt-names = "status", "error";
171			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
172
173			status = "disabled";
174		};
175
176		uart2: uart@4006c000 {
177			compatible = "nxp,kinetis-uart";
178			reg = <0x4006c000 0x1000>;
179			interrupts = <35 0>, <36 0>;
180			interrupt-names = "status", "error";
181			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
182
183			status = "disabled";
184		};
185
186		uart3: uart@4006d000 {
187			compatible = "nxp,kinetis-uart";
188			reg = <0x4006d000 0x1000>;
189			interrupts = <37 0>, <38 0>;
190			interrupt-names = "status", "error";
191			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
192
193			status = "disabled";
194		};
195
196		porta: pinmux@40049000 {
197			compatible = "nxp,port-pinmux";
198			reg = <0x40049000 0xd0>;
199			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
200		};
201
202		portb: pinmux@4004a000 {
203			compatible = "nxp,port-pinmux";
204			reg = <0x4004a000 0xd0>;
205			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
206		};
207
208		portc: pinmux@4004b000 {
209			compatible = "nxp,port-pinmux";
210			reg = <0x4004b000 0xd0>;
211			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
212		};
213
214		portd: pinmux@4004c000 {
215			compatible = "nxp,port-pinmux";
216			reg = <0x4004c000 0xd0>;
217			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
218		};
219
220		porte: pinmux@4004d000 {
221			compatible = "nxp,port-pinmux";
222			reg = <0x4004d000 0xd0>;
223			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
224		};
225
226		gpioa: gpio@400ff000 {
227			compatible = "nxp,kinetis-gpio";
228			status = "disabled";
229			reg = <0x400ff000 0x40>;
230			interrupts = <59 2>;
231			gpio-controller;
232			#gpio-cells = <2>;
233			nxp,kinetis-port = <&porta>;
234		};
235
236		gpiob: gpio@400ff040 {
237			compatible = "nxp,kinetis-gpio";
238			status = "disabled";
239			reg = <0x400ff040 0x40>;
240			interrupts = <60 2>;
241			gpio-controller;
242			#gpio-cells = <2>;
243			nxp,kinetis-port = <&portb>;
244		};
245
246		gpioc: gpio@400ff080 {
247			compatible = "nxp,kinetis-gpio";
248			status = "disabled";
249			reg = <0x400ff080 0x40>;
250			interrupts = <61 2>;
251			gpio-controller;
252			#gpio-cells = <2>;
253			nxp,kinetis-port = <&portc>;
254		};
255
256		gpiod: gpio@400ff0c0 {
257			compatible = "nxp,kinetis-gpio";
258			status = "disabled";
259			reg = <0x400ff0c0 0x40>;
260			interrupts = <62 2>;
261			gpio-controller;
262			#gpio-cells = <2>;
263			nxp,kinetis-port = <&portd>;
264		};
265
266		gpioe: gpio@400ff100 {
267			compatible = "nxp,kinetis-gpio";
268			status = "disabled";
269			reg = <0x400ff100 0x40>;
270			interrupts = <63 2>;
271			gpio-controller;
272			#gpio-cells = <2>;
273			nxp,kinetis-port = <&porte>;
274		};
275
276		spi0: spi@4002c000 {
277			compatible = "nxp,dspi";
278			reg = <0x4002c000 0x88>;
279			interrupts = <26 3>;
280			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
281			#address-cells = <1>;
282			#size-cells = <0>;
283			status = "disabled";
284		};
285
286		spi1: spi@4002d000 {
287			compatible = "nxp,dspi";
288			reg = <0x4002d000 0x88>;
289			interrupts = <27 3>;
290			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
291			#address-cells = <1>;
292			#size-cells = <0>;
293			status = "disabled";
294		};
295
296		wdog: watchdog@40052000 {
297			compatible = "nxp,kinetis-wdog";
298			reg = <0x40052000 16>;
299			interrupts = <22 0>;
300			clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
301		};
302
303		ftm0: ftm@40038000{
304			compatible = "nxp,ftm";
305			reg = <0x40038000 0x98>;
306			interrupts = <42 0>;
307			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>,
308					 <&sim KINETIS_SIM_BUS_CLK 0x103C 24>;
309			prescaler = <16>;
310			status = "disabled";
311		};
312
313		ftm1: ftm@40039000{
314			compatible = "nxp,ftm";
315			reg = <0x40039000 0x98>;
316			interrupts = <43 0>;
317			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>,
318					 <&sim KINETIS_SIM_BUS_CLK 0x103C 25>;
319			prescaler = <16>;
320			status = "disabled";
321		};
322
323		ftm2: ftm@4003a000{
324			compatible = "nxp,ftm";
325			reg = <0x4003a000 0x98>;
326			interrupts = <44 0>;
327			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>,
328					 <&sim KINETIS_SIM_BUS_CLK 0x103C 26>;
329			prescaler = <16>;
330			status = "disabled";
331		};
332
333		ftm3: ftm@400b9000{
334			compatible = "nxp,ftm";
335			reg = <0x400b9000 0x98>;
336			interrupts = <71 0>;
337			clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>,
338					 <&sim KINETIS_SIM_BUS_CLK 0x103C 6>;
339			prescaler = <16>;
340			status = "disabled";
341		};
342
343		adc0: adc@4003b000{
344			compatible = "nxp,kinetis-adc16";
345			reg = <0x4003b000 0x70>;
346			interrupts = <39 0>;
347			status = "disabled";
348			#io-channel-cells = <1>;
349		};
350
351		dac0: dac@4003f000 {
352			compatible = "nxp,kinetis-dac";
353			reg = <0x4003f000 0x1000>;
354			interrupts = <56 0>;
355			voltage-reference = <1>;
356			status = "disabled";
357			#io-channel-cells = <1>;
358		};
359
360		dac1: dac@40028000 {
361			compatible = "nxp,kinetis-dac";
362			reg = <0x40028000 0x1000>;
363			interrupts = <72 0>;
364			voltage-reference = <1>;
365			status = "disabled";
366			#io-channel-cells = <1>;
367		};
368
369		usbotg: usbd@40072000 {
370			compatible = "nxp,kinetis-usbd";
371			reg = <0x40072000 0x1000>;
372			interrupts = <53 1>;
373			interrupt-names = "usb_otg";
374			num-bidir-endpoints = <16>;
375			status = "disabled";
376		};
377
378		rnga: random@40029000 {
379			compatible = "nxp,kinetis-rnga";
380			reg = <0x40029000 0x1000>;
381			status = "okay";
382			interrupts = <23 0>;
383		};
384	};
385};
386
387&nvic {
388	arm,num-irq-priority-bits = <4>;
389};
390