1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7&pinctrl {
8	ftm0_default: ftm0_default {
9		group0 {
10			pinmux = <FTM0_CH6_PTA17>,
11				<FTM0_CH2_PTB14>;
12			drive-strength = "low";
13			slew-rate = "slow";
14		};
15	};
16
17	pwt_default: pwt_default {
18		group0 {
19			pinmux = <PWT_IN1_PTE11>;
20			drive-strength = "low";
21			slew-rate = "slow";
22		};
23	};
24};
25
26/* To test this sample, connect
27 * PTB14(J3-11) ---> PTE11(J2-2)
28 */
29
30/ {
31	pwm_loopback_0 {
32		compatible = "test-pwm-loopback";
33		pwms = <&ftm0 2 0 PWM_POLARITY_NORMAL>, /* PTB14 J3 pin 11 */
34			<&pwt 1 0 PWM_POLARITY_NORMAL>; /* PTE11 J2 pin 2 */
35	};
36};
37
38&ftm0 {
39	status = "okay";
40	compatible = "nxp,ftm-pwm";
41	clocks = <&scg KINETIS_SCG_SIRC_CLK>;
42	prescaler = <128>;
43	#pwm-cells = <3>;
44	pinctrl-0 = <&ftm0_default>;
45	pinctrl-names = "default";
46	clock-source = "system";
47};
48
49&pwt {
50	status = "okay";
51	prescaler = <32>;
52	pinctrl-0 = <&pwt_default>;
53	pinctrl-names = "default";
54};
55
56&scg {
57	core_clk {
58		clocks = <&sirc_clk>;
59	};
60
61	bus_clk {
62		clock-div = <2>;
63	};
64};
65