1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv6-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/kinetis_sim.h>
11#include <zephyr/dt-bindings/clock/kinetis_mcg.h>
12#include <zephyr/dt-bindings/gpio/gpio.h>
13#include <zephyr/dt-bindings/i2c/i2c.h>
14#include <zephyr/dt-bindings/pwm/pwm.h>
15
16/ {
17	chosen {
18		zephyr,flash-controller = &ftfa;
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		cpu0: cpu@0 {
26			device_type = "cpu";
27			compatible = "arm,cortex-m0+";
28			reg = <0>;
29		};
30	};
31
32	sram0: memory@1FFFF000 {
33		compatible = "mmio-sram";
34	};
35
36	/* Dummy pinctrl node, filled with pin mux options at board level */
37	pinctrl: pinctrl {
38		compatible = "nxp,port-pinctrl";
39		status = "okay";
40	};
41
42	clocks {
43		osc: osc {
44			compatible = "nxp,mcxc-osc";
45			#clock-cells = <0>;
46			load-capacitance-picofarads = <0>;
47			mode = "external";
48		};
49	};
50
51	temp0: temp0 {
52		compatible = "nxp,kinetis-temperature";
53		io-channels = <&adc0 26>, <&adc0 27>;
54		io-channel-names = "SENSOR", "BANDGAP";
55		bandgap-voltage = <1000000>;
56		vtemp25 = <716000>;
57		sensor-slope-cold = <1620>;
58		sensor-slope-hot = <1620>;
59		status = "disabled";
60	};
61
62	soc {
63		ftfa: flash-controller@40020000 {
64			compatible = "nxp,kinetis-ftfa";
65			reg = <0x40020000 0x14>;
66			interrupts = <5 0>;
67			status = "disabled";
68			#address-cells = <1>;
69			#size-cells = <1>;
70			fsec = <0xfe>;
71			fopt = <0x3d>;
72			config-field-offset = <0x400>;
73
74			flash0: flash@0 {
75				compatible = "soc-nv-flash";
76				erase-block-size = <1024>;
77				write-block-size = <4>;
78			};
79		};
80
81		mcg: clock-controller@40064000 {
82			compatible = "nxp,kinetis-mcg";
83			reg = <0x40064000 0xd>;
84			fcrdiv = <0>;
85			lircdiv2 = <0>;
86			#clock-cells = <1>;
87		};
88
89		sim: sim@40047000 {
90			compatible = "nxp,kinetis-sim";
91			reg = <0x40047000 0x1060>;
92			#clock-cells = <3>;
93
94			core_clk {
95				compatible = "fixed-factor-clock";
96				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
97				clock-div = <1>;
98				#clock-cells = <0>;
99			};
100
101			flash_clk {
102				compatible = "fixed-factor-clock";
103				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
104				clock-div = <2>;
105				#clock-cells = <0>;
106			};
107		};
108
109		porta: pinmux@40049000 {
110			compatible = "nxp,port-pinmux";
111			reg = <0x40049000 0xd0>;
112			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
113		};
114
115		portb: pinmux@4004a000 {
116			compatible = "nxp,port-pinmux";
117			reg = <0x4004a000 0xd0>;
118			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
119		};
120
121		portc: pinmux@4004b000 {
122			compatible = "nxp,port-pinmux";
123			reg = <0x4004b000 0xd0>;
124			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
125		};
126
127		portd: pinmux@4004c000 {
128			compatible = "nxp,port-pinmux";
129			reg = <0x4004c000 0xd0>;
130			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
131		};
132
133		porte: pinmux@4004d000 {
134			compatible = "nxp,port-pinmux";
135			reg = <0x4004d000 0xd0>;
136			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
137		};
138
139		gpioa: gpio@400ff000 {
140			compatible = "nxp,kinetis-gpio";
141			status = "disabled";
142			reg = <0x400ff000 0x40>;
143			interrupts = <30 2>;
144			gpio-controller;
145			#gpio-cells = <2>;
146			nxp,kinetis-port = <&porta>;
147		};
148
149		gpiob: gpio@400ff040 {
150			compatible = "nxp,kinetis-gpio";
151			status = "disabled";
152			reg = <0x400ff040 0x40>;
153			gpio-controller;
154			#gpio-cells = <2>;
155			nxp,kinetis-port = <&portb>;
156		};
157
158		gpioc: gpio@400ff080 {
159			compatible = "nxp,kinetis-gpio";
160			status = "disabled";
161			reg = <0x400ff080 0x40>;
162			interrupts = <31 2>;
163			gpio-controller;
164			#gpio-cells = <2>;
165			nxp,kinetis-port = <&portc>;
166		};
167
168		gpiod: gpio@400ff0c0 {
169			compatible = "nxp,kinetis-gpio";
170			status = "disabled";
171			reg = <0x400ff0c0 0x40>;
172			gpio-controller;
173			#gpio-cells = <2>;
174			nxp,kinetis-port = <&portd>;
175		};
176
177		gpioe: gpio@400ff100 {
178			compatible = "nxp,kinetis-gpio";
179			status = "disabled";
180			reg = <0x400ff100 0x40>;
181			gpio-controller;
182			#gpio-cells = <2>;
183			nxp,kinetis-port = <&porte>;
184		};
185
186		adc0: adc@4003b000{
187			compatible = "nxp,kinetis-adc16";
188			reg = <0x4003b000 0x70>;
189			interrupts = <15 0>;
190			status = "disabled";
191			#io-channel-cells = <1>;
192		};
193
194		i2c0: i2c@40066000 {
195			compatible = "nxp,kinetis-i2c";
196			clock-frequency = <I2C_BITRATE_STANDARD>;
197			#address-cells = <1>;
198			#size-cells = <0>;
199			reg = <0x40066000 0x1000>;
200			interrupts = <8 0>;
201			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
202			status = "disabled";
203		};
204
205		i2c1: i2c@40067000 {
206			compatible = "nxp,kinetis-i2c";
207			clock-frequency = <I2C_BITRATE_STANDARD>;
208			#address-cells = <1>;
209			#size-cells = <0>;
210			reg = <0x40067000 0x1000>;
211			interrupts = <9 0>;
212			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
213			status = "disabled";
214		};
215
216		usb: usbd@40072000 {
217			compatible = "nxp,kinetis-usbd";
218			reg = <0x40072000 0x1000>;
219			interrupts = <24 1>;
220			interrupt-names = "usb";
221			num-bidir-endpoints = <16>;
222			status = "disabled";
223		};
224
225		lpuart0: uart@40054000 {
226			compatible = "nxp,lpuart";
227			reg = <0x40054000 0x1000>;
228			interrupts = <12 0>;
229			clocks = <&sim KINETIS_SIM_MCGPCLK 0x1038 20>;
230			status = "disabled";
231		};
232
233		lpuart1: uart@40055000 {
234			compatible = "nxp,lpuart";
235			reg = <0x40055000 0x1000>;
236			interrupts = <13 0>;
237			clocks = <&sim KINETIS_SIM_MCGPCLK 0x1038 21>;
238			status = "disabled";
239		};
240
241		uart2: uart@4006c000 {
242			compatible = "nxp,kinetis-uart";
243			reg = <0x4006c000 0x1000>;
244			interrupts = <14 0>;
245			interrupt-names = "status";
246			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
247			status = "disabled";
248		};
249
250		tpm0: pwm@40038000 {
251			compatible = "nxp,kinetis-tpm";
252			reg = <0x40038000 0x88>;
253			interrupts = <17 0>;
254			clocks = <&sim KINETIS_SIM_MCGPCLK 0x103C 24>;
255			prescaler = <16>;
256			status = "disabled";
257			#pwm-cells = <3>;
258		};
259
260		tpm1: pwm@40039000 {
261			compatible = "nxp,kinetis-tpm";
262			reg = <0x40039000 0x88>;
263			interrupts = <18 0>;
264			clocks = <&sim KINETIS_SIM_MCGPCLK 0x103C 25>;
265			prescaler = <16>;
266			status = "disabled";
267			#pwm-cells = <3>;
268		};
269
270		tpm2: pwm@4003a000 {
271			compatible = "nxp,kinetis-tpm";
272			reg = <0x4003a000 0x88>;
273			interrupts = <19 0>;
274			clocks = <&sim KINETIS_SIM_MCGPCLK 0x103C 26>;
275			prescaler = <16>;
276			status = "disabled";
277			#pwm-cells = <3>;
278		};
279
280		lptmr0: lptmr@40040000 {
281			compatible = "nxp,lptmr";
282			reg = <0x40040000 0x1000>;
283			interrupts = <28 0>;
284			clock-frequency = <1000>;
285			prescaler = <1>;
286			prescale-glitch-filter = <1>;
287			clk-source = <1>;
288			resolution = <16>;
289			status = "disabled";
290		};
291
292		rtc: rtc@4003d000 {
293			compatible = "nxp,rtc";
294			reg = <0x4003d000 0x1000>;
295			interrupts = <20 0>, <21 0>;
296			interrupt-names = "alarm", "seconds";
297			clock-frequency = <32768>;
298			prescaler = <32768>;
299			status = "disabled";
300		};
301
302		pit0: pit@40037000 {
303			compatible = "nxp,pit";
304			reg = <0x40037000 0x1000>;
305			clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>;
306			interrupts = <22 0>;
307			max-load-value = <0xffffffff>;
308			status = "disabled";
309			#address-cells = <1>;
310			#size-cells = <0>;
311
312			pit0_channel0: pit0_channel@0 {
313				compatible = "nxp,pit-channel";
314				reg = <0>;
315				status = "disabled";
316			};
317
318			pit0_channel1: pit0_channel@1 {
319				compatible = "nxp,pit-channel";
320				reg = <1>;
321				status = "disabled";
322			};
323		};
324	};
325};
326
327&nvic {
328	arm,num-irq-priority-bits = <2>;
329};
330