| /Zephyr-latest/kernel/ |
| D | Kconfig.obj_core | 5 bool "Object core framework"
8 This option enables the object core framework. This will link
16 bool "Integrate condition variables into object core framework"
20 object core framework.
23 bool "Integrate events into object core framework"
27 core framework.
30 bool "Integrate FIFOs into object core framework"
33 When enabled, this option integrates FIFOs into the object core
37 bool "Integrate LIFOs into object core framework"
40 When enabled, this option integrates LIFOs into the object core
[all …]
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/include/ |
| D | _soc_inthandlers.h | 11 #error core-isa.h interrupt level does not match dispatcher!
14 #error core-isa.h interrupt level does not match dispatcher!
17 #error core-isa.h interrupt level does not match dispatcher!
20 #error core-isa.h interrupt level does not match dispatcher!
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_intel_adsp.h | 89 static inline void intel_adsp_wdt_pause(uint32_t base, const uint32_t core) in intel_adsp_wdt_pause() argument
91 const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core); in intel_adsp_wdt_pause()
108 static inline void intel_adsp_wdt_resume(uint32_t base, const uint32_t core) in intel_adsp_wdt_resume() argument
110 const uint32_t reg_addr = base + DSPCxWDTCS + DSPBRx_OFFSET(core); in intel_adsp_wdt_resume()
127 static inline void intel_adsp_wdt_reset_set(uint32_t base, const uint32_t core, const bool enable) in intel_adsp_wdt_reset_set() argument
129 sys_write32(enable ? DSPCxWDTCS_STORE : 0, base + DSPCxWDTCS + DSPBRx_OFFSET(core)); in intel_adsp_wdt_reset_set()
149 static inline uint32_t intel_adsp_wdt_pointer_get(uint32_t base, const uint32_t core) in intel_adsp_wdt_pointer_get() argument
151 return FIELD_GET(DSPCxWDTIPPTR_PTR, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core))); in intel_adsp_wdt_pointer_get()
162 static inline uint32_t intel_adsp_wdt_version_get(uint32_t base, const uint32_t core) in intel_adsp_wdt_version_get() argument
164 return FIELD_GET(DSPCxWDTIPPTR_VER, sys_read32(base + DSPCxWDTIPPTR + DSPBRx_OFFSET(core))); in intel_adsp_wdt_version_get()
|
| /Zephyr-latest/soc/nxp/imx/imx8x/adsp/ |
| D | _soc_inthandlers.h | 23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
50 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/soc/nxp/imx/imx8/adsp/ |
| D | _soc_inthandlers.h | 23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
50 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/soc/nxp/imx/imx8m/adsp/ |
| D | _soc_inthandlers.h | 23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
50 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/ |
| D | _soc_inthandlers.h | 23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
47 #error core-isa.h interrupt level does not match dispatcher!
50 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/soc/espressif/common/include/ |
| D | _soc_inthandlers.h | 24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
48 #error core-isa.h interrupt level does not match dispatcher!
51 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/soc/cdns/xtensa_sample_controller/include/ |
| D | _soc_inthandlers.h | 17 #error core-isa.h interrupt level does not match dispatcher!
20 #error core-isa.h interrupt level does not match dispatcher!
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
44 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/soc/cdns/sample_controller32/include/ |
| D | _soc_inthandlers.h | 24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
48 #error core-isa.h interrupt level does not match dispatcher!
51 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| /Zephyr-latest/soc/intel/intel_adsp/cavs/ |
| D | _soc_inthandlers.h | 22 #error core-isa.h interrupt level does not match dispatcher!
25 #error core-isa.h interrupt level does not match dispatcher!
28 #error core-isa.h interrupt level does not match dispatcher!
31 #error core-isa.h interrupt level does not match dispatcher!
34 #error core-isa.h interrupt level does not match dispatcher!
37 #error core-isa.h interrupt level does not match dispatcher!
40 #error core-isa.h interrupt level does not match dispatcher!
43 #error core-isa.h interrupt level does not match dispatcher!
46 #error core-isa.h interrupt level does not match dispatcher!
49 #error core-isa.h interrupt level does not match dispatcher!
[all …]
|
| D | multiprocessing.c | 35 IDC[cpu].core[i].tfc = BIT(31); in soc_mp_startup()
122 IDC[curr_cpu].core[cpu_num].ietc = ietc; in soc_start_core()
123 IDC[curr_cpu].core[cpu_num].itc = IDC_MSG_POWER_UP; in soc_start_core()
134 IDC[curr].core[c].itc = BIT(31); in send_ipi()
167 IDC[arch_proc_id()].core[i].tfc = BIT(31); in idc_isr()
181 for (int core = 0; core < num_cpus; core++) { in soc_mp_init() local
182 IDC[core].busy_int |= IDC_CORE_MASK(num_cpus); in soc_mp_init()
183 IDC[core].done_int &= ~IDC_CORE_MASK(num_cpus); in soc_mp_init()
188 CAVS_INTCTRL[core].l2.clear = CAVS_L2_IDC; in soc_mp_init()
194 IDC[i].core[j].tfc = BIT(31); in soc_mp_init()
|
| /Zephyr-latest/samples/subsys/ipc/rpmsg_service/ |
| D | README.rst | 14 perspective and code. Note that the remote and primary image core images can be
59 Master core received a message: 1
60 Master core received a message: 3
61 Master core received a message: 5
63 Master core received a message: 99
73 Remote core received a message: 0
74 Remote core received a message: 2
75 Remote core received a message: 4
77 Remote core received a message: 98
102 and network core images, the following messages (one for master and one for
[all …]
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| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | _soc_inthandlers.h | 21 #error core-isa.h interrupt level does not match dispatcher!
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
45 #error core-isa.h interrupt level does not match dispatcher!
|
| /Zephyr-latest/tests/ztest/fail/ |
| D | CMakeLists.txt | 10 # Set the target binary for the 'core' external project. The path to this must match the one set
12 add_compile_definitions(FAIL_TARGET_BINARY="${CMAKE_BINARY_DIR}/core/bin/testbinary")
16 # Set the target binary for the 'core' external project. The path to this must match the one set
18 add_compile_definitions(FAIL_TARGET_BINARY="${CMAKE_BINARY_DIR}/core/bin/zephyr.exe")
27 # 'core' project as a cmake argument.
35 # Add the 'core' external project which will mirror the configs of this project.
36 ExternalProject_Add(core
37 SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}/core
40 -DCMAKE_INSTALL_PREFIX:PATH=${CMAKE_BINARY_DIR}/core
43 add_dependencies(${target} core)
|
| /Zephyr-latest/samples/boards/nordic/nrf53_sync_rtc/ |
| D | README.rst | 4 Synchronize system and network core RTC clocks.
10 core are synchronized. The result of synchronization is an offset value on network
11 core which can be applied to the system tick for logging timestamping.
14 both cores. Application core periodically reads current system tick and stores it in
16 core. In the context of the IPC interrupt handler, network core is logging timestamp
19 and once procedure is completed timestamps are synchronized. Network core timestamp
63 [00:00:00.054,534] <inf> main: Local timestamp: 1787, application core timestamp: 10056
64 [00:00:00.104,553] <inf> main: Local timestamp: 3426, application core timestamp: 11695
65 [00:00:00.154,571] <inf> main: Local timestamp: 5065, application core timestamp: 13334
66 [00:00:00.204,589] <inf> main: Local timestamp: 6704, application core timestamp: 14973
[all …]
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| /Zephyr-latest/scripts/west_commands/runners/ |
| D | nrf_common.py | 24 from runners.core import RunnerCaps, ZephyrBinaryRunner
295 self.exec_op('recover', core='NRFDL_DEVICE_CORE_NETWORK')
304 core = None
320 core = 'NRFDL_DEVICE_CORE_APPLICATION'
322 core = 'NRFDL_DEVICE_CORE_NETWORK'
324 if generated_uicr and not self.hex_get_uicrs().get(core):
332 self.exec_op('erase', core='NRFDL_DEVICE_CORE_APPLICATION')
333 self.exec_op('erase', core='NRFDL_DEVICE_CORE_NETWORK')
357 core='NRFDL_DEVICE_CORE_APPLICATION',
365 core='NRFDL_DEVICE_CORE_NETWORK',
[all …]
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| /Zephyr-latest/include/zephyr/arch/arc/ |
| D | arch_inlines.h | 20 uint32_t core; in arch_curr_cpu() local
22 core = z_arc_v2_core_id(); in arch_curr_cpu()
24 return &_kernel.cpus[core]; in arch_curr_cpu()
|
| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | Kconfig.soc | 8 this option to target the RI5CY or ZERO-RISCY core. This
9 option should not be used to target either Arm core.
15 OpenISA RV32M1 RI5CY core
21 OpenISA RV32M1 ZERO-RISCY core
|
| /Zephyr-latest/samples/boards/nordic/coresight_stm/pytest/ |
| D | test_stm.py | 53 def _check_benchmark_results(output: str, core: str) -> None:
176 core='app',
182 core='rad',
189 core='ppr',
196 core='flpr',
237 core='app',
243 core='rad',
250 core='ppr',
257 core='flpr',
|
| /Zephyr-latest/samples/subsys/ipc/openamp/ |
| D | README.rst | 12 and code. Note that the remote and primary core images can be flashed
77 Master core received a message: 1
78 Master core received a message: 3
79 Master core received a message: 5
81 Master core received a message: 99
91 Remote core received a message: 0
92 Remote core received a message: 2
93 Remote core received a message: 4
95 Remote core received a message: 98
|
| /Zephyr-latest/boards/nordic/thingy53/doc/ |
| D | index.rst | 13 The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
15 * a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
17 the **application core**
18 * a secondary Arm Cortex-M33 core, with a reduced feature set, running at
19 a fixed 64 MHz, referred to as the **network core**.
22 core on the nRF5340 SoC. The ``thingy53/nrf5340/cpunet`` build target provides
23 support for the network core on the nRF5340 SoC.
|
| /Zephyr-latest/boards/snps/hsdk/support/ |
| D | openocd.cfg | 30 # Contains quad-core ARC HS38.
38 # CHIPNAME will be used to choose core family (600, 700 or EM). As far as
54 # ARC HS38 core 2
65 # Enable L2 cache support for core 2.
69 # ARC HS38 core 3
80 # Enable L2 cache support for core 3.
84 # ARC HS38 core 4
96 # Enable L2 cache support for core 4.
100 # ARC HS38 core 1
111 # Enable L2 cache support for core 1.
|
| /Zephyr-latest/boards/snps/hsdk4xd/support/ |
| D | openocd.cfg | 30 # Contains quad-core ARC HS4x.
38 # CHIPNAME will be used to choose core family (600, 700 or EM). As far as
54 # ARC HS4x core 2
65 # Enable L2 cache support for core 2.
69 # ARC HS4x core 3
80 # Enable L2 cache support for core 3.
84 # ARC HS4x core 4
96 # Enable L2 cache support for core 4.
100 # ARC HS4x core 1
111 # Enable L2 cache support for core 1.
|
| /Zephyr-latest/dts/arm/raspberrypi/rpi_pico/ |
| D | m33.dtsi | 9 /* Model in the device tree a Cortex-M33 core being 'plugged' into each
10 * 'socket' within the SoC. Within the datasheet these are core 0 and core 1.
|
