Home
last modified time | relevance | path

Searched refs:clock_dev (Results 1 – 25 of 124) sorted by relevance

12345

/Zephyr-latest/drivers/dac/
Ddac_esp32.c23 const struct device *clock_dev; member
61 if (!cfg->clock_dev) { in dac_esp32_init()
66 if (!device_is_ready(cfg->clock_dev)) { in dac_esp32_init()
71 if (clock_control_on(cfg->clock_dev, (clock_control_subsys_t)cfg->clock_subsys) != 0) { in dac_esp32_init()
88 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
/Zephyr-latest/drivers/clock_control/
Dclock_control_si32_ahb.c24 const struct device *clock_dev; member
58 if (!device_is_ready(config->clock_dev)) { in clock_control_si32_ahb_init()
65 ret = clock_control_set_rate(config->clock_dev, NULL, &freq); in clock_control_si32_ahb_init()
71 ret = clock_control_on(config->clock_dev, NULL); in clock_control_si32_ahb_init()
98 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Dclock_control_si32_apb.c19 const struct device *clock_dev; member
38 const int ret = clock_control_get_rate(config->clock_dev, NULL, rate); in clock_control_si32_apb_get_rate()
59 if (!device_is_ready(config->clock_dev)) { in clock_control_si32_apb_init()
75 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
/Zephyr-latest/tests/drivers/clock_control/nrf_onoff_and_bt/src/
Dmain.c22 static const struct device *const clock_dev = DEVICE_DT_GET_ONE(nordic_nrf_clock); variable
30 zassert_true(device_is_ready(clock_dev)); in setup()
124 check_hf_status(clock_dev, true, true); in ZTEST()
139 check_hf_status(clock_dev, false, true); in ZTEST()
210 check_hf_status(clock_dev, true, false); in ZTEST()
224 check_hf_status(clock_dev, false, true); in ZTEST()
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_nxp_port.c38 const struct device *clock_dev; member
60 if (!device_is_ready(config->clock_dev)) { in pinctrl_mcux_init()
65 err = clock_control_on(config->clock_dev, config->clock_subsys); in pinctrl_mcux_init()
89 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-latest/drivers/ethernet/eth_nxp_enet_qos/
Deth_nxp_enet_qos.c22 ret = clock_control_on(config->clock_dev, config->clock_subsys); in nxp_enet_qos_init()
35 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-latest/drivers/entropy/
Dentropy_esp32.c101 const struct device *clock_dev = in entropy_esp32_init() local
106 if (!device_is_ready(clock_dev)) { in entropy_esp32_init()
110 ret = clock_control_on(clock_dev, clock_subsys); in entropy_esp32_init()
/Zephyr-latest/drivers/pwm/
Dpwm_rv32m1_tpm.c28 const struct device *clock_dev; member
144 if (!device_is_ready(config->clock_dev)) { in rv32m1_tpm_init()
149 if (clock_control_on(config->clock_dev, config->clock_subsys)) { in rv32m1_tpm_init()
154 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in rv32m1_tpm_init()
191 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_mcux_tpm.c33 const struct device *clock_dev; member
149 if (!device_is_ready(config->clock_dev)) { in mcux_tpm_init()
154 if (clock_control_on(config->clock_dev, config->clock_subsys)) { in mcux_tpm_init()
159 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_tpm_init()
205 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_silabs_siwx91x.c32 const struct device *clock_dev; member
190 ret = clock_control_on(config->clock_dev, config->clock_subsys); in pwm_siwx91x_init()
195 ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &pwm_frequency); in pwm_siwx91x_init()
226 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
Dpwm_mcux.c26 const struct device *clock_dev; member
63 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_pwm_set_cycles_internal()
181 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_pwm_get_cycles_per_sec()
200 if (!device_is_ready(config->clock_dev)) { in pwm_mcux_init()
257 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-latest/drivers/i2c/
Di2c_rv32m1_lpi2c.c27 const struct device *clock_dev; member
86 err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq); in rv32m1_lpi2c_configure()
218 if (!device_is_ready(config->clock_dev)) { in rv32m1_lpi2c_init()
223 err = clock_control_on(config->clock_dev, config->clock_subsys); in rv32m1_lpi2c_init()
229 err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq); in rv32m1_lpi2c_init()
272 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
/Zephyr-latest/drivers/mdio/
Dmdio_nxp_imx_netc.c20 const struct device *clock_dev; member
70 err = clock_control_get_rate(cfg->clock_dev, cfg->clock_subsys, &mdio_config.srcClockHz); in nxp_imx_netc_mdio_initialize()
93 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dmdio_nxp_s32_gmac.c29 const struct device *clock_dev; member
124 if (!device_is_ready(cfg->clock_dev)) { in mdio_nxp_s32_init()
129 if (clock_control_get_rate(cfg->clock_dev, cfg->clock_subsys, &data->clock_freq)) { in mdio_nxp_s32_init()
165 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-latest/drivers/watchdog/
Dwdt_mcux_wdog.c23 const struct device *clock_dev; member
82 if (!device_is_ready(config->clock_dev)) { in mcux_wdog_install_timeout()
87 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_wdog_install_timeout()
170 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Dwdt_esp32.c50 const struct device *clock_dev; member
163 if (!device_is_ready(config->clock_dev)) { in wdt_esp32_init()
168 clock_control_on(config->clock_dev, config->clock_subsys); in wdt_esp32_init()
202 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
Dwdt_silabs_siwx91x.c26 const struct device *clock_dev; member
227 ret = clock_control_on(config->clock_dev, config->clock_subsys); in siwx91x_wdt_init()
231 ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, in siwx91x_wdt_init()
262 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
/Zephyr-latest/drivers/video/
Dvideo_mcux_mipi_csi2rx.c31 const struct device *clock_dev; member
79 ret = clock_control_get_rate(drv_data->clock_dev, drv_data->clock_root, &root_clk_rate); in mipi_csi2rx_update_settings()
85 ret = clock_control_set_rate(drv_data->clock_dev, drv_data->clock_root, in mipi_csi2rx_update_settings()
92 ret = clock_control_get_rate(drv_data->clock_dev, drv_data->clock_ui, &ui_clk_rate); in mipi_csi2rx_update_settings()
99 drv_data->clock_dev, drv_data->clock_ui, in mipi_csi2rx_update_settings()
329 ret = clock_control_set_rate(drv_data->clock_dev, drv_data->clock_esc, in mipi_csi2rx_init()
341 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-latest/drivers/interrupt_controller/
Dintc_rv32m1_intmux.c44 const struct device *clock_dev; member
147 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
158 if (!device_is_ready(config->clock_dev)) { in rv32m1_intmux_init()
163 clock_control_on(config->clock_dev, config->clock_subsys); in rv32m1_intmux_init()
/Zephyr-latest/drivers/can/
Dcan_mcux_mcan.c27 const struct device *clock_dev; member
80 return clock_control_get_rate(mcux_config->clock_dev, mcux_config->clock_subsys, in mcux_mcan_get_core_clock()
91 if (!device_is_ready(mcux_config->clock_dev)) { in mcux_mcan_init()
111 err = clock_control_on(mcux_config->clock_dev, mcux_config->clock_subsys); in mcux_mcan_init()
207 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-latest/drivers/comparator/
Dcomparator_silabs_acmp.c25 const struct device *clock_dev; member
45 err = clock_control_on(config->clock_dev, in acmp_pm_action()
61 err = clock_control_off(config->clock_dev, in acmp_pm_action()
84 err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg); in acmp_init()
233 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
/Zephyr-latest/drivers/serial/
Dserial_esp32_usb.c43 const struct device *clock_dev; member
102 if (!device_is_ready(config->clock_dev)) { in serial_esp32_usb_init()
106 int ret = clock_control_on(config->clock_dev, config->clock_subsys); in serial_esp32_usb_init()
275 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Duart_mcux_iuart.c19 const struct device *clock_dev; member
232 if (!device_is_ready(config->clock_dev)) { in mcux_iuart_init()
236 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_iuart_init()
246 clock_control_on(config->clock_dev, config->clock_subsys); in mcux_iuart_init()
265 clock_control_off(config->clock_dev, config->clock_subsys); in mcux_iuart_init()
329 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-latest/drivers/gpio/
Dwch_gpio_ch32v00x.c20 const struct device *clock_dev; member
127 clock_control_on(config->clock_dev, (clock_control_subsys_t *)(uintptr_t)config->clock_id); in gpio_ch32v00x_init()
139 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
Dgpio_rv32m1.c28 const struct device *clock_dev; member
275 if (config->clock_dev) { in gpio_rv32m1_init()
276 if (!device_is_ready(config->clock_dev)) { in gpio_rv32m1_init()
280 ret = clock_control_on(config->clock_dev, config->clock_subsys); in gpio_rv32m1_init()
318 .clock_dev = INST_DT_CLK_CTRL_DEV(n), \

12345