1 /*
2 * Copyright (c) 2024 GARDENA GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT silabs_si32_ahb
8
9 #include <stdint.h>
10
11 #include <zephyr/device.h>
12 #include <zephyr/devicetree.h>
13 #include <zephyr/drivers/clock_control.h>
14
15 #include <SI32_CLKCTRL_A_Type.h>
16 #include <SI32_FLASHCTRL_A_Type.h>
17 #include <si32_device.h>
18
19 #define LOG_LEVEL LOG_LEVEL_DBG
20 #include <zephyr/logging/log.h>
21 LOG_MODULE_REGISTER(ahb);
22
23 struct clock_control_si32_ahb_config {
24 const struct device *clock_dev;
25 uint32_t freq;
26 };
27
clock_control_si32_ahb_on(const struct device * dev,clock_control_subsys_t sys)28 static int clock_control_si32_ahb_on(const struct device *dev, clock_control_subsys_t sys)
29 {
30 return -ENOTSUP;
31 }
32
clock_control_si32_ahb_off(const struct device * dev,clock_control_subsys_t sys)33 static int clock_control_si32_ahb_off(const struct device *dev, clock_control_subsys_t sys)
34 {
35
36 return -ENOTSUP;
37 }
38
clock_control_si32_ahb_get_rate(const struct device * dev,clock_control_subsys_t sys,uint32_t * rate)39 static int clock_control_si32_ahb_get_rate(const struct device *dev, clock_control_subsys_t sys,
40 uint32_t *rate)
41 {
42 const struct clock_control_si32_ahb_config *config = dev->config;
43 *rate = config->freq;
44 return 0;
45 }
46
47 static DEVICE_API(clock_control, clock_control_si32_ahb_api) = {
48 .on = clock_control_si32_ahb_on,
49 .off = clock_control_si32_ahb_off,
50 .get_rate = clock_control_si32_ahb_get_rate,
51 };
52
clock_control_si32_ahb_init(const struct device * dev)53 static int clock_control_si32_ahb_init(const struct device *dev)
54 {
55 const struct clock_control_si32_ahb_config *config = dev->config;
56 int ret;
57
58 if (!device_is_ready(config->clock_dev)) {
59 return -ENODEV;
60 }
61
62 if (config->freq != 20000000) {
63 uint32_t freq = config->freq;
64
65 ret = clock_control_set_rate(config->clock_dev, NULL, &freq);
66 if (ret) {
67 LOG_ERR("failed to set parent clock rate: %d", ret);
68 return ret;
69 }
70
71 ret = clock_control_on(config->clock_dev, NULL);
72 if (ret) {
73 LOG_ERR("failed to enable parent clock: %d", ret);
74 return ret;
75 }
76
77 uint32_t spmd;
78
79 if (config->freq > 80000000) {
80 spmd = 3;
81 } else if (config->freq > 53000000) {
82 spmd = 2;
83 } else if (config->freq > 26000000) {
84 spmd = 1;
85 } else {
86 spmd = 0;
87 }
88 SI32_FLASHCTRL_A_select_flash_speed_mode(SI32_FLASHCTRL_0, spmd);
89
90 /* TODO: support other clock sources */
91 SI32_CLKCTRL_A_select_ahb_source_pll(SI32_CLKCTRL_0);
92 }
93
94 return 0;
95 }
96
97 static const struct clock_control_si32_ahb_config config = {
98 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
99 .freq = DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency),
100 };
101
102 DEVICE_DT_INST_DEFINE(0, clock_control_si32_ahb_init, NULL, NULL, &config, PRE_KERNEL_1,
103 CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_si32_ahb_api);
104
