1 /*
2 * Copyright 2019 Henrik Brix Andersen <henrik@brixandersen.dk>
3 * Copyright 2020, 2024 NXP
4 *
5 * Heavily based on pwm_mcux_ftm.c, which is:
6 * Copyright (c) 2017, NXP
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10
11 #define DT_DRV_COMPAT nxp_kinetis_tpm
12
13 #include <zephyr/drivers/clock_control.h>
14 #include <errno.h>
15 #include <zephyr/drivers/pwm.h>
16 #include <soc.h>
17 #include <fsl_tpm.h>
18 #include <fsl_clock.h>
19 #include <zephyr/drivers/pinctrl.h>
20
21 #include <zephyr/logging/log.h>
22
23 LOG_MODULE_REGISTER(pwm_mcux_tpm, CONFIG_PWM_LOG_LEVEL);
24
25 #if defined(TPM0)
26 #define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)
27 #else
28 #define MAX_CHANNELS ARRAY_SIZE(TPM1->CONTROLS)
29 #endif
30
31 struct mcux_tpm_config {
32 TPM_Type *base;
33 const struct device *clock_dev;
34 clock_control_subsys_t clock_subsys;
35 tpm_clock_source_t tpm_clock_source;
36 tpm_clock_prescale_t prescale;
37 uint8_t channel_count;
38 tpm_pwm_mode_t mode;
39 const struct pinctrl_dev_config *pincfg;
40 };
41
42 struct mcux_tpm_data {
43 uint32_t clock_freq;
44 uint32_t period_cycles;
45 tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS];
46 };
47
mcux_tpm_set_cycles(const struct device * dev,uint32_t channel,uint32_t period_cycles,uint32_t pulse_cycles,pwm_flags_t flags)48 static int mcux_tpm_set_cycles(const struct device *dev, uint32_t channel,
49 uint32_t period_cycles, uint32_t pulse_cycles,
50 pwm_flags_t flags)
51 {
52 const struct mcux_tpm_config *config = dev->config;
53 struct mcux_tpm_data *data = dev->data;
54 uint8_t duty_cycle;
55
56 if (period_cycles == 0U) {
57 LOG_ERR("Channel can not be set to inactive level");
58 return -ENOTSUP;
59 }
60
61 if (channel >= config->channel_count) {
62 LOG_ERR("Invalid channel");
63 return -ENOTSUP;
64 }
65
66 duty_cycle = pulse_cycles * 100U / period_cycles;
67 data->channel[channel].dutyCyclePercent = duty_cycle;
68
69 if ((flags & PWM_POLARITY_INVERTED) == 0) {
70 data->channel[channel].level = kTPM_HighTrue;
71 } else {
72 data->channel[channel].level = kTPM_LowTrue;
73 }
74
75 LOG_DBG("pulse_cycles=%d, period_cycles=%d, duty_cycle=%d, flags=%d",
76 pulse_cycles, period_cycles, duty_cycle, flags);
77
78 if (period_cycles != data->period_cycles) {
79 uint32_t pwm_freq;
80 status_t status;
81
82 if (data->period_cycles != 0) {
83 /* Only warn when not changing from zero */
84 LOG_WRN("Changing period cycles from %d to %d"
85 " affects all %d channels in %s",
86 data->period_cycles, period_cycles,
87 config->channel_count, dev->name);
88 }
89
90 data->period_cycles = period_cycles;
91
92 pwm_freq = (data->clock_freq >> config->prescale) /
93 period_cycles;
94
95 LOG_DBG("pwm_freq=%d, clock_freq=%d", pwm_freq,
96 data->clock_freq);
97
98 if (pwm_freq == 0U) {
99 LOG_ERR("Could not set up pwm_freq=%d", pwm_freq);
100 return -EINVAL;
101 }
102
103 TPM_StopTimer(config->base);
104
105 status = TPM_SetupPwm(config->base, data->channel,
106 config->channel_count, config->mode,
107 pwm_freq, data->clock_freq);
108
109 if (status != kStatus_Success) {
110 LOG_ERR("Could not set up pwm");
111 return -ENOTSUP;
112 }
113 TPM_StartTimer(config->base, config->tpm_clock_source);
114 } else {
115 TPM_UpdateChnlEdgeLevelSelect(config->base, channel,
116 data->channel[channel].level);
117 TPM_UpdatePwmDutycycle(config->base, channel, config->mode,
118 duty_cycle);
119 }
120
121 return 0;
122 }
123
mcux_tpm_get_cycles_per_sec(const struct device * dev,uint32_t channel,uint64_t * cycles)124 static int mcux_tpm_get_cycles_per_sec(const struct device *dev,
125 uint32_t channel, uint64_t *cycles)
126 {
127 const struct mcux_tpm_config *config = dev->config;
128 struct mcux_tpm_data *data = dev->data;
129
130 *cycles = data->clock_freq >> config->prescale;
131
132 return 0;
133 }
134
mcux_tpm_init(const struct device * dev)135 static int mcux_tpm_init(const struct device *dev)
136 {
137 const struct mcux_tpm_config *config = dev->config;
138 struct mcux_tpm_data *data = dev->data;
139 tpm_chnl_pwm_signal_param_t *channel = data->channel;
140 tpm_config_t tpm_config;
141 int i;
142 int err;
143
144 if (config->channel_count > ARRAY_SIZE(data->channel)) {
145 LOG_ERR("Invalid channel count");
146 return -EINVAL;
147 }
148
149 if (!device_is_ready(config->clock_dev)) {
150 LOG_ERR("clock control device not ready");
151 return -ENODEV;
152 }
153
154 if (clock_control_on(config->clock_dev, config->clock_subsys)) {
155 LOG_ERR("Could not turn on clock");
156 return -EINVAL;
157 }
158
159 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
160 &data->clock_freq)) {
161 LOG_ERR("Could not get clock frequency");
162 return -EINVAL;
163 }
164
165 for (i = 0; i < config->channel_count; i++) {
166 channel->chnlNumber = i;
167 #if !(defined(FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT) && FSL_FEATURE_TPM_HAS_PAUSE_LEVEL_SELECT)
168 channel->level = kTPM_NoPwmSignal;
169 #else
170 channel->level = kTPM_HighTrue;
171 channel->pauseLevel = kTPM_ClearOnPause;
172 #endif
173 channel->dutyCyclePercent = 0;
174 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
175 channel->firstEdgeDelayPercent = 0;
176 #endif
177 channel++;
178 }
179
180 err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
181 if (err) {
182 return err;
183 }
184
185 TPM_GetDefaultConfig(&tpm_config);
186 tpm_config.prescale = config->prescale;
187
188 TPM_Init(config->base, &tpm_config);
189
190 return 0;
191 }
192
193 static DEVICE_API(pwm, mcux_tpm_driver_api) = {
194 .set_cycles = mcux_tpm_set_cycles,
195 .get_cycles_per_sec = mcux_tpm_get_cycles_per_sec,
196 };
197
198 #define TO_TPM_PRESCALE_DIVIDE(val) _DO_CONCAT(kTPM_Prescale_Divide_, val)
199
200 #define TPM_DEVICE(n) \
201 PINCTRL_DT_INST_DEFINE(n); \
202 static const struct mcux_tpm_config mcux_tpm_config_##n = { \
203 .base = (TPM_Type *) \
204 DT_INST_REG_ADDR(n), \
205 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
206 .clock_subsys = (clock_control_subsys_t) \
207 DT_INST_CLOCKS_CELL(n, name), \
208 .tpm_clock_source = kTPM_SystemClock, \
209 .prescale = TO_TPM_PRESCALE_DIVIDE(DT_INST_PROP(n, prescaler)), \
210 .channel_count = FSL_FEATURE_TPM_CHANNEL_COUNTn((TPM_Type *) \
211 DT_INST_REG_ADDR(n)), \
212 .mode = kTPM_EdgeAlignedPwm, \
213 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
214 }; \
215 static struct mcux_tpm_data mcux_tpm_data_##n; \
216 DEVICE_DT_INST_DEFINE(n, &mcux_tpm_init, NULL, \
217 &mcux_tpm_data_##n, \
218 &mcux_tpm_config_##n, \
219 POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
220 &mcux_tpm_driver_api);
221
222 DT_INST_FOREACH_STATUS_OKAY(TPM_DEVICE)
223
