1 /*
2  * Copyright (C) 2017 Intel Corporation
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #define DT_DRV_COMPAT espressif_esp32_watchdog
8 
9 /* Include esp-idf headers first to avoid redefining BIT() macro */
10 #if defined(CONFIG_SOC_SERIES_ESP32C6)
11 #include <soc/lp_aon_reg.h>
12 #else
13 #include <soc/rtc_cntl_reg.h>
14 #endif
15 #include <soc/timer_group_reg.h>
16 #include <hal/mwdt_ll.h>
17 #include <hal/wdt_hal.h>
18 
19 #include <string.h>
20 #include <zephyr/drivers/watchdog.h>
21 #include <zephyr/drivers/clock_control.h>
22 #if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
23 #include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
24 #else
25 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
26 #endif
27 #include <zephyr/device.h>
28 
29 #include <zephyr/logging/log.h>
30 LOG_MODULE_REGISTER(wdt_esp32, CONFIG_WDT_LOG_LEVEL);
31 
32 #if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
33 #define ISR_HANDLER isr_handler_t
34 #else
35 #define ISR_HANDLER intr_handler_t
36 #endif
37 
38 #define MWDT_TICK_PRESCALER		40000
39 #define MWDT_TICKS_PER_US		500
40 
41 struct wdt_esp32_data {
42 	wdt_hal_context_t hal;
43 	uint32_t timeout;
44 	wdt_stage_action_t mode;
45 	wdt_callback_t callback;
46 };
47 
48 struct wdt_esp32_config {
49 	wdt_inst_t wdt_inst;
50 	const struct device *clock_dev;
51 	const clock_control_subsys_t clock_subsys;
52 	void (*connect_irq)(void);
53 	int irq_source;
54 	int irq_priority;
55 	int irq_flags;
56 };
57 
wdt_esp32_seal(const struct device * dev)58 static inline void wdt_esp32_seal(const struct device *dev)
59 {
60 	struct wdt_esp32_data *data = dev->data;
61 
62 	wdt_hal_write_protect_enable(&data->hal);
63 }
64 
wdt_esp32_unseal(const struct device * dev)65 static inline void wdt_esp32_unseal(const struct device *dev)
66 {
67 	struct wdt_esp32_data *data = dev->data;
68 
69 	wdt_hal_write_protect_disable(&data->hal);
70 }
71 
wdt_esp32_enable(const struct device * dev)72 static void wdt_esp32_enable(const struct device *dev)
73 {
74 	struct wdt_esp32_data *data = dev->data;
75 
76 	wdt_esp32_unseal(dev);
77 	wdt_hal_enable(&data->hal);
78 	wdt_esp32_seal(dev);
79 
80 }
81 
wdt_esp32_disable(const struct device * dev)82 static int wdt_esp32_disable(const struct device *dev)
83 {
84 	struct wdt_esp32_data *data = dev->data;
85 
86 	wdt_esp32_unseal(dev);
87 	wdt_hal_disable(&data->hal);
88 	wdt_esp32_seal(dev);
89 
90 	return 0;
91 }
92 
93 static void wdt_esp32_isr(void *arg);
94 
wdt_esp32_feed(const struct device * dev,int channel_id)95 static int wdt_esp32_feed(const struct device *dev, int channel_id)
96 {
97 	struct wdt_esp32_data *data = dev->data;
98 
99 	wdt_esp32_unseal(dev);
100 	wdt_hal_feed(&data->hal);
101 	wdt_esp32_seal(dev);
102 
103 	return 0;
104 }
105 
wdt_esp32_set_config(const struct device * dev,uint8_t options)106 static int wdt_esp32_set_config(const struct device *dev, uint8_t options)
107 {
108 	struct wdt_esp32_data *data = dev->data;
109 
110 	wdt_esp32_unseal(dev);
111 	wdt_hal_config_stage(&data->hal, WDT_STAGE0, data->timeout, WDT_STAGE_ACTION_INT);
112 	wdt_hal_config_stage(&data->hal, WDT_STAGE1, data->timeout, data->mode);
113 	wdt_esp32_enable(dev);
114 	wdt_esp32_seal(dev);
115 	wdt_esp32_feed(dev, 0);
116 
117 	return 0;
118 }
119 
wdt_esp32_install_timeout(const struct device * dev,const struct wdt_timeout_cfg * cfg)120 static int wdt_esp32_install_timeout(const struct device *dev,
121 				     const struct wdt_timeout_cfg *cfg)
122 {
123 	struct wdt_esp32_data *data = dev->data;
124 
125 	if (cfg->window.min != 0U || cfg->window.max == 0U) {
126 		return -EINVAL;
127 	}
128 
129 	data->timeout = cfg->window.max;
130 	data->callback = cfg->callback;
131 
132 	/* Set mode of watchdog and callback */
133 	switch (cfg->flags) {
134 	case WDT_FLAG_RESET_SOC:
135 		data->mode = WDT_STAGE_ACTION_RESET_SYSTEM;
136 		LOG_DBG("Configuring reset SOC mode");
137 		break;
138 
139 	case WDT_FLAG_RESET_CPU_CORE:
140 		data->mode = WDT_STAGE_ACTION_RESET_CPU;
141 		LOG_DBG("Configuring reset CPU mode");
142 		break;
143 
144 	case WDT_FLAG_RESET_NONE:
145 		data->mode = WDT_STAGE_ACTION_OFF;
146 		LOG_DBG("Configuring non-reset mode");
147 		break;
148 
149 	default:
150 		LOG_ERR("Unsupported watchdog config flag");
151 		return -EINVAL;
152 	}
153 
154 	return 0;
155 }
156 
wdt_esp32_init(const struct device * dev)157 static int wdt_esp32_init(const struct device *dev)
158 {
159 	const struct wdt_esp32_config *const config = dev->config;
160 	struct wdt_esp32_data *data = dev->data;
161 	int ret, flags;
162 
163 	if (!device_is_ready(config->clock_dev)) {
164 		LOG_ERR("clock control device not ready");
165 		return -ENODEV;
166 	}
167 
168 	clock_control_on(config->clock_dev, config->clock_subsys);
169 
170 	wdt_hal_init(&data->hal, config->wdt_inst, MWDT_TICK_PRESCALER, true);
171 
172 	flags = ESP_PRIO_TO_FLAGS(config->irq_priority) | ESP_INT_FLAGS_CHECK(config->irq_flags);
173 	ret = esp_intr_alloc(config->irq_source, flags, (ISR_HANDLER)wdt_esp32_isr, (void *)dev,
174 			     NULL);
175 
176 	if (ret != 0) {
177 		LOG_ERR("could not allocate interrupt (err %d)", ret);
178 		return ret;
179 	}
180 
181 #ifndef CONFIG_WDT_DISABLE_AT_BOOT
182 	wdt_esp32_enable(dev);
183 #endif
184 
185 	return 0;
186 }
187 
188 static DEVICE_API(wdt, wdt_api) = {
189 	.setup = wdt_esp32_set_config,
190 	.disable = wdt_esp32_disable,
191 	.install_timeout = wdt_esp32_install_timeout,
192 	.feed = wdt_esp32_feed
193 };
194 
195 #define ESP32_WDT_INIT(idx)							   \
196 	static struct wdt_esp32_data wdt##idx##_data;				   \
197 	static struct wdt_esp32_config wdt_esp32_config##idx = {		   \
198 		.wdt_inst = WDT_MWDT##idx,	\
199 		.irq_source = DT_IRQ_BY_IDX(DT_NODELABEL(wdt##idx), 0, irq),	\
200 		.irq_priority = DT_IRQ_BY_IDX(DT_NODELABEL(wdt##idx), 0, priority),	\
201 		.irq_flags = DT_IRQ_BY_IDX(DT_NODELABEL(wdt##idx), 0, flags),	\
202 		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
203 		.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(idx, offset), \
204 	};									   \
205 										   \
206 	DEVICE_DT_INST_DEFINE(idx,						   \
207 			      wdt_esp32_init,					   \
208 			      NULL,						   \
209 			      &wdt##idx##_data,					   \
210 			      &wdt_esp32_config##idx,				   \
211 			      PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,	   \
212 			      &wdt_api)
213 
wdt_esp32_isr(void * arg)214 static void wdt_esp32_isr(void *arg)
215 {
216 	const struct device *dev = (const struct device *)arg;
217 	struct wdt_esp32_data *data = dev->data;
218 
219 	if (data->callback) {
220 		data->callback(dev, 0);
221 	}
222 
223 	wdt_hal_handle_intr(&data->hal);
224 }
225 
226 
227 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wdt0))
228 ESP32_WDT_INIT(0);
229 #endif
230 
231 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wdt1))
232 ESP32_WDT_INIT(1);
233 #endif
234