| /Zephyr-latest/drivers/memc/ |
| D | memc_sam_smc.c | 28 const struct memc_smc_bank_config *banks; member
49 if (cfg->banks[i].cs >= SMCCS_NUMBER_NUMBER) { in memc_smc_init()
53 bank = &cfg->regs->SMC_CS_NUMBER[cfg->banks[i].cs]; in memc_smc_init()
55 bank->SMC_SETUP = cfg->banks[i].setup_timing; in memc_smc_init()
56 bank->SMC_PULSE = cfg->banks[i].pulse_timing; in memc_smc_init()
57 bank->SMC_CYCLE = cfg->banks[i].cycle_timing; in memc_smc_init()
58 bank->SMC_MODE = cfg->banks[i].mode; in memc_smc_init()
99 .banks = smc_bank_config_##inst, \
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| D | memc_stm32_sdram.c | 32 const struct memc_stm32_sdram_bank_config *banks; member
47 memcpy(&sdram.Init, &config->banks[i].init, sizeof(sdram.Init)); in memc_stm32_sdram_init()
51 (FMC_SDRAM_TimingTypeDef *)&config->banks[i].timing); in memc_stm32_sdram_init()
57 } else if (config->banks[0].init.SDBank == FMC_SDRAM_BANK1) { in memc_stm32_sdram_init()
129 .banks = bank_config,
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| D | memc_stm32_nor_psram.c | 32 const struct memc_stm32_nor_psram_bank_config *banks; member
96 memory_type = config->banks[bank_idx].init.MemoryType; in memc_stm32_nor_psram_init()
100 ret = memc_stm32_nor_init(config, &config->banks[bank_idx]); in memc_stm32_nor_psram_init()
105 ret = memc_stm32_psram_init(config, &config->banks[bank_idx]); in memc_stm32_nor_psram_init()
115 memory_type, config->banks[bank_idx].init.NSBank, ret); in memc_stm32_nor_psram_init()
171 .banks = bank_config,
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| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | comm_widget_messages.c | 17 int adsp_comm_widget_pmc_send_ipc(uint16_t banks) in adsp_comm_widget_pmc_send_ipc() argument
24 FIELD_PREP(CW_PMC_IPC_SRAM_USED_BANKS, banks) | in adsp_comm_widget_pmc_send_ipc()
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/ |
| D | sram.c | 28 static __imr void hp_sram_pm_banks(uint32_t banks) in hp_sram_pm_banks() argument
53 if (banks > EBB_SEG_SIZE) { in hp_sram_pm_banks()
55 ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEG_SIZE - 1, in hp_sram_pm_banks()
59 ebb_mask0 = (uint32_t)GENMASK(banks - 1, 0); in hp_sram_pm_banks()
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/ |
| D | adsp_comm_widget.h | 7 int adsp_comm_widget_pmc_send_ipc(uint16_t banks);
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| /Zephyr-latest/drivers/gpio/ |
| D | Kconfig.rp1 | 9 Enable Driver for GPIO banks on RP1 peripheral controller.
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| /Zephyr-latest/soc/nxp/lpc/lpc55xxx/ |
| D | Kconfig.defconfig | 29 # By default, CMSIS SystemInit will enable the clock to these RAM banks.
30 # Disable this Kconfig to leave the ram banks untouched out of reset.
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| D | CMakeLists.txt | 24 # CMSIS SystemInit allows us to skip enabling clock to SRAM banks via
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| D | Kconfig | 112 bool "CLock LPC SRAM banks"
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| /Zephyr-latest/drivers/can/ |
| D | Kconfig.stm32 | 26 filter banks.
42 filter banks.
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_rt1015.dtsi | 11 flexram,num-ram-banks = <5>;
12 /* Note: RT1015 has five flexram banks, but only 4 of the 5 can
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| D | nxp_rt1020.dtsi | 11 flexram,num-ram-banks = <8>;
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| D | nxp_rt1050.dtsi | 9 flexram,num-ram-banks = <16>;
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| D | nxp_rt1024.dtsi | 11 flexram,num-ram-banks = <8>;
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| D | nxp_rt1064.dtsi | 11 flexram,num-ram-banks = <16>;
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| D | nxp_rt1040.dtsi | 10 flexram,num-ram-banks = <16>;
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| D | nxp_rt1060.dtsi | 18 flexram,num-ram-banks = <16>;
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| /Zephyr-latest/soc/snps/hsdk4xd/ |
| D | Kconfig.defconfig | 19 # Actually cpu has 4 banks but zephys currently supports up to 2
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| /Zephyr-latest/dts/arm/st/f1/ |
| D | stm32f103Xg.dtsi | 20 /* Note that there are actually two banks of
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| /Zephyr-latest/soc/espressif/esp32/ |
| D | Kconfig | 29 ESP32 has two banks of size 192K and 128K which can be used
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| /Zephyr-latest/soc/intel/intel_adsp/ |
| D | Kconfig | 103 Need to power cache SRAM banks on.
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| /Zephyr-latest/doc/hardware/arch/ |
| D | arc-support-status.rst | 42 | Fast interrupts, separate register banks for fast interrupts | Y | Y | …
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| /Zephyr-latest/boards/snps/nsim/arc_classic/doc/ |
| D | index.rst | 22 * ``nsim/nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
28 * ``nsim/nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
29 * ``nsim/nsim_hs/smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
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| /Zephyr-latest/boards/dragino/lsn50/doc/ |
| D | index.rst | 53 - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection
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