1.. zephyr:board:: dragino_lsn50
2
3Overview
4********
5
6The Dragino LSN50 LoRA Sensor Node for IoT allows users to develop
7applications with LoraWAN connectivity via the HopeRF / SX1276/SX1278.
8Dragino LSN50 enables a wide diversity of applications by exploiting
9low-power communication, ARM |reg| Cortex |reg|-M0 core-based
10STM32L0 Series features.
11
12This kit provides:
13
14- STM32L072CZ MCU
15- SX1276/SX1278 LoRa Transceiver
16- Expansion connectors:
17
18        - PMOD
19- Li/SOCI2 Unchargable Battery
20- GPIOs exposed via screw terminals on the carrier board
21- Housing
22
23More information about the board can be found at the `Dragino LSN50 website`_.
24
25Hardware
26********
27
28The STM32L072CZ SoC provides the following hardware IPs:
29
30- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode)
31- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz
32- Clock Sources:
33
34        - 1 to 32 MHz crystal oscillator
35        - 32 kHz crystal oscillator for RTC (LSE)
36        - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
37        - Internal low-power 37 kHz RC ( |plusminus| 5%)
38        - Internal multispeed low-power 65 kHz to 4.2 MHz RC
39- RTC with HW calendar, alarms and calibration
40- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
41- 11x timers:
42
43        - 2x 16-bit with up to 4 channels
44        - 2x 16-bit with up to 2 channels
45        - 1x 16-bit ultra-low-power timer
46        - 1x SysTick
47        - 1x RTC
48        - 2x 16-bit basic for DAC
49        - 2x watchdogs (independent/window)
50- Up to 84 fast I/Os, most 5 V-tolerant.
51- Memories
52
53        - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection
54        - Up to 20 KB of SRAM
55        - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories
56- Rich analog peripherals (independent supply)
57
58        - 1x 12-bit ADC 1.14 MSPS
59        - 2x 12-bit DAC
60        - 2x ultra-low-power comparators
61- 11x communication interfaces
62
63        - USB OTG 2.0 full-speed, LPM and BCD
64        - 3x I2C FM+(1 Mbit/s), SMBus/PMBus
65        - 4x USARTs (ISO 7816, LIN, IrDA, modem)
66        - 6x SPIs (4x SPIs with the Quad SPI)
67- 7-channel DMA controller
68- True random number generator
69- CRC calculation unit, 96-bit unique ID
70- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
71
72
73More information about STM32L072CZ can be found here:
74
75        - `STM32L072CZ on www.st.com`_
76        - `STM32L0x2 reference manual`_
77
78Supported Features
79==================
80
81The Zephyr Dragino LSN50 board configuration supports the following hardware features:
82
83+-----------+------------+-------------------------------------+
84| Interface | Controller | Driver/Component                    |
85+===========+============+=====================================+
86| UART      | on-chip    | serial port-polling;                |
87|           |            | serial port-interrupt               |
88+-----------+------------+-------------------------------------+
89| PINMUX    | on-chip    | pinmux                              |
90+-----------+------------+-------------------------------------+
91| GPIO      | on-chip    | gpio                                |
92+-----------+------------+-------------------------------------+
93
94Other hardware features are not yet supported on this Zephyr port.
95
96The default configuration can be found in the defconfig file:
97:zephyr_file:`boards/dragino/lsn50/dragino_lsn50_defconfig`
98
99
100Connections and IOs
101===================
102
103Dragino LSN50 Board has GPIO controllers. These controllers are responsible for pin muxing,
104input/output, pull-up, etc.
105
106Available pins:
107---------------
108
109For detailed information about available pins please refer to `Dragino LSN50 website`_.
110
111Default Zephyr Peripheral Mapping:
112----------------------------------
113
114- UART_1_TX : PB6
115- UART_1_RX : PB7
116- UART_2_TX : PA2
117- UART_2_RX : PA3
118
119System Clock
120------------
121
122Dragino LSN50 System Clock is at 32MHz,
123
124Serial Port
125-----------
126
127Dragino LSN50 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1.
128Default settings are 115200 8N1.
129
130Programming and Debugging
131*************************
132
133Applications for the ``dragino_lsn50`` board configuration can be built and
134flashed in the usual way (see :ref:`build_an_application` and
135:ref:`application_run` for more details).
136
137Flashing
138========
139
140Dragino LSN50  board requires an external debugger.
141
142Flashing an application to Dragino LSN50
143----------------------------------------
144
145Here is an example for the :zephyr:code-sample:`hello_world` application.
146
147Connect the Dragino LSN50 to a STLinkV2 to your host computer using the USB port, then
148run a serial host program to connect with your board. For example:
149
150.. code-block:: console
151
152   $ minicom -D /dev/ttyACM0
153
154Then build and flash the application:
155
156.. zephyr-app-commands::
157   :zephyr-app: samples/hello_world
158   :board: dragino_lsn50
159   :goals: build flash
160
161You should see the following message on the console:
162
163.. code-block:: console
164
165   $ Hello World! arm
166
167Debugging
168=========
169
170You can debug an application in the usual way.  Here is an example for the
171:zephyr:code-sample:`hello_world` application.
172
173.. zephyr-app-commands::
174   :zephyr-app: samples/hello_world
175   :board: dragino_lsn50
176   :maybe-skip-config:
177   :goals: debug
178
179.. _Dragino LSN50 website:
180   https://www.dragino.com/products/lora-lorawan-end-node/item/128-lsn50.html
181
182.. _STM32L072CZ on www.st.com:
183   https://www.st.com/en/microcontrollers/stm32l072cz.html
184
185.. _STM32L0x2 reference manual:
186   https://www.st.com/resource/en/reference_manual/DM00108281.pdf
187