Home
last modified time | relevance | path

Searched refs:STM32_SRC_PLL1_Q (Results 1 – 25 of 28) sorted by relevance

12

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32wba_clock.h29 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) macro
30 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
Dstm32h7rs_clock.h26 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) macro
27 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
Dstm32h7_clock.h26 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) macro
27 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
Dstm32u5_clock.h31 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) macro
32 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
Dstm32h5_clock.h30 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) macro
31 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
/Zephyr-latest/dts/arm/st/h5/
Dstm32h563.dtsi17 <&rcc STM32_SRC_PLL1_Q SDMMC2_SEL(0)>;
Dstm32h5.dtsi494 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
505 <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>;
516 <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>;
589 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
605 <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>;
621 <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>;
Dstm32h562.dtsi267 <&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>;
483 <&rcc STM32_SRC_PLL1_Q SDMMC1_SEL(0)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dspi1_pllq_1_d1ppre_1.overlay25 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dnucleo_h723zg.overlay17 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
/Zephyr-latest/dts/arm/st/h7/
Dstm32h7a3.dtsi65 <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
77 <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
89 <&rcc STM32_SRC_PLL1_Q SPI6_SEL(0)>;
Dstm32h7.dtsi427 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
438 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
449 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
490 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
504 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
518 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
1012 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>;
1022 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>;
Dstm32h723.dtsi102 <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
114 <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c65 if (pclken[1].bus == STM32_SRC_PLL1_Q) { in ZTEST()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wba.c57 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) || in enabled_clock()
232 case STM32_SRC_PLL1_Q: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h5.c133 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) || in enabled_clock()
288 case STM32_SRC_PLL1_Q: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c139 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) || in enabled_clock()
303 case STM32_SRC_PLL1_Q: in stm32_clock_control_get_subsys_rate()
/Zephyr-latest/boards/st/nucleo_h745zi_q/
Dnucleo_h745zi_q_stm32h745xx_m7.dts154 * <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
/Zephyr-latest/boards/st/nucleo_u575zi_q/
Dnucleo_u575zi_q-common.dtsi183 <&rcc STM32_SRC_PLL1_Q FDCAN1_SEL(1)>;
/Zephyr-latest/boards/st/nucleo_u5a5zj_q/
Dnucleo_u5a5zj_q-common.dtsi176 <&rcc STM32_SRC_PLL1_Q FDCAN1_SEL(1)>;
/Zephyr-latest/boards/st/nucleo_h563zi/
Dnucleo_h563zi-common.dtsi168 <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
/Zephyr-latest/dts/arm/st/h7rs/
Dstm32h7rs.dtsi437 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
448 <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>;
459 <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>;
490 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
/Zephyr-latest/boards/arduino/giga_r1/
Darduino_giga_r1_stm32h747xx_m7.dts147 <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
/Zephyr-latest/boards/arduino/portenta_h7/
Darduino_portenta_h7-common.dtsi117 <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
/Zephyr-latest/boards/st/stm32h573i_dk/
Dstm32h573i_dk.dts258 <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;

12