1/*
2 * Copyright (c) 2021 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/* Set div-q to get test clk freq into acceptable SPI freq range */
8&pll {
9	/delete-property/ div-q;
10	div-q = <8>;
11};
12
13/* Define PLL1_Q as SPI1 kernel clock source */
14&spi1 {
15	/delete-property/ clocks;
16	clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
17		 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
18	slow@0 {
19		compatible = "test-spi-loopback-slow";
20		reg = <0>;
21		spi-max-frequency = <500000>;
22	};
23	fast@0 {
24		compatible = "test-spi-loopback-fast";
25		reg = <0>;
26		spi-max-frequency = <16000000>;
27	};
28};
29