1/*
2 * Copyright 2023 Google LLC
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/h7/stm32h747Xi_m7.dtsi>
9#include <st/h7/stm32h747xihx-pinctrl.dtsi>
10#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
11#include "arduino_giga_r1.dtsi"
12
13/ {
14	model = "Arduino GIGA R1 WiFi Board (M7)";
15	compatible = "arduino,giga-r1";
16
17	chosen {
18		zephyr,console = &usart1;
19		zephyr,shell-uart = &usart1;
20		zephyr,uart-mcumgr = &usart1;
21		zephyr,bt-hci = &bt_hci_uart;
22		zephyr,sram = &sram0;
23		zephyr,flash = &flash0;
24		zephyr,canbus = &fdcan2;
25		zephyr,code-partition = &slot0_partition;
26	};
27
28	sdram1: sdram@c0000000 {
29		compatible = "zephyr,memory-region", "mmio-sram";
30		device_type = "memory";
31		reg = <0xc0000000 DT_SIZE_M(8)>;
32		zephyr,memory-region = "SDRAM1";
33		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
34	};
35
36	aliases {
37		led0 = &red_led;
38		led1 = &green_led;
39		sw0 = &user_button;
40	};
41};
42
43&clk_hse {
44	status = "okay";
45	clock-frequency = <DT_FREQ_M(16)>;
46};
47
48&clk_lse {
49	status = "okay";
50};
51
52&clk_hsi48 {
53	status = "okay";
54};
55
56&pll {
57	div-m = <2>;
58	mul-n = <120>;
59	div-p = <2>;
60	div-q = <4>;
61	div-r = <2>;
62	clocks = <&clk_hse>;
63	status = "okay";
64};
65
66&rcc {
67	clocks = <&pll>;
68	clock-frequency = <DT_FREQ_M(480)>;
69};
70
71&usart1 {
72	status = "okay";
73	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pb7>;
74	pinctrl-names = "default";
75	current-speed = <115200>;
76};
77
78&usart6 {
79	status = "disabled";
80	pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pc7>;
81	pinctrl-names = "default";
82	current-speed = <115200>;
83};
84
85&uart4 {
86	status = "disabled";
87	pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_pi9>;
88	pinctrl-names = "default";
89	current-speed = <115200>;
90};
91
92&uart7 {
93	pinctrl-0 = <&uart7_tx_pf7 &uart7_rx_pa8
94		     &uart7_cts_pf9 &uart7_rts_pf8>;
95	pinctrl-names = "default";
96	current-speed = <115200>;
97	status = "okay";
98	hw-flow-control;
99
100	bt_hci_uart: bt_hci_uart {
101		compatible = "zephyr,bt-hci-uart";
102		status = "okay";
103
104		murata-1dx {
105			compatible = "infineon,cyw43xxx-bt-hci";
106			bt-reg-on-gpios = <&gpioa 10 GPIO_ACTIVE_HIGH>;
107			bt-host-wake-gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>;
108			bt-dev-wake-gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
109			fw-download-speed = <115200>;
110		};
111	};
112};
113
114&i2c4 {
115	status = "okay";
116	pinctrl-0 = <&i2c4_scl_pb6 &i2c4_sda_ph12>;
117	pinctrl-names = "default";
118	clock-frequency = <I2C_BITRATE_STANDARD>;
119};
120
121&i2c1 {
122	status = "disabled";
123	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
124	pinctrl-names = "default";
125	clock-frequency = <I2C_BITRATE_FAST>;
126};
127
128&i2c2 {
129	status = "disabled";
130	pinctrl-0 = <&i2c2_scl_ph4 &i2c2_sda_pb11>;
131	pinctrl-names = "default";
132	clock-frequency = <I2C_BITRATE_FAST>;
133};
134
135&spi5 {
136	status = "okay";
137	pinctrl-0 = <&spi5_nss_pk1 &spi5_sck_ph6
138		     &spi5_miso_pj11 &spi5_mosi_pj10>;
139	pinctrl-names = "default";
140};
141
142&fdcan2 {
143	status = "okay";
144	pinctrl-0 = <&fdcan2_tx_pb13 &fdcan2_rx_pb5>;
145	pinctrl-names = "default";
146	clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
147		 <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
148};
149
150&flash0 {
151	partitions {
152		compatible = "fixed-partitions";
153		#address-cells = <1>;
154		#size-cells = <1>;
155
156		boot_partition: partition@0 {
157			label = "bootloader";
158			reg = <0x0 0x40000>;
159			read-only;
160		};
161
162		slot0_partition: partition@40000 {
163			label = "image-0";
164			reg = <0x40000 0x000c0000>;
165		};
166	};
167};
168
169&quadspi {
170	pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk1_ncs_pg6
171		     &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12
172		     &quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pf6>;
173	pinctrl-names = "default";
174	status = "okay";
175
176	n25q128a1: qspi-nor-flash@90000000 {
177		compatible = "st,stm32-qspi-nor";
178		reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
179		qspi-max-frequency = <72000000>;
180		status = "okay";
181
182		partitions {
183			compatible = "fixed-partitions";
184			#address-cells = <1>;
185			#size-cells = <1>;
186
187			slot1_partition: partition@0 {
188				label = "image-1";
189				reg = <0x00000000 DT_SIZE_M(1)>;
190			};
191
192			storage_partition: partition@100000 {
193				label = "storage";
194				reg = <0x00100000 DT_SIZE_M(15)>;
195			};
196		};
197	};
198};
199
200&rng {
201	status = "okay";
202};
203
204&dac1 {
205	status = "okay";
206	pinctrl-0 = <&dac1_out1_pa4 &dac1_out2_pa5>;
207	pinctrl-names = "default";
208};
209
210&fmc {
211	status = "okay";
212	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
213		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke0_ph2
214		     &fmc_sdne0_ph3 &fmc_sdnras_pf11 &fmc_sdncas_pg15
215
216		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
217		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
218		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2
219		     &fmc_a14_pg4 &fmc_a15_pg5
220
221		     &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1
222		     &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10
223		     &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14
224		     &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>;
225	pinctrl-names = "default";
226
227	sdram {
228		status = "okay";
229
230		power-up-delay = <100>;
231		num-auto-refresh = <8>;
232		mode-register = <0x220>;
233		refresh-rate = <603>;
234
235		bank@0 {
236			reg = <0>;
237			st,sdram-control = <STM32_FMC_SDRAM_NC_8
238					    STM32_FMC_SDRAM_NR_12
239					    STM32_FMC_SDRAM_MWID_16
240					    STM32_FMC_SDRAM_NB_4
241					    STM32_FMC_SDRAM_CAS_2
242					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
243					    STM32_FMC_SDRAM_RBURST_ENABLE
244					    STM32_FMC_SDRAM_RPIPE_0>;
245			st,sdram-timing = <2 6 4 6 2 2 2>;
246		};
247	};
248};
249
250zephyr_udc0: &usbotg_fs {
251	status = "okay";
252	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
253	pinctrl-names = "default";
254};
255