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Searched refs:STM32_SRC_HSI48 (Results 1 – 25 of 49) sorted by relevance

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/Zephyr-latest/dts/arm/st/l4/
Dstm32l496.dtsi25 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
65 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
70 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
Dstm32l412.dtsi26 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
39 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
Dstm32l432.dtsi25 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
73 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
Dstm32l452.dtsi23 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
Dstm32l431.dtsi45 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
118 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
Dstm32l451.dtsi43 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
151 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32l0_clock.h30 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) macro
32 #define STM32_SRC_PCLK (STM32_SRC_HSI48 + 1)
Dstm32f0_clock.h27 #define STM32_SRC_HSI48 (STM32_SRC_HSI14 + 1) macro
29 #define STM32_SRC_PCLK (STM32_SRC_HSI48 + 1)
Dstm32c0_clock.h27 #define STM32_SRC_HSI48 (STM32_SRC_LSI + 1) macro
28 #define STM32_SRC_HSE (STM32_SRC_HSI48 + 1)
Dstm32wb_clock.h30 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) macro
31 #define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
Dstm32u0_clock.h29 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) macro
30 #define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
Dstm32g0_clock.h28 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) macro
29 #define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
Dstm32g4_clock.h31 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) macro
32 #define STM32_SRC_HSE (STM32_SRC_HSI48 + 1)
Dstm32l4_clock.h30 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) macro
31 #define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
Dstm32h7rs_clock.h21 #define STM32_SRC_HSI48 (STM32_SRC_HSE + 1) macro
22 #define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1) /* HSI + HSIKERON */
Dstm32h7_clock.h21 #define STM32_SRC_HSI48 (STM32_SRC_HSE + 1) macro
22 #define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1) /* HSI + HSIKERON */
Dstm32u5_clock.h21 #define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1) macro
22 #define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1)
Dstm32h5_clock.h22 #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) macro
24 #define STM32_SRC_HCLK (STM32_SRC_HSI48 + 1)
/Zephyr-latest/dts/arm/st/u5/
Dstm32u575.dtsi23 <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
Dstm32u545.dtsi26 <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
/Zephyr-latest/dts/arm/st/l0/
Dstm32l053.dtsi33 <&rcc STM32_SRC_HSI48 HSI48_SEL(1)>;
Dstm32l072.dtsi36 <&rcc STM32_SRC_HSI48 HSI48_SEL(1)>;
/Zephyr-latest/boards/st/nucleo_u083rc/
Dnucleo_u083rc.dts171 <&rcc STM32_SRC_HSI48 CLK48_SEL(1)>;
181 <&rcc STM32_SRC_HSI48 CLK48_SEL(1)>;
/Zephyr-latest/boards/shields/weact_ov2640_cam_module/boards/
Dmini_stm32h743.overlay34 clocks = <&rcc STM32_SRC_HSI48 MCO1_SEL(MCO1_SEL_HSI48)>;
/Zephyr-latest/dts/arm/st/h7/
Dstm32h745.dtsi58 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
72 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;

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