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Searched refs:GD32_RESET_WWDGT (Results 1 – 15 of 15) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32f3x0.h44 #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) macro
Dgd32l23x.h48 #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) macro
Dgd32vf103.h49 #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) macro
Dgd32a50x.h48 #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) macro
Dgd32e10x.h56 #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) macro
Dgd32f403.h57 #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) macro
Dgd32e50x.h62 #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) macro
Dgd32f4xx.h72 #define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U) macro
/Zephyr-latest/dts/arm/gd/gd32f3x0/
Dgd32f3x0.dtsi115 resets = <&rctl GD32_RESET_WWDGT>;
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi210 resets = <&rctl GD32_RESET_WWDGT>;
/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi236 resets = <&rctl GD32_RESET_WWDGT>;
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e50x.dtsi213 resets = <&rctl GD32_RESET_WWDGT>;
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi177 resets = <&rctl GD32_RESET_WWDGT>;
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi215 resets = <&rctl GD32_RESET_WWDGT>;
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi287 resets = <&rctl GD32_RESET_WWDGT>;