Home
last modified time | relevance | path

Searched refs:DT_NODELABEL (Results 1 – 25 of 692) sorted by relevance

12345678910>>...28

/Zephyr-latest/modules/hal_silabs/simplicity_sdk/config/
Dsl_clock_manager_tree_config.h26 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(fsrco)) \
28 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(hfrcodpll)) \
30 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(hfxo)) \
32 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(sysclk)), DT_NODELABEL(clkin0)) \
41 CONCAT(CMU_SYSCLKCTRL_HCLKPRESC_DIV, DT_PROP(DT_NODELABEL(hclk), clock_div))
44 CONCAT(CMU_SYSCLKCTRL_PCLKPRESC_DIV, DT_PROP(DT_NODELABEL(pclk), clock_div))
48 #if DT_NUM_CLOCKS(DT_NODELABEL(traceclk)) == 0
54 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(sysclk)) \
56 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hfrcodpllrt)) \
58 : COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(hfrcoem23)), ( \
[all …]
Dsl_clock_manager_oscillator_config.h15 #define SL_CLOCK_MANAGER_HFXO_EN DT_NODE_HAS_STATUS(DT_NODELABEL(hfxo), okay)
16 #define SL_CLOCK_MANAGER_HFXO_MODE DT_ENUM_IDX(DT_NODELABEL(hfxo), mode)
17 #define SL_CLOCK_MANAGER_HFXO_FREQ DT_PROP(DT_NODELABEL(hfxo), clock_frequency)
18 #define SL_CLOCK_MANAGER_HFXO_CTUNE DT_PROP(DT_NODELABEL(hfxo), ctune)
19 #define SL_CLOCK_MANAGER_HFXO_PRECISION DT_PROP(DT_NODELABEL(hfxo), precision)
23 #define SL_CLOCK_MANAGER_LFXO_EN DT_NODE_HAS_STATUS(DT_NODELABEL(lfxo), okay)
24 #define SL_CLOCK_MANAGER_LFXO_MODE (DT_ENUM_IDX(DT_NODELABEL(lfxo), mode) << _LFXO_CFG_MODE_SHIFT)
26 #define SL_CLOCK_MANAGER_LFXO_CTUNE DT_PROP(DT_NODELABEL(lfxo), ctune)
27 #define SL_CLOCK_MANAGER_LFXO_PRECISION DT_PROP(DT_NODELABEL(lfxo), precision)
29 (DT_ENUM_IDX(DT_NODELABEL(lfxo), timeout) << _LFXO_CFG_TIMEOUT_SHIFT)
[all …]
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h69 #define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
73 #define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
74 #define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
75 #define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
76 #define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
77 #define STM32_APB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb4_prescaler)
78 #define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler)
79 #define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
80 #define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
81 #define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
[all …]
Dadi_max32_clock_control.h40 #define ADI_MAX32_SYSCLK_PRESCALER DT_PROP_OR(DT_NODELABEL(gcr), sysclk_prescaler, 1)
42 #define ADI_MAX32_CLK_IPO_FREQ DT_PROP(DT_NODELABEL(clk_ipo), clock_frequency)
43 #define ADI_MAX32_CLK_ERFO_FREQ DT_PROP_OR(DT_NODELABEL(clk_erfo), clock_frequency, 0)
44 #define ADI_MAX32_CLK_IBRO_FREQ DT_PROP_OR(DT_NODELABEL(clk_ibro), clock_frequency, 0)
45 #define ADI_MAX32_CLK_ISO_FREQ DT_PROP_OR(DT_NODELABEL(clk_iso), clock_frequency, 0)
46 #define ADI_MAX32_CLK_INRO_FREQ DT_PROP(DT_NODELABEL(clk_inro), clock_frequency)
47 #define ADI_MAX32_CLK_ERTCO_FREQ DT_PROP(DT_NODELABEL(clk_ertco), clock_frequency)
48 #define ADI_MAX32_CLK_IPLL_FREQ DT_PROP_OR(DT_NODELABEL(clk_ipll), clock_frequency, 0)
49 #define ADI_MAX32_CLK_EBO_FREQ DT_PROP_OR(DT_NODELABEL(clk_ebo), clock_frequency, 0)
51 #define ADI_MAX32_CLK_EXTCLK_FREQ DT_PROP_OR(DT_NODELABEL(clk_extclk), clock_frequency, 0)
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_ifx_cat1.c17 #define GET_CLK_SOURCE_ORD(N) DT_DEP_ORD(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(N), 0))
21 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo))
25 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho))
29 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux0))
33 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux1))
37 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux2))
41 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux3))
45 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux4))
49 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf0))
53 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf1))
[all …]
/Zephyr-latest/soc/nxp/imx/imx9/imx93/a55/
Dmmu_regions.c13 MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
14 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
17 MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
18 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
21 MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)),
24 MMU_REGION_FLAT_ENTRY("ANA_PLL", DT_REG_ADDR(DT_NODELABEL(ana_pll)),
25 DT_REG_SIZE(DT_NODELABEL(ana_pll)),
28 MMU_REGION_FLAT_ENTRY("IOMUXC", DT_REG_ADDR(DT_NODELABEL(iomuxc)),
29 DT_REG_SIZE(DT_NODELABEL(iomuxc)),
39 MMU_REGION_FLAT_ENTRY("MU2_A", DT_REG_ADDR(DT_NODELABEL(mu2_a)),
[all …]
/Zephyr-latest/soc/nxp/rw/
Dpower.c31 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin1))
35 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0))
38 uint8_t level = ~(DT_ENUM_IDX(DT_NODELABEL(pin0), wakeup_level)) & 0x1; in pin0_isr()
41 NVIC_ClearPendingIRQ(DT_IRQN(DT_NODELABEL(pin0))); in pin0_isr()
42 DisableIRQ(DT_IRQN(DT_NODELABEL(pin0))); in pin0_isr()
43 POWER_DisableWakeup(DT_IRQN(DT_NODELABEL(pin0))); in pin0_isr()
47 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin1))
50 uint8_t level = ~(DT_ENUM_IDX(DT_NODELABEL(pin1), wakeup_level)) & 0x1; in pin1_isr()
53 NVIC_ClearPendingIRQ(DT_IRQN(DT_NODELABEL(pin1))); in pin1_isr()
54 DisableIRQ(DT_IRQN(DT_NODELABEL(pin1))); in pin1_isr()
[all …]
Dsoc.c145 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(os_timer), nxp_os_timer, okay) in clock_init()
149 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt), nxp_lpc_wwdt, okay)) in clock_init()
167 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay)) && CONFIG_SERIAL in clock_init()
171 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_usart, okay)) && CONFIG_SERIAL in clock_init()
175 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_usart, okay)) && CONFIG_SERIAL in clock_init()
179 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_usart, okay)) && CONFIG_SERIAL in clock_init()
183 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm14), nxp_lpc_usart, okay)) && CONFIG_SERIAL in clock_init()
189 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_i2c, okay)) && CONFIG_I2C in clock_init()
192 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2c, okay)) && CONFIG_I2C in clock_init()
195 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay)) && CONFIG_I2C in clock_init()
[all …]
/Zephyr-latest/boards/nxp/frdm_mcxa156/
Dboard.c69 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta)) in board_early_init_hook()
73 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb)) in board_early_init_hook()
77 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc)) in board_early_init_hook()
81 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd)) in board_early_init_hook()
85 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porte)) in board_early_init_hook()
89 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0)) in board_early_init_hook()
94 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) in board_early_init_hook()
99 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2)) in board_early_init_hook()
104 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3)) in board_early_init_hook()
109 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4)) in board_early_init_hook()
[all …]
/Zephyr-latest/tests/subsys/pm/device_driver_init/src/
Dmain.c39 DEVICE_STATE_IS(DT_NODELABEL(test_reg), PM_DEVICE_STATE_ACTIVE); in ZTEST()
40 DEVICE_STATE_IS(DT_NODELABEL(test_reg_chained), PM_DEVICE_STATE_ACTIVE); in ZTEST()
41 POWER_GPIO_CONFIG_IS(DT_NODELABEL(test_reg), GPIO_OUTPUT_HIGH); in ZTEST()
42 POWER_GPIO_CONFIG_IS(DT_NODELABEL(test_reg_chained), GPIO_OUTPUT_HIGH); in ZTEST()
46 DEVICE_STATE_IS(DT_NODELABEL(test_reg_chained_auto), PM_DEVICE_STATE_SUSPENDED); in ZTEST()
47 DEVICE_STATE_IS(DT_NODELABEL(test_reg_auto), PM_DEVICE_STATE_SUSPENDED); in ZTEST()
48 POWER_GPIO_CONFIG_IS(DT_NODELABEL(test_reg_chained_auto), GPIO_OUTPUT_LOW); in ZTEST()
49 POWER_GPIO_CONFIG_IS(DT_NODELABEL(test_reg_auto), GPIO_OUTPUT_LOW); in ZTEST()
53 DEVICE_STATE_IS(DT_NODELABEL(test_reg_auto_chained), PM_DEVICE_STATE_OFF); in ZTEST()
54 DEVICE_STATE_IS(DT_NODELABEL(test_reg_auto_chained_auto), PM_DEVICE_STATE_OFF); in ZTEST()
[all …]
/Zephyr-latest/soc/nxp/imx/imx6sx/
Dsoc.c26 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart1)) in SOC_RdcInit()
30 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2)) in SOC_RdcInit()
34 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart3)) in SOC_RdcInit()
38 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart4)) in SOC_RdcInit()
42 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart5)) in SOC_RdcInit()
46 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart6)) in SOC_RdcInit()
50 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) in SOC_RdcInit()
54 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2)) in SOC_RdcInit()
58 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3)) in SOC_RdcInit()
62 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4)) in SOC_RdcInit()
[all …]
/Zephyr-latest/soc/intel/intel_socfpga/agilex5/
Dmmu_regions.c12 DT_REG_ADDR(DT_NODELABEL(clock)),
13 DT_REG_SIZE(DT_NODELABEL(clock)),
18 DT_REG_ADDR(DT_NODELABEL(sysmgr)),
19 DT_REG_SIZE(DT_NODELABEL(sysmgr)),
23 DT_REG_ADDR_BY_IDX(DT_NODELABEL(pinmux), 0),
24 DT_REG_SIZE_BY_IDX(DT_NODELABEL(pinmux), 0),
28 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
29 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
33 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
34 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
[all …]
/Zephyr-latest/soc/nxp/imx/imx8m/a53/
Dmmu_regions.c14 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
15 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
19 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
20 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
24 DT_REG_ADDR(DT_NODELABEL(ccm)),
25 DT_REG_SIZE(DT_NODELABEL(ccm)),
29 DT_REG_ADDR(DT_NODELABEL(ana_pll)),
30 DT_REG_SIZE(DT_NODELABEL(ana_pll)),
34 DT_REG_ADDR(DT_NODELABEL(iomuxc)),
35 DT_REG_SIZE(DT_NODELABEL(iomuxc)),
[all …]
/Zephyr-latest/soc/nuvoton/numaker/m2l31x/
Dsoc.c28 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt) in soc_reset_hook()
30 if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_ENABLE) { in soc_reset_hook()
34 } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_DISABLE) { in soc_reset_hook()
39 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt) in soc_reset_hook()
41 if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_ENABLE) { in soc_reset_hook()
45 } else if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_DISABLE) { in soc_reset_hook()
60 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48m) in soc_reset_hook()
62 if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48m) == NUMAKER_SCC_CLKSW_ENABLE) { in soc_reset_hook()
66 } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48m) == NUMAKER_SCC_CLKSW_DISABLE) { in soc_reset_hook()
71 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv) in soc_reset_hook()
[all …]
/Zephyr-latest/soc/nuvoton/numaker/m46x/
Dsoc.c28 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt) in soc_reset_hook()
30 if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_ENABLE) { in soc_reset_hook()
34 } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_DISABLE) { in soc_reset_hook()
39 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt) in soc_reset_hook()
41 if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_ENABLE) { in soc_reset_hook()
45 } else if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_DISABLE) { in soc_reset_hook()
60 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48m) in soc_reset_hook()
62 if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48m) == NUMAKER_SCC_CLKSW_ENABLE) { in soc_reset_hook()
66 } else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48m) == NUMAKER_SCC_CLKSW_DISABLE) { in soc_reset_hook()
71 #if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv) in soc_reset_hook()
[all …]
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.c134 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) in board_early_init_hook()
150 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm1)) in board_early_init_hook()
156 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm2)) in board_early_init_hook()
162 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm4)) in board_early_init_hook()
168 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm7)) in board_early_init_hook()
174 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(os_timer)) in board_early_init_hook()
178 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0)) in board_early_init_hook()
182 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) in board_early_init_hook()
186 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2)) in board_early_init_hook()
190 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3)) in board_early_init_hook()
[all …]
/Zephyr-latest/boards/nxp/frdm_mcxn236/
Dboard.c102 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1)) in board_early_init_hook()
121 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm1)) in board_early_init_hook()
127 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm2)) in board_early_init_hook()
133 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm3)) in board_early_init_hook()
139 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm4)) in board_early_init_hook()
145 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm5)) in board_early_init_hook()
150 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(os_timer)) in board_early_init_hook()
154 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0)) in board_early_init_hook()
158 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1)) in board_early_init_hook()
162 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2)) in board_early_init_hook()
[all …]
/Zephyr-latest/boards/nxp/mimxrt700_evk/
Dboard.c18 #define SYSCON_BASE DT_REG_ADDR(DT_NODELABEL(syscon0))
21 #define SYSCON_BASE DT_REG_ADDR(DT_NODELABEL(syscon1))
179 #if DT_NODE_HAS_STATUS(DT_NODELABEL(edma0), okay) in board_early_init_hook()
185 #if DT_NODE_HAS_STATUS(DT_NODELABEL(edma1), okay) in board_early_init_hook()
191 #if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon), okay) in board_early_init_hook()
196 #if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon1), okay) in board_early_init_hook()
201 #if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon2), okay) in board_early_init_hook()
211 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm0), okay) in board_early_init_hook()
215 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay) in board_early_init_hook()
219 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay) in board_early_init_hook()
[all …]
/Zephyr-latest/soc/intel/intel_socfpga/agilex/
Dmmu_regions.c15 DT_REG_ADDR(DT_NODELABEL(sysmgr)),
16 DT_REG_SIZE(DT_NODELABEL(sysmgr)),
20 DT_REG_ADDR(DT_NODELABEL(clock)),
21 DT_REG_SIZE(DT_NODELABEL(clock)),
25 DT_REG_ADDR(DT_NODELABEL(uart0)),
26 DT_REG_SIZE(DT_NODELABEL(uart0)),
30 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
31 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
35 DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
36 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
/Zephyr-latest/drivers/gpio/
Dgpio_mchp_xec.c344 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio_000_036))
350 DT_NODELABEL(gpio_000_036)),
352 .pcr1_base = (uint32_t *) DT_REG_ADDR(DT_NODELABEL(gpio_000_036)),
354 #if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_000_036), irq)
364 DEVICE_DT_DEFINE(DT_NODELABEL(gpio_000_036),
373 #if DT_IRQ_HAS_CELL(DT_NODELABEL(gpio_000_036), irq) in gpio_xec_port000_036_init()
379 IRQ_CONNECT(DT_IRQ(DT_NODELABEL(gpio_000_036), irq), in gpio_xec_port000_036_init()
380 DT_IRQ(DT_NODELABEL(gpio_000_036), priority), in gpio_xec_port000_036_init()
382 DEVICE_DT_GET(DT_NODELABEL(gpio_000_036)), 0U); in gpio_xec_port000_036_init()
384 irq_enable(DT_IRQ(DT_NODELABEL(gpio_000_036), irq)); in gpio_xec_port000_036_init()
[all …]
/Zephyr-latest/tests/drivers/memc/ram/src/
Dmain.c15 Z_GENERIC_SECTION(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(label)))
35 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sdram1))
38 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sdram2))
41 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram1))
44 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram2))
47 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(memc))
51 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ram0))
52 #define RAM_SIZE DT_REG_SIZE(DT_NODELABEL(ram0))
53 static uint32_t *buf_ram0 = (uint32_t *)DT_REG_ADDR(DT_NODELABEL(ram0));
60 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sdram1)) in ZTEST()
[all …]
/Zephyr-latest/soc/nxp/imx/imx9/imx91/
Dmmu_regions.c12 MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
13 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
16 MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
17 DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
20 MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)),
23 MMU_REGION_FLAT_ENTRY("ANA_PLL", DT_REG_ADDR(DT_NODELABEL(ana_pll)),
24 DT_REG_SIZE(DT_NODELABEL(ana_pll)),
27 MMU_REGION_FLAT_ENTRY("IOMUXC", DT_REG_ADDR(DT_NODELABEL(iomuxc)),
28 DT_REG_SIZE(DT_NODELABEL(iomuxc)),
/Zephyr-latest/soc/nordic/common/
Dnrf54hx_nrf92x_mpu_regions.c10 #define USBHS_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(usbhs), core)
11 #define USBHS_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(usbhs), core)
13 #define CAN120_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can120), message_ram)
14 #define CAN120_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), message_ram) + \
15 DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), m_can)
17 #define CAN121_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can121), message_ram)
18 #define CAN121_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), message_ram) + \
19 DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), m_can)
31 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usbhs))
35 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(can120))
[all …]
/Zephyr-latest/soc/nuvoton/numaker/m55m1x/
Dmpu_regions.c19 #if DT_NODE_EXISTS(DT_NODELABEL(itcm))
21 DT_REG_ADDR(DT_NODELABEL(itcm)),
22 REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(itcm)),
23 DT_REG_SIZE(DT_NODELABEL(itcm)))),
26 #if DT_NODE_EXISTS(DT_NODELABEL(dtcm))
28 DT_REG_ADDR(DT_NODELABEL(dtcm)),
29 REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(dtcm)),
30 DT_REG_SIZE(DT_NODELABEL(dtcm)))),
/Zephyr-latest/soc/espressif/esp32s3/
Dmemory.h10 #define SRAM0_IRAM_START DT_REG_ADDR(DT_NODELABEL(sram0))
11 #define SRAM0_SIZE DT_REG_SIZE(DT_NODELABEL(sram0))
12 #define SRAM1_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram1))
16 #define SRAM2_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram2))
17 #define SRAM2_SIZE DT_REG_SIZE(DT_NODELABEL(sram2))
84 #define AMP_COMM_SIZE DT_REG_SIZE(DT_NODELABEL(ipmmem0)) + DT_REG_SIZE(DT_NODELABEL(shm0)) + \
85 DT_REG_SIZE(DT_NODELABEL(ipm0)) + DT_REG_SIZE(DT_NODELABEL(mbox0))
102 #define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0))
103 #define ICACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(icache0))
104 #define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0))
[all …]

12345678910>>...28