1 /*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 /**
9 * @brief Clock control driver for Infineon CAT1 MCU family.
10 */
11
12 #include <zephyr/drivers/clock_control.h>
13 #include <cyhal_clock.h>
14 #include <cyhal_utils.h>
15 #include <cyhal_clock_impl.h>
16
17 #define GET_CLK_SOURCE_ORD(N) DT_DEP_ORD(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(N), 0))
18
19 /* Enumeration of enabled in device tree Clock, uses for indexing clock info table */
20 enum {
21 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo))
22 INFINEON_CAT1_CLOCK_IMO,
23 #endif
24
25 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho))
26 INFINEON_CAT1_CLOCK_IHO,
27 #endif
28
29 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux0))
30 INFINEON_CAT1_CLOCK_PATHMUX0,
31 #endif
32
33 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux1))
34 INFINEON_CAT1_CLOCK_PATHMUX1,
35 #endif
36
37 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux2))
38 INFINEON_CAT1_CLOCK_PATHMUX2,
39 #endif
40
41 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux3))
42 INFINEON_CAT1_CLOCK_PATHMUX3,
43 #endif
44
45 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux4))
46 INFINEON_CAT1_CLOCK_PATHMUX4,
47 #endif
48
49 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf0))
50 INFINEON_CAT1_CLOCK_HF0,
51 #endif
52
53 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf1))
54 INFINEON_CAT1_CLOCK_HF1,
55 #endif
56
57 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf2))
58 INFINEON_CAT1_CLOCK_HF2,
59 #endif
60
61 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf3))
62 INFINEON_CAT1_CLOCK_HF3,
63 #endif
64
65 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf4))
66 INFINEON_CAT1_CLOCK_HF4,
67 #endif
68
69 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf5))
70 INFINEON_CAT1_CLOCK_HF5,
71 #endif
72
73 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf6))
74 INFINEON_CAT1_CLOCK_HF6,
75 #endif
76
77 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf7))
78 INFINEON_CAT1_CLOCK_HF7,
79 #endif
80
81 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf8))
82 INFINEON_CAT1_CLOCK_HF8,
83 #endif
84
85 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf9))
86 INFINEON_CAT1_CLOCK_HF9,
87 #endif
88
89 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf10))
90 INFINEON_CAT1_CLOCK_HF10,
91 #endif
92
93 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf11))
94 INFINEON_CAT1_CLOCK_HF11,
95 #endif
96
97 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf12))
98 INFINEON_CAT1_CLOCK_HF12,
99 #endif
100
101 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf13))
102 INFINEON_CAT1_CLOCK_HF13,
103 #endif
104
105 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_fast))
106 INFINEON_CAT1_CLOCK_FAST,
107 #endif
108
109 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_slow))
110 INFINEON_CAT1_CLOCK_SLOW,
111 #endif
112
113 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_peri))
114 INFINEON_CAT1_CLOCK_PERI,
115 #endif
116
117 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll0))
118 INFINEON_CAT1_CLOCK_PLL0,
119 #endif
120
121 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1))
122 INFINEON_CAT1_CLOCK_PLL1,
123 #endif
124
125 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(fll0))
126 INFINEON_CAT1_CLOCK_FLL0,
127 #endif
128
129 /* Count of enabled clock */
130 INFINEON_CAT1_ENABLED_CLOCK_COUNT
131 }; /* infineon_cat1_clock_info_name_t */
132
133 /* Clock info structure */
134 struct infineon_cat1_clock_info_t {
135 cyhal_clock_t obj; /* Hal Clock object */
136 uint32_t dt_ord; /* Device tree node's dependency ordinal */
137 };
138
139 /* Lookup table which presents clock objects (cyhal_clock_t) correspondence to ordinal
140 * number of device tree clock nodes.
141 */
142 static struct infineon_cat1_clock_info_t
143 clock_info_table[INFINEON_CAT1_ENABLED_CLOCK_COUNT] = {
144 /* We always have IMO */
145 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo))
146 [INFINEON_CAT1_CLOCK_IMO] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_imo)) },
147 #endif
148
149 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho))
150 [INFINEON_CAT1_CLOCK_IHO] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_iho)) },
151 #endif
152
153 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux0))
154 [INFINEON_CAT1_CLOCK_PATHMUX0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux0)) },
155 #endif
156
157 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux1))
158 [INFINEON_CAT1_CLOCK_PATHMUX1] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux1)) },
159 #endif
160
161 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux2))
162 [INFINEON_CAT1_CLOCK_PATHMUX2] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux2)) },
163 #endif
164
165 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux3))
166 [INFINEON_CAT1_CLOCK_PATHMUX3] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux3)) },
167 #endif
168
169 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux4))
170 [INFINEON_CAT1_CLOCK_PATHMUX4] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(path_mux4)) },
171 #endif
172
173 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf0))
174 [INFINEON_CAT1_CLOCK_HF0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf0)) },
175 #endif
176
177 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf1))
178 [INFINEON_CAT1_CLOCK_HF1] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf1)) },
179 #endif
180
181 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf2))
182 [INFINEON_CAT1_CLOCK_HF2] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf2)) },
183 #endif
184
185 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf3))
186 [INFINEON_CAT1_CLOCK_HF3] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf3)) },
187 #endif
188
189 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf4))
190 [INFINEON_CAT1_CLOCK_HF4] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf4)) },
191 #endif
192
193 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf5))
194 [INFINEON_CAT1_CLOCK_HF5] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf5)) },
195 #endif
196
197 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf6))
198 [INFINEON_CAT1_CLOCK_HF6] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf6)) },
199 #endif
200
201 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf7))
202 [INFINEON_CAT1_CLOCK_HF7] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf7)) },
203 #endif
204
205 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf8))
206 [INFINEON_CAT1_CLOCK_HF8] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf8)) },
207 #endif
208
209 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf9))
210 [INFINEON_CAT1_CLOCK_HF9] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf9)) },
211 #endif
212
213 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf10))
214 [INFINEON_CAT1_CLOCK_HF10] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf10)) },
215 #endif
216
217 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf11))
218 [INFINEON_CAT1_CLOCK_HF11] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf11)) },
219 #endif
220
221 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf12))
222 [INFINEON_CAT1_CLOCK_HF12] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf12)) },
223 #endif
224
225 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf13))
226 [INFINEON_CAT1_CLOCK_HF13] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_hf13)) },
227 #endif
228
229 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_fast))
230 [INFINEON_CAT1_CLOCK_FAST] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_fast)) },
231 #endif
232
233 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_slow))
234 [INFINEON_CAT1_CLOCK_SLOW] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_slow)) },
235 #endif
236
237 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_peri))
238 [INFINEON_CAT1_CLOCK_PERI] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(clk_peri)) },
239 #endif
240
241 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll0))
242 [INFINEON_CAT1_CLOCK_PLL0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(pll0)) },
243 #endif
244
245 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1))
246 [INFINEON_CAT1_CLOCK_PLL1] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(pll1)) },
247 #endif
248
249 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(fll0))
250 [INFINEON_CAT1_CLOCK_FLL0] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(fll0)) },
251 #endif
252 };
253
_configure_path_mux(cyhal_clock_t * clock_obj,cyhal_clock_t * clock_source_obj,const cyhal_clock_t * reserve_obj)254 static cy_rslt_t _configure_path_mux(cyhal_clock_t *clock_obj,
255 cyhal_clock_t *clock_source_obj,
256 const cyhal_clock_t *reserve_obj)
257 {
258 cy_rslt_t rslt;
259
260 ARG_UNUSED(clock_source_obj);
261
262 rslt = cyhal_clock_reserve(clock_obj, reserve_obj);
263
264 if (rslt == CY_RSLT_SUCCESS) {
265 rslt = cyhal_clock_set_source(clock_obj, clock_source_obj);
266 }
267
268 return rslt;
269 }
270
_configure_clk_hf(cyhal_clock_t * clock_obj,cyhal_clock_t * clock_source_obj,const cyhal_clock_t * reserve_obj,uint32_t clock_div)271 static cy_rslt_t _configure_clk_hf(cyhal_clock_t *clock_obj,
272 cyhal_clock_t *clock_source_obj,
273 const cyhal_clock_t *reserve_obj,
274 uint32_t clock_div)
275 {
276 cy_rslt_t rslt;
277
278 rslt = cyhal_clock_reserve(clock_obj, reserve_obj);
279
280 if (rslt == CY_RSLT_SUCCESS) {
281 rslt = cyhal_clock_set_source(clock_obj, clock_source_obj);
282 }
283
284 if (rslt == CY_RSLT_SUCCESS) {
285 rslt = cyhal_clock_set_divider(clock_obj, clock_div);
286 }
287
288 if (rslt == CY_RSLT_SUCCESS) {
289 rslt = cyhal_clock_set_enabled(clock_obj, true, true);
290 }
291
292 return rslt;
293 }
294
_configure_clk_frequency_and_enable(cyhal_clock_t * clock_obj,cyhal_clock_t * clock_source_obj,const cyhal_clock_t * reserve_obj,uint32_t frequency)295 static cy_rslt_t _configure_clk_frequency_and_enable(cyhal_clock_t *clock_obj,
296 cyhal_clock_t *clock_source_obj,
297 const cyhal_clock_t *reserve_obj,
298 uint32_t frequency)
299 {
300 ARG_UNUSED(clock_source_obj);
301 cy_rslt_t rslt;
302
303 rslt = cyhal_clock_reserve(clock_obj, reserve_obj);
304
305 if (rslt == CY_RSLT_SUCCESS) {
306 rslt = cyhal_clock_set_frequency(clock_obj, frequency, NULL);
307 }
308
309 if (rslt == CY_RSLT_SUCCESS) {
310 rslt = cyhal_clock_set_enabled(clock_obj, true, true);
311 }
312
313 return rslt;
314 }
315
_get_hal_obj_from_ord(uint32_t dt_ord)316 static cyhal_clock_t *_get_hal_obj_from_ord(uint32_t dt_ord)
317 {
318 cyhal_clock_t *ret_obj = NULL;
319
320 for (uint32_t i = 0u; i < INFINEON_CAT1_ENABLED_CLOCK_COUNT; i++) {
321 if (clock_info_table[i].dt_ord == dt_ord) {
322 ret_obj = &clock_info_table[i].obj;
323 return ret_obj;
324 }
325 }
326 return ret_obj;
327 }
328
329 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp))
cycfg_ClockStartupError(uint32_t error)330 __WEAK void cycfg_ClockStartupError(uint32_t error)
331 {
332 (void)error; /* Suppress the compiler warning */
333 while (1) {
334 }
335 }
336
Cy_SysClk_Dpll_Hp0_Init(void)337 void Cy_SysClk_Dpll_Hp0_Init(void)
338 {
339 #define CY_CFG_SYSCLK_PLL_ERROR 3
340
341 static cy_stc_dpll_hp_config_t srss_0_clock_0_pll500m_0_hp_pllConfig = {
342 .pDiv = 0,
343 .nDiv = 15,
344 .kDiv = 1,
345 .nDivFract = 0,
346 .freqModeSel = CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL,
347 .ivrTrim = 0x8U,
348 .clkrSel = 0x1U,
349 .alphaCoarse = 0xCU,
350 .betaCoarse = 0x5U,
351 .flockThresh = 0x3U,
352 .flockWait = 0x6U,
353 .flockLkThres = 0x7U,
354 .flockLkWait = 0x4U,
355 .alphaExt = 0x14U,
356 .betaExt = 0x14U,
357 .lfEn = 0x1U,
358 .dcEn = 0x1U,
359 .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
360 };
361 static cy_stc_pll_manual_config_t srss_0_clock_0_pll500m_0_pllConfig = {
362 .hpPllCfg = &srss_0_clock_0_pll500m_0_hp_pllConfig,
363 };
364
365 #if !defined(CY_PDL_TZ_ENABLED)
366 if (Cy_SysClk_PllIsEnabled(SRSS_DPLL_HP_0_PATH_NUM)) {
367 return;
368 }
369 #endif
370 Cy_SysClk_PllDisable(SRSS_DPLL_HP_0_PATH_NUM);
371 if (CY_SYSCLK_SUCCESS !=
372 Cy_SysClk_PllManualConfigure(SRSS_DPLL_HP_0_PATH_NUM,
373 &srss_0_clock_0_pll500m_0_pllConfig)) {
374 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
375 }
376 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_DPLL_HP_0_PATH_NUM, 10000u)) {
377 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
378 }
379 }
380 #endif
381
clock_control_infineon_cat1_init(const struct device * dev)382 static int clock_control_infineon_cat1_init(const struct device *dev)
383 {
384 ARG_UNUSED(dev);
385 cy_rslt_t rslt;
386 cyhal_clock_t *clock_obj = NULL;
387 cyhal_clock_t *clock_source_obj = NULL;
388
389 __attribute__((unused)) uint32 frequency;
390 uint32 clock_div;
391
392 /* Configure IMO */
393 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo))
394 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IMO].obj;
395 if (cyhal_clock_get(clock_obj, &CYHAL_CLOCK_RSC_IMO)) {
396 return -EIO;
397 }
398 #endif
399 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho))
400 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_IHO].obj;
401 if (cyhal_clock_get(clock_obj, &CYHAL_CLOCK_RSC_IHO)) {
402 return -EIO;
403 }
404 #endif
405 #if !DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo)) && \
406 !DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho))
407 #error "IMO clock or IHO clock must be enabled"
408 #endif
409
410 /* Configure the PathMux[0] to source defined in tree device 'path_mux0' node */
411 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux0))
412 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX0].obj;
413 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux0));
414
415 if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[0])) {
416 return -EIO;
417 }
418 #endif
419
420 /* Configure the PathMux[1] to source defined in tree device 'path_mux1' node */
421 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux1))
422 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX1].obj;
423 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux1));
424
425 if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[1])) {
426 return -EIO;
427 }
428 #endif
429
430 /* Configure the PathMux[2] to source defined in tree device 'path_mux2' node */
431 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux2))
432 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX2].obj;
433 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux2));
434
435 if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[2])) {
436 return -EIO;
437 }
438 #endif
439
440 /* Configure the PathMux[3] to source defined in tree device 'path_mux3' node */
441 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux3))
442 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX3].obj;
443 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux3));
444
445 if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[3])) {
446 return -EIO;
447 }
448 #endif
449
450 /* Configure the PathMux[4] to source defined in tree device 'path_mux4' node */
451 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(path_mux4))
452 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PATHMUX4].obj;
453 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(path_mux4));
454
455 if (_configure_path_mux(clock_obj, clock_source_obj, &CYHAL_CLOCK_PATHMUX[4])) {
456 return -EIO;
457 }
458 #endif
459
460 /* Configure FLL0 */
461 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(fll0))
462 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FLL0].obj;
463 frequency = DT_PROP(DT_NODELABEL(fll0), clock_frequency);
464
465 rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj,
466 &CYHAL_CLOCK_FLL, frequency);
467 if (rslt) {
468 return -EIO;
469 }
470 #endif
471
472 /* Configure PLL0 */
473 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll0))
474 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL0].obj;
475 frequency = DT_PROP(DT_NODELABEL(pll0), clock_frequency);
476
477 rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj,
478 &CYHAL_CLOCK_PLL[0], frequency);
479
480 if (rslt) {
481 return -EIO;
482 }
483 #endif
484
485 /* Configure PLL1 */
486 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1))
487 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PLL1].obj;
488 frequency = DT_PROP(DT_NODELABEL(pll1), clock_frequency);
489
490 rslt = _configure_clk_frequency_and_enable(clock_obj, clock_source_obj,
491 &CYHAL_CLOCK_PLL[1], frequency);
492 if (rslt) {
493 return -EIO;
494 }
495 #endif
496
497 /* Configure the HF[0] to source defined in tree device 'clk_hf0' node */
498 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf0))
499 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF0].obj;
500 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf0));
501 clock_div = DT_PROP(DT_NODELABEL(clk_hf0), clock_div);
502
503 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[0], clock_div)) {
504 return -EIO;
505 }
506 #endif
507
508 /* Configure the HF[1] to source defined in tree device 'clk_hf1' node */
509 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf1))
510 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF1].obj;
511 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf1));
512 clock_div = DT_PROP(DT_NODELABEL(clk_hf1), clock_div);
513
514 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[1], clock_div)) {
515 return -EIO;
516 }
517 #endif
518
519 /* Configure the HF[2] to source defined in tree device 'clk_hf2' node */
520 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf2))
521 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF2].obj;
522 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf2));
523 clock_div = DT_PROP(DT_NODELABEL(clk_hf2), clock_div);
524
525 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[2], clock_div)) {
526 return -EIO;
527 }
528 #endif
529
530 /* Configure the HF[3] to source defined in tree device 'clk_hf3' node */
531 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf3))
532 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF3].obj;
533 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf3));
534 clock_div = DT_PROP(DT_NODELABEL(clk_hf3), clock_div);
535
536 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[3], clock_div)) {
537 return -EIO;
538 }
539 #endif
540
541 /* Configure the HF[4] to source defined in tree device 'clk_hf4' node */
542 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf4))
543 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF4].obj;
544 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf4));
545 clock_div = DT_PROP(DT_NODELABEL(clk_hf4), clock_div);
546
547 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[4], clock_div)) {
548 return -EIO;
549 }
550 #endif
551
552 /* Configure the HF[5] to source defined in tree device 'clk_hf5' node */
553 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf5))
554 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF5].obj;
555 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf5));
556 clock_div = DT_PROP(DT_NODELABEL(clk_hf5), clock_div);
557
558 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[5], clock_div)) {
559 return -EIO;
560 }
561 #endif
562
563 /* Configure the HF[6] to source defined in tree device 'clk_hf6' node */
564 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf6))
565 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF6].obj;
566 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf6));
567 clock_div = DT_PROP(DT_NODELABEL(clk_hf6), clock_div);
568
569 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[6], clock_div)) {
570 return -EIO;
571 }
572 #endif
573
574 /* Configure the HF[7] to source defined in tree device 'clk_hf7' node */
575 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf7))
576 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF7].obj;
577 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf7));
578 clock_div = DT_PROP(DT_NODELABEL(clk_hf7), clock_div);
579
580 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[7], clock_div)) {
581 return -EIO;
582 }
583 #endif
584
585 /* Configure the HF[8] to source defined in tree device 'clk_hf8' node */
586 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf8))
587 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF8].obj;
588 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf8));
589 clock_div = DT_PROP(DT_NODELABEL(clk_hf8), clock_div);
590
591 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[8], clock_div)) {
592 return -EIO;
593 }
594 #endif
595
596 /* Configure the HF[9] to source defined in tree device 'clk_hf9' node */
597 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf9))
598 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF9].obj;
599 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf9));
600 clock_div = DT_PROP(DT_NODELABEL(clk_hf9), clock_div);
601
602 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[9], clock_div)) {
603 return -EIO;
604 }
605 #endif
606
607 /* Configure the HF[10] to source defined in tree device 'clk_hf10' node */
608 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf10))
609 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF10].obj;
610 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf10));
611 clock_div = DT_PROP(DT_NODELABEL(clk_hf10), clock_div);
612
613 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[10], clock_div)) {
614 return -EIO;
615 }
616 #endif
617
618 /* Configure the HF[11] to source defined in tree device 'clk_hf11' node */
619 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf11))
620 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF11].obj;
621 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf11));
622 clock_div = DT_PROP(DT_NODELABEL(clk_hf11), clock_div);
623
624 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[11], clock_div)) {
625 return -EIO;
626 }
627 #endif
628
629 /* Configure the HF[12] to source defined in tree device 'clk_hf12' node */
630 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf12))
631 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF12].obj;
632 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf12));
633 clock_div = DT_PROP(DT_NODELABEL(clk_hf12), clock_div);
634
635 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[12], clock_div)) {
636 return -EIO;
637 }
638 #endif
639
640 /* Configure the HF[13] to source defined in tree device 'clk_hf13' node */
641 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_hf13))
642 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_HF13].obj;
643 clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf13));
644 clock_div = DT_PROP(DT_NODELABEL(clk_hf13), clock_div);
645
646 if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[13], clock_div)) {
647 return -EIO;
648 }
649 #endif
650
651 /* Configure the clock fast to source defined in tree device 'clk_fast' node */
652 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_fast))
653 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_FAST].obj;
654 clock_div = DT_PROP(DT_NODELABEL(clk_fast), clock_div);
655
656 rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_FAST);
657 if (rslt == CY_RSLT_SUCCESS) {
658 rslt = cyhal_clock_set_divider(clock_obj, clock_div);
659 }
660 if (rslt) {
661 return -EIO;
662 }
663 #endif
664
665 /* Configure the clock peri to source defined in tree device 'clk_peri' node */
666 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_peri))
667 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_PERI].obj;
668 clock_div = DT_PROP(DT_NODELABEL(clk_peri), clock_div);
669
670 rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_PERI);
671 if (rslt == CY_RSLT_SUCCESS) {
672 rslt = cyhal_clock_set_divider(clock_obj, clock_div);
673 }
674 if (rslt) {
675 return -EIO;
676 }
677 #endif
678
679 /* Configure the clock slow to source defined in tree device 'clk_slow' node */
680 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_slow))
681 clock_obj = &clock_info_table[INFINEON_CAT1_CLOCK_SLOW].obj;
682 clock_div = DT_PROP(DT_NODELABEL(clk_slow), clock_div);
683
684 rslt = cyhal_clock_reserve(clock_obj, &CYHAL_CLOCK_SLOW);
685 if (rslt == CY_RSLT_SUCCESS) {
686 rslt = cyhal_clock_set_divider(clock_obj, clock_div);
687 }
688 if (rslt) {
689 return -EIO;
690 }
691 #endif
692
693 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp))
694 Cy_SysClk_Dpll_Hp0_Init();
695 SystemCoreClockUpdate();
696 #endif
697
698 return (int) rslt;
699 }
700
clock_control_infineon_cat_on_off(const struct device * dev,clock_control_subsys_t sys)701 static int clock_control_infineon_cat_on_off(const struct device *dev,
702 clock_control_subsys_t sys)
703 {
704 ARG_UNUSED(dev);
705 ARG_UNUSED(sys);
706
707 /* On/off functionality are not supported */
708 return -ENOSYS;
709 }
710
711 static DEVICE_API(clock_control, clock_control_infineon_cat1_api) = {
712 .on = clock_control_infineon_cat_on_off,
713 .off = clock_control_infineon_cat_on_off
714 };
715
716 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_imo))
717 DEVICE_DT_DEFINE(DT_NODELABEL(clk_imo),
718 clock_control_infineon_cat1_init,
719 NULL,
720 NULL,
721 NULL,
722 PRE_KERNEL_1,
723 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
724 &clock_control_infineon_cat1_api);
725 #endif
726 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_iho))
727 DEVICE_DT_DEFINE(DT_NODELABEL(clk_iho),
728 clock_control_infineon_cat1_init,
729 NULL,
730 NULL,
731 NULL,
732 PRE_KERNEL_1,
733 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
734 &clock_control_infineon_cat1_api);
735 #endif
736
