1 /* 2 * Copyright (c) 2024 Nordic Semiconductor ASA. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/devicetree.h> 8 #include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h> 9 10 #define USBHS_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(usbhs), core) 11 #define USBHS_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(usbhs), core) 12 13 #define CAN120_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can120), message_ram) 14 #define CAN120_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), message_ram) + \ 15 DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), m_can) 16 17 #define CAN121_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can121), message_ram) 18 #define CAN121_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), message_ram) + \ 19 DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), m_can) 20 21 static struct arm_mpu_region mpu_regions[] = { 22 MPU_REGION_ENTRY("FLASH_0", 23 CONFIG_FLASH_BASE_ADDRESS, 24 REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, 25 CONFIG_FLASH_SIZE * 1024)), 26 MPU_REGION_ENTRY("SRAM_0", 27 CONFIG_SRAM_BASE_ADDRESS, 28 REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, 29 CONFIG_SRAM_SIZE * 1024)), 30 31 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usbhs)) 32 MPU_REGION_ENTRY("USBHS_CORE", USBHS_BASE, 33 REGION_RAM_NOCACHE_ATTR(USBHS_BASE, USBHS_SIZE)), 34 #endif 35 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(can120)) 36 MPU_REGION_ENTRY("CAN120_MCAN", CAN120_BASE, 37 REGION_RAM_NOCACHE_ATTR(CAN120_BASE, CAN120_SIZE)), 38 #endif 39 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(can121)) 40 MPU_REGION_ENTRY("CAN121_MCAN", CAN121_BASE, 41 REGION_RAM_NOCACHE_ATTR(CAN121_BASE, CAN121_SIZE)), 42 #endif 43 }; 44 45 const struct arm_mpu_config mpu_config = { 46 .num_regions = ARRAY_SIZE(mpu_regions), 47 .mpu_regions = mpu_regions, 48 }; 49
