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Searched refs:TG1_WDT_LEVEL_INTR_SOURCE (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c3-intmux.h45 #define TG1_WDT_LEVEL_INTR_SOURCE 35 macro
Desp-xtensa-intmux.h30 #define TG1_WDT_LEVEL_INTR_SOURCE 20 /* TIMER_GROUP1, WATCHDOG, level */ macro
Desp-esp32c6-intmux.h66 #define TG1_WDT_LEVEL_INTR_SOURCE 56 /* interrupt of TIMER_GROUP1, WATCHDOG, level*/ macro
Desp32s3-xtensa-intmux.h61 #define TG1_WDT_LEVEL_INTR_SOURCE 55 /* interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ macro
Desp32s2-xtensa-intmux.h31 #define TG1_WDT_LEVEL_INTR_SOURCE 21 /* TIMER_GROUP1, WATCHDOG, level */ macro
/Zephyr-latest/dts/riscv/espressif/esp32c6/
Desp32c6_common.dtsi170 interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c3/
Desp32c3_common.dtsi291 interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi328 interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi365 interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi453 interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;