Home
last modified time | relevance | path

Searched refs:FROM_CPU_INTR1_SOURCE (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h47 #define FROM_CPU_INTR1_SOURCE 37 macro
Desp-esp32c3-intmux.h61 #define FROM_CPU_INTR1_SOURCE 51 macro
Desp-xtensa-intmux.h35 #define FROM_CPU_INTR1_SOURCE 25 /* int1 from a CPU, level */ macro
Desp-esp32c6-intmux.h33 #define FROM_CPU_INTR1_SOURCE 23 /* interrupt1 generated from a CPU, level*/ macro
Desp32s3-xtensa-intmux.h86 #define FROM_CPU_INTR1_SOURCE 80 /* interrupt1 generated from a CPU, level*/ macro
Desp32s2-xtensa-intmux.h39 #define FROM_CPU_INTR1_SOURCE 29 /* int1 from a CPU, level */ macro
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi133 <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
145 <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
210 interrupts = <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi125 <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
137 <FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;