Home
last modified time | relevance | path

Searched refs:FROM_CPU_INTR0_SOURCE (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h46 #define FROM_CPU_INTR0_SOURCE 36 macro
Desp-esp32c3-intmux.h60 #define FROM_CPU_INTR0_SOURCE 50 macro
Desp-xtensa-intmux.h34 #define FROM_CPU_INTR0_SOURCE 24 /* int0 from a CPU, level */ macro
Desp-esp32c6-intmux.h32 #define FROM_CPU_INTR0_SOURCE 22 /* interrupt0 generated from a CPU, level*/ macro
Desp32s3-xtensa-intmux.h85 #define FROM_CPU_INTR0_SOURCE 79 /* interrupt0 generated from a CPU, level*/ macro
Desp32s2-xtensa-intmux.h38 #define FROM_CPU_INTR0_SOURCE 28 /* int0 from a CPU, level */ macro
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi132 <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
144 <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
203 interrupts = <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi124 <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
136 <FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,