Searched full:selector (Results 1 – 25 of 44) sorted by relevance
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| /Zephyr-latest/include/zephyr/arch/x86/ia32/ |
| D | segmentation.h | 222 * Full linear address (segment selector+offset), for far jumps/calls
227 /** Far pointer segment/gate selector. */
237 * fields in the segment selector well before that.
372 * @param segment_selector Segment selector
389 * @param seg_selector Segment selector of handler
407 * @param sel Segment selector in GDT for desired TSS
416 * Get the TSS segment selector in the GDT for the current IA task
418 * @return Segment selector for current IA task
454 * @return Segment selector in the GDT for the current LDT
468 * @param ldt Segment selector in the GDT for an LDT
[all …]
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| D | thread.h | 114 unsigned short cs; /* 2 : x87 FPU instruction pointer selector */
118 unsigned short ds; /* 2 : x87 FPU instr operand ptr selector */
159 unsigned short cs; /* 2 : x87 FPU instruction pointer selector */
162 unsigned short ds; /* 2 : x87 FPU instr operand ptr selector */
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| D | arch.h | 92 /** If nonzero, specifies a TSS segment selector. Will configure
140 * @param tss_p GDT/LDT segment selector for the TSS representing the task
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| /Zephyr-latest/arch/x86/ |
| D | gen_gdt.py | 207 # Selector 0x08: code descriptor
211 # Selector 0x10: data descriptor
219 # Selector 0x18: main TSS
222 # Selector 0x20: double-fault TSS
226 # Selector 0x28: code descriptor, dpl = 3
230 # Selector 0x30: data descriptor, dpl = 3
235 # Selector 0x18, 0x28 or 0x38 (depending on entries above):
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| D | gen_idt.py | 43 # This will never change, first selector in the GDT after the null selector
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| /Zephyr-latest/include/zephyr/drivers/firmware/scmi/ |
| D | pinctrl.h | 21 #define SCMI_PINCTRL_CONFIG_ATTRIBUTES(fid_valid, cfg_num, selector) \ argument
24 SCMI_FIELD_MAKE(selector, GENMASK(1, 0), 0))
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| /Zephyr-latest/dts/bindings/adc/ |
| D | renesas,smartbond-sdadc.yaml | 23 SDADC clock frequency selector;
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| /Zephyr-latest/dts/bindings/power-domain/ |
| D | power-domain-gpio.yaml | 19 selector. The Linux enable-active-high and gpio-open-drain
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| /Zephyr-latest/dts/bindings/regulator/ |
| D | regulator-fixed.yaml | 32 selector. The Linux enable-active-high and gpio-open-drain
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| D | regulator-gpio.yaml | 65 the GPIO polarity and open-drain status in the phandle selector. The
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| /Zephyr-latest/scripts/kconfig/ |
| D | kconfig.py | 254 for selector in selectors:
255 selector_name = split_expr(selector, AND)[0].name
265 for selector in selectors:
266 selector_name = split_expr(selector, AND)[0].name
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| /Zephyr-latest/arch/x86/core/ia32/ |
| D | crt0.S | 133 movw $DATA_SEG, %ax /* data segment selector (entry = 3) */
346 /* Entry 0 (selector=0x0000): The "NULL descriptor". The CPU never
356 /* Entry 1 (selector=0x0008): Code descriptor: DPL0 */
365 /* Entry 2 (selector=0x0010): Data descriptor: DPL0 */
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| /Zephyr-latest/samples/subsys/usb/audio/headset/src/ |
| D | main.c | 48 LOG_DBG("Control selector %d for channel %d updated", in feature_update()
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| /Zephyr-latest/soc/atmel/sam0/samr21/ |
| D | soc.h | 56 /** GCLK1 source frequency selector */
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| /Zephyr-latest/samples/subsys/usb/audio/headphones_microphone/src/ |
| D | main.c | 50 LOG_DBG("Control selector %d for channel %d updated", in feature_update()
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| /Zephyr-latest/arch/x86/include/intel64/ |
| D | kernel_arch_data.h | 23 uint16_t tr; /* selector for task register */
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| /Zephyr-latest/boards/microchip/ev11l78a/doc/ |
| D | index.rst | 17 - Sink PDO Selector Switch
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| /Zephyr-latest/soc/atmel/sam0/samd21/ |
| D | soc.h | 70 /** GCLK1 source frequency selector */
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| /Zephyr-latest/dts/bindings/i3c/ |
| D | nuvoton,npcx-i3c.yaml | 78 PID[32] ID type selector (i'b1 ramdom value, 1'b0 vendor fixed).
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| /Zephyr-latest/include/zephyr/net/ |
| D | mii.h | 136 /** Selector Field Mask */
138 /** Selector Field */
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| /Zephyr-latest/soc/atmel/sam0/samd20/ |
| D | soc.h | 76 /** GCLK1 source frequency selector */
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| /Zephyr-latest/subsys/usb/device_next/ |
| D | usbd_class.h | 33 * @param[in] speed Speed-dependent descriptor selector
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| /Zephyr-latest/soc/nxp/lpc/lpc55xxx/ |
| D | soc.c | 141 /* Switch PLL1 clock source selector to XTAL32M */ in clock_init()
157 /* Switch PLL0 clock source selector to XTAL32M */ in clock_init()
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_dw.h | 342 * @param pclk_cycles Reset pulse length selector (2 to 256 pclk cycles)
358 * @param timeout_period Timeout period value selector
384 * @param timeout_period Timeout period value selector
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| /Zephyr-latest/include/zephyr/xen/public/ |
| D | xen.h | 343 * per-vcpu selector word to be set. Each bit in the selector covers a
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