1 /* 2 * Copyright (c) 2019 Intel Corp. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_ARCH_X86_INCLUDE_INTEL64_KERNEL_ARCH_DATA_H_ 7 #define ZEPHYR_ARCH_X86_INCLUDE_INTEL64_KERNEL_ARCH_DATA_H_ 8 9 #include <zephyr/arch/x86/mmustructs.h> 10 11 #ifndef _ASMLANGUAGE 12 13 /* linker symbols defining the bounds of the kernel part loaded in locore */ 14 15 extern char _locore_start[], _locore_end[]; 16 17 /* 18 * Per-CPU bootstrapping parameters. See locore.S and cpu.c. 19 */ 20 21 struct x86_cpuboot { 22 volatile int ready; /* CPU has started */ 23 uint16_t tr; /* selector for task register */ 24 struct x86_tss64 *gs_base; /* Base address for GS segment */ 25 uint64_t sp; /* initial stack pointer */ 26 size_t stack_size; /* size of stack */ 27 arch_cpustart_t fn; /* kernel entry function */ 28 void *arg; /* argument for above function */ 29 uint8_t cpu_id; /* CPU ID */ 30 }; 31 32 typedef struct x86_cpuboot x86_cpuboot_t; 33 34 extern uint8_t x86_cpu_loapics[]; /* CPU logical ID -> local APIC ID */ 35 36 #endif /* _ASMLANGUAGE */ 37 38 #ifdef CONFIG_X86_KPTI 39 #define Z_X86_TRAMPOLINE_STACK_SIZE 128 40 #endif 41 42 #ifdef CONFIG_X86_KPTI 43 #define TRAMPOLINE_STACK(n) \ 44 uint8_t z_x86_trampoline_stack##n[Z_X86_TRAMPOLINE_STACK_SIZE] \ 45 __attribute__ ((section(".trampolines"))); 46 47 #define TRAMPOLINE_INIT(n) \ 48 .ist2 = (uint64_t)z_x86_trampoline_stack##n + Z_X86_TRAMPOLINE_STACK_SIZE, 49 #else 50 #define TRAMPOLINE_STACK(n) 51 #define TRAMPOLINE_INIT(n) 52 #endif /* CONFIG_X86_KPTI */ 53 54 #define ACPI_CPU_INIT(n, _) \ 55 uint8_t z_x86_exception_stack##n[CONFIG_X86_EXCEPTION_STACK_SIZE] __aligned(16); \ 56 uint8_t z_x86_nmi_stack##n[CONFIG_X86_EXCEPTION_STACK_SIZE] __aligned(16); \ 57 TRAMPOLINE_STACK(n); \ 58 Z_GENERIC_SECTION(.tss) \ 59 struct x86_tss64 tss##n = { \ 60 TRAMPOLINE_INIT(n) \ 61 .ist6 = (uint64_t)z_x86_nmi_stack##n + CONFIG_X86_EXCEPTION_STACK_SIZE, \ 62 .ist7 = (uint64_t)z_x86_exception_stack##n + CONFIG_X86_EXCEPTION_STACK_SIZE, \ 63 .iomapb = 0xFFFF, .cpu = &(_kernel.cpus[n]) \ 64 } 65 66 #define X86_CPU_BOOT_INIT(n, _) \ 67 { \ 68 .tr = (0x40 + (16 * n)), \ 69 .gs_base = &tss##n, \ 70 .sp = (uint64_t)z_interrupt_stacks[n] + \ 71 K_KERNEL_STACK_LEN(CONFIG_ISR_STACK_SIZE), \ 72 .stack_size = K_KERNEL_STACK_LEN(CONFIG_ISR_STACK_SIZE), \ 73 .fn = z_prep_c, \ 74 .arg = &x86_cpu_boot_arg, \ 75 } 76 77 #define STACK_ARRAY_IDX(n, _) n 78 79 #define DEFINE_STACK_ARRAY_IDX\ 80 LISTIFY(CONFIG_MP_MAX_NUM_CPUS, STACK_ARRAY_IDX, (,)) 81 82 #endif /* ZEPHYR_ARCH_X86_INCLUDE_INTEL64_KERNEL_ARCH_DATA_H_ */ 83
