1 /* 2 * Copyright (c) 2018 Sean Nyekjaer 3 * Copyright (c) 2023 Ionut Catalin Pavel <iocapa@iocapa.com> 4 * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com> 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef _SOC_ATMEL_SAM0_SAMD20_SOC_H_ 10 #define _SOC_ATMEL_SAM0_SAMD20_SOC_H_ 11 12 #ifndef _ASMLANGUAGE 13 14 #define DONT_USE_CMSIS_INIT 15 16 #include <zephyr/types.h> 17 18 #if defined(CONFIG_SOC_SAMD20E14) 19 #include <samd20e14.h> 20 #elif defined(CONFIG_SOC_SAMD20E15) 21 #include <samd20e15.h> 22 #elif defined(CONFIG_SOC_SAMD20E16) 23 #include <samd20e16.h> 24 #elif defined(CONFIG_SOC_SAMD20E17) 25 #include <samd20e17.h> 26 #elif defined(CONFIG_SOC_SAMD20E18) 27 #include <samd20e18.h> 28 #elif defined(CONFIG_SOC_SAMD20G14) 29 #include <samd20g14.h> 30 #elif defined(CONFIG_SOC_SAMD20G15) 31 #include <samd20g15.h> 32 #elif defined(CONFIG_SOC_SAMD20G16) 33 #include <samd20g16.h> 34 #elif defined(CONFIG_SOC_SAMD20G17) 35 #include <samd20g17.h> 36 #elif defined(CONFIG_SOC_SAMD20G18) 37 #include <samd20g18.h> 38 #elif defined(CONFIG_SOC_SAMD20G17U) 39 #include <samd20g17u.h> 40 #elif defined(CONFIG_SOC_SAMD20G18U) 41 #include <samd20g18u.h> 42 #elif defined(CONFIG_SOC_SAMD20J14) 43 #include <samd20j14.h> 44 #elif defined(CONFIG_SOC_SAMD20J15) 45 #include <samd20j15.h> 46 #elif defined(CONFIG_SOC_SAMD20J16) 47 #include <samd20j16.h> 48 #elif defined(CONFIG_SOC_SAMD20J17) 49 #include <samd20j17.h> 50 #elif defined(CONFIG_SOC_SAMD20J18) 51 #include <samd20j18.h> 52 #else 53 #error Library does not support the specified device. 54 #endif 55 56 #endif /* _ASMLANGUAGE */ 57 58 #include "adc_fixup_sam0.h" 59 #include "../common/soc_port.h" 60 #include "../common/atmel_sam0_dt.h" 61 62 /** Processor Clock (HCLK) Frequency */ 63 #define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ 64 65 /** Master Clock (MCK) Frequency */ 66 #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ 67 68 /** Known values */ 69 #define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 70 #define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 71 #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 72 #define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 73 #define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 74 #define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 75 76 /** GCLK1 source frequency selector */ 77 #if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) 78 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 79 #elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) 80 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 81 #elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) 82 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 83 #elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) 84 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 85 #elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) 86 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ 87 #else 88 #error Unsupported GCLK1 clock source. 89 #endif 90 91 /** Dividers and frequency for GCLK0 */ 92 #define SOC_ATMEL_SAM0_GCLK0_DIV \ 93 (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) 94 #define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 95 96 /** DFLL48M output frequency */ 97 #define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ 98 (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) 99 100 /** Dividers and frequency for GCLK1 */ 101 #define SOC_ATMEL_SAM0_GCLK1_DIV \ 102 (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) 103 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ 104 (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) 105 106 /** DFLL48M output multiplier */ 107 #define SOC_ATMEL_SAM0_DFLL48M_MUL \ 108 (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) 109 110 /** Frequency for GCLK2 */ 111 #define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 112 113 /** Dividers and frequency for GCLK3 */ 114 #define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 115 #define SOC_ATMEL_SAM0_GCLK3_DIV \ 116 (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) 117 118 #define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 119 #define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 120 #define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 121 122 #endif /* _SOC_ATMEL_SAM0_SAMD20_SOC_H_ */ 123
