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/Zephyr-Core-3.5.0/tests/bluetooth/tester/src/
Dbtp_l2cap.c1 /* l2cap.c - Bluetooth L2CAP Tester */
6 * SPDX-License-Identifier: Apache-2.0
25 #define CHANNELS 2 macro
28 NET_BUF_POOL_FIXED_DEFINE(data_pool, CHANNELS, DATA_BUF_SIZE, 8, NULL);
39 } channels[CHANNELS]; variable
58 ev->chan_id = chan->chan_id; in recv_cb()
59 ev->data_length = sys_cpu_to_le16(buf->len); in recv_cb()
60 memcpy(ev->data, buf->data, buf->len); in recv_cb()
63 recv_cb_buf, sizeof(*ev) + buf->len); in recv_cb()
65 if (chan->hold_credit && !chan->pending_credit) { in recv_cb()
[all …]
/Zephyr-Core-3.5.0/dts/bindings/dac/
Dgd,gd32-dac.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "gd,gd32-dac"
8 include: [dac-controller.yaml, reset-device.yaml, pinctrl-device.yaml]
20 num-channels:
22 description: Number of DAC output channels
25 reset-val:
30 "#io-channel-cells":
33 io-channel-cells:
34 - output
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32f3x0/
Dgd32f350.dtsi4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "gd,gd32-dac";
17 num-channels = <1>;
19 #io-channel-cells = <1>;
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32a50x/
Dgd32a50x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32a50x-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32a50x.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/dma/
Dnxp,lpc-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-dma"
8 include: dma-controller.yaml
17 dma-channels:
20 nxp,dma-num-of-otrigs:
24 nxp,dma-otrig-base-address:
28 nxp,dma-itrig-base-address:
32 "#dma-cells":
37 # - #dma-cells : Must be <1>.
40 dma-cells:
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/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32e50x/
Dgd32e50x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/clock/gd32e50x-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32e50x.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-m33";
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/Zephyr-Core-3.5.0/samples/drivers/led_lp50xx/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/led/led.h>
52 for (color = 0; color < info->num_colors; color++) { in prepare_color_buffer()
53 switch (info->color_mapping[color]) { in prepare_color_buffer()
65 info->color_mapping[color]); in prepare_color_buffer()
66 return -EINVAL; in prepare_color_buffer()
74 * @brief Run tests on a single LED using the LED-based API syscalls.
154 * @brief Run tests on all the LEDs using the channel-based API syscalls.
184 col = &buffer[info->index * 3]; in run_channel_test()
198 LOG_ERR("Failed to write channels, start=%d num=%d" in run_channel_test()
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/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32e10x/
Dgd32e10x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/gd32e10x-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32e10x.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(120)>;
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/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32f4xx/
Dgd32f4xx.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <zephyr/dt-bindings/clock/gd32f4xx-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32f4xx.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
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/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32f403/
Dgd32f403.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32f403-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32f403.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-m4f";
[all …]
/Zephyr-Core-3.5.0/dts/arm/atmel/
Dsaml21.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "atmel,sam0-usb";
16 num-bidir-endpoints = <8>;
20 compatible = "atmel,sam0-dmac";
23 #dma-cells = <2>;
27 compatible = "atmel,sam0-tcc";
31 clock-names = "GCLK", "MCLK";
33 channels = <4>;
34 counter-size = <24>;
38 compatible = "atmel,sam0-tcc";
[all …]
Dsamr21.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 port-c = &portc;
16 compatible = "atmel,sam0-usb";
20 num-bidir-endpoints = <8>;
24 compatible = "atmel,sam0-dmac";
27 #dma-cells = <2>;
34 compatible = "atmel,sam0-gpio";
36 gpio-controller;
37 #gpio-cells = <2>;
38 #atmel,pin-cells = <2>;
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Dsamd21.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 tc-6 = &tc6;
16 compatible = "atmel,sam0-usb";
20 num-bidir-endpoints = <8>;
24 compatible = "atmel,sam0-dmac";
27 #dma-cells = <2>;
31 compatible = "atmel,sam0-tc32";
35 clock-names = "GCLK", "PM";
39 compatible = "atmel,sam0-tcc";
43 clock-names = "GCLK", "PM";
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/Zephyr-Core-3.5.0/dts/arm/st/h7/
Dstm32h745.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h745", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
23 compatible = "st,stm32-nv-flash", "soc-nv-flash";
24 write-block-size = <32>;
[all …]
Dstm32h743.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h743", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
25 dma-requests= <107>;
29 dma-requests= <107>;
[all …]
Dstm32h750.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h750", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
25 dma-requests= <107>;
29 dma-requests= <107>;
[all …]
Dstm32h7a3.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
9 #include <zephyr/dt-bindings/flash_controller/ospi.h>
11 /delete-node/ &adc3;
15 compatible = "st,stm32h7a3", "st,stm32h7", "simple-bus";
17 flash-controller@52002000 {
19 compatible = "st,stm32-nv-flash", "soc-nv-flash";
20 write-block-size = <16>;
21 erase-block-size = <DT_SIZE_K(8)>;
23 max-erase-time = <3>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/adc/
Dst,stm32-adc.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "st,stm32-adc"
9 include: [adc-controller.yaml, pinctrl-device.yaml]
21 "#io-channel-cells":
24 pinctrl-0:
27 pinctrl-names:
30 st,adc-clock-source:
34 - 1 # SYNC for synchronous ADC clock source
35 - 2 # ASYNC for asynchronous ADC clock source
38 - <SYNC>: derived from the bus clock.
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/Zephyr-Core-3.5.0/dts/arm/nxp/
Dnxp_lpc55S2x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
21 zephyr,flash-controller = &iap;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
Dnxp_lpc55S6x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 #include <arm/armv8-m.dtsi>
22 zephyr,flash-controller = &iap;
26 #address-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/interrupt-controller/
Dcypress,psoc6-intmux.yaml3 # SPDX-License-Identifier: Apache-2.0
8 The PSoC-6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
10 to be processed in the Cortex-M0+ CPU.
13 configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
14 4 interrupt sources by grouping intmux channels. These means that each byte
17 Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
21 configuration and how the Cortex-M0+ NVIC sources are organized. Each
22 channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
23 The vector number selects the PSoC-6 peripheral interrupt source for the
24 Cortex-M0+ NVIC controller line.
[all …]
/Zephyr-Core-3.5.0/dts/riscv/gigadevice/
Dgd32vf103.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/timer/nuclei-systimer.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32vf103-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32vf103.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/c0/
Dstm32c0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/stm32c0_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
14 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
15 #include <zephyr/dt-bindings/reset/stm32c0_reset.h>
[all …]
/Zephyr-Core-3.5.0/drivers/dma/
Ddma_gd32.c4 * SPDX-License-Identifier: Apache-2.0
63 uint32_t channels; member
81 struct dma_gd32_channel *channels; member
227 gd32_dma_transfer_number_config(uint32_t reg, dma_channel_enum ch, uint32_t num) in gd32_dma_transfer_number_config() argument
229 GD32_DMA_CHCNT(reg, ch) = (num & DMA_CHXCNT_CNT); in gd32_dma_transfer_number_config()
245 DMA_INTC1(reg) |= DMA_FLAG_ADD(flag, ch - DMA_CH4); in gd32_dma_interrupt_flag_clear()
259 DMA_INTC1(reg) |= DMA_FLAG_ADD(flag, ch - DMA_CH4); in gd32_dma_flag_clear()
273 return (DMA_INTF1(reg) & DMA_FLAG_ADD(flag, ch - DMA_CH4)); in gd32_dma_interrupt_flag_get()
294 DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, ch - DMA_CH4); in gd32_dma_deinit()
342 const struct dma_gd32_config *cfg = dev->config; in dma_gd32_config()
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/l0/
Dstm32l0.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32l0_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]

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