1/* 2 * Copyright (c) 2020, Linaro Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <zephyr/dt-bindings/adc/adc.h> 9#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> 10#include <zephyr/dt-bindings/gpio/gpio.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12#include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h> 13#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 14#include <arm/armv8-m.dtsi> 15 16/ { 17 aliases { 18 watchdog0 = &wwdt0; 19 }; 20 21 chosen { 22 zephyr,flash-controller = &iap; 23 }; 24 25 cpus: cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu@0 { 30 compatible = "arm,cortex-m33f"; 31 reg = <0>; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 mpu: mpu@e000ed90 { 36 compatible = "arm,armv8m-mpu"; 37 reg = <0xe000ed90 0x40>; 38 arm,num-mpu-regions = <8>; 39 }; 40 }; 41 cpu@1 { 42 compatible = "arm,cortex-m33"; 43 reg = <1>; 44 }; 45 }; 46}; 47 48&sram { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 52 sramx: memory@4000000 { 53 compatible = "mmio-sram"; 54 reg = <0x4000000 DT_SIZE_K(32)>; 55 }; 56 57 /* lpc55S6x Memory configurations: 58 * 59 * RAM blocks SRAM0 through SRAM4 are contiguous address ranges 60 * 61 * LPC55S66: 144KB RAM, RAMX: 32K, SRAM0: 32K 62 * LPC55S69: 320KB RAM, RAMX: 32K, SRAM0: 64K, SRAM1: 64K, 63 * SRAM2: 64K, SRAM3: 64K, SRAM4: 16K 64 */ 65 sram0: memory@20000000 { 66 compatible = "mmio-sram"; 67 reg = <0x20000000 DT_SIZE_K(64)>; 68 }; 69 70 sram1: memory@20010000 { 71 compatible = "mmio-sram"; 72 reg = <0x20010000 DT_SIZE_K(64)>; 73 }; 74 75 sram2: memory@20020000 { 76 compatible = "mmio-sram"; 77 reg = <0x20020000 DT_SIZE_K(64)>; 78 }; 79 80 sram3: memory@20030000 { 81 compatible = "mmio-sram"; 82 reg = <0x20030000 DT_SIZE_K(64)>; 83 }; 84 85 sram4: memory@20040000 { 86 compatible = "mmio-sram"; 87 reg = <0x20040000 DT_SIZE_K(16)>; 88 }; 89}; 90 91&peripheral { 92 #address-cells = <1>; 93 #size-cells = <1>; 94 95 usb_sram: memory@100000 { 96 compatible = "zephyr,memory-region", "mmio-sram"; 97 reg = <0x100000 DT_SIZE_K(16)>; 98 zephyr,memory-region = "USB_SRAM"; 99 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; 100 }; 101 102 syscon: syscon@0 { 103 compatible = "nxp,lpc-syscon"; 104 reg = <0x0 0x1000>; 105 #clock-cells = <1>; 106 }; 107 108 iap: flash-controller@34000 { 109 compatible = "nxp,iap-fmc55"; 110 reg = <0x34000 0x1000>; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 status = "disabled"; 114 flash0: flash@0 { 115 compatible = "soc-nv-flash"; 116 reg = <0x0 DT_SIZE_K(630)>; 117 erase-block-size = <512>; 118 write-block-size = <512>; 119 }; 120 121 flash_reserved: flash@9D800 { 122 compatible = "soc-nv-flash"; 123 reg = <0x9D800 DT_SIZE_K(9)>; 124 status = "disabled"; 125 }; 126 127 uuid: flash@9fc70 { 128 compatible = "nxp,lpc-uid"; 129 reg = <0x9fc70 0x10>; 130 }; 131 132 boot_rom: flash@3000000 { 133 compatible = "soc-nv-flash"; 134 reg = <0x3000000 DT_SIZE_K(128)>; 135 }; 136 }; 137 138 iocon: iocon@1000 { 139 compatible = "nxp,lpc-iocon"; 140 reg = <0x1000 0x100>; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 ranges = <0x0 0x1000 0x100>; 144 pinctrl: pinctrl { 145 compatible = "nxp,lpc-iocon-pinctrl"; 146 }; 147 }; 148 149 gpio0: gpio@0 { 150 compatible = "nxp,lpc-gpio"; 151 reg = <0x8c000 0x2488>; 152 int-source = "pint"; 153 gpio-controller; 154 #gpio-cells = <2>; 155 port = <0>; 156 }; 157 158 gpio1: gpio@1 { 159 compatible = "nxp,lpc-gpio"; 160 reg = <0x8c000 0x2488>; 161 int-source = "pint"; 162 gpio-controller; 163 #gpio-cells = <2>; 164 port = <1>; 165 }; 166 167 pint: pint@4000 { 168 compatible = "nxp,pint"; 169 reg = <0x4000 0x1000>; 170 interrupt-controller; 171 #interrupt-cells = <1>; 172 #address-cells = <0>; 173 interrupts = <4 2>, <5 2>, <6 2>, <7 2>, 174 <32 2>, <33 2>, <34 2>, <35 2>; 175 num-lines = <8>; 176 num-inputs = <64>; 177 }; 178 179 dma0: dma-controller@82000 { 180 compatible = "nxp,lpc-dma"; 181 reg = <0x82000 0x1000>; 182 interrupts = <1 0>; 183 dma-channels = <23>; 184 nxp,dma-num-of-otrigs = <4>; 185 nxp,dma-otrig-base-address = <LPC55S69_DMA0_OTRIG_BASE>; 186 nxp,dma-itrig-base-address = <LPC55S69_DMA0_ITRIG_BASE>; 187 status = "disabled"; 188 #dma-cells = <1>; 189 }; 190 191 dma1: dma-controller@a7000 { 192 compatible = "nxp,lpc-dma"; 193 reg = <0xa7000 0x1000>; 194 interrupts = <58 0>; 195 dma-channels = <10>; 196 nxp,dma-num-of-otrigs = <4>; 197 nxp,dma-otrig-base-address = <LPC55S69_DMA1_OTRIG_BASE>; 198 nxp,dma-itrig-base-address = <LPC55S69_DMA1_ITRIG_BASE>; 199 status = "disabled"; 200 #dma-cells = <1>; 201 }; 202 203 mailbox0:mailbox@8b000 { 204 compatible = "nxp,lpc-mailbox"; 205 reg = <0x8b000 0xEC>; 206 interrupts = <31 0>; 207 status = "disabled"; 208 }; 209 210 flexcomm0: flexcomm@86000 { 211 compatible = "nxp,lpc-flexcomm"; 212 reg = <0x86000 0x1000>; 213 interrupts = <14 0>; 214 clocks = <&syscon MCUX_FLEXCOMM0_CLK>; 215 status = "disabled"; 216 }; 217 218 flexcomm1: flexcomm@87000 { 219 compatible = "nxp,lpc-flexcomm"; 220 reg = <0x87000 0x1000>; 221 interrupts = <15 0>; 222 clocks = <&syscon MCUX_FLEXCOMM1_CLK>; 223 status = "disabled"; 224 }; 225 226 flexcomm2: flexcomm@88000 { 227 compatible = "nxp,lpc-flexcomm"; 228 reg = <0x88000 0x1000>; 229 interrupts = <16 0>; 230 clocks = <&syscon MCUX_FLEXCOMM2_CLK>; 231 status = "disabled"; 232 }; 233 234 flexcomm3: flexcomm@89000 { 235 compatible = "nxp,lpc-flexcomm"; 236 reg = <0x89000 0x1000>; 237 interrupts = <17 0>; 238 clocks = <&syscon MCUX_FLEXCOMM3_CLK>; 239 status = "disabled"; 240 }; 241 242 flexcomm4: flexcomm@8a000 { 243 compatible = "nxp,lpc-flexcomm"; 244 reg = <0x8a000 0x1000>; 245 interrupts = <18 0>; 246 clocks = <&syscon MCUX_FLEXCOMM4_CLK>; 247 status = "disabled"; 248 }; 249 250 flexcomm5: flexcomm@96000 { 251 compatible = "nxp,lpc-flexcomm"; 252 reg = <0x96000 0x1000>; 253 interrupts = <19 0>; 254 clocks = <&syscon MCUX_FLEXCOMM5_CLK>; 255 status = "disabled"; 256 }; 257 258 flexcomm6: flexcomm@97000 { 259 compatible = "nxp,lpc-flexcomm"; 260 reg = <0x97000 0x1000>; 261 interrupts = <20 0>; 262 clocks = <&syscon MCUX_FLEXCOMM6_CLK>; 263 status = "disabled"; 264 }; 265 266 flexcomm7: flexcomm@98000 { 267 compatible = "nxp,lpc-flexcomm"; 268 reg = <0x98000 0x1000>; 269 interrupts = <21 0>; 270 clocks = <&syscon MCUX_FLEXCOMM7_CLK>; 271 status = "disabled"; 272 }; 273 274 sdif: sdif@9b000 { 275 compatible = "nxp,lpc-sdif"; 276 reg = <0x9b000 0x1000>; 277 interrupts = <42 0>; 278 clocks = <&syscon MCUX_SDIF_CLK>; 279 status = "disabled"; 280 }; 281 282 hs_lspi: spi@9f000 { 283 compatible = "nxp,lpc-spi"; 284 /* Enabling cs-gpios below will allow using GPIO CS, 285 rather than Flexcomm SS */ 286 /* cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>, 287 <&gpio1 1 GPIO_ACTIVE_LOW>, 288 <&gpio1 12 GPIO_ACTIVE_LOW>, 289 <&gpio1 26 GPIO_ACTIVE_LOW>; */ 290 reg = <0x9f000 0x1000>; 291 interrupts = <59 0>; 292 clocks = <&syscon MCUX_HS_SPI_CLK>; 293 status = "disabled"; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 }; 297 298 rng: rng@3a000 { 299 compatible = "nxp,lpc-rng"; 300 reg = <0x3a000 0x1000>; 301 status = "okay"; 302 }; 303 304 wwdt0: watchdog@c000 { 305 compatible = "nxp,lpc-wwdt"; 306 reg = <0xc000 0x1000>; 307 interrupts = <0 0>; 308 status = "disabled"; 309 clk-divider = <1>; 310 }; 311 312 adc0: adc@A0000 { 313 compatible = "nxp,lpc-lpadc"; 314 reg = <0xA0000 0x1000>; 315 interrupts = <22 0>; 316 status = "disabled"; 317 clk-divider = <8>; 318 clk-source = <0>; 319 voltage-ref= <1>; 320 calibration-average = <128>; 321 power-level = <0>; 322 offset-value-a = <10>; 323 offset-value-b = <10>; 324 #io-channel-cells = <1>; 325 }; 326 327 usbfs: usbfs@84000 { 328 compatible = "nxp,mcux-usbd"; 329 reg = <0x84000 0x1000>; 330 interrupts = <28 1>; 331 num-bidir-endpoints = <5>; 332 maximum-speed = "full-speed"; 333 usb-controller-index = "LpcIp3511Fs0"; 334 status = "disabled"; 335 }; 336 337 usbhs: usbhs@94000 { 338 compatible = "nxp,mcux-usbd"; 339 reg = <0x94000 0x1000>; 340 interrupts = <47 1>; 341 num-bidir-endpoints = <6>; 342 usb-controller-index = "LpcIp3511Hs0"; 343 status = "disabled"; 344 }; 345 346 ctimer0: ctimer@8000 { 347 compatible = "nxp,lpc-ctimer"; 348 reg = <0x8000 0x1000>; 349 interrupts = <10 0>; 350 status = "disabled"; 351 clk-source = <3>; 352 clocks = <&syscon MCUX_CTIMER0_CLK>; 353 mode = <0>; 354 input = <0>; 355 prescale = <0>; 356 }; 357 358 ctimer1: ctimer@9000 { 359 compatible = "nxp,lpc-ctimer"; 360 reg = <0x9000 0x1000>; 361 interrupts = <11 0>; 362 status = "disabled"; 363 clk-source = <3>; 364 clocks = <&syscon MCUX_CTIMER1_CLK>; 365 mode = <0>; 366 input = <0>; 367 prescale = <0>; 368 }; 369 370 ctimer2: ctimer@28000 { 371 compatible = "nxp,lpc-ctimer"; 372 reg = <0x28000 0x1000>; 373 interrupts = <36 0>; 374 status = "disabled"; 375 clk-source = <3>; 376 clocks = <&syscon MCUX_CTIMER2_CLK>; 377 mode = <0>; 378 input = <0>; 379 prescale = <0>; 380 }; 381 382 ctimer3: ctimer@29000 { 383 compatible = "nxp,lpc-ctimer"; 384 reg = <0x29000 0x1000>; 385 interrupts = <13 0>; 386 status = "disabled"; 387 clk-source = <3>; 388 clocks = <&syscon MCUX_CTIMER3_CLK>; 389 mode = <0>; 390 input = <0>; 391 prescale = <0>; 392 }; 393 394 ctimer4: ctimer@2A000 { 395 compatible = "nxp,lpc-ctimer"; 396 reg = <0x2A000 0x1000>; 397 interrupts = <37 0>; 398 status = "disabled"; 399 clk-source = <3>; 400 clocks = <&syscon MCUX_CTIMER4_CLK>; 401 mode = <0>; 402 input = <0>; 403 prescale = <0>; 404 }; 405 406 sc_timer: pwm@85000 { 407 compatible = "nxp,sctimer-pwm"; 408 reg = <0x85000 0x1000>; 409 interrupts = <12 0>; 410 status = "disabled"; 411 clocks = <&syscon MCUX_SCTIMER_CLK>; 412 prescaler = <2>; 413 #pwm-cells = <3>; 414 }; 415}; 416 417&nvic { 418 arm,num-irq-priority-bits = <3>; 419}; 420
