1/* 2 * Copyright (c) 2020 Lemonbeat GmbH 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8-m.dtsi> 8#include <zephyr/dt-bindings/adc/adc.h> 9#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> 10#include <zephyr/dt-bindings/gpio/gpio.h> 11#include <zephyr/dt-bindings/i2c/i2c.h> 12#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 13#include <mem.h> 14 15/ { 16 aliases { 17 watchdog0 = &wwdt0; 18 }; 19 20 chosen { 21 zephyr,flash-controller = &iap; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu@0 { 29 compatible = "arm,cortex-m33f"; 30 reg = <0>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 34 mpu: mpu@e000ed90 { 35 compatible = "arm,armv8m-mpu"; 36 reg = <0xe000ed90 0x40>; 37 arm,num-mpu-regions = <8>; 38 }; 39 }; 40 }; 41}; 42 43&sram { 44 #address-cells = <1>; 45 #size-cells = <1>; 46 47 sramx: memory@4000000 { 48 compatible = "mmio-sram"; 49 reg = <0x4000000 DT_SIZE_K(32)>; 50 }; 51 52 sram0: memory@20000000 { 53 compatible = "mmio-sram"; 54 reg = <0x20000000 DT_SIZE_K(64)>; 55 }; 56 57 sram1: memory@20010000 { 58 compatible = "zephyr,memory-region", "mmio-sram"; 59 reg = <0x20010000 DT_SIZE_K(64)>; 60 zephyr,memory-region = "SRAM1"; 61 }; 62 63 sram2: memory@20020000 { 64 compatible = "zephyr,memory-region", "mmio-sram"; 65 reg = <0x20020000 DT_SIZE_K(64)>; 66 zephyr,memory-region = "SRAM2"; 67 }; 68 69 sram4: memory@20040000 { 70 compatible = "zephyr,memory-region", "mmio-sram"; 71 reg = <0x20040000 DT_SIZE_K(16)>; 72 zephyr,memory-region = "SRAM4"; 73 }; 74 75 usb_sram: memory@40100000 { 76 compatible = "zephyr,memory-region", "mmio-sram"; 77 reg = <0x40100000 DT_SIZE_K(16)>; 78 zephyr,memory-region = "USB_SRAM"; 79 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; 80 }; 81}; 82 83&peripheral { 84 #address-cells = <1>; 85 #size-cells = <1>; 86 87 syscon: syscon@0 { 88 compatible = "nxp,lpc-syscon"; 89 reg = <0x0 0x1000>; 90 #clock-cells = <1>; 91 }; 92 93 iap: flash-controller@34000 { 94 compatible = "nxp,iap-fmc55"; 95 reg = <0x34000 0x1000>; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 status = "disabled"; 99 100 flash0: flash@0 { 101 compatible = "soc-nv-flash"; 102 reg = <0x0 DT_SIZE_K(512)>; 103 erase-block-size = <512>; 104 write-block-size = <512>; 105 }; 106 107 uuid: flash@9fc70 { 108 compatible = "nxp,lpc-uid"; 109 reg = <0x9fc70 0x10>; 110 }; 111 112 boot_rom: flash@3000000 { 113 compatible = "soc-nv-flash"; 114 reg = <0x3000000 DT_SIZE_K(128)>; 115 }; 116 }; 117 118 iocon: iocon@1000 { 119 compatible = "nxp,lpc-iocon"; 120 reg = <0x1000 0x100>; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0x0 0x1000 0x100>; 124 pinctrl: pinctrl { 125 compatible = "nxp,lpc-iocon-pinctrl"; 126 }; 127 }; 128 129 gpio0: gpio@0 { 130 compatible = "nxp,lpc-gpio"; 131 reg = <0x8c000 0x2488>; 132 int-source = "pint"; 133 gpio-controller; 134 #gpio-cells = <2>; 135 port = <0>; 136 }; 137 138 gpio1: gpio@1 { 139 compatible = "nxp,lpc-gpio"; 140 reg = <0x8c000 0x2488>; 141 int-source = "pint"; 142 gpio-controller; 143 #gpio-cells = <2>; 144 port = <1>; 145 }; 146 147 pint: pint@4000 { 148 compatible = "nxp,pint"; 149 reg = <0x4000 0x1000>; 150 interrupt-controller; 151 #interrupt-cells = <1>; 152 #address-cells = <0>; 153 interrupts = <4 2>, <5 2>, <6 2>, <7 2>, 154 <32 2>, <33 2>, <34 2>, <35 2>; 155 num-lines = <8>; 156 num-inputs = <64>; 157 }; 158 159 dma0: dma-controller@82000 { 160 compatible = "nxp,lpc-dma"; 161 reg = <0x82000 0x1000>; 162 interrupts = <1 0>; 163 dma-channels = <23>; 164 status = "disabled"; 165 #dma-cells = <1>; 166 }; 167 168 dma1: dma-controller@a7000 { 169 compatible = "nxp,lpc-dma"; 170 reg = <0xa7000 0x1000>; 171 interrupts = <58 0>; 172 dma-channels = <10>; 173 status = "disabled"; 174 #dma-cells = <1>; 175 }; 176 177 flexcomm0: flexcomm@86000 { 178 compatible = "nxp,lpc-flexcomm"; 179 reg = <0x86000 0x1000>; 180 interrupts = <14 0>; 181 clocks = <&syscon MCUX_FLEXCOMM0_CLK>; 182 status = "disabled"; 183 }; 184 185 flexcomm1: flexcomm@87000 { 186 compatible = "nxp,lpc-flexcomm"; 187 reg = <0x87000 0x1000>; 188 interrupts = <15 0>; 189 clocks = <&syscon MCUX_FLEXCOMM1_CLK>; 190 status = "disabled"; 191 }; 192 193 flexcomm2: flexcomm@88000 { 194 compatible = "nxp,lpc-flexcomm"; 195 reg = <0x88000 0x1000>; 196 interrupts = <16 0>; 197 clocks = <&syscon MCUX_FLEXCOMM2_CLK>; 198 status = "disabled"; 199 }; 200 201 flexcomm3: flexcomm@89000 { 202 compatible = "nxp,lpc-flexcomm"; 203 reg = <0x89000 0x1000>; 204 interrupts = <17 0>; 205 clocks = <&syscon MCUX_FLEXCOMM3_CLK>; 206 status = "disabled"; 207 }; 208 209 flexcomm4: flexcomm@8a000 { 210 compatible = "nxp,lpc-flexcomm"; 211 reg = <0x8a000 0x1000>; 212 interrupts = <18 0>; 213 clocks = <&syscon MCUX_FLEXCOMM4_CLK>; 214 status = "disabled"; 215 }; 216 217 flexcomm5: flexcomm@96000 { 218 compatible = "nxp,lpc-flexcomm"; 219 reg = <0x96000 0x1000>; 220 interrupts = <19 0>; 221 clocks = <&syscon MCUX_FLEXCOMM5_CLK>; 222 status = "disabled"; 223 }; 224 225 flexcomm6: flexcomm@97000 { 226 compatible = "nxp,lpc-flexcomm"; 227 reg = <0x97000 0x1000>; 228 interrupts = <20 0>; 229 clocks = <&syscon MCUX_FLEXCOMM6_CLK>; 230 status = "disabled"; 231 }; 232 233 flexcomm7: flexcomm@98000 { 234 compatible = "nxp,lpc-flexcomm"; 235 reg = <0x98000 0x1000>; 236 interrupts = <21 0>; 237 clocks = <&syscon MCUX_FLEXCOMM7_CLK>; 238 status = "disabled"; 239 }; 240 241 hs_lspi: spi@9f000 { 242 compatible = "nxp,lpc-spi"; 243 /* Enabling cs-gpios below will allow using GPIO CS, 244 rather than Flexcomm SS */ 245 /* cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>, 246 <&gpio1 1 GPIO_ACTIVE_LOW>, 247 <&gpio1 12 GPIO_ACTIVE_LOW>, 248 <&gpio1 26 GPIO_ACTIVE_LOW>; */ 249 reg = <0x9f000 0x1000>; 250 interrupts = <59 0>; 251 clocks = <&syscon MCUX_HS_SPI_CLK>; 252 status = "disabled"; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 }; 256 257 rng: rng@3a000 { 258 compatible = "nxp,lpc-rng"; 259 reg = <0x3a000 0x1000>; 260 status = "okay"; 261 }; 262 263 wwdt0: watchdog@c000 { 264 compatible = "nxp,lpc-wwdt"; 265 reg = <0xc000 0x1000>; 266 interrupts = <0 0>; 267 status = "disabled"; 268 clk-divider = <1>; 269 }; 270 271 adc0: adc@a0000 { 272 compatible = "nxp,lpc-lpadc"; 273 reg = <0xa0000 0x1000>; 274 interrupts = <22 0>; 275 status = "disabled"; 276 clk-divider = <8>; 277 clk-source = <0>; 278 voltage-ref= <1>; 279 calibration-average = <128>; 280 power-level = <0>; 281 offset-value-a = <10>; 282 offset-value-b = <10>; 283 #io-channel-cells = <1>; 284 }; 285 286 usbhs: usbhs@144000 { 287 compatible = "nxp,mcux-usbd"; 288 reg = <0x94000 0x1000>; 289 interrupts = <47 1>; 290 num-bidir-endpoints = <6>; 291 usb-controller-index = "LpcIp3511Hs0"; 292 status = "disabled"; 293 }; 294}; 295 296&nvic { 297 arm,num-irq-priority-bits = <3>; 298}; 299
