1# Copyright (c) 2018 Foundries.io
2# Copyright (c) 2020 ATL Electronics
3# SPDX-License-Identifier: Apache-2.0
4
5description: |
6  Cypress Interrupt Multiplex
7
8  The PSoC-6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
9  user can select up to 32 interrupts sources from the 240 possible vectors
10  to be processed in the Cortex-M0+ CPU.
11
12  At CPU Sub System (CPUSS) there are 8 special registers (intmux[0~7]) to
13  configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
14  4 interrupt sources by grouping intmux channels. These means that each byte
15  from intmux[0~7] store a 'vector number' which selects the peripheral
16  interrupt source in the multiplexer. The multiplexer is placed before
17  Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
18  directly connected to NVIC and doesn't require any special configuration.
19
20  On a general view, the below represents the Interrupt Multiplexer
21  configuration and how the Cortex-M0+ NVIC sources are organized. Each
22  channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
23  The vector number selects the PSoC-6 peripheral interrupt source for the
24  Cortex-M0+ NVIC controller line.
25
26  intmux[0] = {ch03, ch02, ch01, ch00}
27  intmux[1] = {ch07, ch06, ch05, ch04}
28  ...
29  intmux[7] = {ch31, ch30, ch29, ch28}
30
31  In pratical terms, the Cortex-M0+ requires user to define all NVIC interrupt
32  sources and the proper NVIC interrupt order. With that, the system configures
33  the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
34  More information about it at PSoC-6 Architecture Technical Reference Manual,
35  section CPU Sub System (CPUSS) Registers.
36
37
38  The below fragment configure the GPIO Port 0 to generate an interrupt at
39  Cortex-M0+ NVIC:
40
41  At psoc6.dtsi file the gpio_prt0 peripheral had the interrupt source 2:
42
43  gpio_prt0: gpio@40320100 {
44    interrupts = <2 1>;
45  };
46
47  In order to enable gpio_prt0 interrupt at Cortex-M0+ an interrupt parent
48  must be defined at gpio_prt0 node selecting the Interrupt Multiplex Channel.
49  This can be defined at <board>_m0.dts file:
50
51  &gpio_prt0 {
52    interrupt-parent = <&intmux_ch20>;
53  };
54
55  The translation of these two definitions is:
56         CH   REGS  INT NUM    CH   CH/REG
57  intmux[20 mod 8] |= 0x02 << (20 mod 4);
58
59  These results in Cortex-M0+ NVIC line 20 handling PSoC-6 interrupt source 2.
60  The interrupt can be enabled/disable at NVIC at line 20 as usual.
61
62  Notes:
63  1) Multiple definitions will generate multiple interrutps
64  2) The interrupt sources are shared between Cortex-M0+/M4. These means, can
65     trigger action in parallel in both processors.
66  3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels
67     at interrupt-parent properties.
68  4) Only the peripherals used by Cortex-M0+ should be configured.
69
70compatible: "cypress,psoc6-intmux"
71
72include: base.yaml
73
74properties:
75  reg:
76    required: true
77