1/*
2 * Copyright (c) 2020 Teslabs Engineering S.L.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/h7/stm32h7.dtsi>
8#include <zephyr/dt-bindings/display/panel.h>
9
10/ {
11	soc {
12		compatible = "st,stm32h750", "st,stm32h7", "simple-bus";
13
14		flash-controller@52002000 {
15			flash0: flash@8000000 {
16				compatible = "st,stm32-nv-flash", "soc-nv-flash";
17				write-block-size = <32>;
18				erase-block-size = <DT_SIZE_K(128)>;
19				/* maximum erase time for a 128K sector */
20				max-erase-time = <4000>;
21			};
22		};
23
24		dmamux1: dmamux@40020800 {
25			dma-requests= <107>;
26		};
27
28		dmamux2: dmamux@58025800 {
29			dma-requests= <107>;
30		};
31
32		usbotg_fs: usb@40080000 {
33			compatible = "st,stm32-otgfs";
34			reg = <0x40080000 0x40000>;
35			interrupts = <98 0>, <99 0>, <100 0>, <101 0>;
36			interrupt-names = "ep1_out", "ep1_in", "wkup", "otgfs";
37			num-bidir-endpoints = <9>;
38			ram-size = <DT_SIZE_K(4)>;
39			maximum-speed = "full-speed";
40			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
41				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
42			phys = <&otghs_fs_phy>;
43			status = "disabled";
44		};
45
46		ltdc: display-controller@50001000 {
47			compatible = "st,stm32-ltdc";
48			reg = <0x50001000 0x200>;
49			interrupts = <88 0>, <89 0>;
50			interrupt-names = "ltdc", "ltdc_er";
51			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
52			status = "disabled";
53		};
54
55		rtc@58004000 {
56			bbram: backup_regs {
57				compatible = "st,stm32-bbram";
58				st,backup-regs = <32>;
59				status = "disabled";
60			};
61		};
62	};
63
64	/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
65	sram0: memory@24000000 {
66		reg = <0x24000000 DT_SIZE_K(512)>;
67		compatible = "mmio-sram";
68	};
69
70	/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
71	sram1: memory@30000000 {
72		reg = <0x30000000 DT_SIZE_K(128)>;
73		compatible = "zephyr,memory-region", "mmio-sram";
74		zephyr,memory-region = "SRAM1";
75	};
76
77	/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
78	sram2: memory@30020000 {
79		compatible = "zephyr,memory-region", "mmio-sram";
80		reg = <0x30020000 DT_SIZE_K(128)>;
81		zephyr,memory-region = "SRAM2";
82	};
83
84	/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
85	sram3: memory@30040000 {
86		compatible = "zephyr,memory-region", "mmio-sram";
87		reg = <0x30040000 DT_SIZE_K(32)>;
88		zephyr,memory-region = "SRAM3";
89	};
90
91	/* System data RAM accessible over AHB bus: SRAM4 in D3 domain  */
92	sram4: memory@38000000 {
93		reg = <0x38000000 DT_SIZE_K(64)>;
94		compatible = "zephyr,memory-region", "mmio-sram";
95		zephyr,memory-region = "SRAM4";
96	};
97
98	dtcm: memory@20000000 {
99		compatible = "zephyr,memory-region", "arm,dtcm";
100		reg = <0x20000000 DT_SIZE_K(128)>;
101		zephyr,memory-region = "DTCM";
102	};
103
104	otghs_fs_phy: otghs_fs_phy {
105		compatible = "usb-nop-xceiv";
106		#phy-cells = <0>;
107	};
108
109	vref: vref {
110		io-channels = <&adc3 19>;
111	};
112
113	vbat: vbat {
114		io-channels = <&adc3 17>;
115	};
116};
117