1/*
2 * Copyright (c) 2021, ATL Electronics
3 * Copyright (c) 2021, Teslabs Engineering S.L.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <freq.h>
9#include <arm/armv7-m.dtsi>
10#include <zephyr/dt-bindings/adc/adc.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13#include <zephyr/dt-bindings/clock/gd32f403-clocks.h>
14#include <zephyr/dt-bindings/reset/gd32f403.h>
15
16/ {
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			compatible = "arm,cortex-m4f";
23			clock-frequency = <DT_FREQ_M(168)>;
24			reg = <0>;
25			#address-cells = <1>;
26			#size-cells = <1>;
27
28			mpu: mpu@e000ed90 {
29				compatible = "arm,armv7m-mpu";
30				reg = <0xe000ed90 0x40>;
31				arm,num-mpu-regions = <8>;
32			};
33		};
34	};
35
36	soc {
37		sram0: memory@20000000 {
38			compatible = "mmio-sram";
39		};
40
41		rcu: reset-clock-controller@40021000 {
42			compatible = "gd,gd32-rcu";
43			reg = <0x40021000 0x400>;
44			status = "okay";
45
46			cctl: clock-controller {
47				compatible = "gd,gd32-cctl";
48				#clock-cells = <1>;
49				status = "okay";
50			};
51
52			rctl: reset-controller {
53				compatible = "gd,gd32-rctl";
54				#reset-cells = <1>;
55				status = "okay";
56			};
57		};
58
59		fmc: flash-controller@40022000 {
60			compatible = "gd,gd32-flash-controller";
61			reg = <0x40022000 0x400>;
62			#address-cells = <1>;
63			#size-cells = <1>;
64
65			flash0: flash@8000000 {
66				compatible = "gd,gd32-nv-flash-v2", "soc-nv-flash";
67				write-block-size = <2>;
68				max-erase-time-ms = <300>;
69				bank0-page-size = <DT_SIZE_K(2)>;
70				bank1-page-size = <DT_SIZE_K(4)>;
71			};
72		};
73
74		usart0: usart@40013800 {
75			compatible = "gd,gd32-usart";
76			reg = <0x40013800 0x400>;
77			interrupts = <37 0>;
78			clocks = <&cctl GD32_CLOCK_USART0>;
79			resets = <&rctl GD32_RESET_USART0>;
80			status = "disabled";
81		};
82
83		usart1: usart@40004400 {
84			compatible = "gd,gd32-usart";
85			reg = <0x40004400 0x400>;
86			interrupts = <38 0>;
87			clocks = <&cctl GD32_CLOCK_USART1>;
88			resets = <&rctl GD32_RESET_USART1>;
89			status = "disabled";
90		};
91
92		usart2: usart@40004800 {
93			compatible = "gd,gd32-usart";
94			reg = <0x40004800 0x400>;
95			interrupts = <39 0>;
96			clocks = <&cctl GD32_CLOCK_USART2>;
97			resets = <&rctl GD32_RESET_USART2>;
98			status = "disabled";
99		};
100
101		uart3: usart@40004c00 {
102			compatible = "gd,gd32-usart";
103			reg = <0x40004c00 0x400>;
104			interrupts = <52 0>;
105			clocks = <&cctl GD32_CLOCK_UART3>;
106			resets = <&rctl GD32_RESET_UART3>;
107			status = "disabled";
108		};
109
110		uart4: usart@40005000 {
111			compatible = "gd,gd32-usart";
112			reg = <0x40005000 0x400>;
113			interrupts = <53 0>;
114			clocks = <&cctl GD32_CLOCK_UART4>;
115			resets = <&rctl GD32_RESET_UART4>;
116			status = "disabled";
117		};
118
119		spi0: spi@40013000 {
120			compatible = "gd,gd32-spi";
121			reg = <0x40013000 0x400>;
122			interrupts = <35 0>;
123			clocks = <&cctl GD32_CLOCK_SPI0>;
124			resets = <&rctl GD32_RESET_SPI0>;
125			status = "disabled";
126			#address-cells = <1>;
127			#size-cells = <0>;
128		};
129
130		spi1: spi@40003800 {
131			compatible = "gd,gd32-spi";
132			reg = <0x40003800 0x400>;
133			interrupts = <36 0>;
134			clocks = <&cctl GD32_CLOCK_SPI1>;
135			resets = <&rctl GD32_RESET_SPI1>;
136			status = "disabled";
137			#address-cells = <1>;
138			#size-cells = <0>;
139		};
140
141		spi2: spi@40003c00 {
142			compatible = "gd,gd32-spi";
143			reg = <0x40003c00 0x400>;
144			interrupts = <51 0>;
145			clocks = <&cctl GD32_CLOCK_SPI2>;
146			resets = <&rctl GD32_RESET_SPI2>;
147			status = "disabled";
148			#address-cells = <1>;
149			#size-cells = <0>;
150		};
151
152		adc0: adc@40012400 {
153			compatible = "gd,gd32-adc";
154			reg = <0x40012400 0x400>;
155			interrupts = <18 0>;
156			clocks = <&cctl GD32_CLOCK_ADC0>;
157			resets = <&rctl GD32_RESET_ADC0>;
158			channels = <16>;
159			status = "disabled";
160			#io-channel-cells = <1>;
161		};
162
163		adc1: adc@40012800 {
164			compatible = "gd,gd32-adc";
165			reg = <0x40012800 0x400>;
166			interrupts = <18 0>;
167			clocks = <&cctl GD32_CLOCK_ADC1>;
168			resets = <&rctl GD32_RESET_ADC1>;
169			channels = <16>;
170			status = "disabled";
171			#io-channel-cells = <1>;
172		};
173
174		adc2: adc@40013c00 {
175			compatible = "gd,gd32-adc";
176			reg = <0x40013c00 0x400>;
177			interrupts = <47 0>;
178			clocks = <&cctl GD32_CLOCK_ADC2>;
179			resets = <&rctl GD32_RESET_ADC2>;
180			channels = <16>;
181			status = "disabled";
182			#io-channel-cells = <1>;
183		};
184
185		exti: interrupt-controller@40010400 {
186			compatible = "gd,gd32-exti";
187			interrupt-controller;
188			#interrupt-cells = <1>;
189			reg = <0x40010400 0x400>;
190			num-lines = <19>;
191			interrupts = <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <23 0>,
192				     <40 0>;
193			interrupt-names = "line0", "line1", "line2",
194					  "line3", "line4", "line5-9",
195					  "line10-15";
196			status = "okay";
197		};
198
199		afio: afio@40010000 {
200			compatible = "gd,gd32-afio";
201			reg = <0x40010000 0x400>;
202			clocks = <&cctl GD32_CLOCK_AFIO>;
203			status = "okay";
204		};
205
206		fwdgt: watchdog@40003000 {
207			compatible = "gd,gd32-fwdgt";
208			reg = <0x40003000 0x400>;
209			status = "disabled";
210		};
211
212		wwdgt: watchdog@40002c00 {
213			compatible = "gd,gd32-wwdgt";
214			reg = <0x40002C00 0x400>;
215			clocks = <&cctl GD32_CLOCK_WWDGT>;
216			resets = <&rctl GD32_RESET_WWDGT>;
217			interrupts = <0 0>;
218			status = "disabled";
219		};
220
221		pinctrl: pin-controller@40010800 {
222			compatible = "gd,gd32-pinctrl-afio";
223			reg = <0x40010800 0x1c00>;
224			#address-cells = <1>;
225			#size-cells = <1>;
226			status = "okay";
227
228			gpioa: gpio@40010800 {
229				compatible = "gd,gd32-gpio";
230				gpio-controller;
231				#gpio-cells = <2>;
232				reg = <0x40010800 0x400>;
233				clocks = <&cctl GD32_CLOCK_GPIOA>;
234				resets = <&rctl GD32_RESET_GPIOA>;
235				status = "disabled";
236			};
237
238			gpiob: gpio@40010c00 {
239				compatible = "gd,gd32-gpio";
240				gpio-controller;
241				#gpio-cells = <2>;
242				reg = <0x40010c00 0x400>;
243				clocks = <&cctl GD32_CLOCK_GPIOB>;
244				resets = <&rctl GD32_RESET_GPIOB>;
245				status = "disabled";
246			};
247
248			gpioc: gpio@40011000 {
249				compatible = "gd,gd32-gpio";
250				gpio-controller;
251				#gpio-cells = <2>;
252				reg = <0x40011000 0x400>;
253				clocks = <&cctl GD32_CLOCK_GPIOC>;
254				resets = <&rctl GD32_RESET_GPIOC>;
255				status = "disabled";
256			};
257
258			gpiod: gpio@40011400 {
259				compatible = "gd,gd32-gpio";
260				gpio-controller;
261				#gpio-cells = <2>;
262				reg = <0x40011400 0x400>;
263				clocks = <&cctl GD32_CLOCK_GPIOD>;
264				resets = <&rctl GD32_RESET_GPIOD>;
265				status = "disabled";
266			};
267
268			gpioe: gpio@40011800 {
269				compatible = "gd,gd32-gpio";
270				gpio-controller;
271				#gpio-cells = <2>;
272				reg = <0x40011800 0x400>;
273				clocks = <&cctl GD32_CLOCK_GPIOE>;
274				resets = <&rctl GD32_RESET_GPIOE>;
275				status = "disabled";
276			};
277
278			gpiof: gpio@40011c00 {
279				compatible = "gd,gd32-gpio";
280				gpio-controller;
281				#gpio-cells = <2>;
282				reg = <0x40011c00 0x400>;
283				clocks = <&cctl GD32_CLOCK_GPIOF>;
284				resets = <&rctl GD32_RESET_GPIOF>;
285				status = "disabled";
286			};
287
288			gpiog: gpio@40012000 {
289				compatible = "gd,gd32-gpio";
290				gpio-controller;
291				#gpio-cells = <2>;
292				reg = <0x40012000 0x400>;
293				clocks = <&cctl GD32_CLOCK_GPIOG>;
294				resets = <&rctl GD32_RESET_GPIOG>;
295				status = "disabled";
296			};
297		};
298
299		timer0: timer@40012c00 {
300			compatible = "gd,gd32-timer";
301			reg = <0x40012c00 0x400>;
302			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
303			interrupt-names = "brk", "up", "trgcom", "cc";
304			clocks = <&cctl GD32_CLOCK_TIMER0>;
305			resets = <&rctl GD32_RESET_TIMER0>;
306			is-advanced;
307			channels = <4>;
308			status = "disabled";
309
310			pwm {
311				compatible = "gd,gd32-pwm";
312				status = "disabled";
313				#pwm-cells = <3>;
314			};
315		};
316
317		timer2: timer@40000400 {
318			compatible = "gd,gd32-timer";
319			reg = <0x40000400 0x400>;
320			interrupts = <29 0>;
321			interrupt-names = "global";
322			clocks = <&cctl GD32_CLOCK_TIMER2>;
323			resets = <&rctl GD32_RESET_TIMER2>;
324			channels = <4>;
325			status = "disabled";
326
327			pwm {
328				compatible = "gd,gd32-pwm";
329				status = "disabled";
330				#pwm-cells = <3>;
331			};
332		};
333
334		timer3: timer@40000800 {
335			compatible = "gd,gd32-timer";
336			reg = <0x40000800 0x400>;
337			interrupts = <30 0>;
338			interrupt-names = "global";
339			clocks = <&cctl GD32_CLOCK_TIMER3>;
340			resets = <&rctl GD32_RESET_TIMER3>;
341			channels = <4>;
342			status = "disabled";
343
344			pwm {
345				compatible = "gd,gd32-pwm";
346				status = "disabled";
347				#pwm-cells = <3>;
348			};
349		};
350
351		timer5: timer@40001000 {
352			compatible = "gd,gd32-timer";
353			reg = <0x40001000 0x400>;
354			interrupts = <54 0>;
355			interrupt-names = "global";
356			clocks = <&cctl GD32_CLOCK_TIMER5>;
357			resets = <&rctl GD32_RESET_TIMER5>;
358			channels = <0>;
359			status = "disabled";
360		};
361
362		timer6: timer@40001400 {
363			compatible = "gd,gd32-timer";
364			reg = <0x40001400 0x400>;
365			interrupts = <55 0>;
366			interrupt-names = "global";
367			clocks = <&cctl GD32_CLOCK_TIMER6>;
368			resets = <&rctl GD32_RESET_TIMER6>;
369			channels = <0>;
370			status = "disabled";
371		};
372
373		timer7: timer@40013400 {
374			compatible = "gd,gd32-timer";
375			reg = <0x40013400 0x400>;
376			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
377			interrupt-names = "brk", "up", "trgcom", "cc";
378			clocks = <&cctl GD32_CLOCK_TIMER7>;
379			resets = <&rctl GD32_RESET_TIMER7>;
380			is-advanced;
381			channels = <4>;
382			status = "disabled";
383
384			pwm {
385				compatible = "gd,gd32-pwm";
386				status = "disabled";
387				#pwm-cells = <3>;
388			};
389		};
390
391		timer8: timer@40014c00 {
392			compatible = "gd,gd32-timer";
393			reg = <0x40014c00 0x400>;
394			interrupts = <24 0>;
395			interrupt-names = "global";
396			clocks = <&cctl GD32_CLOCK_TIMER8>;
397			resets = <&rctl GD32_RESET_TIMER8>;
398			channels = <2>;
399			status = "disabled";
400
401			pwm {
402				compatible = "gd,gd32-pwm";
403				status = "disabled";
404				#pwm-cells = <3>;
405			};
406		};
407
408		timer9: timer@40015000 {
409			compatible = "gd,gd32-timer";
410			reg = <0x40015000 0x400>;
411			interrupts = <25 0>;
412			interrupt-names = "global";
413			clocks = <&cctl GD32_CLOCK_TIMER9>;
414			resets = <&rctl GD32_RESET_TIMER9>;
415			channels = <1>;
416			status = "disabled";
417
418			pwm {
419				compatible = "gd,gd32-pwm";
420				status = "disabled";
421				#pwm-cells = <3>;
422			};
423		};
424
425		timer10: timer@40015400 {
426			compatible = "gd,gd32-timer";
427			reg = <0x40015400 0x400>;
428			interrupts = <26 0>;
429			interrupt-names = "global";
430			clocks = <&cctl GD32_CLOCK_TIMER10>;
431			resets = <&rctl GD32_RESET_TIMER10>;
432			channels = <1>;
433			status = "disabled";
434
435			pwm {
436				compatible = "gd,gd32-pwm";
437				status = "disabled";
438				#pwm-cells = <3>;
439			};
440		};
441
442		timer11: timer@40001800 {
443			compatible = "gd,gd32-timer";
444			reg = <0x40001800 0x400>;
445			interrupts = <43 0>;
446			interrupt-names = "global";
447			clocks = <&cctl GD32_CLOCK_TIMER11>;
448			resets = <&rctl GD32_RESET_TIMER11>;
449			channels = <2>;
450			status = "disabled";
451
452			pwm {
453				compatible = "gd,gd32-pwm";
454				status = "disabled";
455				#pwm-cells = <3>;
456			};
457		};
458
459		timer12: timer@40001c00 {
460			compatible = "gd,gd32-timer";
461			reg = <0x40001c00 0x400>;
462			interrupts = <44 0>;
463			interrupt-names = "global";
464			clocks = <&cctl GD32_CLOCK_TIMER12>;
465			resets = <&rctl GD32_RESET_TIMER12>;
466			channels = <1>;
467			status = "disabled";
468
469			pwm {
470				compatible = "gd,gd32-pwm";
471				status = "disabled";
472				#pwm-cells = <3>;
473			};
474		};
475
476		timer13: timer@40002000 {
477			compatible = "gd,gd32-timer";
478			reg = <0x40002000 0x400>;
479			interrupts = <45 0>;
480			interrupt-names = "global";
481			clocks = <&cctl GD32_CLOCK_TIMER13>;
482			resets = <&rctl GD32_RESET_TIMER13>;
483			channels = <1>;
484			status = "disabled";
485
486			pwm {
487				compatible = "gd,gd32-pwm";
488				status = "disabled";
489				#pwm-cells = <3>;
490			};
491		};
492
493		dma0: dma@40020000 {
494			compatible = "gd,gd32-dma";
495			reg = <0x40020000 0x400>;
496			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
497				     <15 0>, <16 0>, <17 0>;
498			clocks = <&cctl GD32_CLOCK_DMA0>;
499			dma-channels = <7>;
500			gd,mem2mem;
501			#dma-cells = <2>;
502			status = "disabled";
503		};
504
505		dma1: dma@40020400 {
506			compatible = "gd,gd32-dma";
507			reg = <0x40020400 0x400>;
508			interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
509				     <60 0>;
510			clocks = <&cctl GD32_CLOCK_DMA1>;
511			dma-channels = <5>;
512			gd,mem2mem;
513			#dma-cells = <2>;
514			status = "disabled";
515		};
516	};
517};
518
519&nvic {
520	arm,num-irq-priority-bits = <4>;
521};
522