1/*
2 * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <zephyr/dt-bindings/adc/adc.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/timer/nuclei-systimer.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13#include <zephyr/dt-bindings/clock/gd32vf103-clocks.h>
14#include <zephyr/dt-bindings/reset/gd32vf103.h>
15
16/ {
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu: cpu@0 {
25			clock-frequency = <DT_FREQ_M(108)>;
26			mcause-exception-mask = <0x7ff>;
27			compatible = "nuclei,bumblebee";
28			riscv,isa = "rv32imac_zicsr_zifencei";
29			reg = <0>;
30		};
31	};
32
33	sram0: memory@20000000 {
34		compatible = "mmio-sram";
35	};
36
37	soc {
38		#address-cells = <1>;
39		#size-cells = <1>;
40		compatible = "simple-bus";
41		interrupt-parent = <&eclic>;
42		ranges;
43
44		systimer: timer@d1000000 {
45			compatible = "nuclei,systimer";
46			reg = <0xd1000000 0x10000>;
47			interrupts = <3 0>, <7 0>;
48			clk-divider = <NUCLEI_SYSTIMER_DIVIDER_4>;
49		};
50
51		eclic: interrupt-controller@d2000000 {
52			compatible = "nuclei,eclic";
53			#address-cells = <0>;
54			#interrupt-cells = <2>;
55			interrupt-controller;
56			reg =  <0xd2000000 0x0001
57				0xd2000004 0x0004
58				0xd200000b 0x0001
59				0xd2001000 0x1000>;
60		};
61
62		rcu: reset-clock-controller@40021000 {
63			compatible = "gd,gd32-rcu";
64			reg = <0x40021000 0x400>;
65			status = "okay";
66
67			cctl: clock-controller {
68				compatible = "gd,gd32-cctl";
69				#clock-cells = <1>;
70				status = "okay";
71			};
72
73			rctl: reset-controller {
74				compatible = "gd,gd32-rctl";
75				#reset-cells = <1>;
76				status = "okay";
77			};
78		};
79
80		fmc: flash-controller@40022000 {
81			compatible = "gd,gd32-flash-controller";
82			reg = <0x40022000 0x400>;
83			#address-cells = <1>;
84			#size-cells = <1>;
85
86			flash0: flash@8000000 {
87				compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
88				write-block-size = <2>;
89				max-erase-time-ms = <300>;
90				page-size = <DT_SIZE_K(1)>;
91			};
92		};
93
94		usart0: serial@40013800 {
95			compatible = "gd,gd32-usart";
96			reg = <0x40013800 0x400>;
97			interrupts = <56 0>;
98			clocks = <&cctl GD32_CLOCK_USART0>;
99			resets = <&rctl GD32_RESET_USART0>;
100			status = "disabled";
101		};
102
103		usart1: serial@40004400 {
104			compatible = "gd,gd32-usart";
105			reg = <0x40004400 0x400>;
106			interrupts = <57 0>;
107			clocks = <&cctl GD32_CLOCK_USART1>;
108			resets = <&rctl GD32_RESET_USART1>;
109			status = "disabled";
110		};
111
112		usart2: serial@40004800 {
113			compatible = "gd,gd32-usart";
114			reg = <0x40004800 0x400>;
115			interrupts = <58 0>;
116			clocks = <&cctl GD32_CLOCK_USART2>;
117			resets = <&rctl GD32_RESET_USART2>;
118			status = "disabled";
119		};
120
121		uart3: serial@40004c00 {
122			compatible = "gd,gd32-usart";
123			reg = <0x40004c00 0x400>;
124			interrupts = <71 0>;
125			clocks = <&cctl GD32_CLOCK_UART3>;
126			resets = <&rctl GD32_RESET_UART3>;
127			status = "disabled";
128		};
129
130		uart4: serial@40005000 {
131			compatible = "gd,gd32-usart";
132			reg = <0x40005000 0x400>;
133			interrupts = <72 0>;
134			clocks = <&cctl GD32_CLOCK_UART4>;
135			resets = <&rctl GD32_RESET_UART4>;
136			status = "disabled";
137		};
138
139		adc0: adc@40012400 {
140			compatible = "gd,gd32-adc";
141			reg = <0x40012400 0x400>;
142			interrupts = <37 0>;
143			clocks = <&cctl GD32_CLOCK_ADC0>;
144			resets = <&rctl GD32_RESET_ADC0>;
145			channels = <16>;
146			status = "disabled";
147			#io-channel-cells = <1>;
148		};
149
150		adc1: adc@40012800 {
151			compatible = "gd,gd32-adc";
152			reg = <0x40012800 0x400>;
153			interrupts = <37 0>;
154			clocks = <&cctl GD32_CLOCK_ADC1>;
155			resets = <&rctl GD32_RESET_ADC1>;
156			channels = <16>;
157			status = "disabled";
158			#io-channel-cells = <1>;
159		};
160
161		dac: dac@40007400 {
162			compatible = "gd,gd32-dac";
163			reg = <0x40007400 0x400>;
164			clocks = <&cctl GD32_CLOCK_DAC>;
165			resets = <&rctl GD32_RESET_DAC>;
166			num-channels = <2>;
167			status = "disabled";
168			#io-channel-cells = <1>;
169		};
170
171		i2c0: i2c@40005400 {
172			compatible = "gd,gd32-i2c";
173			reg = <0x40005400 0x400>;
174			#address-cells = <1>;
175			#size-cells = <0>;
176			clock-frequency = <I2C_BITRATE_STANDARD>;
177			interrupts = <50 0>, <51 0>;
178			interrupt-names = "event", "error";
179			clocks = <&cctl GD32_CLOCK_I2C0>;
180			resets = <&rctl GD32_RESET_I2C0>;
181			status = "disabled";
182		};
183
184		spi0: spi@40013000 {
185			compatible = "gd,gd32-spi";
186			reg = <0x40013000 0x400>;
187			interrupts = <54 0>;
188			clocks = <&cctl GD32_CLOCK_SPI0>;
189			resets = <&rctl GD32_RESET_SPI0>;
190			status = "disabled";
191			#address-cells = <1>;
192			#size-cells = <0>;
193		};
194
195		spi1: spi@40003800 {
196			compatible = "gd,gd32-spi";
197			reg = <0x40003800 0x400>;
198			interrupts = <55 0>;
199			clocks = <&cctl GD32_CLOCK_SPI1>;
200			resets = <&rctl GD32_RESET_SPI1>;
201			status = "disabled";
202			#address-cells = <1>;
203			#size-cells = <0>;
204		};
205
206		afio: afio@40010000 {
207			compatible = "gd,gd32-afio";
208			reg = <0x40010000 0x400>;
209			clocks = <&cctl GD32_CLOCK_AFIO>;
210			status = "okay";
211		};
212
213		exti: interrupt-controller@40010400 {
214			compatible = "gd,gd32-exti";
215			#address-cells = <0>;
216			interrupt-controller;
217			#interrupt-cells = <1>;
218			reg = <0x40010400 0x400>;
219			num-lines = <19>;
220			interrupts = <25 0>, <26 0>, <27 0>, <28 0>, <29 0>,
221				     <42 0>, <59 0>;
222			interrupt-names = "line0", "line1", "line2", "line3",
223					  "line4", "line5-9", "line10-15";
224			status = "okay";
225		};
226
227		fwdgt: watchdog@40003000 {
228			compatible = "gd,gd32-fwdgt";
229			reg = <0x40003000 0x400>;
230			status = "disabled";
231		};
232
233		wwdgt: watchdog@40002c00 {
234			compatible = "gd,gd32-wwdgt";
235			reg = <0x40002C00 0x400>;
236			clocks = <&cctl GD32_CLOCK_WWDGT>;
237			resets = <&rctl GD32_RESET_WWDGT>;
238			interrupts = <0 0>;
239			status = "disabled";
240		};
241
242		pinctrl: pin-controller@40010800 {
243			compatible = "gd,gd32-pinctrl-afio";
244			reg = <0x40010800 0x1c00>;
245			#address-cells = <1>;
246			#size-cells = <1>;
247			status = "okay";
248
249			gpioa: gpio@40010800 {
250				compatible = "gd,gd32-gpio";
251				reg = <0x40010800 0x400>;
252				gpio-controller;
253				#gpio-cells = <2>;
254				clocks = <&cctl GD32_CLOCK_GPIOA>;
255				resets = <&rctl GD32_RESET_GPIOA>;
256				status = "disabled";
257			};
258
259			gpiob: gpio@40010c00 {
260				compatible = "gd,gd32-gpio";
261				reg = <0x40010c00 0x400>;
262				gpio-controller;
263				#gpio-cells = <2>;
264				clocks = <&cctl GD32_CLOCK_GPIOB>;
265				resets = <&rctl GD32_RESET_GPIOB>;
266				status = "disabled";
267			};
268
269			gpioc: gpio@40011000 {
270				compatible = "gd,gd32-gpio";
271				reg = <0x40011000 0x400>;
272				gpio-controller;
273				#gpio-cells = <2>;
274				clocks = <&cctl GD32_CLOCK_GPIOC>;
275				resets = <&rctl GD32_RESET_GPIOC>;
276				status = "disabled";
277			};
278
279			gpiod: gpio@40011400 {
280				compatible = "gd,gd32-gpio";
281				reg = <0x40011400 0x400>;
282				gpio-controller;
283				#gpio-cells = <2>;
284				clocks = <&cctl GD32_CLOCK_GPIOD>;
285				resets = <&rctl GD32_RESET_GPIOD>;
286				status = "disabled";
287			};
288
289			gpioe: gpio@40011800 {
290				compatible = "gd,gd32-gpio";
291				reg = <0x40011800 0x400>;
292				gpio-controller;
293				#gpio-cells = <2>;
294				clocks = <&cctl GD32_CLOCK_GPIOE>;
295				resets = <&rctl GD32_RESET_GPIOE>;
296				status = "disabled";
297			};
298		};
299
300		timer0: timer@40012c00 {
301			compatible = "gd,gd32-timer";
302			reg = <0x40012c00 0x400>;
303			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
304			interrupt-names = "brk", "up", "trgcom", "cc";
305			clocks = <&cctl GD32_CLOCK_TIMER0>;
306			resets = <&rctl GD32_RESET_TIMER0>;
307			is-advanced;
308			channels = <4>;
309			status = "disabled";
310
311			pwm {
312				compatible = "gd,gd32-pwm";
313				status = "disabled";
314				#pwm-cells = <3>;
315			};
316		};
317
318		timer1: timer@40000000 {
319			compatible = "gd,gd32-timer";
320			reg = <0x40000000 0x400>;
321			interrupts = <47 0>;
322			interrupt-names = "global";
323			clocks = <&cctl GD32_CLOCK_TIMER1>;
324			resets = <&rctl GD32_RESET_TIMER1>;
325			channels = <4>;
326			status = "disabled";
327
328			pwm {
329				compatible = "gd,gd32-pwm";
330				status = "disabled";
331				#pwm-cells = <3>;
332			};
333		};
334
335		timer2: timer@40000400 {
336			compatible = "gd,gd32-timer";
337			reg = <0x40000400 0x400>;
338			interrupts = <48 0>;
339			interrupt-names = "global";
340			clocks = <&cctl GD32_CLOCK_TIMER2>;
341			resets = <&rctl GD32_RESET_TIMER2>;
342			channels = <4>;
343			status = "disabled";
344
345			pwm {
346				compatible = "gd,gd32-pwm";
347				status = "disabled";
348				#pwm-cells = <3>;
349			};
350		};
351
352		timer3: timer@40000800 {
353			compatible = "gd,gd32-timer";
354			reg = <0x40000800 0x400>;
355			interrupts = <49 0>;
356			interrupt-names = "global";
357			clocks = <&cctl GD32_CLOCK_TIMER3>;
358			resets = <&rctl GD32_RESET_TIMER3>;
359			channels = <4>;
360			status = "disabled";
361
362			pwm {
363				compatible = "gd,gd32-pwm";
364				status = "disabled";
365				#pwm-cells = <3>;
366			};
367		};
368
369		timer4: timer@40000c00 {
370			compatible = "gd,gd32-timer";
371			reg = <0x40000c00 0x400>;
372			interrupts = <69 0>;
373			interrupt-names = "global";
374			clocks = <&cctl GD32_CLOCK_TIMER4>;
375			resets = <&rctl GD32_RESET_TIMER4>;
376			channels = <4>;
377			status = "disabled";
378
379			pwm {
380				compatible = "gd,gd32-pwm";
381				status = "disabled";
382				#pwm-cells = <3>;
383			};
384		};
385
386		timer5: timer@40001000 {
387			compatible = "gd,gd32-timer";
388			reg = <0x40001000 0x400>;
389			interrupts = <73 0>;
390			interrupt-names = "global";
391			clocks = <&cctl GD32_CLOCK_TIMER5>;
392			resets = <&rctl GD32_RESET_TIMER5>;
393			channels = <0>;
394			status = "disabled";
395		};
396
397		timer6: timer@40001400 {
398			compatible = "gd,gd32-timer";
399			reg = <0x40001400 0x400>;
400			interrupts = <74 0>;
401			interrupt-names = "global";
402			clocks = <&cctl GD32_CLOCK_TIMER6>;
403			resets = <&rctl GD32_RESET_TIMER6>;
404			channels = <0>;
405			status = "disabled";
406		};
407
408		dma0: dma@40020000 {
409			compatible = "gd,gd32-dma";
410			reg = <0x40020000 0x400>;
411			interrupts = <30 0>, <31 0>, <32 0>, <33 0>,
412				     <34 0>, <35 0>, <36 0>;
413			clocks = <&cctl GD32_CLOCK_DMA0>;
414			dma-channels = <7>;
415			gd,mem2mem;
416			#dma-cells = <2>;
417			status = "disabled";
418		};
419
420		dma1: dma@40020400 {
421			compatible = "gd,gd32-dma";
422			reg = <0x40020400 0x400>;
423			interrupts = <75 0>, <76 0>, <77 0>, <78 0>,
424				     <79 0>;
425			clocks = <&cctl GD32_CLOCK_DMA1>;
426			dma-channels = <5>;
427			gd,mem2mem;
428			#dma-cells = <2>;
429			status = "disabled";
430		};
431	};
432};
433