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Searched +full:mram +full:- +full:cfg (Results 1 – 19 of 19) sorted by relevance

/Zephyr-Core-3.5.0/drivers/can/
Dcan_sam0.c6 * SPDX-License-Identifier: Apache-2.0
23 mem_addr_t mram; member
34 const struct can_mcan_config *mcan_config = dev->config; in can_sam0_read_reg()
35 const struct can_sam0_config *sam_config = mcan_config->custom; in can_sam0_read_reg()
37 return can_mcan_sys_read_reg(sam_config->base, reg, val); in can_sam0_read_reg()
42 const struct can_mcan_config *mcan_config = dev->config; in can_sam0_write_reg()
43 const struct can_sam0_config *sam_config = mcan_config->custom; in can_sam0_write_reg()
59 return can_mcan_sys_write_reg(sam_config->base, reg, val); in can_sam0_write_reg()
64 const struct can_mcan_config *mcan_config = dev->config; in can_sam0_read_mram()
65 const struct can_sam0_config *sam_config = mcan_config->custom; in can_sam0_read_mram()
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/Zephyr-Core-3.5.0/dts/arm/atmel/
Dsamc21.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 sercom-4 = &sercom4;
12 sercom-5 = &sercom5;
17 compatible = "atmel,sam0-adc";
21 interrupt-names = "resrdy";
23 clock-names = "GCLK", "MCLK";
26 #io-channel-cells = <1>;
30 compatible = "atmel,sam0-sercom";
34 clock-names = "GCLK", "MCLK";
39 compatible = "atmel,sam0-sercom";
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Dsame70.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
21 zephyr,flash-controller = &eefc;
29 #address-cells = <1>;
30 #size-cells = <0>;
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/Zephyr-Core-3.5.0/dts/bindings/can/
Dbosch,m_can-base.yaml1 description: Bosch M_CAN CAN-FD controller base
3 include: [can-fd-controller.yaml]
6 bosch,mram-cfg:
12 <offset std-filter-elements ext-filter-elements rx-fifo0-elements rx-fifo1-elements
13 rx-buffer-elements tx-event-fifo-elements tx-buffer-elements>
16 from. This is normally set to 0x0 when using a non-shared message RAM. The remaining cells
20 11-bit Filter 0-128 elements / 0-128 words
21 29-bit Filter 0-64 elements / 0-128 words
22 Rx FIFO 0 0-64 elements / 0-1152 words
23 Rx FIFO 1 0-64 elements / 0-1152 words
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Dti,tcan4x5x.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Texas Instruments TCAN4x5x SPI CAN-FD controller.
12 spi-max-frequency = <18000000>;
13 clock-frequency = <40000000>;
14 device-state-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
15 device-wake-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
16 reset-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
17 int-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
18 bosch,mram-cfg = <0x0 15 15 5 5 0 10 10>;
19 sample-point = <875>;
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/Zephyr-Core-3.5.0/boards/shields/tcan4550evm/
Dtcan4550evm.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
17 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
22 /* reduced spi-max-frequency to accommodate flywire connections */
23 spi-max-frequency = <2000000>;
25 clock-frequency = <40000000>;
26 device-state-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 */
27 device-wake-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
28 reset-gpios = <&arduino_header 14 GPIO_ACTIVE_HIGH>; /* D8 */
29 int-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */
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/Zephyr-Core-3.5.0/dts/arm/st/g4/
Dstm32g491.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g491", "st,stm32g4", "simple-bus";
14 compatible = "st,stm32-fdcan";
16 reg-names = "m_can", "message_ram";
18 interrupt-names = "LINE_0", "LINE_1";
20 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
21 sample-point = <875>;
22 sample-point-data = <875>;
27 compatible = "st,stm32-timers";
32 interrupt-names = "brk", "up", "trgcom", "cc";
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Dstm32g473.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g473", "st,stm32g4", "simple-bus";
14 compatible = "st,stm32-timers";
19 interrupt-names = "global";
24 compatible = "st,stm32-pwm";
26 #pwm-cells = <3>;
31 compatible = "st,stm32-adc";
36 #io-channel-cells = <1>;
41 sampling-times = <3 7 13 25 48 93 248 641>;
42 st,adc-sequencer = <FULLY_CONFIGURABLE>;
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Dstm32g4.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32g4_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/adc/adc.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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/Zephyr-Core-3.5.0/dts/arm/st/g0/
Dstm32g0b1.dtsi3 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
5 * SPDX-License-Identifier: Apache-2.0
12 compatible = "st,stm32g0b1", "st,stm32g0", "simple-bus";
15 clk_hsi48: clk-hsi48 {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-frequency = <DT_FREQ_M(48)>;
23 pinctrl: pin-controller@50000000 {
25 compatible = "st,stm32-gpio";
26 gpio-controller;
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/Zephyr-Core-3.5.0/dts/arm/st/h7/
Dstm32h723.dtsi5 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/display/panel.h>
11 #include <zephyr/dt-bindings/flash_controller/ospi.h>
15 compatible = "st,stm32h723", "st,stm32h7", "simple-bus";
17 flash-controller@52002000 {
19 compatible = "st,stm32-nv-flash", "soc-nv-flash";
20 write-block-size = <32>;
21 erase-block-size = <DT_SIZE_K(128)>;
23 max-erase-time = <4000>;
28 compatible = "st,stm32-uart";
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Dstm32h7.dtsi6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32h7_adc.h>
17 #include <zephyr/dt-bindings/reset/stm32h7_reset.h>
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/Zephyr-Core-3.5.0/dts/arm/nxp/
Dnxp_lpc55S1x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
22 #address-cells = <1>;
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Dnxp_lpc55S0x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-m33f";
20 #address-cells = <1>;
21 #size-cells = <1>;
24 compatible = "arm,armv8m-mpu";
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Dnxp_lpc55S3x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-m33f";
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/Zephyr-Core-3.5.0/dts/arm/st/h5/
Dstm32h562.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/flash_controller/ospi.h>
14 #clock-cells = <0>;
15 compatible = "st,stm32u5-pll-clock";
21 compatible = "st,stm32h562", "st,stm32h5", "simple-bus";
23 pinctrl: pin-controller@42020000 {
25 compatible = "st,stm32-gpio";
26 gpio-controller;
27 #gpio-cells = <2>;
33 compatible = "st,stm32-gpio";
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Dstm32h5.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/stm32h5_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/reset/stm32h5_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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/Zephyr-Core-3.5.0/include/zephyr/drivers/can/
Dcan_mcan.h5 * SPDX-License-Identifier: Apache-2.0
399 * @name Indexes for the cells in the devicetree bosch,mram-cfg property
402 * These match the description of the cells in the bosch,m_can-base devicetree binding.
408 /** std-filter-elements cell index */
410 /** ext-filter-elements cell index */
412 /** rx-fifo0-elements cell index */
414 /** rx-fifo1-elements cell index */
416 /** rx-buffer-elements cell index */
418 /** tx-event-fifo-elements cell index */
420 /** tx-buffer-elements cell index */
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/Zephyr-Core-3.5.0/dts/arm/st/u5/
Dstm32u5.dtsi6 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv8-m.dtsi>
11 #include <zephyr/dt-bindings/adc/adc.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/stm32u5_clock.h>
14 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #include <zephyr/dt-bindings/i2c/i2c.h>
16 #include <zephyr/dt-bindings/flash_controller/ospi.h>
17 #include <zephyr/dt-bindings/reset/stm32u5_reset.h>
18 #include <zephyr/dt-bindings/dma/stm32_dma.h>
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