1/*
2 * Copyright (c) 2021 Guðni Már Gilbert
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/g4/stm32g491.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32g473", "st,stm32g4", "simple-bus";
12
13		timers5: timers@40000c00 {
14			compatible = "st,stm32-timers";
15			reg = <0x40000c00 0x400>;
16			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
17			resets = <&rctl STM32_RESET(APB1L, 3U)>;
18			interrupts = <50 0>;
19			interrupt-names = "global";
20			st,prescaler = <0>;
21			status = "disabled";
22
23			pwm {
24				compatible = "st,stm32-pwm";
25				status = "disabled";
26				#pwm-cells = <3>;
27			};
28		};
29
30		adc4: adc@50000500 {
31			compatible = "st,stm32-adc";
32			reg = <0x50000500 0x100>;
33			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>;
34			interrupts = <61 0>;
35			status = "disabled";
36			#io-channel-cells = <1>;
37			resolutions = <STM32_ADC_RES(12, 0x00)
38				       STM32_ADC_RES(10, 0x01)
39				       STM32_ADC_RES(8, 0x02)
40				       STM32_ADC_RES(6, 0x03)>;
41			sampling-times = <3 7 13 25 48 93 248 641>;
42			st,adc-sequencer = <FULLY_CONFIGURABLE>;
43		};
44
45		adc5: adc@50000600 {
46			compatible = "st,stm32-adc";
47			reg = <0x50000600 0x100>;
48			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>;
49			interrupts = <62 0>;
50			status = "disabled";
51			#io-channel-cells = <1>;
52			resolutions = <STM32_ADC_RES(12, 0x00)
53				       STM32_ADC_RES(10, 0x01)
54				       STM32_ADC_RES(8, 0x02)
55				       STM32_ADC_RES(6, 0x03)>;
56			sampling-times = <3 7 13 25 48 93 248 641>;
57			st,adc-sequencer = <FULLY_CONFIGURABLE>;
58		};
59
60		spi4: spi@40013c00 {
61			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
62			#address-cells = <1>;
63			#size-cells = <0>;
64			reg = <0x40013c00 0x400>;
65			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
66			interrupts = <84 5>;
67			status = "disabled";
68		};
69
70		dac2: dac@50000c00 {
71			compatible = "st,stm32-dac";
72			reg = <0x50000c00 0x400>;
73			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00020000>;
74			status = "disabled";
75			#io-channel-cells = <1>;
76		};
77
78		dac4: dac@50001400 {
79			compatible = "st,stm32-dac";
80			reg = <0x50001400 0x400>;
81			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00080000>;
82			status = "disabled";
83			#io-channel-cells = <1>;
84		};
85
86		i2c4: i2c@40008400 {
87			compatible = "st,stm32-i2c-v2";
88			clock-frequency = <I2C_BITRATE_STANDARD>;
89			#address-cells = <1>;
90			#size-cells = <0>;
91			reg = <0x40008400 0x400>;
92			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
93			interrupts = <82 0>, <83 0>;
94			interrupt-names = "event", "error";
95			status = "disabled";
96		};
97
98		fdcan3: can@40006c00 {
99			compatible = "st,stm32-fdcan";
100			reg = <0x40006c00 0x400>, <0x4000a400 0x9f0>;
101			reg-names = "m_can", "message_ram";
102			interrupts = <88 0>, <89 0>;
103			interrupt-names = "LINE_0", "LINE_1";
104			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
105			bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>;
106			sample-point = <875>;
107			sample-point-data = <875>;
108			status = "disabled";
109		};
110	};
111};
112