1/* 2 * Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com> 3 * Copyright (c) 2022 Georgij Cernysiov <geo.cgv@gmail.com> 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9#include <st/h7/stm32h7.dtsi> 10#include <zephyr/dt-bindings/display/panel.h> 11#include <zephyr/dt-bindings/flash_controller/ospi.h> 12 13/ { 14 soc { 15 compatible = "st,stm32h723", "st,stm32h7", "simple-bus"; 16 17 flash-controller@52002000 { 18 flash0: flash@8000000 { 19 compatible = "st,stm32-nv-flash", "soc-nv-flash"; 20 write-block-size = <32>; 21 erase-block-size = <DT_SIZE_K(128)>; 22 /* maximum erase time for a 128K sector */ 23 max-erase-time = <4000>; 24 }; 25 }; 26 27 uart9: serial@40011800 { 28 compatible = "st,stm32-uart"; 29 reg = <0x40011800 0x400>; 30 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>; 31 resets = <&rctl STM32_RESET(APB2, 6U)>; 32 interrupts = <155 0>; 33 status = "disabled"; 34 }; 35 36 usart10: serial@40011c00 { 37 compatible = "st,stm32-usart", "st,stm32-uart"; 38 reg = <0x40011c00 0x400>; 39 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>; 40 resets = <&rctl STM32_RESET(APB2, 7U)>; 41 interrupts = <156 0>; 42 status = "disabled"; 43 }; 44 45 /* 46 * ADC3 on STM32H723, 725, 730, 733 & 735 is a 12-bit resolution 47 * ADC, so we redefine the resolution for these devices. 48 */ 49 adc3: adc@58026000 { 50 resolutions = <STM32H72X_ADC3_RES(12, 0x00) 51 STM32H72X_ADC3_RES(10, 0x01) 52 STM32H72X_ADC3_RES(8, 0x02) 53 STM32H72X_ADC3_RES(6, 0x03)>; 54 sampling-times = <3 7 13 25 48 93 248 641>; 55 st,adc-sequencer = <FULLY_CONFIGURABLE>; 56 }; 57 58 dmamux1: dmamux@40020800 { 59 dma-requests= <129>; 60 }; 61 62 dmamux2: dmamux@58025800 { 63 dma-requests= <129>; 64 }; 65 66 rng: rng@48021800 { 67 health-test-magic = <0x17590abc>; 68 health-test-config = <0xaa74>; 69 }; 70 71 usbotg_hs: usb@40040000 { 72 compatible = "st,stm32-otghs"; 73 reg = <0x40040000 0x40000>; 74 interrupts = <77 0>, <74 0>, <75 0>; 75 interrupt-names = "otghs", "ep1_out", "ep1_in"; 76 num-bidir-endpoints = <9>; 77 ram-size = <DT_SIZE_K(4)>; 78 maximum-speed = "full-speed"; 79 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>, 80 <&rcc STM32_SRC_HSI48 USB_SEL(3)>; 81 phys = <&otghs_fs_phy>; 82 status = "disabled"; 83 }; 84 85 ltdc: display-controller@50001000 { 86 compatible = "st,stm32-ltdc"; 87 reg = <0x50001000 0x200>; 88 interrupts = <88 0>, <89 0>; 89 interrupt-names = "ltdc", "ltdc_er"; 90 clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>; 91 status = "disabled"; 92 }; 93 94 octospi1: octospi@52005000 { 95 compatible = "st,stm32-ospi"; 96 reg = <0x52005000 0x1000>; 97 interrupts = <92 0>; 98 clock-names = "ospix", "ospi-ker"; 99 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00004000>, 100 <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; 101 #address-cells = <1>; 102 #size-cells = <0>; 103 status = "disabled"; 104 }; 105 106 octospi2: octospi@5200a000 { 107 compatible = "st,stm32-ospi"; 108 reg = <0x5200a000 0x1000>; 109 interrupts = <150 0>; 110 clock-names = "ospix", "ospi-ker"; 111 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x000080000>, 112 <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 status = "disabled"; 116 }; 117 118 fdcan3: can@4000d400 { 119 compatible = "st,stm32h7-fdcan"; 120 reg = <0x4000d400 0x400>, <0x4000ac00 0x9f0>; 121 reg-names = "m_can", "message_ram"; 122 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>; 123 interrupts = <159 0>, <160 0>, <63 0>; 124 interrupt-names = "LINE_0", "LINE_1", "CALIB"; 125 bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>; 126 sample-point = <875>; 127 sample-point-data = <875>; 128 status = "disabled"; 129 }; 130 131 rtc@58004000 { 132 bbram: backup_regs { 133 compatible = "st,stm32-bbram"; 134 st,backup-regs = <32>; 135 status = "disabled"; 136 }; 137 }; 138 }; 139 140 /* D1 domain, AXI SRAM (128KB with shared ITCM 192KB as `TCM_AXI_SHARED` is `000`) */ 141 sram0: memory@24000000 { 142 reg = <0x24000000 DT_SIZE_K(320)>; 143 compatible = "mmio-sram"; 144 }; 145 146 /* D2 domain, AHB SRAM */ 147 sram1: memory@30000000 { 148 reg = <0x30000000 DT_SIZE_K(16)>; 149 compatible = "zephyr,memory-region", "mmio-sram"; 150 zephyr,memory-region = "SRAM1"; 151 }; 152 153 /* D2 domain, AHB SRAM */ 154 sram2: memory@30004000 { 155 reg = <0x30004000 DT_SIZE_K(16)>; 156 compatible = "zephyr,memory-region", "mmio-sram"; 157 zephyr,memory-region = "SRAM2"; 158 }; 159 160 /* D3 domain, AHB SRAM */ 161 sram4: memory@38000000 { 162 reg = <0x38000000 DT_SIZE_K(16)>; 163 compatible = "zephyr,memory-region", "mmio-sram"; 164 zephyr,memory-region = "SRAM4"; 165 }; 166 167 /* Data TCM RAM */ 168 dtcm: memory@20000000 { 169 compatible = "zephyr,memory-region", "arm,dtcm"; 170 reg = <0x20000000 DT_SIZE_K(128)>; 171 zephyr,memory-region = "DTCM"; 172 }; 173 174 /* Instruction TCM RAM (64KB as `TCM_AXI_SHARED` is `000`) */ 175 itcm: memory@0 { 176 compatible = "zephyr,memory-region", "arm,itcm"; 177 reg = <0x00000000 DT_SIZE_K(64)>; 178 zephyr,memory-region = "ITCM"; 179 }; 180 181 otghs_fs_phy: otghs_fs_phy { 182 compatible = "usb-nop-xceiv"; 183 #phy-cells = <0>; 184 }; 185 186 die_temp: dietemp { 187 io-channels = <&adc3 17>; 188 ts-cal2-temp = <130>; 189 }; 190 191 vref: vref { 192 io-channels = <&adc3 18>; 193 }; 194 195 vbat: vbat { 196 io-channels = <&adc3 16>; 197 }; 198}; 199
