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/Zephyr-latest/drivers/interrupt_controller/
DKconfig.rv32m11 # RV32M1 INTMUX config
7 bool "OpenISA RV32M1 INTMUX interrupt controller support"
12 Select this option to enable support for the RV32M1 INTMUX
14 The INTMUX peripheral combines level 2 interrupts into
21 int "INTMUX driver initialization priority"
24 Boot time initialization priority for INTMUX driver.
28 bool "INTMUX channel 0"
30 Enable support for INTMUX channel 0.
33 bool "INTMUX channel 1"
35 Enable support for INTMUX channel 1.
[all …]
Dintc_rv32m1_intmux.c11 * @brief RV32M1 INTMUX (interrupt multiplexer) driver
14 * SoC using the INTMUX peripheral.
16 * Each of the RI5CY and ZERO-RISCY cores has an INTMUX peripheral;
20 * For this reason, only a single intmux device is declared here. The
21 * dtsi for each core needs to set up the intmux device and any
33 #include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h>
120 * of chapter 36 INTMUX of RV32M1 RM, in rv32m1_intmux_isr()
121 * Note: Unlike the NVIC, the INTMUX does not latch pending source in rv32m1_intmux_isr()
122 * interrupts. This means that the INTMUX output channel ISRs must in rv32m1_intmux_isr()
162 /* Enable INTMUX clock. */ in rv32m1_intmux_init()
/Zephyr-latest/dts/arm/infineon/cat1a/legacy/
Dpsoc6_cm0.dtsi20 intmux: intmux@40210020 { label
22 compatible = "cypress,psoc6-intmux";
30 compatible = "cypress,psoc6-intmux-ch";
38 compatible = "cypress,psoc6-intmux-ch";
46 compatible = "cypress,psoc6-intmux-ch";
54 compatible = "cypress,psoc6-intmux-ch";
62 compatible = "cypress,psoc6-intmux-ch";
70 compatible = "cypress,psoc6-intmux-ch";
78 compatible = "cypress,psoc6-intmux-ch";
86 compatible = "cypress,psoc6-intmux-ch";
[all …]
/Zephyr-latest/soc/openisa/rv32m1/
Dsoc.h20 * go through one of the 8 channels in the INTMUX
21 * peripheral. There are 32 level 1 interrupts, including 8 INTMUX
22 * interrupts. Each INTMUX interrupt can mux at most
58 * @brief INTMUX channel (i.e. level 2 aggregator number) for an IRQ
62 * @param irq The IRQ number whose INTMUX channel / level 2 aggregator
64 * @return INTMUX channel number associated with the IRQ
71 * - the INTMUX output IRQ numbers are arranged consecutively in rv32m1_intmux_channel()
84 * @brief INTMUX interrupt ID number for an IRQ
88 * @param The IRQ number whose INTMUX interrupt ID to get, in the Zephyr
90 * @return The INTMUX interrupt ID, in the inclusive range 0 to 31
Dsoc.c120 * directly at the INTMUX registers. We can't in arch_irq_is_enabled()
127 ier = INTMUX->CHANNEL[channel].CHn_IER_31_0 & BIT(line); in arch_irq_is_enabled()
138 * events, and find the INTMUX device if necessary.
DKconfig.defconfig8 # 32 from event unit + 32 * (1 + max enabled INTMUX channel)
/Zephyr-latest/dts/bindings/interrupt-controller/
Dcypress,psoc6-intmux.yaml12 At CPU Sub System (CPUSS) there are 8 special registers (intmux[0~7]) to
14 4 interrupt sources by grouping intmux channels. These means that each byte
15 from intmux[0~7] store a 'vector number' which selects the peripheral
26 intmux[0] = {ch03, ch02, ch01, ch00}
27 intmux[1] = {ch07, ch06, ch05, ch04}
29 intmux[7] = {ch31, ch30, ch29, ch28}
57 intmux[20 mod 8] |= 0x02 << (20 mod 4);
70 compatible: "cypress,psoc6-intmux"
Dopenisa,rv32m1-intmux.yaml4 description: RV32M1 INTMUX IP
6 compatible: "openisa,rv32m1-intmux"
Dopenisa,rv32m1-intmux-ch.yaml4 description: RV32M1 INTMUX channel
6 compatible: "openisa,rv32m1-intmux-ch"
Dcypress,psoc6-intmux-ch.yaml8 see cypress,psoc6-intmux
10 compatible: "cypress,psoc6-intmux-ch"
/Zephyr-latest/dts/riscv/openisa/
Drv32m1.dtsi6 #include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h>
88 intmux0: intmux@4004f000 {
89 compatible = "openisa,rv32m1-intmux";
99 compatible = "openisa,rv32m1-intmux-ch";
109 compatible = "openisa,rv32m1-intmux-ch";
119 compatible = "openisa,rv32m1-intmux-ch";
129 compatible = "openisa,rv32m1-intmux-ch";
139 compatible = "openisa,rv32m1-intmux-ch";
149 compatible = "openisa,rv32m1-intmux-ch";
159 compatible = "openisa,rv32m1-intmux-ch";
[all …]
Drv32m1_ri5cy.dtsi10 intmux = &intmux0;
41 * INTMUX channels below are somewhat arbitrary.
Drv32m1_zero_riscy.dtsi10 intmux = &intmux1;
41 * INTMUX channels below are somewhat arbitrary.
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/
Dll_irqs.h14 * We'll use the INTMUX ISR for channel 2 instead of LPTMR1 ISR
21 * We'll use the INTMUX ISR for channel 3 instead of radio ISR
Dcntr.c11 #include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h>
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dopenisa-intmux.h11 * Level 1 IRQ offsets for each INTMUX channel.
/Zephyr-latest/soc/sensry/ganymed/sy1xx/common/
Dsoc.c70 * events, and find the INTMUX device if necessary.
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dintc_esp32.h150 * sources, as defined in esp-xtensa-intmux.h, or one of the internal
188 * sources, as defined in esp-xtensa-intmux.h, or one of the internal
/Zephyr-latest/dts/riscv/espressif/esp32c2/
Desp32c2_common.dtsi11 #include <zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h>
/Zephyr-latest/dts/riscv/espressif/esp32c6/
Desp32c6_common.dtsi10 #include <zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h>
/Zephyr-latest/dts/riscv/espressif/esp32c3/
Desp32c3_common.dtsi11 #include <zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h>
/Zephyr-latest/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi13 #include <zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h>
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi13 #include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h>
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi13 #include <zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h>
/Zephyr-latest/boards/openisa/rv32m1_vega/doc/
Dindex.rst70 | INTMUX | on-chip | level 2 interrupt controller |
98 | INTMUX | on-chip | level 2 interrupt controller |

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