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/Zephyr-latest/dts/arm/infineon/cat1a/legacy/
Dpsoc6_cm0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
13 compatible = "arm,cortex-m0+";
16 /delete-node/ cpu@1;
21 /* see cypress,psoc6-int-mux.yaml */
22 compatible = "cypress,psoc6-intmux";
26 #address-cells = <1>;
27 #size-cells = <1>;
29 intmux_ch0: interrupt-controller@0 {
30 compatible = "cypress,psoc6-intmux-ch";
[all …]
/Zephyr-latest/dts/xtensa/nxp/
Dnxp_imx8qxp.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 irqsteer: interrupt-controller@51080000 {
11 compatible = "nxp,irqsteer-intc";
13 power-domains = <&irqstr_pd>;
15 #size-cells = <0>;
16 #address-cells = <1>;
18 master0: interrupt-controller@0 {
19 compatible = "nxp,irqsteer-master";
21 interrupt-controller;
22 #interrupt-cells = <1>;
[all …]
Dnxp_imx8qm.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 irqsteer: interrupt-controller@510a0000 {
12 compatible = "nxp,irqsteer-intc";
14 power-domains = <&irqstr_pd>;
16 #size-cells = <0>;
17 #address-cells = <1>;
19 master0: interrupt-controller@0 {
20 compatible = "nxp,irqsteer-master";
22 interrupt-controller;
23 #interrupt-cells = <1>;
[all …]
Dnxp_imx8m.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/imx_ccm.h>
13 #address-cells = <1>;
14 #size-cells = <0>;
18 compatible = "cdns,tensilica-xtensa-lx6";
21 #address-cells = <1>;
22 #size-cells = <0>;
24 clic: interrupt-controller@0 {
25 compatible = "cdns,xtensa-core-intc";
27 interrupt-controller;
[all …]
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.dw2 # SPDX-License-Identifier: Apache-2.0
5 bool "Designware Interrupt Controller for ACE"
10 Designware Interrupt Controller used by ACE.
13 bool "Designware Interrupt Controller"
18 Designware Interrupt Controller can be used as a 2nd level interrupt
19 controller which combines several sources of interrupt into one line
20 that is then routed to the 1st level interrupt controller.
26 string "Name for Designware Interrupt Controller"
29 Give a name for the instance of Designware Interrupt Controller
36 the ISRs for Designware Interrupt Controller are assigned.
[all …]
DKconfig1 # interrupt controller configuration options
4 # SPDX-License-Identifier: Apache-2.0
6 menu "Interrupt controller drivers"
9 bool "ARCv2 Interrupt Unit"
13 The ARCv2 interrupt unit has 16 allocated exceptions associated with
15 The interrupt unit is optional in the ARCv2-based processors. When
17 interrupt unit. The ARCv2 interrupt unit is highly programmable.
20 bool "SweRV EH1 Programmable Interrupt Controller (PIC)"
24 Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU.
27 bool "VexRiscv LiteX Interrupt controller"
[all …]
DKconfig.nxp_s321 # Configuration for NXP S32 external interrupt controller
3 # Copyright 2022-2024 NXP
4 # SPDX-License-Identifier: Apache-2.0
7 bool "External interrupt controller driver for NXP S32 MCUs"
13 External interrupt controller driver for NXP S32 MCUs
22 Number of SIUL2 external interrupts per controller. This is a SoC
30 interrupt line. This is a SoC integration option.
35 bool "Wake-up Unit interrupt controller driver for NXP S32 MCUs"
39 Wake-up Unit interrupt controller driver for NXP S32 MCUs
48 Number of WKPU external and internal sources per controller. This is
/Zephyr-latest/dts/bindings/gpio/
Dnxp,s32-gpio.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
5 NXP S32 GPIO controller.
7 The GPIO controller provides the option to route external input pad interrupts
8 to either the SIUL2 EIRQ interrupt controller or, when available on the SoC,
9 the WKPU interrupt controller. By default, GPIO interrupts are routed to the
10 SIUL2 EIRQ interrupt controller.
12 To route external interrupts to the WKPU interrupt controller, the GPIO
14 the following snippet of devicetree source code instructs the GPIO controller
15 to route the interrupt from pin 9 of `gpioa` to the WKPU interrupt controller:
[all …]
/Zephyr-latest/tests/kernel/interrupt/
Dmultilevel_irq.overlay3 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = < 0x1 >;
9 #size-cells = < 0x1 >;
11 test_cpu_intc: interrupt-controller {
12 compatible = "vnd,cpu-intc";
13 #address-cells = <0>;
14 #interrupt-cells = < 0x01 >;
15 interrupt-controller;
18 test_l1_irq: interrupt-controller@bbbbcccc {
21 interrupt-controller;
[all …]
/Zephyr-latest/dts/riscv/qemu/
Dvirt-riscv.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 * qemu-system-riscv32 -machine virt,dumpdtb=virt.dtb -smp 8 -m 256
13 /dts-v1/;
16 #address-cells = < 0x01 >;
17 #size-cells = < 0x01 >;
18 compatible = "riscv-virtio";
19 model = "riscv-virtio,qemu";
22 bank-width = < 0x04 >;
24 compatible = "cfi-flash";
29 interrupt-parent = < &plic >;
[all …]
/Zephyr-latest/dts/x86/intel/
Dgpio_common.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/acpi/acpi.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
15 interrupt-parent = <&intc>;
17 gpio-controller;
18 #gpio-cells = <2>;
24 interrupt-parent = <&intc>;
26 gpio-controller;
27 #gpio-cells = <2>;
[all …]
/Zephyr-latest/tests/drivers/build_all/interrupt_controller/common/boards/
Dimx8mp_evk_mimx8ml8_adsp.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * Made-up devicetree to build intc_nxp_irqsteer.c, refer to:
9 * https://github.com/zephyrproject-rtos/zephyr/pull/62776#issuecomment-1727846332
14 irqsteer: interrupt-controller@30a80000 {
15 compatible = "nxp,irqsteer-intc";
18 #size-cells = <0>;
19 #address-cells = <1>;
21 master0: interrupt-controller@0 {
22 compatible = "nxp,irqsteer-master";
24 interrupt-controller;
[all …]
/Zephyr-latest/dts/riscv/openisa/
Drv32m1.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h>
7 #include <zephyr/dt-bindings/gpio/gpio.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
17 zephyr,flash-controller = &ftfe;
21 #address-cells = <1>;
22 #size-cells = <0>;
[all …]
/Zephyr-latest/include/zephyr/devicetree/
Dinterrupt_controller.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Interrupt controller devicetree macro public API header file.
23 * @defgroup devicetree-interrupt_controller Devicetree Interrupt Controller API
29 * @brief Get the aggregator level of an interrupt controller
34 * @param node_id node identifier of an interrupt controller
36 * @return Level of the interrupt controller
41 * @brief Get the aggregator level of a `DT_DRV_COMPAT` interrupt controller
46 * @param inst instance of an interrupt controller
48 * @return Level of the interrupt controller
/Zephyr-latest/dts/riscv/microchip/
Dmpfs.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
18 clock-frequency = <0>;
23 hlic0: interrupt-controller {
24 compatible = "riscv,cpu-intc";
25 #address-cells = <0>;
[all …]
/Zephyr-latest/dts/riscv/andes/
Dandes_v5_ae350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 compatible = "andestech,andescore-v5", "riscv";
24 mmu-type = "riscv,sv32";
25 clock-frequency = <60000000>;
[all …]
/Zephyr-latest/scripts/dts/python-devicetree/tests/
Dtest.dts4 * SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
16 interrupt-parent-test {
17 controller {
18 compatible = "interrupt-three-cell";
19 #interrupt-cells = <3>;
20 interrupt-controller;
24 interrupt-names = "foo", "bar";
25 interrupt-parent = <&{/interrupt-parent-test/controller}>;
28 interrupts-extended-test {
[all …]
/Zephyr-latest/arch/arm64/core/
Dirq_init.c4 * SPDX-License-Identifier: Apache-2.0
9 * @brief ARM64 Cortex-A interrupt initialisation
18 * This function invokes the ARM Generic Interrupt Controller (GIC) driver to
19 * initialise the interrupt system on the SoCs that use the GIC as the primary
20 * interrupt controller.
22 * When a custom interrupt controller is used, however, the SoC layer function
23 * is invoked for SoC-specific interrupt system initialisation.
28 /* Invoke SoC-specific interrupt controller initialisation */ in z_arm64_interrupt_init()
/Zephyr-latest/dts/riscv/sifive/
Driscv64-fu740.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 pclk: p-clk {
[all …]
/Zephyr-latest/arch/arm64/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
21 non-GIC) interrupt controller.
23 A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
24 allow interfacing to a custom external interrupt controller and this
25 option must be selected when such cores are connected to an interrupt
26 controller that is not the ARM Generic Interrupt Controller (GIC).
28 When this option is selected, the architecture interrupt control
29 functions are mapped to the SoC interrupt control interface, which is
/Zephyr-latest/dts/bindings/interrupt-controller/
Dgd,gd32-exti.yaml1 description: GigaDevice External Interrupt Controller
3 compatible: "gd,gd32-exti"
5 include: [base.yaml, interrupt-controller.yaml]
14 "#interrupt-cells":
17 num-lines:
20 description: Number of lines supported by the interrupt controller.
22 interrupt-cells:
23 - line
Drenesas,ra-interrupt-controller-unit.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Renesas RA series interrupt controller unit
6 compatible: "renesas,ra-interrupt-controller-unit"
8 include: [interrupt-controller.yaml, base.yaml]
14 "#interrupt-cells":
17 interrupt-cells:
18 - irq
19 - priority
20 - flags
Dsnps,archs-idu-intc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 ARC-HS Interrupt Distribution Unit 2nd-level interrupt controller. Can be
7 common/external IRQs towards the core interrupt controller.
9 compatible: "snps,archs-idu-intc"
11 include: [interrupt-controller.yaml, base.yaml]
13 interrupt-cells:
14 - irq
15 - priority
/Zephyr-latest/boards/mediatek/mt8196/
Dmt8196_adsp.dts2 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #address-cells = <1>;
10 #size-cells = <1>;
14 compatible = "mmio-sram";
20 compatible = "mmio-sram";
26 compatible = "mmio-sram";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 compatible = "cdns,xtensa-core-intc";
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dnxp-s32-gpio.h4 * SPDX-License-Identifier: Apache-2.0
15 * - Bit 8: Interrupt controller to which the respective GPIO interrupt is routed.
27 * @name NXP S32 GPIO interrupt controller routing flags
28 * @brief NXP S32 GPIO interrupt controller routing flags
32 /** Interrupt routed to the WKPU controller */

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