Lines Matching +full:interrupt +full:- +full:controller
4 * SPDX-License-Identifier: Apache-2.0
9 * qemu-system-riscv32 -machine virt,dumpdtb=virt.dtb -smp 8 -m 256
13 /dts-v1/;
16 #address-cells = < 0x01 >;
17 #size-cells = < 0x01 >;
18 compatible = "riscv-virtio";
19 model = "riscv-virtio,qemu";
22 bank-width = < 0x04 >;
24 compatible = "cfi-flash";
29 interrupt-parent = < &plic >;
30 clock-frequency = < 0x384000 >;
33 reg-shift = < 0 >;
37 #address-cells = < 0x01 >;
38 #size-cells = < 0x00 >;
44 compatible = "qemu,riscv-virt", "riscv";
46 hlic0: interrupt-controller {
47 compatible = "riscv,cpu-intc";
48 #address-cells = <0>;
49 #interrupt-cells = < 0x01 >;
50 interrupt-controller;
58 compatible = "qemu,riscv-virt", "riscv";
60 hlic1: interrupt-controller {
61 compatible = "riscv,cpu-intc";
62 #address-cells = <0>;
63 #interrupt-cells = < 0x01 >;
64 interrupt-controller;
72 compatible = "qemu,riscv-virt", "riscv";
74 hlic2: interrupt-controller {
75 compatible = "riscv,cpu-intc";
76 #address-cells = <0>;
77 #interrupt-cells = < 0x01 >;
78 interrupt-controller;
86 compatible = "qemu,riscv-virt", "riscv";
88 hlic3: interrupt-controller {
89 compatible = "riscv,cpu-intc";
90 #address-cells = <0>;
91 #interrupt-cells = < 0x01 >;
92 interrupt-controller;
100 compatible = "qemu,riscv-virt", "riscv";
102 hlic4: interrupt-controller {
103 compatible = "riscv,cpu-intc";
104 #address-cells = <0>;
105 #interrupt-cells = < 0x01 >;
106 interrupt-controller;
114 compatible = "qemu,riscv-virt", "riscv";
116 hlic5: interrupt-controller {
117 compatible = "riscv,cpu-intc";
118 #address-cells = <0>;
119 #interrupt-cells = < 0x01 >;
120 interrupt-controller;
128 compatible = "qemu,riscv-virt", "riscv";
130 hlic6: interrupt-controller {
131 compatible = "riscv,cpu-intc";
132 #address-cells = <0>;
133 #interrupt-cells = < 0x01 >;
134 interrupt-controller;
142 compatible = "qemu,riscv-virt", "riscv";
144 hlic7: interrupt-controller {
145 compatible = "riscv,cpu-intc";
146 #address-cells = <0>;
147 #interrupt-cells = < 0x01 >;
148 interrupt-controller;
159 #address-cells = < 0x01 >;
160 #size-cells = < 0x01 >;
161 compatible = "simple-bus";
164 plic: interrupt-controller@c000000 {
165 riscv,max-priority = <7>;
168 interrupts-extended = <
178 interrupt-controller;
179 compatible = "sifive,plic-1.0.0";
180 #address-cells = < 0x00 >;
181 #interrupt-cells = < 0x02 >;
187 interrupts-extended = <&hlic0 0x03 &hlic0 0x07