Home
last modified time | relevance | path

Searched +full:input +full:- +full:latch (Results 1 – 25 of 27) sorted by relevance

12

/Zephyr-latest/dts/bindings/gpio/
Dti,tca9538.yaml3 # SPDX-License-Identifier: Apache-2.0
9 include: [i2c-device.yaml, gpio-controller.yaml]
12 "#gpio-cells":
21 nint-gpios:
22 type: phandle-array
24 Connection for the NINT signal. This signal is active-low when
27 input-latch:
30 Input latch register bit is 0 by default and the input pin state
31 is not latched. When input latch register bit is 1 and the input
34 interrupt-mask:
[all …]
Dadi,max22190-gpio.yaml3 # SPDX-License-Identifier: Apache-2.0
6 ADI MAX22190 octal industrial Input with advanced diagnostic
10 filter-wbes = <CH0 CH1 CH2 ... CH7 > for wire break
12 filter-fbps and filter-delays.
16 pinctrl-names = "default";
18 compatible = "adi,max22190-gpio";
21 spi-max-frequency = <1000000>;
24 gpio-controller;
25 #gpio-cells = <2>;
29 max22190-mode = <1>; // modes range from 0-4
[all …]
Dadi,max14906-gpio.yaml3 # SPDX-License-Identifier: Apache-2.0
5 description: ADI MAX14906 quad industrial Input/Output with advanced diagnostics
7 compatible: "adi,max14906-gpio"
10 "#gpio-cells":
17 drdy-gpios:
19 High-Side Open-Drain Output. READY is passive low when the internal
22 type: phandle-array
23 fault-gpios:
27 type: phandle-array
28 sync-gpios:
[all …]
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_vci.h4 * SPDX-License-Identifier: Apache-2.0
31 /* VCI Latch Enable register */
32 /* VCI Latch Reset register */
45 /* VCI Input Enable register */
Dmec_tach.h4 * SPDX-License-Identifier: Apache-2.0
28 /* Enable input filter */
32 /* Select read mode. Latch data on rising edge of selected trigger */
50 /* Enable input toggle interrupt */
54 /* Read-only latched TACH pulse counter */
61 * bits[0, 2-3] are R/W1C
62 * bit[1] is Read-Only
/Zephyr-latest/dts/bindings/pinctrl/
Dpincfg-node.yaml2 # SPDX-License-Identifier: Apache-2.0
16 https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
19 bias-disable:
23 bias-high-impedance:
25 description: high impedance mode ("third-state", "floating")
27 bias-bus-hold:
29 description: latch weakly
31 bias-pull-up:
33 description: enable pull-up resistor
35 bias-pull-down:
[all …]
Dnxp,mcux-rt11xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
15 drive-strength = "high";
16 slew-rate = "slow";
20 Both pins will be configured with a weak latch, high drive strength,
25 drive-open-drain: ODE/ODE_LPSR=1
26 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
27 bias-pull-down: PUE=1, PUS=0
28 bias-pull-up: PUE=1, PUS=1
29 bias-disable: PULL=11 (in supported registers)
[all …]
Dnxp,mcux-rt-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "100-mhz";
21 Both pins will be configured with a weak latch, drive strength of "r0-6",
26 input-schmitt-enable: HYS=1
27 drive-open-drain: ODE=1
28 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
29 bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
[all …]
/Zephyr-latest/include/zephyr/drivers/gpio/
Dgpio_cmsdk_ahb.h4 * SPDX-License-Identifier: Apache-2.0
15 /* ARM LTD CMSDK AHB General Purpose Input/Output (GPIO) */
19 /* Offset: 0x004 (r/w) data output latch register */
49 /* Offset: 0x400 - 0x7fc lower byte masked access register (r/w) */
51 /* Offset: 0x800 - 0xbfc upper byte masked access register (r/w) */
/Zephyr-latest/drivers/gpio/
Dgpio_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
27 * data access, bit access, mode, latch and wake-up controller are defined in
40 uint32_t latch; member
95 WAKEUP->WKUP_CTRL_REG = 0; in gpio_smartbond_wkup_init()
96 WAKEUP->WKUP_CLEAR_P0_REG = 0xffffffff; in gpio_smartbond_wkup_init()
97 WAKEUP->WKUP_CLEAR_P1_REG = 0xffffffff; in gpio_smartbond_wkup_init()
98 WAKEUP->WKUP_SELECT_P0_REG = 0; in gpio_smartbond_wkup_init()
99 WAKEUP->WKUP_SELECT_P1_REG = 0; in gpio_smartbond_wkup_init()
100 WAKEUP->WKUP_SEL_GPIO_P0_REG = 0; in gpio_smartbond_wkup_init()
101 WAKEUP->WKUP_SEL_GPIO_P1_REG = 0; in gpio_smartbond_wkup_init()
[all …]
Dgpio_max14906.c5 * SPDX-License-Identifier: Apache-2.0
29 struct max14906_data *data = dev->data; in max14906_pars_spi_diag()
33 LOG_ERR("[DIAG] MAX14906 in SPI diag - error detected\n"); in max14906_pars_spi_diag()
34 data->glob.interrupt.reg_bits.SHT_VDD_FAULT = MAX149X6_GET_BIT(rx_diag_buff[0], 5); in max14906_pars_spi_diag()
35 data->glob.interrupt.reg_bits.ABOVE_VDD_FAULT = in max14906_pars_spi_diag()
37 data->glob.interrupt.reg_bits.OW_OFF_FAULT = MAX149X6_GET_BIT(rx_diag_buff[0], 3); in max14906_pars_spi_diag()
38 data->glob.interrupt.reg_bits.CURR_LIM = MAX149X6_GET_BIT(rx_diag_buff[0], 2); in max14906_pars_spi_diag()
39 data->glob.interrupt.reg_bits.OVER_LD_FAULT = MAX149X6_GET_BIT(rx_diag_buff[0], 1); in max14906_pars_spi_diag()
43 ret = -EIO; in max14906_pars_spi_diag()
45 PRINT_ERR(data->glob.interrupt.reg_bits.SHT_VDD_FAULT); in max14906_pars_spi_diag()
[all …]
Dgpio_pcal64xxa.c5 * SPDX-License-Identifier: Apache-2.0
131 struct pcal64xxa_drv_data *drv_data = dev->data; in pcal64xxa_pin_configure()
132 const struct pcal64xxa_drv_cfg *drv_cfg = dev->config; in pcal64xxa_pin_configure()
137 LOG_DBG("%s: configure pin %i with flags 0x%08X", dev->name, pin, flags); in pcal64xxa_pin_configure()
139 /* This device does not support open-source outputs, and open-drain in pcal64xxa_pin_configure()
140 * outputs can be only configured port-wise. in pcal64xxa_pin_configure()
143 return -ENOTSUP; in pcal64xxa_pin_configure()
151 return -ENOTSUP; in pcal64xxa_pin_configure()
155 return -EWOULDBLOCK; in pcal64xxa_pin_configure()
158 k_sem_take(&drv_data->lock, K_FOREVER); in pcal64xxa_pin_configure()
[all …]
Dgpio_max22190.c5 * SPDX-License-Identifier: Apache-2.0
202 * @param data - Data array to calculate CRC for.
216 * https://www.analog.com/en/design-notes/guidelines-to-implement-crc-algorithm.html in max22190_crc()
230 for (i = 0; i < length - 1; i++) { in max22190_crc()
232 ((datainput >> (length - 2 - i)) & 0x01)); in max22190_crc()
247 * @param dev - MAX22190 device.
248 * @param val - value to be set.
252 struct max22190_data *data = dev->data; in max22190_update_wb_stat()
255 data->wb[ch_n] = (val >> ch_n) & 0x1; in max22190_update_wb_stat()
262 * @param dev - MAX22190 device.
[all …]
Dgpio_pca95xx.c6 * SPDX-License-Identifier: Apache-2.0
12 * @file Driver for PCA95XX and PCAL95XX I2C-based GPIO driver.
86 uint16_t input; member
98 /* Self-reference to the driver instance */
123 const struct gpio_pca95xx_config * const config = dev->config; in read_port_reg()
131 ret = i2c_reg_read_byte_dt(&config->bus, reg, &b_buf); in read_port_reg()
134 config->bus.addr, reg, ret); in read_port_reg()
147 config->bus.addr, reg, b_buf); in read_port_reg()
167 const struct gpio_pca95xx_config * const config = dev->config; in read_port_regs()
171 ret = i2c_burst_read_dt(&config->bus, reg, (uint8_t *)&port_data, in read_port_regs()
[all …]
Dgpio_pca_series.c4 * SPDX-License-Identifier: Apache-2.0
8 * @file Driver for PCA(L)xxxx SERIES I2C-based GPIO expander.
70 * - Type 0: PCA953X, PCA955X
71 * - Type 1: PCAL953X, PCAL955X, PCAL64XXA
72 * - Type 2: PCA957X
73 * - Type 3: PCAL65XX
103 * port-level "pin output configuration" register.
144 uint8_t port_no; /* number of 8-pin ports on device */
171 * - if CONFIG_GPIO_PCA_SERIES_CACHE_ALL is set,
173 * - if CONFIG_GPIO_PCA_SERIES_CACHE_ALL is not set,
[all …]
/Zephyr-latest/soc/mediatek/mt8xxx/
Dcpuclk.c2 * SPDX-License-Identifier: Apache-2.0
13 * * power-on default is 26Mhz, confirmed with a hacked SOF that
72 /* Can't use CPU-counted loops when changing CPU speed, and don't have
82 while (TIMER - t0 < (us * 13)) { in delay_us()
107 * used to set 4-bit fields at a specific offset. After that, a
109 * presumably to latch the input.
162 mtk_adsp_set_cpu_freq(freqs[ARRAY_SIZE(freqs) - 1].mhz); in mtk_adsp_cpu_freq_init()
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dcavs-idc.h4 * SPDX-License-Identifier: Apache-2.0
31 * also latch an interrupt to send back to the originator if unmasked
41 * the PRID of the CPU, equal to arch_curr_cpu()->id in Zephyr) to
61 * level 2 bit for IDC in the per-core INTCTRL DSP register AND the
89 * level 2-5 interrupts). The "mask" field shows the current masking
119 #define CAVS_L2_SHA BIT(16) /* SHA-256 */
130 #define CAVS_L3_DSPGHIS(n) BIT(n) /* DSP Gateway Host Input Stream */
134 #define CAVS_L4_DSPGLIS(n) BIT(n) /* DSP Gateway Link Input Stream */
/Zephyr-latest/dts/arm/renesas/smartbond/
Dda1469x.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/adc/smartbond-adc.h>
11 #include <zephyr/dt-bindings/pinctrl/smartbond-pinctrl.h>
12 #include <zephyr/dt-bindings/dma/dma_smartbond.h>
17 zephyr,flash-controller = &flash_controller;
21 compatible = "zephyr,lvgl-pointer-input";
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/Zephyr-latest/tests/kernel/context/src/
Dmain.c2 * Copyright (c) 2012-2015 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
42 #define UNKNOWN_COMMAND -1
43 #define INVALID_BEHAVIOUR -2
54 * The Cortex-M use the SYSTICK exception for the system timer, which is
75 /* Cortex-M1 and Nios II do have a power saving instruction, so k_cpu_idle()
138 if (arch_current_thread()->base.prio < 0) { in isr_handler()
251 dt = k_uptime_ticks() - t0; in _test_kernel_cpu_idle()
252 zassert_true(abs((int32_t) (dt - dur)) <= slop, in _test_kernel_cpu_idle()
294 * - The kernel architecture provide an idle function to be run when the system
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
75 /* Frame Filtering Behave as a Co-ordinator */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
126 /* System Time Counter (40-bit) */
180 * of non-standard values
203 /* Bit mask to access Transmit buffer index offset 10-bit field */
[all …]
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/
Disoal.c4 * SPDX-License-Identifier: Apache-2.0
72 /* Defined the wrapping point and mid point in the range of time input values,
100 * Zero-init entire ISO-AL state
109 * @brief Initialize ISO-AL
146 * @return Validity - valid if time_after leads time_before with
160 if ((time_before - time_after) <= ISOAL_TIME_SPAN_HALF_US) { in isoal_get_time_diff()
164 *result = time_after + ISOAL_TIME_SPAN_FULL_US - time_before; in isoal_get_time_diff()
172 *result = time_after - time_before; in isoal_get_time_diff()
197 * @brief Find free sink from statically-sized pool and allocate it
288 session->handle = handle; in isoal_sink_create()
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
[all …]
/Zephyr-latest/drivers/wifi/nxp/
DKconfig.nxp1 # Copyright 2022-2024 NXP
2 # SPDX-License-Identifier: Apache-2.0
5 bool "NXP Wi-Fi driver support"
14 Enable NXP SoC Wi-Fi support.
28 bool "Custom NXP Wi-Fi part"
30 Customize NXP Wi-Fi chip support.
33 prompt "Select NXP Wi-Fi part"
36 Choose NXP Wi-Fi chip support.
39 bool "NXP RW610-based Chipset"
44 Select this option if you have a NXP RW610-based
[all …]
/Zephyr-latest/drivers/serial/
Duart_mchp_xec.c2 * Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
6 * SPDX-License-Identifier: Apache-2.0
97 * RXRDY pin will go inactive when there are no more charac-
102 * reached, the RXRDY pin will go low active. Once it is acti-
107 * FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
140 #define LCR_DLAB 0x80 /* divisor latch access enable */
173 #define IIRC(dev) (((struct uart_xec_dev_data *)(dev)->data)->iir_cache)
242 struct uart_xec_device_config const *dev_cfg = dev->config; in uart_clr_slp_en()
244 z_mchp_xec_pcr_periph_sleep(dev_cfg->pcr_idx, dev_cfg->pcr_bitpos, 0); in uart_clr_slp_en()
249 struct uart_xec_device_config const *dev_cfg = dev->config; in uart_xec_girq_clr()
[all …]
/Zephyr-latest/include/zephyr/arch/
Darch_interface.h4 * SPDX-License-Identifier: Apache-2.0
8 * @defgroup arch-interface Architecture Interface
13 * call architecture-specific API so will have the prototypes for the
14 * architecture-specific APIs here. Architecture APIs that aren't used in this
17 * The set of architecture-specific APIs used internally by public macros and
53 * @defgroup arch-timing Architecture timing APIs
54 * @ingroup arch-interface
82 * through the full 64 bit space, wrapping at 2^64-1. Hardware with
92 * @addtogroup arch-threads
126 * buffer, defined as the area usable for thread stack context and thread-
[all …]

12