1 /*
2 * Copyright (c) 2024 Analog Devices Inc.
3 * Copyright (c) 2024 Baylibre SAS
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/gpio.h>
9 #include <zephyr/drivers/spi.h>
10 #include <zephyr/kernel.h>
11 #include <zephyr/sys/byteorder.h>
12
13 #define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
14 #include <zephyr/logging/log.h>
15
16 LOG_MODULE_REGISTER(gpio_max14906);
17
18 #include <zephyr/drivers/gpio/gpio_utils.h>
19
20 #include "gpio_max14906.h"
21 #include "gpio_max149x6.h"
22
23 #define DT_DRV_COMPAT adi_max14906_gpio
24
25 static int gpio_max14906_diag_chan_get(const struct device *dev);
26
max14906_pars_spi_diag(const struct device * dev,uint8_t * rx_diag_buff,uint8_t rw)27 static int max14906_pars_spi_diag(const struct device *dev, uint8_t *rx_diag_buff, uint8_t rw)
28 {
29 struct max14906_data *data = dev->data;
30 int ret = 0;
31
32 if (rx_diag_buff[0]) {
33 LOG_ERR("[DIAG] MAX14906 in SPI diag - error detected\n");
34 data->glob.interrupt.reg_bits.SHT_VDD_FAULT = MAX149X6_GET_BIT(rx_diag_buff[0], 5);
35 data->glob.interrupt.reg_bits.ABOVE_VDD_FAULT =
36 MAX149X6_GET_BIT(rx_diag_buff[0], 4);
37 data->glob.interrupt.reg_bits.OW_OFF_FAULT = MAX149X6_GET_BIT(rx_diag_buff[0], 3);
38 data->glob.interrupt.reg_bits.CURR_LIM = MAX149X6_GET_BIT(rx_diag_buff[0], 2);
39 data->glob.interrupt.reg_bits.OVER_LD_FAULT = MAX149X6_GET_BIT(rx_diag_buff[0], 1);
40
41 uint8_t globlf = MAX149X6_GET_BIT(rx_diag_buff[0], 0);
42
43 ret = -EIO;
44
45 PRINT_ERR(data->glob.interrupt.reg_bits.SHT_VDD_FAULT);
46 PRINT_ERR(data->glob.interrupt.reg_bits.ABOVE_VDD_FAULT);
47 PRINT_ERR(data->glob.interrupt.reg_bits.OW_OFF_FAULT);
48 PRINT_ERR(data->glob.interrupt.reg_bits.CURR_LIM);
49 PRINT_ERR(data->glob.interrupt.reg_bits.OVER_LD_FAULT);
50 PRINT_ERR(globlf);
51 }
52
53 if (rw == MAX149x6_WRITE && (rx_diag_buff[1] & 0x0f)) {
54 /* +-----------------------------------------------------------------------+
55 * | LSB BYTE 2 MSB |
56 * +--------+--------+--------+--------+--------+--------+--------+--------+
57 * | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 |
58 * +--------+--------+--------+--------+--------+--------+--------+--------+
59 * | Fault1 | Fault2 | Fault3 | Fault4 | DiLvl1 | DiLvl2 | DiLvl3 | DiLvl4 |
60 * +--------+--------+--------+--------+--------+--------+--------+--------+
61 */
62
63 LOG_ERR("[DIAG] Flt1[%x] Flt2[%x] Flt3[%x] Flt4[%x]",
64 MAX149X6_GET_BIT(rx_diag_buff[1], 0), MAX149X6_GET_BIT(rx_diag_buff[1], 1),
65 MAX149X6_GET_BIT(rx_diag_buff[1], 2), MAX149X6_GET_BIT(rx_diag_buff[1], 3));
66 if (rx_diag_buff[1] & 0x0f) {
67 LOG_ERR("[DIAG] gpio_max14906_diag_chan_get(%x)\n", rx_diag_buff[1] & 0x0f);
68 ret = gpio_max14906_diag_chan_get(dev);
69 }
70 }
71
72 return ret;
73 }
74
max14906_reg_trans_spi_diag(const struct device * dev,uint8_t addr,uint8_t tx,uint8_t rw)75 static int max14906_reg_trans_spi_diag(const struct device *dev, uint8_t addr, uint8_t tx,
76 uint8_t rw)
77 {
78 const struct max14906_config *config = dev->config;
79 uint8_t rx_diag_buff[2];
80
81 if (!gpio_pin_get_dt(&config->fault_gpio)) {
82 LOG_ERR("[FAULT] pin triggered");
83 }
84
85 uint8_t ret = max149x6_reg_transceive(dev, addr, tx, rx_diag_buff, rw);
86
87 if (max14906_pars_spi_diag(dev, rx_diag_buff, rw)) {
88 ret = -EIO;
89 }
90
91 return ret;
92 }
93
94 #define MAX14906_REG_READ(dev, addr) max14906_reg_trans_spi_diag(dev, addr, 0, MAX149x6_READ)
95 #define MAX14906_REG_WRITE(dev, addr, val) \
96 max14906_reg_trans_spi_diag(dev, addr, val, MAX149x6_WRITE)
97
98 /*
99 * @brief Register update function for MAX14906
100 *
101 * @param dev - MAX149x6 device.
102 * @param addr - Register valueto wich data is updated.
103 * @param mask - Corresponding mask to the data that will be updated.
104 * @param val - Updated value to be written in the register at update.
105 * @return 0 in case of success, negative error code otherwise.
106 */
max14906_reg_update(const struct device * dev,uint8_t addr,uint8_t mask,uint8_t val)107 static int max14906_reg_update(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val)
108 {
109 int ret;
110 uint32_t reg_val = 0;
111
112 ret = MAX14906_REG_READ(dev, addr);
113
114 reg_val = ret;
115 reg_val &= ~mask;
116 reg_val |= mask & val;
117
118 return MAX14906_REG_WRITE(dev, addr, reg_val);
119 }
120
gpio_max14906_diag_chan_get(const struct device * dev)121 static int gpio_max14906_diag_chan_get(const struct device *dev)
122 {
123 const struct max14906_config *config = dev->config;
124 struct max14906_data *data = dev->data;
125 int ret;
126
127 if (!gpio_pin_get_dt(&config->fault_gpio)) {
128 LOG_ERR("[DIAG] FAULT flag is rised");
129 }
130
131 data->glob.interrupt.reg_raw =
132 max149x6_reg_transceive(dev, MAX14906_INT_REG, 0, NULL, MAX149x6_READ);
133 if (data->glob.interrupt.reg_raw) {
134 if (data->glob.interrupt.reg_bits.OVER_LD_FAULT ||
135 data->glob.interrupt.reg_bits.CURR_LIM) {
136 data->chan.ovr_ld.reg_raw = max149x6_reg_transceive(
137 dev, MAX14906_OVR_LD_REG, 0, NULL, MAX149x6_READ);
138 }
139 if (data->glob.interrupt.reg_bits.OW_OFF_FAULT ||
140 data->glob.interrupt.reg_bits.ABOVE_VDD_FAULT) {
141 data->chan.opn_wir.reg_raw = max149x6_reg_transceive(
142 dev, MAX14906_OPN_WIR_FLT_REG, 0, NULL, MAX149x6_READ);
143 }
144 if (data->glob.interrupt.reg_bits.SHT_VDD_FAULT) {
145 data->chan.sht_vdd.reg_raw = max149x6_reg_transceive(
146 dev, MAX14906_SHT_VDD_FLT_REG, 0, NULL, MAX149x6_READ);
147 }
148 if (data->glob.interrupt.reg_bits.DE_MAG_FAULT) {
149 data->chan.doi_level.reg_raw = max149x6_reg_transceive(
150 dev, MAX14906_DOILEVEL_REG, 0, NULL, MAX149x6_READ);
151 if (data->chan.doi_level.reg_raw) {
152 PRINT_ERR(data->chan.doi_level.reg_bits.VDDOK_FAULT1);
153 PRINT_ERR(data->chan.doi_level.reg_bits.VDDOK_FAULT2);
154 PRINT_ERR(data->chan.doi_level.reg_bits.VDDOK_FAULT3);
155 PRINT_ERR(data->chan.doi_level.reg_bits.VDDOK_FAULT4);
156 PRINT_ERR(data->chan.doi_level.reg_bits.SAFE_DAMAGE_F1);
157 PRINT_ERR(data->chan.doi_level.reg_bits.SAFE_DAMAGE_F2);
158 PRINT_ERR(data->chan.doi_level.reg_bits.SAFE_DAMAGE_F3);
159 PRINT_ERR(data->chan.doi_level.reg_bits.SAFE_DAMAGE_F4);
160 }
161 }
162 if (data->glob.interrupt.reg_bits.SUPPLY_ERR) {
163 data->glob.glob_err.reg_raw = max149x6_reg_transceive(
164 dev, MAX14906_GLOB_ERR_REG, 0, NULL, MAX149x6_READ);
165 PRINT_ERR(data->glob.glob_err.reg_bits.VINT_UV);
166 PRINT_ERR(data->glob.glob_err.reg_bits.V5_UVLO);
167 PRINT_ERR(data->glob.glob_err.reg_bits.VDD_LOW);
168 PRINT_ERR(data->glob.glob_err.reg_bits.VDD_WARN);
169 PRINT_ERR(data->glob.glob_err.reg_bits.VDD_UVLO);
170 PRINT_ERR(data->glob.glob_err.reg_bits.THRMSHUTD);
171 PRINT_ERR(data->glob.glob_err.reg_bits.LOSSGND);
172 PRINT_ERR(data->glob.glob_err.reg_bits.WDOG_ERR);
173 }
174 if (data->glob.interrupt.reg_bits.COM_ERR) {
175 LOG_ERR("[DIAG] MAX14906 Communication Error");
176 }
177 }
178
179 ret = data->chan.doi_level.reg_raw | data->chan.ovr_ld.reg_raw |
180 data->chan.opn_wir.reg_raw | data->chan.sht_vdd.reg_raw;
181
182 return ret;
183 }
184
185 /**
186 * @brief Configure a channel's function.
187 * @param desc - device descriptor for the MAX14906
188 * @param ch - channel index (0 based).
189 * @param function - channel configuration (input, output or high-z).
190 * @return 0 in case of success, negative error code otherwise
191 */
max14906_ch_func(const struct device * dev,uint32_t ch,enum max14906_function function)192 static int max14906_ch_func(const struct device *dev, uint32_t ch, enum max14906_function function)
193 {
194 uint8_t setout_reg_val;
195
196 switch (function) {
197 case MAX14906_HIGH_Z:
198 setout_reg_val = MAX14906_IN;
199 max14906_reg_update(dev, MAX14906_CONFIG_DO_REG, MAX14906_DO_MASK(ch),
200 FIELD_PREP(MAX14906_DO_MASK(ch), MAX14906_PUSH_PULL));
201 break;
202 case MAX14906_IN:
203 setout_reg_val = MAX14906_IN;
204 max14906_reg_update(dev, MAX14906_CONFIG_DO_REG, MAX14906_DO_MASK(ch),
205 FIELD_PREP(MAX14906_DO_MASK(ch), MAX14906_HIGH_SIDE));
206 break;
207 case MAX14906_OUT:
208 setout_reg_val = MAX14906_OUT;
209 break;
210 default:
211 return -EINVAL;
212 }
213
214 return max14906_reg_update(dev, MAX14906_SETOUT_REG, MAX14906_CH_DIR_MASK(ch),
215 FIELD_PREP(MAX14906_CH_DIR_MASK(ch), setout_reg_val));
216 }
217
gpio_max14906_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)218 static int gpio_max14906_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
219 {
220 int ret;
221 uint32_t reg_val = 0;
222
223 ret = MAX14906_REG_READ(dev, MAX14906_SETOUT_REG);
224 reg_val = ret | (pins & 0x0f);
225
226 return MAX14906_REG_WRITE(dev, MAX14906_SETOUT_REG, reg_val);
227 }
228
gpio_max14906_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)229 static int gpio_max14906_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
230 {
231 int ret;
232 uint32_t reg_val = 0;
233
234 ret = MAX14906_REG_READ(dev, MAX14906_SETOUT_REG);
235 reg_val = ret & (0xf0 & ~pins);
236
237 return MAX14906_REG_WRITE(dev, MAX14906_SETOUT_REG, reg_val);
238 }
239
gpio_max14906_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)240 static int gpio_max14906_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
241 {
242 int err = 0;
243
244 if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
245 return -ENOTSUP;
246 }
247
248 if ((flags & GPIO_SINGLE_ENDED) != 0) {
249 return -ENOTSUP;
250 }
251
252 if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
253 return -ENOTSUP;
254 }
255
256 if (flags & GPIO_INT_ENABLE) {
257 return -ENOTSUP;
258 }
259
260 switch (flags & GPIO_DIR_MASK) {
261 case GPIO_INPUT:
262 max14906_ch_func(dev, (uint32_t)pin, MAX14906_IN);
263 LOG_DBG("SETUP AS INPUT %d", pin);
264 break;
265 case GPIO_OUTPUT:
266 max14906_ch_func(dev, (uint32_t)pin, MAX14906_OUT);
267 LOG_DBG("SETUP AS OUTPUT %d", pin);
268 break;
269 default:
270 LOG_ERR("On MAX14906 only input option is available!");
271 err = -ENOTSUP;
272 break;
273 }
274
275 return err;
276 }
277
gpio_max14906_port_get_raw(const struct device * dev,gpio_port_value_t * value)278 static int gpio_max14906_port_get_raw(const struct device *dev, gpio_port_value_t *value)
279 {
280 /* We care only for first 4 bits of the reg.
281 * Next set of bits is for direction.
282 * NOTE : in case and only if pin is INPUT DOILEVEL reg bits 0-4 shows PIN state.
283 * In case PIN is OUTPUT same bits show VDDOKFault state.
284 */
285
286 *value = (0x0f & MAX14906_REG_READ(dev, MAX14906_DOILEVEL_REG));
287
288 return 0;
289 }
290
gpio_max14906_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)291 static int gpio_max14906_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
292 {
293 int ret;
294 uint32_t reg_val, direction, state, new_reg_val;
295
296 ret = MAX14906_REG_READ(dev, MAX14906_SETOUT_REG);
297
298 direction = ret & 0xf0;
299 state = ret & 0x0f;
300 reg_val = state ^ pins;
301 new_reg_val = direction | (0x0f & state);
302
303 return MAX14906_REG_WRITE(dev, MAX14906_SETOUT_REG, new_reg_val);
304 }
305
gpio_max14906_clean_on_power(const struct device * dev)306 static int gpio_max14906_clean_on_power(const struct device *dev)
307 {
308 int ret;
309
310 /* Clear the latched faults generated at power up */
311 ret = MAX14906_REG_READ(dev, MAX14906_OPN_WIR_FLT_REG);
312 if (ret < 0) {
313 LOG_ERR("Error reading MAX14906_OPN_WIR_FLT_REG");
314 goto err_clean_on_power_max14906;
315 }
316
317 ret = MAX14906_REG_READ(dev, MAX14906_OVR_LD_REG);
318 if (ret < 0) {
319 LOG_ERR("Error reading MAX14906_OVR_LD_REG");
320 goto err_clean_on_power_max14906;
321 }
322
323 ret = MAX14906_REG_READ(dev, MAX14906_SHT_VDD_FLT_REG);
324 if (ret < 0) {
325 LOG_ERR("Error reading MAX14906_SHD_VDD_FLT_REG");
326 goto err_clean_on_power_max14906;
327 }
328
329 ret = MAX14906_REG_READ(dev, MAX14906_GLOB_ERR_REG);
330 if (ret < 0) {
331 LOG_ERR("Error reading MAX14906_GLOBAL_FLT_REG");
332 goto err_clean_on_power_max14906;
333 }
334
335 err_clean_on_power_max14906:
336 return ret;
337 }
338
gpio_max14906_config_diag(const struct device * dev)339 static int gpio_max14906_config_diag(const struct device *dev)
340 {
341 const struct max14906_data *data = dev->data;
342 const struct max14906_config *config = dev->config;
343
344 /* Set Config1 and Config2 regs */
345 MAX14906_REG_WRITE(dev, MAX14906_CONFIG1_REG, config->config1.reg_raw);
346 MAX14906_REG_WRITE(dev, MAX14906_CONFIG2_REG, config->config2.reg_raw);
347
348 /* Configure per channel diagnostics */
349 MAX14906_REG_WRITE(dev, MAX14906_OPN_WR_EN_REG, data->chan_en.opn_wr_en.reg_raw);
350 MAX14906_REG_WRITE(dev, MAX14906_SHT_VDD_EN_REG, data->chan_en.sht_vdd_en.reg_raw);
351
352 return 0;
353 }
354
gpio_max14906_init(const struct device * dev)355 static int gpio_max14906_init(const struct device *dev)
356 {
357 const struct max14906_config *config = dev->config;
358 int err = 0;
359
360 LOG_DBG(" --- GPIO MAX14906 init IN ---");
361
362 if (!spi_is_ready_dt(&config->spi)) {
363 LOG_ERR("SPI bus is not ready\n");
364 return -ENODEV;
365 }
366
367 /* setup READY gpio - normal low */
368 if (!gpio_is_ready_dt(&config->ready_gpio)) {
369 LOG_ERR("READY GPIO device not ready");
370 return -ENODEV;
371 }
372
373 err = gpio_pin_configure_dt(&config->ready_gpio, GPIO_INPUT);
374 if (err < 0) {
375 LOG_ERR("Failed to configure reset GPIO");
376 return err;
377 }
378
379 /* setup FAULT gpio - normal high */
380 if (!gpio_is_ready_dt(&config->fault_gpio)) {
381 LOG_ERR("FAULT GPIO device not ready");
382 return -ENODEV;
383 }
384
385 err = gpio_pin_configure_dt(&config->fault_gpio, GPIO_INPUT);
386 if (err < 0) {
387 LOG_ERR("Failed to configure DC GPIO");
388 return err;
389 }
390
391 /* setup LATCH gpio - normal high */
392 if (!gpio_is_ready_dt(&config->sync_gpio)) {
393 LOG_ERR("SYNC GPIO device not ready");
394 return -ENODEV;
395 }
396
397 err = gpio_pin_configure_dt(&config->sync_gpio, GPIO_OUTPUT_INACTIVE);
398 if (err < 0) {
399 LOG_ERR("Failed to configure busy GPIO");
400 return err;
401 }
402
403 /* setup LATCH gpio - normal high */
404 if (!gpio_is_ready_dt(&config->en_gpio)) {
405 LOG_ERR("SYNC GPIO device not ready");
406 return -ENODEV;
407 }
408
409 err = gpio_pin_configure_dt(&config->en_gpio, GPIO_OUTPUT_INACTIVE);
410 if (err < 0) {
411 LOG_ERR("Failed to configure busy GPIO");
412 return err;
413 }
414
415 gpio_pin_set_dt(&config->en_gpio, 1);
416 gpio_pin_set_dt(&config->sync_gpio, 1);
417
418 LOG_DBG("[GPIO] FAULT - %d\n", gpio_pin_get_dt(&config->fault_gpio));
419 LOG_DBG("[GPIO] READY - %d\n", gpio_pin_get_dt(&config->ready_gpio));
420 LOG_DBG("[GPIO] SYNC - %d\n", gpio_pin_get_dt(&config->sync_gpio));
421 LOG_DBG("[GPIO] EN - %d\n", gpio_pin_get_dt(&config->en_gpio));
422
423 int ret = gpio_max14906_clean_on_power(dev);
424
425 MAX14906_REG_WRITE(dev, MAX14906_SETOUT_REG, 0);
426
427 gpio_max14906_config_diag(dev);
428
429 LOG_DBG(" --- GPIO MAX14906 init OUT ---");
430
431 return ret;
432 }
433
434 static DEVICE_API(gpio, gpio_max14906_api) = {
435 .pin_configure = gpio_max14906_config,
436 .port_get_raw = gpio_max14906_port_get_raw,
437 .port_set_bits_raw = gpio_max14906_port_set_bits_raw,
438 .port_clear_bits_raw = gpio_max14906_port_clear_bits_raw,
439 .port_toggle_bits = gpio_max14906_port_toggle_bits,
440 };
441
442 #define GPIO_MAX14906_DEVICE(id) \
443 static const struct max14906_config max14906_##id##_cfg = { \
444 .spi = SPI_DT_SPEC_INST_GET(id, SPI_OP_MODE_MASTER | SPI_WORD_SET(8U), 0U), \
445 .ready_gpio = GPIO_DT_SPEC_INST_GET(id, drdy_gpios), \
446 .fault_gpio = GPIO_DT_SPEC_INST_GET(id, fault_gpios), \
447 .sync_gpio = GPIO_DT_SPEC_INST_GET(id, sync_gpios), \
448 .en_gpio = GPIO_DT_SPEC_INST_GET(id, en_gpios), \
449 .crc_en = DT_INST_PROP(id, crc_en), \
450 .config1.reg_bits.FLED_SET = DT_INST_PROP(id, fled_set), \
451 .config1.reg_bits.SLED_SET = DT_INST_PROP(id, sled_set), \
452 .config1.reg_bits.FLED_STRETCH = DT_INST_PROP(id, fled_stretch), \
453 .config1.reg_bits.FFILTER_EN = DT_INST_PROP(id, ffilter_en), \
454 .config1.reg_bits.FILTER_LONG = DT_INST_PROP(id, filter_long), \
455 .config1.reg_bits.FLATCH_EN = DT_INST_PROP(id, flatch_en), \
456 .config1.reg_bits.LED_CURR_LIM = DT_INST_PROP(id, led_cur_lim), \
457 .config2.reg_bits.VDD_ON_THR = DT_INST_PROP(id, vdd_on_thr), \
458 .config2.reg_bits.SYNCH_WD_EN = DT_INST_PROP(id, synch_wd_en), \
459 .config2.reg_bits.SHT_VDD_THR = DT_INST_PROP(id, sht_vdd_thr), \
460 .config2.reg_bits.OW_OFF_CS = DT_INST_PROP(id, ow_off_cs), \
461 .config2.reg_bits.WD_TO = DT_INST_PROP(id, wd_to), \
462 .pkt_size = (DT_INST_PROP(id, crc_en) & 0x1) ? 3 : 2, \
463 .spi_addr = DT_INST_PROP(id, spi_addr), \
464 }; \
465 \
466 static struct max14906_data max14906_##id##_data = { \
467 .chan_en.opn_wr_en.reg_bits = \
468 { \
469 .OW_OFF_EN1 = DT_INST_PROP_BY_IDX(id, ow_en, 0), \
470 .OW_OFF_EN2 = DT_INST_PROP_BY_IDX(id, ow_en, 1), \
471 .OW_OFF_EN3 = DT_INST_PROP_BY_IDX(id, ow_en, 2), \
472 .OW_OFF_EN4 = DT_INST_PROP_BY_IDX(id, ow_en, 3), \
473 .GDRV_EN1 = DT_INST_PROP_BY_IDX(id, gdrv_en, 0), \
474 .GDRV_EN1 = DT_INST_PROP_BY_IDX(id, gdrv_en, 1), \
475 .GDRV_EN2 = DT_INST_PROP_BY_IDX(id, gdrv_en, 2), \
476 .GDRV_EN3 = DT_INST_PROP_BY_IDX(id, gdrv_en, 3), \
477 }, \
478 .chan_en.sht_vdd_en.reg_bits = \
479 { \
480 .VDD_OV_EN1 = DT_INST_PROP_BY_IDX(id, vdd_ov_en, 0), \
481 .VDD_OV_EN2 = DT_INST_PROP_BY_IDX(id, vdd_ov_en, 1), \
482 .VDD_OV_EN3 = DT_INST_PROP_BY_IDX(id, vdd_ov_en, 2), \
483 .VDD_OV_EN4 = DT_INST_PROP_BY_IDX(id, vdd_ov_en, 3), \
484 .SH_VDD_EN1 = DT_INST_PROP_BY_IDX(id, sh_vdd_en, 0), \
485 .SH_VDD_EN2 = DT_INST_PROP_BY_IDX(id, sh_vdd_en, 1), \
486 .SH_VDD_EN3 = DT_INST_PROP_BY_IDX(id, sh_vdd_en, 2), \
487 .SH_VDD_EN4 = DT_INST_PROP_BY_IDX(id, sh_vdd_en, 3), \
488 }, \
489 }; \
490 \
491 DEVICE_DT_INST_DEFINE(id, &gpio_max14906_init, NULL, &max14906_##id##_data, \
492 &max14906_##id##_cfg, POST_KERNEL, \
493 CONFIG_GPIO_MAX14906_INIT_PRIORITY, &gpio_max14906_api);
494
495 DT_INST_FOREACH_STATUS_OKAY(GPIO_MAX14906_DEVICE)
496
