1# Copyright (c) 2024 Analog Devices Inc. 2# Copyright (c) 2024 BayLibre SAS 3# SPDX-License-Identifier: Apache-2.0 4 5description: ADI MAX14906 quad industrial Input/Output with advanced diagnostics 6 7compatible: "adi,max14906-gpio" 8 9properties: 10 "#gpio-cells": 11 const: 2 12 ngpios: 13 type: int 14 required: true 15 const: 4 16 description: Number of gpios supported 17 drdy-gpios: 18 description: | 19 High-Side Open-Drain Output. READY is passive low when the internal 20 logic supply is higher than the UVLO threshold, indicating that the 21 registers have adequate supply voltage. 22 type: phandle-array 23 fault-gpios: 24 description: | 25 Fault pin indicates when there is Fault state in either FAULT1 or FAULT2 26 bothe of which are cleaned on read once problem is not persistent. 27 type: phandle-array 28 sync-gpios: 29 description: | 30 Latch the data so it could be read (partially duplicate CS). 31 type: phandle-array 32 en-gpios: 33 description: | 34 DOI Enable Pin. Drive the EN pin high to enable the DOI_ outputs. 35 Drive EN low to disable/three-state all DOI_ outputs. 36 type: phandle-array 37 crc-en: 38 description: | 39 Notify driver if crc pin is enabled. 40 type: boolean 41 spi-addr: 42 type: int 43 default: 0 44 required: true 45 enum: 46 - 0 47 - 1 48 - 2 49 - 3 50 description: | 51 On MAX14906PMB module default address is 0 (A0-LOW, A1-LOW) 52 Selectable device address, configurable from A0 and A1 53 ow-en: 54 type: array 55 default: [0, 0, 0, 0] 56 description: | 57 Default values are from documentation. 58 Enable or disable open-wire functionality per channel. 59 - 0 mean disable 60 - 1 mean enable 61 channels indentation start from CH0...CH3 62 vdd-ov-en: 63 type: array 64 default: [0, 0, 0, 0] 65 description: | 66 Default values are from documentation. 67 VDDOVEN 68 Enable or disable open-wire functionality per channel. 69 - 0 mean disable 70 - 1 mean enable 71 channels indentation start from CH0...CH3 72 gdrv-en: 73 type: array 74 default: [0, 0, 0, 0] 75 description: | 76 Default values are from documentation. 77 GDrvEn - Gate drive enabl disable for power eff 78 Enable or disable open-wire functionality per channel. 79 - 0 mean disable 80 - 1 mean enable 81 channels indentation start from CH0...CH3 82 sh-vdd-en: 83 type: array 84 default: [0, 0, 0, 0] 85 description: | 86 Default values are from documentation. 87 ShVddEN - Short to VDD enable 88 Enable or disable short to VDD functionality per channel. 89 - 0 mean disable 90 - 1 mean enable 91 channels indentation start from CH0...CH3 92 fled-set: 93 type: boolean 94 description: | 95 Internal fault diagnostics include (if enabled): SafeDemagF_, SHVDD_, 96 VDDOV_, OWOff_, AboveVDD_, CL_, OVL_, VDDOKFault_. 97 sled-set: 98 type: boolean 99 description: | 100 Enable status LEDs 101 fled-stretch: 102 type: int 103 default: 0 104 enum: 105 - 0 106 - 1 107 - 2 108 - 3 109 description: | 110 Default values are from documentation. 111 Set minimum on time for FLEDs in case of fault 112 0 - Disable minimum fault LED (FLED) on-time 113 1 - Minimum fault LED (FLED) on-time = 1s (typ) 114 2 - Minimum fault LED (FLED) on-time = 2s (typ) 115 3 - Minimum fault LED (FLED) on-time = 3s (typ) 116 ffilter-en: 117 type: boolean 118 description: | 119 When the fault LEDs (FLEDs) are controlled internally (FLEDSet = 0), open- 120 wire and short-to-V DD diagnostics always use filtering and cannot be disabled 121 by the FFilterEn bit. 122 filter-long: 123 type: boolean 124 description: | 125 false: To select regular blanking time (4ms, typ) for diagnostic fault bits, OWOff_ 126 and SHVDD_ 127 true: To select long blanking time (8ms, typ) for diagnostic fault bits, OWOff_ 128 and SHVDD_ 129 flatch-en: 130 type: boolean 131 description: | 132 false: Disable latching of diagnostic fault bits in the OvrLdChF, OpnWirChF, and 133 ShtVDDChF registers 134 true: Enable latching of diagnostic fault bits in the OvrLdChF, OpnWirChF, and 135 ShtVDDChF registers 136 led-cur-lim: 137 type: boolean 138 description: | 139 false: Disable fault LEDs (FLEDs) signaling current limit 140 true: Enable fault LEDs (FLEDs) signaling current limit 141 vdd-on-thr: 142 type: boolean 143 description: | 144 Enable higher voltage thresholds for VDD and VDD_ undervoltage monitoring 145 synch-wd-en: 146 type: boolean 147 description: | 148 The SYNCH watchdog timeout is defined by the WDTo[1:0] bits if the SPI 149 watchdog is enabled. When WDTo[1:0] = 00 (SPI watchdog disabled), the 150 SYNCH watchdog timeout is 600ms (typ) if enabled. 151 sht-vdd-thr: 152 type: int 153 default: 0 154 enum: 155 - 0 156 - 1 157 - 2 158 - 3 159 description: | 160 Default values are from documentation. 161 Set threshold voltage for short-to-V DD detection 162 0: Set threshold voltage for short-to-VDD detection to 9V (typ) 163 1: Set threshold voltage for short-to-VDD detection to 10V (typ) 164 2: Set threshold voltage for short-to-VDD detection to 12V (typ) 165 3: Set threshold voltage for short-to-VDD detection to 14V (typ) 166 ow-off-cs: 167 type: int 168 default: 0 169 enum: 170 - 0 171 - 1 172 - 2 173 - 3 174 description: | 175 Default values are from documentation. 176 Set the pullup current for open-wire and short-to-VDD detection 177 0: Set open-wire and short-to-VDD detection current to 60μA (typ) 178 1: Set open-wire and short-to-VDD detection current to 100μA (typ) 179 2: Set open-wire and short-to-VDD detection current to 300μA (typ) 180 3: Set open-wire and short-to-VDD detection current to 600μA (typ) 181 wd-to: 182 type: int 183 default: 0 184 enum: 185 - 0 186 - 1 187 - 2 188 - 3 189 description: | 190 Default values are from documentation. 191 SPI Watchdog Status, set SPI and SYNCH Watchdog Timeout 192 0: Disable SPI Watchdog Status and SPI Watchdog Timeout 193 1: Enable SPI Watchdog Status, set SPI and SYNCH Watchdog Timeout to 200ms (typ) 194 2: Enable SPI Watchdog Status, set SPI and SYNCH Watchdog Timeout to 600ms (typ) 195 3: Enable SPI Watchdog Status, set SPI and SYNCH Watchdog Timeout to 1.2s (typ) 196 197gpio-cells: 198 - pin 199 - flags 200 201include: [gpio-controller.yaml, spi-device.yaml] 202