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/hal_stm32-3.6.0/.github/workflows/
Dtest.yml7 runs-on: ubuntu-latest
9 fail-fast: false
11 python-version: ['3.7', '3.8', '3.9', '3.10']
13 - uses: actions/checkout@v1
14 - name: Set up Python
15 uses: actions/setup-python@v1
17 python-version: ${{ matrix.python-version }}
18 - name: install dependencies
20 pip3 install -r scripts/requirements.txt
21 pip3 install -r scripts/requirements-test.txt
[all …]
/hal_stm32-3.6.0/stm32cube/stm32h5xx/soc/
Dstm32h573xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
[all …]
Dstm32h563xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
[all …]
Dstm32h562xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
[all …]
Dstm32h503xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
[all …]
/hal_stm32-3.6.0/stm32cube/stm32h7xx/soc/
Dstm32h742xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
50 /****** Cortex-M Processor Exceptions Numbers ****************************************************…
51 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
52 …HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt …
53 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
54 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
55 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
[all …]
Dstm32h755xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
50 /****** Cortex-M Processor Exceptions Numbers ****************************************************…
51 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
52 …HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt …
53 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
54 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
55 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
[all …]
Dstm32h745xg.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
50 /****** Cortex-M Processor Exceptions Numbers ****************************************************…
51 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
52 …HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt …
53 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
54 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
55 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
[all …]
Dstm32h745xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
50 /****** Cortex-M Processor Exceptions Numbers ****************************************************…
51 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
52 …HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt …
53 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
54 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
55 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
[all …]
Dstm32h753xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
50 /****** Cortex-M Processor Exceptions Numbers ****************************************************…
51 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
52 …HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt …
53 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
54 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
55 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
[all …]
Dstm32h750xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
50 /****** Cortex-M Processor Exceptions Numbers ****************************************************…
51 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
52 …HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt …
53 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
54 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
55 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
[all …]
Dstm32h743xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
50 /****** Cortex-M Processor Exceptions Numbers ****************************************************…
51 …NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt …
52 …HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt …
53 …MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt …
54 …BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt …
55 …UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt …
[all …]
/hal_stm32-3.6.0/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2020-2021 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
55 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************…
56 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
57 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
58 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
59 …BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt …
[all …]
Dstm32wle5xx.h10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2020-2021 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
55 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************…
56 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
57 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
58 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
59 …BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt …
[all …]
Dstm32wl54xx.h10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2020-2021 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
57 …/****** Cortex-M0 Processor Exceptions Numbers **************************************************…
58 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
59 …HardFault_IRQn = -13, /*!< Cortex-M0+ Hard Fault Interrupt …
60 …SVCall_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt …
61 …PendSV_IRQn = -2, /*!< Cortex-M0+ Pend SV Interrupt …
[all …]
Dstm32wl55xx.h10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2020-2021 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
57 …/****** Cortex-M0 Processor Exceptions Numbers **************************************************…
58 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
59 …HardFault_IRQn = -13, /*!< Cortex-M0+ Hard Fault Interrupt …
60 …SVCall_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt …
61 …PendSV_IRQn = -2, /*!< Cortex-M0+ Pend SV Interrupt …
[all …]
Dstm32wl5mxx.h10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2020-2021 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
57 …/****** Cortex-M0 Processor Exceptions Numbers **************************************************…
58 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
59 …HardFault_IRQn = -13, /*!< Cortex-M0+ Hard Fault Interrupt …
60 …SVCall_IRQn = -5, /*!< Cortex-M0+ SV Call Interrupt …
61 …PendSV_IRQn = -2, /*!< Cortex-M0+ Pend SV Interrupt …
[all …]
/hal_stm32-3.6.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
[all …]
Dstm32u585xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
[all …]
Dstm32u595xx.h8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
[all …]
/hal_stm32-3.6.0/stm32cube/stm32wbxx/soc/
Dstm32wb30xx.h10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2019-2022 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
69 …/****** Cortex-M4 Processor Exceptions Numbers **************************************************…
70 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
71 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
72 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
[all …]
Dstm32wb50xx.h10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2019-2022 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
69 …/****** Cortex-M4 Processor Exceptions Numbers **************************************************…
70 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
71 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
72 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
[all …]
Dstm32wb1mxx.h10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2019-2022 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
69 …/****** Cortex-M4 Processor Exceptions Numbers **************************************************…
70 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
71 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
72 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
[all …]
/hal_stm32-3.6.0/stm32cube/stm32wbxx/soc/Include/
Dstm32wb15xx.h10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2019-2022 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
69 …/****** Cortex-M4 Processor Exceptions Numbers **************************************************…
70 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
71 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
72 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
[all …]
Dstm32wb10xx.h10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2019-2022 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
69 …/****** Cortex-M4 Processor Exceptions Numbers **************************************************…
70 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
71 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
72 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
[all …]

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