Lines Matching +full:fail +full:- +full:fast
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
17 * Copyright (c) 2019-2022 STMicroelectronics.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
69 …/****** Cortex-M4 Processor Exceptions Numbers **************************************************…
70 …NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt …
71 …HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt …
72 …MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt …
73 …BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt …
74 …UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt …
75 …SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt …
76 …DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt …
77 …PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt …
78 …SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt …
132 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
165 … uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
170 … uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
175 … uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
213 …uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 …
286 …ED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */
290 …ED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */
303 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
308 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
313 * @brief Inter-integrated Circuit Interface
370 …__IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset:…
371 …__IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset:…
372 …__IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset:…
373 …__IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset:…
374 …__IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset:…
375 …__IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset:…
376 …t RESERVED2[2]; /*!< Reserved, Address offset: 0x38-0x3C */
377 …__IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset:…
378 …__IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset:…
379 …t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */
380 …__IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset:…
381 …__IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset:…
382 …t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */
397 … Address offset: 0x10-0x14 */
432 … Address offset: 0xA0-0x104 */
434 … Address offset: 0x10C-0x144 */
456 * @brief Real-Time Clock
474 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address …
526 …SCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
532 …served, Address offset: 0x2C-0xFC */
533 …__IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status regis…
534 …__IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status regis…
535 …__IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis…
536 …__IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status regis…
557 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
563 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
647 * @brief Inter-Processor Communication
651 …__IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, …
652 …__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, …
653 …__IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, …
654 …__IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status reg…
655 …__IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, …
656 …__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, …
657 …__IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, …
658 …__IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status regi…
678 …4]; /*!< Reserved, Address offset: 0x10 - 0x1C */
683 …4]; /*!< Reserved, Address offset: 0x30 - 0x3C */
684 …8]; /*!< Reserved, Address offset: 0x40 - 0x5C */
685 …8]; /*!< Reserved, Address offset: 0x60 - 0x7C */
688 …2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
691 …10]; /*!< Reserved, Address offset: 0x98 - 0xBC */
694 …2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
707 …uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03F…
708 …__IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F…
716 …__IO uint32_t R[32]; /*!< HSEM 2-step write lock and read back registers, Address offset: 0…
717 …__IO uint32_t RLR[32]; /*!< HSEM 1-step read lock registers, Address offset: 8…
726 …32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/
755 #define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) …
756 #define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) …
757 #define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) …
758 #define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) …
771 #define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 - 0x200…
772 #define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x200…
773 #define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x200…
775 #define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) …
776 #define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) …
777 #define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) …
778 #define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) …
865 #define UID64_BASE ((uint32_t)0x1FFF7580UL) /*!< 64-bit Unique device Identificati…
1911 … ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
1935 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2029 … CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data regist…
3403 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3404 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3407 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Mont…
3410 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
3411 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3412 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input stora…
3413 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base …
3414 #define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
3415 #define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3418 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output stor…
3419 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
3420 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
3421 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base…
3422 #define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM a…
3425 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input expon…
3426 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3427 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3428 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3429 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3430 #define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input stora…
3431 #define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' o…
3432 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3433 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3436 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3437 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3438 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last…
3439 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last…
3440 #define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last…
3441 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output chec…
3442 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output chec…
3443 #define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output chec…
3446 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3447 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3448 #define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3449 #define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3450 #define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3451 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3452 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3455 #define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output erro…
3458 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order…
3459 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3460 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3461 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3462 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3463 #define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k val…
3464 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3465 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3466 #define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, ha…
3467 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, pr…
3468 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, or…
3471 #define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output erro…
3472 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output sign…
3473 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output sign…
3474 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output fina…
3475 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output fina…
3478 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order…
3479 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3480 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign …
3481 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC c…
3482 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3483 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3484 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initi…
3485 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input publi…
3486 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input publi…
3487 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, pa…
3488 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, pa…
3489 #define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, ha…
3490 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, or…
3493 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3496 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3497 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CR…
3498 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CR…
3499 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv …
3500 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime…
3501 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime…
3502 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base …
3505 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3508 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3509 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3510 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3511 #define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3514 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3517 #define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3518 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3519 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3522 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3525 #define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3526 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3527 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3530 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3533 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3534 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3535 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3538 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3541 #define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3542 #define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3543 #define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3546 #define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3549 #define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3550 #define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3551 #define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3552 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3555 #define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3558 #define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3559 #define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3560 #define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3563 #define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3566 #define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3567 #define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3568 #define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3569 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3572 #define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3575 #define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3576 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3577 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3578 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modul…
3581 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3584 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3585 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3586 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3587 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input opera…
3590 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output resu…
3655 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programmin…
3658 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programmin…
3699 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programmin…
3722 …CC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail …
3725 … FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail …
3867 #define FLASH_SRRVR_SNBRSA FLASH_SRRVR_SNBRSA_Msk /* Secure non-backu…
3870 #define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2…
3913 #define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast progra…
3916 #define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast progra…
3948 #define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast progra…
5506 /* Inter-integrated Circuit Interface (I2C) */
5583 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressi…
5586 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address …
5615 …AR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
5777 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive d…
5782 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit …
5853 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-P…
5877 … PWR_CR3_EWUP_Msk /*!< Enable all external Wake-Up lines */
5891 … PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configurat…
5908 #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Internal Wake-U…
5913 #define PWR_CR4_WP PWR_CR4_WP_Msk /*!< Wake-Up polarit…
5916 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 […
5919 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 […
5975 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power regul…
5978 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power regul…
5994 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up F…
5997 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up P…
6000 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up P…
6030 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Pin PA0 Pull-Up…
6033 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Pin PA1 Pull-Up…
6036 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Pin PA2 Pull-Up…
6039 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Pin PA3 Pull-Up…
6042 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Pin PA4 Pull-Up…
6045 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Pin PA5 Pull-Up…
6048 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Pin PA6 Pull-Up…
6051 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Pin PA7 Pull-Up…
6054 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Pin PA8 Pull-Up…
6057 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Pin PA9 Pull-Up…
6060 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Pin PA10 Pull-U…
6063 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Pin PA11 Pull-U…
6066 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Pin PA12 Pull-U…
6069 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Pin PA13 Pull-U…
6072 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Pin PA15 Pull-U…
6077 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Pin PA0 Pull-Do…
6080 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Pin PA1 Pull-Do…
6083 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Pin PA2 Pull-Do…
6086 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Pin PA3 Pull-Do…
6089 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Pin PA4 Pull-Do…
6092 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Pin PA5 Pull-Do…
6095 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Pin PA6 Pull-Do…
6098 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Pin PA7 Pull-Do…
6101 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Pin PA8 Pull-Do…
6104 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Pin PA9 Pull-Do…
6107 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Pin PA10 Pull-D…
6110 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Pin PA11 Pull-D…
6113 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Pin PA12 Pull-D…
6116 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Pin PA14 Pull-D…
6121 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Pin PB0 Pull-Up…
6124 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Pin PB1 Pull-Up…
6127 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Pin PB2 Pull-Up…
6130 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Pin PB3 Pull-Up…
6133 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Pin PB4 Pull-Up…
6136 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Pin PB5 Pull-Up…
6139 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Pin PB6 Pull-Up…
6142 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Pin PB7 Pull-Up…
6145 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Pin PB8 Pull-Up…
6148 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Pin PB9 Pull-Up…
6153 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Pin PB0 Pull-Do…
6156 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Pin PB1 Pull-Do…
6159 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Pin PB2 Pull-Do…
6162 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Pin PB3 Pull-Do…
6165 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Pin PB5 Pull-Do…
6168 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Pin PB6 Pull-Do…
6171 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Pin PB7 Pull-Do…
6174 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Pin PB8 Pull-Do…
6177 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Pin PB9 Pull-Do…
6182 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Pin PC14 Pull-U…
6185 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Pin PC15 Pull-U…
6190 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Pin PC14 Pull-D…
6193 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Pin PC15 Pull-D…
6198 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Pin PE4 Pull-Up…
6203 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Pin PE4 Pull-Do…
6208 #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Pin PH3 Pull-Up…
6213 #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Pin PH3 Pull-Do…
6242 … PWR_C2CR3_EWUP_Msk /*!< Enable all external Wake-Up lines for CPU2 */
6259 … PWR_C2CR3_APC_Msk /*!< Apply pull-up and pull-down configurat…
6263 #define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-U…
7384 /* Real-Time Clock (RTC) */
7512 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Time-stamp inte…
7614 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-rel…
7858 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< Use a 8-second …
7861 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< Use a 16-second…
7887 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< RTC_TAMPx pull-…
7920 … RTC_ALRMASSR_MASKSS_Msk /*!< Alarm A mask the most-significant bits star…
7932 … RTC_ALRMBSSR_MASKSS_Msk /*!< Alarm B mask the most-significant bits star…
8223 …6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8226 …7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8229 …8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8232 …9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< Fast-mode Plus (Fm+) dri…
8235 … SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast-mode Plus (Fm+) dri…
8469 …GE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */
8472 …GE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */
8475 …GE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */
8478 …GE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */
8481 …GE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */
8484 …GE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */
8487 …GE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */
8490 …GE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */
8493 …GE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */
8496 …GE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */
8499 …GE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */
8502 …GE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */
8505 …GE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */
8508 …GE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */
8511 …GE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */
8514 …GE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */
8517 …GE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */
8520 …GE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */
8523 …GE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */
8526 …GE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */
8529 …GE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */
8532 …GE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */
8535 …GE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */
8538 …GE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */
8541 …GE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */
8544 …GE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */
8547 …GE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */
8550 …GE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */
8553 …GE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */
8556 …GE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */
8559 …GE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */
8562 …GE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */
8572 …GE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */
8575 …GE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */
8578 …GE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */
8581 …GE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */
8584 …GE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */
8587 …GE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */
8590 …GE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */
8593 …GE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */
8596 …GE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */
8599 …GE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */
8602 …GE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */
8605 …GE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */
8608 …GE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */
8611 …GE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */
8614 …GE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */
8617 …GE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */
8620 …GE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */
8623 …GE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */
8626 …GE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */
8629 …GE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */
8632 …GE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */
8635 …GE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */
8638 …GE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */
8641 …GE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */
8644 …GE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */
8647 …GE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */
8650 …GE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */
8653 …GE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */
8656 …GE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */
8659 …GE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */
8662 …GE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */
8665 …GE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */
8667 …r SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) ************…
8711 …r SYSCFG_IMR2 register (Interrupt masks control and status register on CPU1 - part 2) ************…
8719 …SYSCFG_C2IMR1 register (Interrupt masks control and status register on CPU2 - part 1) ************…
8794 …SYSCFG_C2IMR2 register (Interrupt masks control and status register on CPU2 - part 2) ************…
8861 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
8867 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload prel…
9120 …R1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
9145 …R1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
9162 /*----------------------------------------------------------------------------*/
9200 …R2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
9225 …R2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
9242 /*----------------------------------------------------------------------------*/
9274 …R3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
9293 …R3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
9385 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-relo…
9434 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
9452 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Select…
9455 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Select…
9485 …BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
9488 …DTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
9768 /* Inter-Processor Communication Controller (IPCC) */
10143 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - …
10152 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
10177 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - …
10198 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit…
10242 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate…
10245 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
10250 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-…
10264 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power…
10267 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Se…
10306 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
10362 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate…
10427 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate…
10430 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate…
10542 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-B…
10558 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-b…
10703 /*********************** UART Instances : Half-Duplex mode ********************/
10709 /*********************** UART Instances : Wake-up from Stop mode **************/
10950 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/