1 /**
2   ******************************************************************************
3   * @file    stm32h503xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32H503xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral’s registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2023 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 #ifndef STM32H503xx_H
26 #define STM32H503xx_H
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 /** @addtogroup ST
33   * @{
34   */
35 
36 
37 /** @addtogroup STM32H503xx
38   * @{
39   */
40 
41 
42 /** @addtogroup Configuration_of_CMSIS
43   * @{
44   */
45 
46 
47 /* =========================================================================================================================== */
48 /* ================                                Interrupt Number Definition                                ================ */
49 /* =========================================================================================================================== */
50 
51 typedef enum
52 {
53 /* =======================================  ARM Cortex-M33 Specific Interrupt Numbers  ======================================= */
54   Reset_IRQn                = -15,    /*!< -15 Reset Vector, invoked on Power up and warm reset              */
55   NonMaskableInt_IRQn       = -14,    /*!< -14 Non maskable Interrupt, cannot be stopped or preempted        */
56   HardFault_IRQn            = -13,    /*!< -13 Hard Fault, all classes of Fault                              */
57   MemoryManagement_IRQn     = -12,    /*!< -12 Memory Management, MPU mismatch, including Access Violation
58                                                and No Match                                                  */
59   BusFault_IRQn             = -11,    /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
60                                                related Fault                                                 */
61   UsageFault_IRQn           = -10,    /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
62   SVCall_IRQn               =  -5,    /*!< -5  System Service Call via SVC instruction                       */
63   DebugMonitor_IRQn         =  -4,    /*!< -4  Debug Monitor                                                 */
64   PendSV_IRQn               =  -2,    /*!< -2  Pendable request for system service                           */
65   SysTick_IRQn              =  -1,    /*!< -1  System Tick Timer                                             */
66 
67 /* ===========================================  STM32H503xx Specific Interrupt Numbers  ====================================== */
68   WWDG_IRQn                 = 0,      /*!< Window WatchDog interrupt                                         */
69   PVD_AVD_IRQn              = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */
70   RTC_IRQn                  = 2,      /*!< RTC non-secure interrupt                                          */
71   TAMP_IRQn                 = 4,      /*!< Tamper global interrupt                                           */
72   RAMCFG_IRQn               = 5,      /*!< RAMCFG global interrupt                                           */
73   FLASH_IRQn                = 6,      /*!< FLASH non-secure global interrupt                                 */
74   RCC_IRQn                  = 9,      /*!< RCC non secure global interrupt                                   */
75   EXTI0_IRQn                = 11,     /*!< EXTI Line0 interrupt                                              */
76   EXTI1_IRQn                = 12,     /*!< EXTI Line1 interrupt                                              */
77   EXTI2_IRQn                = 13,     /*!< EXTI Line2 interrupt                                              */
78   EXTI3_IRQn                = 14,     /*!< EXTI Line3 interrupt                                              */
79   EXTI4_IRQn                = 15,     /*!< EXTI Line4 interrupt                                              */
80   EXTI5_IRQn                = 16,     /*!< EXTI Line5 interrupt                                              */
81   EXTI6_IRQn                = 17,     /*!< EXTI Line6 interrupt                                              */
82   EXTI7_IRQn                = 18,     /*!< EXTI Line7 interrupt                                              */
83   EXTI8_IRQn                = 19,     /*!< EXTI Line8 interrupt                                              */
84   EXTI9_IRQn                = 20,     /*!< EXTI Line9 interrupt                                              */
85   EXTI10_IRQn               = 21,     /*!< EXTI Line10 interrupt                                             */
86   EXTI11_IRQn               = 22,     /*!< EXTI Line11 interrupt                                             */
87   EXTI12_IRQn               = 23,     /*!< EXTI Line12 interrupt                                             */
88   EXTI13_IRQn               = 24,     /*!< EXTI Line13 interrupt                                             */
89   EXTI14_IRQn               = 25,     /*!< EXTI Line14 interrupt                                             */
90   EXTI15_IRQn               = 26,     /*!< EXTI Line15 interrupt                                             */
91   GPDMA1_Channel0_IRQn      = 27,     /*!< GPDMA1 Channel 0 global interrupt                                 */
92   GPDMA1_Channel1_IRQn      = 28,     /*!< GPDMA1 Channel 1 global interrupt                                 */
93   GPDMA1_Channel2_IRQn      = 29,     /*!< GPDMA1 Channel 2 global interrupt                                 */
94   GPDMA1_Channel3_IRQn      = 30,     /*!< GPDMA1 Channel 3 global interrupt                                 */
95   GPDMA1_Channel4_IRQn      = 31,     /*!< GPDMA1 Channel 4 global interrupt                                 */
96   GPDMA1_Channel5_IRQn      = 32,     /*!< GPDMA1 Channel 5 global interrupt                                 */
97   GPDMA1_Channel6_IRQn      = 33,     /*!< GPDMA1 Channel 6 global interrupt                                 */
98   GPDMA1_Channel7_IRQn      = 34,     /*!< GPDMA1 Channel 7 global interrupt                                 */
99   IWDG_IRQn                 = 35,     /*!< IWDG global interrupt                                             */
100   ADC1_IRQn                 = 37,     /*!< ADC1 global interrupt                                             */
101   DAC1_IRQn                 = 38,     /*!< DAC1 global interrupt                                             */
102   FDCAN1_IT0_IRQn           = 39,     /*!< FDCAN1 interrupt 0                                                */
103   FDCAN1_IT1_IRQn           = 40,     /*!< FDCAN1 interrupt 1                                                */
104   TIM1_BRK_IRQn             = 41,     /*!< TIM1 Break interrupt                                              */
105   TIM1_UP_IRQn              = 42,     /*!< TIM1 Update interrupt                                             */
106   TIM1_TRG_COM_IRQn         = 43,     /*!< TIM1 Trigger and Commutation interrupt                            */
107   TIM1_CC_IRQn              = 44,     /*!< TIM1 Capture Compare interrupt                                    */
108   TIM2_IRQn                 = 45,     /*!< TIM2 global interrupt                                             */
109   TIM3_IRQn                 = 46,     /*!< TIM3 global interrupt                                             */
110   TIM6_IRQn                 = 49,     /*!< TIM6 global interrupt                                             */
111   TIM7_IRQn                 = 50,     /*!< TIM7 global interrupt                                             */
112   I2C1_EV_IRQn              = 51,     /*!< I2C1 Event interrupt                                              */
113   I2C1_ER_IRQn              = 52,     /*!< I2C1 Error interrupt                                              */
114   I2C2_EV_IRQn              = 53,     /*!< I2C2 Event interrupt                                              */
115   I2C2_ER_IRQn              = 54,     /*!< I2C2 Error interrupt                                              */
116   SPI1_IRQn                 = 55,     /*!< SPI1 global interrupt                                             */
117   SPI2_IRQn                 = 56,     /*!< SPI2 global interrupt                                             */
118   SPI3_IRQn                 = 57,     /*!< SPI3 global interrupt                                             */
119   USART1_IRQn               = 58,     /*!< USART1 global interrupt                                           */
120   USART2_IRQn               = 59,     /*!< USART2 global interrupt                                           */
121   USART3_IRQn               = 60,     /*!< USART3 global interrupt                                           */
122   LPUART1_IRQn              = 63,     /*!< LPUART1 global interrupt                                          */
123   LPTIM1_IRQn               = 64,     /*!< LPTIM1 global interrupt                                           */
124   LPTIM2_IRQn               = 70,     /*!< LPTIM2 global interrupt                                           */
125   USB_DRD_FS_IRQn           = 74,     /*!< USB FS global interrupt                                           */
126   CRS_IRQn                  = 75,     /*!< CRS global interrupt                                              */
127   GPDMA2_Channel0_IRQn      = 90,     /*!< GPDMA2 Channel 0 global interrupt                                 */
128   GPDMA2_Channel1_IRQn      = 91,     /*!< GPDMA2 Channel 1 global interrupt                                 */
129   GPDMA2_Channel2_IRQn      = 92,     /*!< GPDMA2 Channel 2 global interrupt                                 */
130   GPDMA2_Channel3_IRQn      = 93,     /*!< GPDMA2 Channel 3 global interrupt                                 */
131   GPDMA2_Channel4_IRQn      = 94,     /*!< GPDMA2 Channel 4 global interrupt                                 */
132   GPDMA2_Channel5_IRQn      = 95,     /*!< GPDMA2 Channel 5 global interrupt                                 */
133   GPDMA2_Channel6_IRQn      = 96,     /*!< GPDMA2 Channel 6 global interrupt                                 */
134   GPDMA2_Channel7_IRQn      = 97,     /*!< GPDMA2 Channel 7 global interrupt                                 */
135   FPU_IRQn                  = 103,    /*!< FPU global interrupt                                              */
136   ICACHE_IRQn               = 104,    /*!< Instruction cache global interrupt                                */
137   DTS_IRQn                  = 113,    /*!< DTS global interrupt                                              */
138   RNG_IRQn                  = 114,    /*!< RNG global interrupt                                              */
139   HASH_IRQn                 = 117,    /*!< HASH global interrupt                                             */
140   I3C1_EV_IRQn              = 123,    /*!< I3C1 event interrupt                                              */
141   I3C1_ER_IRQn              = 124,    /*!< I3C1 error interrupt                                              */
142   I3C2_EV_IRQn              = 131,    /*!< I3C2 Event interrupt                                              */
143   I3C2_ER_IRQn              = 132,    /*!< I3C2 Error interrupt                                              */
144   COMP1_IRQn                = 133,    /*!< COMP global interrupt                                             */
145 } IRQn_Type;
146 
147 
148 
149 /* =========================================================================================================================== */
150 /* ================                           Processor and Core Peripheral Section                           ================ */
151 /* =========================================================================================================================== */
152 
153 /* -------  Start of section using anonymous unions and disabling warnings  ------- */
154 #if   defined (__CC_ARM)
155   #pragma push
156   #pragma anon_unions
157 #elif defined (__ICCARM__)
158   #pragma language=extended
159 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
160   #pragma clang diagnostic push
161   #pragma clang diagnostic ignored "-Wc11-extensions"
162   #pragma clang diagnostic ignored "-Wreserved-id-macro"
163 #elif defined (__GNUC__)
164   /* anonymous unions are enabled by default */
165 #elif defined (__TMS470__)
166   /* anonymous unions are enabled by default */
167 #elif defined (__TASKING__)
168   #pragma warning 586
169 #elif defined (__CSMC__)
170   /* anonymous unions are enabled by default */
171 #else
172   #warning Not supported compiler type
173 #endif
174 
175 
176 /* --------  Configuration of the Cortex-M33 Processor and Core Peripherals  ------ */
177 #define __CM33_REV                0x0000U   /* Core revision r0p1 */
178 #define __SAUREGION_PRESENT       1U        /* SAU regions present */
179 #define __MPU_PRESENT             1U        /* MPU present */
180 #define __VTOR_PRESENT            1U        /* VTOR present */
181 #define __NVIC_PRIO_BITS          4U        /* Number of Bits used for Priority Levels */
182 #define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
183 #define __FPU_PRESENT             1U        /* FPU present */
184 #define __DSP_PRESENT             1U        /* DSP extension present */
185 
186 /** @} */ /* End of group Configuration_of_CMSIS */
187 
188 
189 #include <core_cm33.h>                       /*!< ARM Cortex-M33 processor and core peripherals */
190 #include "system_stm32h5xx.h"                /*!< STM32H5xx System */
191 
192 
193 /* =========================================================================================================================== */
194 /* ================                            Device Specific Peripheral Section                             ================ */
195 /* =========================================================================================================================== */
196 
197 
198 /** @addtogroup STM32H5xx_peripherals
199   * @{
200   */
201 
202 /**
203   * @brief CRC calculation unit
204   */
205 typedef struct
206 {
207   __IO uint32_t DR;             /*!< CRC Data register,                           Address offset: 0x00 */
208   __IO uint32_t IDR;            /*!< CRC Independent data register,               Address offset: 0x04 */
209   __IO uint32_t CR;             /*!< CRC Control register,                        Address offset: 0x08 */
210        uint32_t RESERVED2;      /*!< Reserved,                                                    0x0C */
211   __IO uint32_t INIT;           /*!< Initial CRC value register,                  Address offset: 0x10 */
212   __IO uint32_t POL;            /*!< CRC polynomial register,                     Address offset: 0x14 */
213        uint32_t RESERVED3[246]; /*!< Reserved,                                                         */
214   __IO uint32_t HWCFGR;         /*!< CRC IP HWCFGR register,                     Address offset: 0x3F0 */
215   __IO uint32_t VERR;           /*!< CRC IP version register,                    Address offset: 0x3F4 */
216   __IO uint32_t PIDR;           /*!< CRC IP type identification register,        Address offset: 0x3F8 */
217   __IO uint32_t SIDR;           /*!< CRC IP map Size ID register,                Address offset: 0x3FC */
218 } CRC_TypeDef;
219 
220 /**
221   * @brief Inter-integrated Circuit Interface
222   */
223 typedef struct
224 {
225   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
226   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
227   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
228   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
229   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
230   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
231   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
232   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
233   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
234   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
235   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
236 } I2C_TypeDef;
237 
238 /**
239   * @brief Improved Inter-integrated Circuit Interface
240   */
241 typedef struct
242 {
243   __IO uint32_t CR;             /*!< I3C Control register,                      Address offset: 0x00      */
244   __IO uint32_t CFGR;           /*!< I3C Controller Configuration register,     Address offset: 0x04      */
245   uint32_t      RESERVED1[2];   /*!< Reserved,                                  Address offset: 0x08-0x0C */
246   __IO uint32_t RDR;            /*!< I3C Received Data register,                Address offset: 0x10      */
247   __IO uint32_t RDWR;           /*!< I3C Received Data Word register,           Address offset: 0x14      */
248   __IO uint32_t TDR;            /*!< I3C Transmit Data register,                Address offset: 0x18      */
249   __IO uint32_t TDWR;           /*!< I3C Transmit Data Word register,           Address offset: 0x1C      */
250   __IO uint32_t IBIDR;          /*!< I3C IBI payload Data register,             Address offset: 0x20      */
251   __IO uint32_t TGTTDR;         /*!< I3C Target Transmit register,              Address offset: 0x24      */
252   uint32_t      RESERVED2[2];   /*!< Reserved,                                  Address offset: 0x28-0x2C */
253   __IO uint32_t SR;             /*!< I3C Status register,                       Address offset: 0x30      */
254   __IO uint32_t SER;            /*!< I3C Status Error register,                 Address offset: 0x34      */
255   uint32_t      RESERVED3[2];   /*!< Reserved,                                  Address offset: 0x38-0x3C */
256   __IO uint32_t RMR;            /*!< I3C Received Message register,             Address offset: 0x40      */
257   uint32_t      RESERVED4[3];   /*!< Reserved,                                  Address offset: 0x44-0x4C */
258   __IO uint32_t EVR;            /*!< I3C Event register,                        Address offset: 0x50      */
259   __IO uint32_t IER;            /*!< I3C Interrupt Enable register,             Address offset: 0x54      */
260   __IO uint32_t CEVR;           /*!< I3C Clear Event register,                  Address offset: 0x58      */
261   uint32_t RESERVED5;           /*!< Reserved,                                  Address offset: 0x5C      */
262   __IO uint32_t DEVR0;          /*!< I3C own Target characteristics register,   Address offset: 0x60      */
263   __IO uint32_t DEVRX[4];       /*!< I3C Target x (1<=x<=4) register,           Address offset: 0x64-0x70 */
264   uint32_t      RESERVED6[7];   /*!< Reserved,                                  Address offset: 0x74-0x8C */
265   __IO uint32_t MAXRLR;         /*!< I3C Maximum Read Length register,          Address offset: 0x90      */
266   __IO uint32_t MAXWLR;         /*!< I3C Maximum Write Length register,         Address offset: 0x94      */
267   uint32_t      RESERVED7[2];   /*!< Reserved,                                  Address offset: 0x98-0x9C */
268   __IO uint32_t TIMINGR0;       /*!< I3C Timing 0 register,                     Address offset: 0xA0      */
269   __IO uint32_t TIMINGR1;       /*!< I3C Timing 1 register,                     Address offset: 0xA4      */
270   __IO uint32_t TIMINGR2;       /*!< I3C Timing 2 register,                     Address offset: 0xA8      */
271   uint32_t      RESERVED9[5];   /*!< Reserved,                                  Address offset: 0xAC-0xBC */
272   __IO uint32_t BCR;            /*!< I3C Bus Characteristics register,          Address offset: 0xC0      */
273   __IO uint32_t DCR;            /*!< I3C Device Characteristics register,       Address offset: 0xC4      */
274   __IO uint32_t GETCAPR;        /*!< I3C GET CAPabilities register,             Address offset: 0xC8      */
275   __IO uint32_t CRCAPR;         /*!< I3C Controller CAPabilities register,      Address offset: 0xCC      */
276   __IO uint32_t GETMXDSR;       /*!< I3C GET Max Data Speed register,           Address offset: 0xD0      */
277   __IO uint32_t EPIDR;          /*!< I3C Extended Provisioned ID register,      Address offset: 0xD4      */
278 } I3C_TypeDef;
279 
280 /**
281   * @brief DAC
282   */
283 typedef struct
284 {
285   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
286   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
287   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
288   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
289   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
290   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
291   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
292   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
293   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
294   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
295   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
296   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
297   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
298   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
299   __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
300   __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
301   __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
302   __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
303   __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
304   __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
305   __IO uint32_t RESERVED[1];
306   __IO uint32_t AUTOCR;      /*!< DAC Autonomous mode register,                         Address offset: 0x54 */
307 } DAC_TypeDef;
308 
309 /**
310   * @brief Clock Recovery System
311   */
312 typedef struct
313 {
314 __IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
315 __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
316 __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
317 __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
318 } CRS_TypeDef;
319 
320 
321 /**
322   * @brief HASH
323   */
324 typedef struct
325 {
326   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
327   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
328   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
329   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
330   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
331   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
332        uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
333   __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
334 } HASH_TypeDef;
335 
336 /**
337   * @brief HASH_DIGEST
338   */
339 typedef struct
340 {
341   __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */
342 } HASH_DIGEST_TypeDef;
343 
344 /**
345   * @brief RNG
346   */
347 typedef struct
348 {
349   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
350   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
351   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
352   uint32_t RESERVED;
353   __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
354 } RNG_TypeDef;
355 
356 /**
357   * @brief Debug MCU
358   */
359 typedef struct
360 {
361   __IO uint32_t IDCODE;       /*!< MCU device ID code,                 Address offset: 0x00  */
362   __IO uint32_t CR;           /*!< Debug MCU configuration register,   Address offset: 0x04  */
363   __IO uint32_t APB1FZR1;     /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08  */
364   __IO uint32_t APB1FZR2;     /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C  */
365   __IO uint32_t APB2FZR;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10  */
366   __IO uint32_t APB3FZR;      /*!< Debug MCU APB3 freeze register,     Address offset: 0x14  */
367        uint32_t RESERVED1[2]; /*!< Reserved,                                    0x18 - 0x1C  */
368   __IO uint32_t AHB1FZR;      /*!< Debug MCU AHB1 freeze register,     Address offset: 0x20  */
369        uint32_t RESERVED2[54]; /*!< Reserved,                                   0x24 - 0xF8  */
370   __IO uint32_t SR;           /*!< Debug MCU SR register,              Address offset: 0xFC  */
371   __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register,      Address offset: 0x100 */
372   __IO uint32_t DBG_AUTH_DEV;  /*!< Debug DBG_AUTH_DEV register,       Address offset: 0x104 */
373   __IO uint32_t DBG_AUTH_ACK;  /*!< Debug DBG_AUTH_ACK register,       Address offset: 0x108 */
374        uint32_t RESERVED3[945]; /*!< Reserved,                                 0x10C - 0xFCC */
375   __IO uint32_t PIDR4;       /*!< Debug MCU Peripheral ID register 4,  Address offset: 0xFD0 */
376   __IO uint32_t PIDR5;       /*!< Debug MCU Peripheral ID register 5,  Address offset: 0xFD4 */
377   __IO uint32_t PIDR6;       /*!< Debug MCU Peripheral ID register 6,  Address offset: 0xFD8 */
378   __IO uint32_t PIDR7;       /*!< Debug MCU Peripheral ID register 7,  Address offset: 0xFDC */
379   __IO uint32_t PIDR0;       /*!< Debug MCU Peripheral ID register 0,  Address offset: 0xFE0 */
380   __IO uint32_t PIDR1;       /*!< Debug MCU Peripheral ID register 1,  Address offset: 0xFE4 */
381   __IO uint32_t PIDR2;       /*!< Debug MCU Peripheral ID register 2,  Address offset: 0xFE8 */
382   __IO uint32_t PIDR3;       /*!< Debug MCU Peripheral ID register 3,  Address offset: 0xFEC */
383   __IO uint32_t CIDR0;       /*!< Debug MCU Component ID register 0,   Address offset: 0xFF0 */
384   __IO uint32_t CIDR1;       /*!< Debug MCU Component ID register 1,   Address offset: 0xFF4 */
385   __IO uint32_t CIDR2;       /*!< Debug MCU Component ID register 2,   Address offset: 0xFF8 */
386   __IO uint32_t CIDR3;       /*!< Debug MCU Component ID register 3,   Address offset: 0xFFC */
387 } DBGMCU_TypeDef;
388 
389 
390 /**
391   * @brief DMA Controller
392   */
393 typedef struct
394 {
395        uint32_t RESERVED0;   /*!< Reserved                                         Address offset: 0x00  */
396   __IO uint32_t PRIVCFGR;    /*!< DMA privileged configuration register,           Address offset: 0x04  */
397        uint32_t RESERVED1;   /*!< Reserved                                         Address offset: 0x08  */
398   __IO uint32_t MISR;        /*!< DMA non secure masked interrupt status register, Address offset: 0x0C  */
399        uint32_t RESERVED2;   /*!< Reserved                                         Address offset: 0x08  */
400 } DMA_TypeDef;
401 
402 typedef struct
403 {
404   __IO uint32_t CLBAR;        /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
405        uint32_t RESERVED1[2]; /*!< Reserved 1,                                      Address offset: 0x54 -- 0x58      */
406   __IO uint32_t CFCR;         /*!< DMA channel x flag clear register,               Address offset: 0x5C + (x * 0x80) */
407   __IO uint32_t CSR;          /*!< DMA channel x flag status register,              Address offset: 0x60 + (x * 0x80) */
408   __IO uint32_t CCR;          /*!< DMA channel x control register,                  Address offset: 0x64 + (x * 0x80) */
409        uint32_t RESERVED2[10];/*!< Reserved 2,                                      Address offset: 0x68 -- 0x8C      */
410   __IO uint32_t CTR1;         /*!< DMA channel x transfer register 1,               Address offset: 0x90 + (x * 0x80) */
411   __IO uint32_t CTR2;         /*!< DMA channel x transfer register 2,               Address offset: 0x94 + (x * 0x80) */
412   __IO uint32_t CBR1;         /*!< DMA channel x block register 1,                  Address offset: 0x98 + (x * 0x80) */
413   __IO uint32_t CSAR;         /*!< DMA channel x source address register,           Address offset: 0x9C + (x * 0x80) */
414   __IO uint32_t CDAR;         /*!< DMA channel x destination address register,      Address offset: 0xA0 + (x * 0x80) */
415   __IO uint32_t CTR3;         /*!< DMA channel x transfer register 3,               Address offset: 0xA4 + (x * 0x80) */
416   __IO uint32_t CBR2;         /*!< DMA channel x block register 2,                  Address offset: 0xA8 + (x * 0x80) */
417        uint32_t RESERVED3[8]; /*!< Reserved 3,                                      Address offset: 0xAC -- 0xC8      */
418   __IO uint32_t CLLR;         /*!< DMA channel x linked-list address register,      Address offset: 0xCC + (x * 0x80) */
419 } DMA_Channel_TypeDef;
420 
421 
422 /**
423   * @brief Asynch Interrupt/Event Controller (EXTI)
424   */
425 typedef struct
426 {
427   __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
428   __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
429   __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
430   __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
431   __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
432   __IO uint32_t SECCFGR1;       /*!< EXTI Security Configuration Register 1,          Address offset:   0x14 */
433   __IO uint32_t PRIVCFGR1;      /*!< EXTI Privilege Configuration Register 1,         Address offset:   0x18 */
434        uint32_t RESERVED1;      /*!< Reserved 1,                                      Address offset:   0x1C */
435   __IO uint32_t RTSR2;          /*!< EXTI Rising Trigger Selection Register 2,        Address offset:   0x20 */
436   __IO uint32_t FTSR2;          /*!< EXTI Falling Trigger Selection Register 2,       Address offset:   0x24 */
437   __IO uint32_t SWIER2;         /*!< EXTI Software Interrupt event Register 2,        Address offset:   0x28 */
438   __IO uint32_t RPR2;           /*!< EXTI Rising Pending Register 2,                  Address offset:   0x2C */
439   __IO uint32_t FPR2;           /*!< EXTI Falling Pending Register 2,                 Address offset:   0x30 */
440   __IO uint32_t SECCFGR2;       /*!< EXTI Security Configuration Register 2,          Address offset:   0x34 */
441   __IO uint32_t PRIVCFGR2;      /*!< EXTI Privilege Configuration Register 2,         Address offset:   0x38 */
442        uint32_t RESERVED2[9];   /*!< Reserved 2,                                                 0x3C-- 0x5C */
443   __IO uint32_t EXTICR[4];      /*!< EXIT External Interrupt Configuration Register,            0x60 -- 0x6C */
444        uint32_t RESERVED3[4];   /*!< Reserved 3,                                                0x70 -- 0x7C */
445   __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
446   __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
447        uint32_t RESERVED4[2];   /*!< Reserved 4,                                                0x88 -- 0x8C */
448   __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
449   __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
450 } EXTI_TypeDef;
451 
452 /**
453   * @brief FLASH Registers
454   */
455 typedef struct
456 {
457   __IO uint32_t ACR;             /*!< FLASH access control register,                                     Address offset: 0x00 */
458   __IO uint32_t NSKEYR;          /*!< FLASH non-secure key register,                                     Address offset: 0x04 */
459        uint32_t RESERVED1;       /*!< Reserved1,                                                         Address offset: 0x08 */
460   __IO uint32_t OPTKEYR;         /*!< FLASH option key register,                                         Address offset: 0x0C */
461        uint32_t RESERVED2[2];    /*!< Reserved2,                                                         Address offset: 0x10-0x14 */
462   __IO uint32_t OPSR;            /*!< FLASH OPSR register,                                               Address offset: 0x18 */
463   __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                                     Address offset: 0x1C */
464   __IO uint32_t NSSR;            /*!< FLASH non-secure status register,                                  Address offset: 0x20 */
465        uint32_t RESERVED3;       /*!< Reserved3,                                                         Address offset: 0x24 */
466   __IO uint32_t NSCR;            /*!< FLASH non-secure control register,                                 Address offset: 0x28 */
467        uint32_t RESERVED4;       /*!< Reserved4,                                                         Address offset: 0x2C */
468   __IO uint32_t NSCCR;           /*!< FLASH non-secure clear control register,                           Address offset: 0x30 */
469        uint32_t RESERVED5[2];    /*!< Reserved5,                                                         Address offset: 0x34-0x38 */
470   __IO uint32_t PRIVCFGR;        /*!< FLASH privilege configuration register,                            Address offset: 0x3C */
471        uint32_t RESERVED6[2];    /*!< Reserved6,                                                         Address offset: 0x40-0x44 */
472   __IO uint32_t HDPEXTR;         /*!< FLASH HDP extension register,                                      Address offset: 0x48 */
473        uint32_t RESERVED7;       /*!< Reserved7,                                                         Address offset: 0x4C */
474   __IO uint32_t OPTSR_CUR;       /*!< FLASH option status current register,                              Address offset: 0x50 */
475   __IO uint32_t OPTSR_PRG;       /*!< FLASH option status to program register,                           Address offset: 0x54 */
476        uint32_t RESERVED8[2];    /*!< Reserved8,                                                         Address offset: 0x58-0x5C */
477   __IO uint32_t NSEPOCHR_CUR;    /*!< FLASH non-secure epoch current register,                           Address offset: 0x60 */
478   __IO uint32_t NSEPOCHR_PRG;    /*!< FLASH non-secure epoch to program register,                        Address offset: 0x64 */
479        uint32_t RESERVED9[2];    /*!< Reserved9,                                                         Address offset: 0x68-0x6C */
480   __IO uint32_t OPTSR2_CUR;      /*!< FLASH option status current register 2,                            Address offset: 0x70 */
481   __IO uint32_t OPTSR2_PRG;      /*!< FLASH option status to program register 2,                         Address offset: 0x74 */
482        uint32_t RESERVED10[2];   /*!< Reserved10,                                                        Address offset: 0x78-0x7C */
483   __IO uint32_t NSBOOTR_CUR;     /*!< FLASH non-secure unique boot entry current register,               Address offset: 0x80 */
484   __IO uint32_t NSBOOTR_PRG;     /*!< FLASH non-secure unique boot entry to program register,            Address offset: 0x84 */
485       uint32_t RESERVED11[2];    /*!< Reserved11,                                                        Address offset: 0x88-0x8C */
486   __IO uint32_t OTPBLR_CUR;      /*!< FLASH OTP block lock current register,                             Address offset: 0x90 */
487   __IO uint32_t OTPBLR_PRG;      /*!< FLASH OTP block Lock to program register,                          Address offset: 0x94 */
488       uint32_t RESERVED12[10];    /*!< Reserved12,                                                        Address offset: 0x98-0xBC */
489   __IO uint32_t PRIVBB1R1;       /*!< FLASH privilege block-based bank 1 register 1,                     Address offset: 0xC0 */
490       uint32_t RESERVED13[9];    /*!< Reserved13,                                                        Address offset: 0xC4-0xE4 */
491   __IO uint32_t WRP1R_CUR;       /*!< FLASH write sector group protection current register for bank1,    Address offset: 0xE8 */
492   __IO uint32_t WRP1R_PRG;       /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */
493       uint32_t RESERVED14[2];    /*!< Reserved14,                                                        Address offset: 0xF0-0xF4 */
494   __IO uint32_t HDP1R_CUR;       /*!< FLASH HDP configuration current register for bank1,                Address offset: 0xF8 */
495   __IO uint32_t HDP1R_PRG;       /*!< FLASH HDP configuration to program register for bank1,             Address offset: 0xFC */
496   __IO uint32_t ECCCORR;         /*!< FLASH ECC correction register,                                     Address offset: 0x100 */
497   __IO uint32_t ECCDETR;         /*!< FLASH ECC detection register,                                      Address offset: 0x104 */
498   __IO uint32_t ECCDR;           /*!< FLASH ECC data register,                                           Address offset: 0x108 */
499       uint32_t RESERVED15[45];   /*!< Reserved15,                                                        Address offset: 0x10C-0x1BC */
500   __IO uint32_t PRIVBB2R1;       /*!< FLASH privilege block-based bank 2 register 1,                     Address offset: 0x1C0 */
501       uint32_t RESERVED16[9];    /*!< Reserved16,                                                        Address offset: 0x1C4-0x1E4 */
502   __IO uint32_t WRP2R_CUR;       /*!< FLASH write sector group protection current register for bank2,    Address offset: 0x1E8 */
503   __IO uint32_t WRP2R_PRG;       /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */
504       uint32_t RESERVED17[2];    /*!< Reserved17,                                                        Address offset: 0x1F0-0x1F4 */
505   __IO uint32_t HDP2R_CUR;       /*!< FLASH HDP configuration current register for bank2,                Address offset: 0x1F8 */
506   __IO uint32_t HDP2R_PRG;       /*!< FLASH HDP configuration to program register for bank2,             Address offset: 0x1FC */
507 } FLASH_TypeDef;
508 
509 /**
510   * @brief General Purpose I/O
511   */
512 typedef struct
513 {
514   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
515   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
516   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
517   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
518   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
519   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
520   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
521   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
522   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
523   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
524   __IO uint32_t HSLVR;       /*!< GPIO high-speed low voltage register,  Address offset: 0x2C      */
525   __IO uint32_t SECCFGR;     /*!< GPIO secure configuration register,    Address offset: 0x30      */
526 } GPIO_TypeDef;
527 
528 /**
529   * @brief Global TrustZone Controller
530   */
531 typedef struct
532 {
533        uint32_t RESERVED1[8];   /*!< Reserved1,                                                            Address offset: 0x00-0x1C */
534   __IO uint32_t PRIVCFGR1;      /*!< TZSC privilege configuration register 1,                              Address offset: 0x20      */
535   __IO uint32_t PRIVCFGR2;      /*!< TZSC privilege configuration register 2,                              Address offset: 0x24      */
536   __IO uint32_t PRIVCFGR3;      /*!< TZSC privilege configuration register 3,                              Address offset: 0x28      */
537        uint32_t RESERVED3[17];  /*!< Reserved3,                                                            Address offset: 0x2C-0x6C */
538   __IO uint32_t MPCWM4ACFGR;    /*!< TZSC memory 4 sub-region A watermark configuration register,          Address offset: 0x70      */
539   __IO uint32_t MPCWM4AR;       /*!< TZSC memory 4 sub-region A watermark register,                        Address offset: 0x74      */
540   __IO uint32_t MPCWM4BCFGR;    /*!< TZSC memory 4 sub-region B watermark configuration register,          Address offset: 0x78      */
541   __IO uint32_t MPCWM4BR;       /*!< TZSC memory 4 sub-region B watermark register,                        Address offset: 0x7c      */
542 } GTZC_TZSC_TypeDef;
543 
544 typedef struct
545 {
546   uint32_t RESERVED1[128];      /*!< Reserved1,                                Address offset: 0x000-0x1FC */
547   __IO uint32_t PRIVCFGR[32];   /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
548 } GTZC_MPCBB_TypeDef;
549 
550 /**
551   * @brief Instruction Cache
552   */
553 typedef struct
554 {
555   __IO uint32_t CR;             /*!< ICACHE control register,                Address offset: 0x00 */
556   __IO uint32_t SR;             /*!< ICACHE status register,                 Address offset: 0x04 */
557   __IO uint32_t IER;            /*!< ICACHE interrupt enable register,       Address offset: 0x08 */
558   __IO uint32_t FCR;            /*!< ICACHE Flag clear register,             Address offset: 0x0C */
559   __IO uint32_t HMONR;          /*!< ICACHE hit monitor register,            Address offset: 0x10 */
560   __IO uint32_t MMONR;          /*!< ICACHE miss monitor register,           Address offset: 0x14 */
561 } ICACHE_TypeDef;
562 
563 /**
564   * @brief TIM
565   */
566 typedef struct
567 {
568   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
569   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
570   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
571   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
572   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
573   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
574   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
575   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
576   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
577   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
578   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
579   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
580   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
581   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
582   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
583   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
584   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
585   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
586   __IO uint32_t CCR5;        /*!< TIM capture/compare register 5,           Address offset: 0x48 */
587   __IO uint32_t CCR6;        /*!< TIM capture/compare register 6,           Address offset: 0x4C */
588   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x50 */
589   __IO uint32_t DTR2;        /*!< TIM deadtime register 2,                  Address offset: 0x54 */
590   __IO uint32_t ECR;         /*!< TIM encoder control register,             Address offset: 0x58 */
591   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x5C */
592   __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
593   __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
594        uint32_t RESERVED0[221];/*!< Reserved,                               Address offset: 0x68 */
595   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x3DC */
596   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x3E0 */
597 } TIM_TypeDef;
598 
599 /**
600   * @brief LPTIMER
601   */
602 typedef struct
603 {
604   __IO uint32_t ISR;            /*!< LPTIM Interrupt and Status register,    Address offset: 0x00 */
605   __IO uint32_t ICR;            /*!< LPTIM Interrupt Clear register,         Address offset: 0x04 */
606   __IO uint32_t DIER;           /*!< LPTIM Interrupt Enable register,        Address offset: 0x08 */
607   __IO uint32_t CFGR;           /*!< LPTIM Configuration register,           Address offset: 0x0C */
608   __IO uint32_t CR;             /*!< LPTIM Control register,                 Address offset: 0x10 */
609   __IO uint32_t CCR1;           /*!< LPTIM Capture/Compare register 1,       Address offset: 0x14 */
610   __IO uint32_t ARR;            /*!< LPTIM Autoreload register,              Address offset: 0x18 */
611   __IO uint32_t CNT;            /*!< LPTIM Counter register,                 Address offset: 0x1C */
612   __IO uint32_t RESERVED0;      /*!< Reserved,                               Address offset: 0x20 */
613   __IO uint32_t CFGR2;          /*!< LPTIM Configuration register 2,         Address offset: 0x24 */
614   __IO uint32_t RCR;            /*!< LPTIM Repetition register,              Address offset: 0x28 */
615   __IO uint32_t CCMR1;          /*!< LPTIM Capture/Compare mode register,    Address offset: 0x2C */
616   __IO uint32_t RESERVED1;      /*!< Reserved,                               Address offset: 0x30 */
617   __IO uint32_t CCR2;           /*!< LPTIM Capture/Compare register 2,       Address offset: 0x34 */
618 } LPTIM_TypeDef;
619 
620 /**
621   * @brief Comparator
622   */
623 typedef struct
624 {
625   __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */
626   __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,      Address offset: 0x04 */
627 } COMPOPT_TypeDef;
628 
629 typedef struct
630 {
631   __IO uint32_t SR;         /*!< Comparator status register,                   Address offset: 0x00 */
632   __IO uint32_t ICFR;       /*!< Comparator interrupt clear flag register,     Address offset: 0x04 */
633   __IO uint32_t RESERVED1;  /*!< Reserved,                                     Address offset: 0x08 */
634   __IO uint32_t CFGR1;      /*!< Comparator configuration register 1  ,        Address offset: 0x0C */
635   __IO uint32_t CFGR2;      /*!< Comparator configuration register 2 ,         Address offset: 0x10 */
636 } COMP_TypeDef;
637 
638 typedef struct
639 {
640   __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
641 } COMP_Common_TypeDef;
642 
643 /**
644   * @brief Operational Amplifier (OPAMP)
645   */
646 
647 typedef struct
648 {
649   __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */
650   __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */
651   __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
652 } OPAMP_TypeDef;
653 
654 
655 
656 /**
657   * @brief Power Control
658   */
659 typedef struct
660 {
661   __IO uint32_t PMCR;         /*!< Power mode control register ,          Address offset: 0x00      */
662   __IO uint32_t PMSR;         /*!< Power mode status register ,           Address offset: 0x04      */
663        uint32_t RESERVED1[2]; /*!< Reserved,                              Address offset: 0x08-0x0C */
664   __IO uint32_t VOSCR;        /*!< Voltage scaling control register ,     Address offset: 0x10      */
665   __IO uint32_t VOSSR;        /*!< Voltage sacling status register ,      Address offset: 0x14      */
666        uint32_t RESERVED2[2]; /*!< Reserved,                              Address offset: 0x18-0x1C */
667   __IO uint32_t BDCR;         /*!< BacKup domain control register ,       Address offset: 0x20      */
668   __IO uint32_t DBPCR;        /*!< DBP control register,                  Address offset: 0x24      */
669   __IO uint32_t BDSR;         /*!< BacKup domain status register,         Address offset: 0x28      */
670        uint32_t RESERVED3;    /*!< Reserved,                              Address offset: 0x38      */
671   __IO uint32_t SCCR;         /*!< Supply configuration control register, Address offset: 0x30      */
672   __IO uint32_t VMCR;         /*!< Voltage Monitor Control Register,      Address offset: 0x34      */
673        uint32_t RESERVED4;    /*!< Reserved,                              Address offset: 0x38      */
674   __IO uint32_t VMSR;         /*!< Status Register Voltage Monitoring,    Address offset: 0x3C      */
675   __IO uint32_t WUSCR;        /*!< WakeUP status clear register,          Address offset: 0x40      */
676   __IO uint32_t WUSR;         /*!< WakeUP status Register,                Address offset: 0x44      */
677   __IO uint32_t WUCR;         /*!< WakeUP configuration register,         Address offset: 0x48      */
678        uint32_t RESERVED5;    /*!< Reserved,                              Address offset: 0x4C      */
679   __IO uint32_t IORETR;       /*!< IO RETention Register,                 Address offset: 0x50      */
680        uint32_t RESERVED6[43];/*!< Reserved,                              Address offset: 0x54-0xFC */
681        uint32_t RESERVED7;    /*!< Reserved,                              Address offset: 0x100     */
682   __IO uint32_t PRIVCFGR;     /*!< Privilege configuration register,     Address offset: 0x104      */
683 }PWR_TypeDef;
684 
685 /**
686   * @brief SRAMs configuration controller
687   */
688 typedef struct
689 {
690   __IO uint32_t CR;       /*!< Control Register,                  Address offset: 0x00 */
691   __IO uint32_t IER;      /*!< Interrupt Enable Register,         Address offset: 0x04 */
692   __IO uint32_t ISR;      /*!< Interrupt Status Register,         Address offset: 0x08 */
693   __IO uint32_t SEAR;     /*!< ECC Single Error Address Register, Address offset: 0x0C */
694   __IO uint32_t DEAR;     /*!< ECC Double Error Address Register, Address offset: 0x10 */
695   __IO uint32_t ICR;      /*!< Interrupt Clear Register,          Address offset: 0x14 */
696   __IO uint32_t WPR1;     /*!< SRAM Write Protection Register 1,  Address offset: 0x18 */
697   __IO uint32_t WPR2;     /*!< SRAM Write Protection Register 2,  Address offset: 0x1C */
698   uint32_t      RESERVED; /*!< Reserved,                          Address offset: 0x20 */
699   __IO uint32_t ECCKEY;   /*!< SRAM ECC Key Register,             Address offset: 0x24 */
700   __IO uint32_t ERKEYR;   /*!< SRAM Erase Key Register,           Address offset: 0x28 */
701 }RAMCFG_TypeDef;
702 
703 /**
704   * @brief Reset and Clock Control
705   */
706 typedef struct
707 {
708   __IO uint32_t CR;            /*!< RCC clock control register                                               Address offset: 0x00 */
709   uint32_t      RESERVED1[3];  /*!< Reserved,                                                                Address offset: 0x04 */
710   __IO uint32_t HSICFGR;       /*!< RCC HSI Clock Calibration Register,                                      Address offset: 0x10 */
711   __IO uint32_t CRRCR;         /*!< RCC Clock Recovery RC Register,                                          Address offset: 0x14 */
712   __IO uint32_t CSICFGR;       /*!< RCC CSI Clock Calibration Register,                                      Address offset: 0x18 */
713   __IO uint32_t CFGR1;         /*!< RCC clock configuration register 1                                       Address offset: 0x1C */
714   __IO uint32_t CFGR2;         /*!< RCC clock configuration register 2                                       Address offset: 0x20 */
715   uint32_t      RESERVED2;     /*!< Reserved,                                                                Address offset: 0x24 */
716   __IO uint32_t PLL1CFGR;      /*!< RCC PLL1 Configuration Register                                          Address offset: 0x28 */
717   __IO uint32_t PLL2CFGR;      /*!< RCC PLL2 Configuration Register                                          Address offset: 0x2C */
718   uint32_t      RESERVED3;     /*!< Reserved,                                                                Address offset: 0x30 */
719   __IO uint32_t PLL1DIVR;      /*!< RCC PLL1 Dividers Configuration Register                                 Address offset: 0x34 */
720   __IO uint32_t PLL1FRACR;     /*!< RCC PLL1 Fractional Divider Configuration Register                       Address offset: 0x38 */
721   __IO uint32_t PLL2DIVR;      /*!< RCC PLL2 Dividers Configuration Register                                 Address offset: 0x3C */
722   __IO uint32_t PLL2FRACR;     /*!< RCC PLL2 Fractional Divider Configuration Register                       Address offset: 0x40 */
723   uint32_t      RESERVED4[2];  /*!< Reserved,                                                                Address offset: 0x44 */
724   uint32_t      RESERVED5;     /*!< Reserved                                                                 Address offset: 0x4C */
725   __IO uint32_t CIER;          /*!< RCC Clock Interrupt Enable Register                                      Address offset: 0x50 */
726   __IO uint32_t CIFR;          /*!< RCC Clock Interrupt Flag Register                                        Address offset: 0x54 */
727   __IO uint32_t CICR;          /*!< RCC Clock Interrupt Clear Register                                       Address offset: 0x58 */
728   uint32_t      RESERVED6;     /*!< Reserved                                                                 Address offset: 0x5C */
729   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 Peripherals Reset Register                                      Address offset: 0x60 */
730   __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 Peripherals Reset Register                                      Address offset: 0x64 */
731   uint32_t      RESERVED7;     /*!< Reserved                                                                 Address offset: 0x68 */
732   uint32_t      RESERVED8;     /*!< Reserved,                                                                Address offset: 0x6C */
733   uint32_t      RESERVED9;     /*!< Reserved                                                                 Address offset: 0x70 */
734   __IO uint32_t APB1LRSTR;     /*!< RCC APB1 Peripherals reset Low Word register                             Address offset: 0x74 */
735   __IO uint32_t APB1HRSTR;     /*!< RCC APB1 Peripherals reset High Word register                            Address offset: 0x78 */
736   __IO uint32_t APB2RSTR;      /*!< RCC APB2 Peripherals Reset Register                                      Address offset: 0x7C */
737   __IO uint32_t APB3RSTR;      /*!< RCC APB3 Peripherals Reset Register                                      Address offset: 0x80 */
738   uint32_t      RESERVED10;    /*!< Reserved                                                                 Address offset: 0x84 */
739   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 Peripherals Clock Enable Register                               Address offset: 0x88 */
740   __IO uint32_t AHB2ENR;       /*!< RCC AHB2 Peripherals Clock Enable Register                               Address offset: 0x8C */
741   uint32_t      RESERVED11;    /*!< Reserved                                                                 Address offset: 0x90 */
742   uint32_t      RESERVED12;    /*!< Reserved,                                                                Address offset: 0x94 */
743   uint32_t      RESERVED13;    /*!< Reserved                                                                 Address offset: 0x98 */
744   __IO uint32_t APB1LENR;      /*!< RCC APB1 Peripherals clock Enable Low Word register                      Address offset: 0x9C */
745   __IO uint32_t APB1HENR;      /*!< RCC APB1 Peripherals clock Enable High Word register                     Address offset: 0xA0 */
746   __IO uint32_t APB2ENR;       /*!< RCC APB2 Peripherals Clock Enable Register                               Address offset: 0xA4 */
747   __IO uint32_t APB3ENR;       /*!< RCC APB3 Peripherals Clock Enable Register                               Address offset: 0xA8 */
748   uint32_t      RESERVED14;    /*!< Reserved                                                                 Address offset: 0xAC */
749   __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 Peripheral sleep clock Register                                 Address offset: 0xB0 */
750   __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 Peripheral sleep clock Register                                 Address offset: 0xB4 */
751   uint32_t      RESERVED15;    /*!< Reserved                                                                 Address offset: 0xB8 */
752   uint32_t      RESERVED16;    /*!< Reserved,                                                                Address offset: 0xBC */
753   uint32_t      RESERVED17;    /*!< Reserved                                                                 Address offset: 0xC0 */
754   __IO uint32_t APB1LLPENR;    /*!< RCC APB1 Peripherals sleep clock Low Word Register                       Address offset: 0xC4 */
755   __IO uint32_t APB1HLPENR;    /*!< RCC APB1 Peripherals sleep clock High Word Register                      Address offset: 0xC8 */
756   __IO uint32_t APB2LPENR;     /*!< RCC APB2 Peripherals sleep clock Register                                Address offset: 0xCC */
757   __IO uint32_t APB3LPENR;     /*!< RCC APB3 Peripherals Clock Low Power Enable Register                     Address offset: 0xD0 */
758   uint32_t      RESERVED18;    /*!< Reserved                                                                 Address offset: 0xD4 */
759   __IO uint32_t CCIPR1;        /*!< RCC IPs Clocks Configuration Register 1                                  Address offset: 0xD8 */
760   __IO uint32_t CCIPR2;        /*!< RCC IPs Clocks Configuration Register 2                                  Address offset: 0xDC */
761   __IO uint32_t CCIPR3;        /*!< RCC IPs Clocks Configuration Register 3                                  Address offset: 0xE0 */
762   __IO uint32_t CCIPR4;        /*!< RCC IPs Clocks Configuration Register 4                                  Address offset: 0xE4 */
763   __IO uint32_t CCIPR5;        /*!< RCC IPs Clocks Configuration Register 5                                  Address offset: 0xE8 */
764   uint32_t      RESERVED19;    /*!< Reserved,                                                                Address offset: 0xEC */
765   __IO uint32_t BDCR;          /*!< RCC VSW Backup Domain & V33 Domain Control Register                      Address offset: 0xF0 */
766   __IO uint32_t RSR;           /*!< RCC Reset status Register                                                Address offset: 0xF4 */
767   uint32_t      RESERVED20[6]; /*!< Reserved                                                                 Address offset: 0xF8 */
768   uint32_t      RESERVED21;    /*!< Reserved,                                                                Address offset: 0x110 */
769   __IO uint32_t PRIVCFGR;      /*!< RCC Privilege configuration register                                     Address offset: 0x114 */
770 } RCC_TypeDef;
771 
772 /*
773 * @brief RTC Specific device feature definitions
774 */
775 #define RTC_BKP_NB         32U
776 #define RTC_TAMP_NB        2U
777 
778 /**
779   * @brief Real-Time Clock
780   */
781 typedef struct
782 {
783   __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
784   __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
785   __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
786   __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
787   __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
788   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
789   __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
790   __IO uint32_t PRIVCFGR;    /*!< RTC privilege mode control register,            Address offset: 0x1C */
791        uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x20 */
792   __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
793   __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
794   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
795   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
796   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
797   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
798        uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x3C */
799   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
800   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
801   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
802   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
803   __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
804   __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
805        uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x58 */
806   __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
807   __IO uint32_t OR;          /*!< RTC option register,                            Address offset: 0x60 */
808        uint32_t RESERVED3[3];/*!< Reserved,                                       Address offset: 0x64 */
809   __IO uint32_t ALRABINR;    /*!< RTC alarm A binary mode register,               Address offset: 0x70 */
810   __IO uint32_t ALRBBINR;    /*!< RTC alarm B binary mode register,               Address offset: 0x74 */
811 } RTC_TypeDef;
812 
813 /**
814   * @brief Tamper and backup registers
815   */
816 typedef struct
817 {
818   __IO uint32_t CR1;         /*!< TAMP control register 1,                  Address offset: 0x00 */
819   __IO uint32_t CR2;         /*!< TAMP control register 2,                  Address offset: 0x04 */
820   __IO uint32_t CR3;         /*!< TAMP control register 3,                  Address offset: 0x08 */
821   __IO uint32_t FLTCR;       /*!< TAMP filter control register,             Address offset: 0x0C */
822   __IO uint32_t ATCR1;       /*!< TAMP filter control register 1            Address offset: 0x10 */
823   __IO uint32_t ATSEEDR;     /*!< TAMP active tamper seed register,         Address offset: 0x14 */
824   __IO uint32_t ATOR;        /*!< TAMP active tamper output register,       Address offset: 0x18 */
825   __IO uint32_t ATCR2;       /*!< TAMP filter control register 2,           Address offset: 0x1C */
826   __IO uint32_t SECCFGR;     /*!< TAMP secure mode control register,        Address offset: 0x20 */
827   __IO uint32_t PRIVCFGR;    /*!< TAMP privilege mode control register,     Address offset: 0x24 */
828        uint32_t RESERVED0;   /*!< Reserved,                                 Address offset: 0x28 */
829   __IO uint32_t IER;         /*!< TAMP interrupt enable register,           Address offset: 0x2C */
830   __IO uint32_t SR;          /*!< TAMP status register,                     Address offset: 0x30 */
831   __IO uint32_t MISR;        /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
832        uint32_t RESERVED1;   /*!< Reserved,                                 Address offset: 0x38 */
833   __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
834   __IO uint32_t COUNT1R;     /*!< TAMP monotonic counter register,          Address offset: 0x40 */
835        uint32_t RESERVED2[3];/*!< Reserved,                                 Address offset: 0x44 -- 0x4C */
836   __IO uint32_t OR;          /*!< TAMP option register,                     Address offset: 0x50 */
837   __IO uint32_t ERCFGR;      /*!< TAMP erase configuration register,        Address offset: 0x54 */
838        uint32_t RESERVED3[42];/*!< Reserved,                                Address offset: 0x58 -- 0xFC */
839   __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
840   __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
841   __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
842   __IO uint32_t BKP3R;       /*!< TAMP backup register 3,                   Address offset: 0x10C */
843   __IO uint32_t BKP4R;       /*!< TAMP backup register 4,                   Address offset: 0x110 */
844   __IO uint32_t BKP5R;       /*!< TAMP backup register 5,                   Address offset: 0x114 */
845   __IO uint32_t BKP6R;       /*!< TAMP backup register 6,                   Address offset: 0x118 */
846   __IO uint32_t BKP7R;       /*!< TAMP backup register 7,                   Address offset: 0x11C */
847   __IO uint32_t BKP8R;       /*!< TAMP backup register 8,                   Address offset: 0x120 */
848   __IO uint32_t BKP9R;       /*!< TAMP backup register 9,                   Address offset: 0x124 */
849   __IO uint32_t BKP10R;      /*!< TAMP backup register 10,                  Address offset: 0x128 */
850   __IO uint32_t BKP11R;      /*!< TAMP backup register 11,                  Address offset: 0x12C */
851   __IO uint32_t BKP12R;      /*!< TAMP backup register 12,                  Address offset: 0x130 */
852   __IO uint32_t BKP13R;      /*!< TAMP backup register 13,                  Address offset: 0x134 */
853   __IO uint32_t BKP14R;      /*!< TAMP backup register 14,                  Address offset: 0x138 */
854   __IO uint32_t BKP15R;      /*!< TAMP backup register 15,                  Address offset: 0x13C */
855   __IO uint32_t BKP16R;      /*!< TAMP backup register 16,                  Address offset: 0x140 */
856   __IO uint32_t BKP17R;      /*!< TAMP backup register 17,                  Address offset: 0x144 */
857   __IO uint32_t BKP18R;      /*!< TAMP backup register 18,                  Address offset: 0x148 */
858   __IO uint32_t BKP19R;      /*!< TAMP backup register 19,                  Address offset: 0x14C */
859   __IO uint32_t BKP20R;      /*!< TAMP backup register 20,                  Address offset: 0x150 */
860   __IO uint32_t BKP21R;      /*!< TAMP backup register 21,                  Address offset: 0x154 */
861   __IO uint32_t BKP22R;      /*!< TAMP backup register 22,                  Address offset: 0x158 */
862   __IO uint32_t BKP23R;      /*!< TAMP backup register 23,                  Address offset: 0x15C */
863   __IO uint32_t BKP24R;      /*!< TAMP backup register 24,                  Address offset: 0x160 */
864   __IO uint32_t BKP25R;      /*!< TAMP backup register 25,                  Address offset: 0x164 */
865   __IO uint32_t BKP26R;      /*!< TAMP backup register 26,                  Address offset: 0x168 */
866   __IO uint32_t BKP27R;      /*!< TAMP backup register 27,                  Address offset: 0x16C */
867   __IO uint32_t BKP28R;      /*!< TAMP backup register 28,                  Address offset: 0x170 */
868   __IO uint32_t BKP29R;      /*!< TAMP backup register 29,                  Address offset: 0x174 */
869   __IO uint32_t BKP30R;      /*!< TAMP backup register 30,                  Address offset: 0x178 */
870   __IO uint32_t BKP31R;      /*!< TAMP backup register 31,                  Address offset: 0x17C */
871 } TAMP_TypeDef;
872 
873 /**
874   * @brief Universal Synchronous Asynchronous Receiver Transmitter
875   */
876 typedef struct
877 {
878   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
879   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
880   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
881   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
882   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
883   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14  */
884   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
885   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
886   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
887   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
888   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
889   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
890 } USART_TypeDef;
891 
892 /**
893   * @brief System configuration, Boot and Security
894   */
895 typedef struct
896 {
897        uint32_t RESERVED1[4];   /*!< RESERVED1,                                       Address offset: 0x00 - 0x0C */
898   __IO uint32_t HDPLCR;         /*!< SBS HDPL Control Register,                       Address offset: 0x10 */
899   __IO uint32_t HDPLSR;         /*!< SBS HDPL Status Register,                        Address offset: 0x14 */
900   __IO uint32_t RESERVED2[2];   /*!< RESERVED2,                                       Address offset: 0x18 - 0x1C */
901   __IO uint32_t DBGCR;          /*!< SBS Debug Control Register,                      Address offset: 0x20 */
902   __IO uint32_t DBGLOCKR;       /*!< SBS Debug Lock Register,                         Address offset: 0x24 */
903        uint32_t RESERVED3[3];   /*!< RESERVED3,                                       Address offset: 0x28 - 0x30 */
904        uint32_t RESERVED4[36];   /*!< RESERVED4,                                      Address offset: 0x34 - 0xC0 */
905        uint32_t RESERVED6[15];  /*!< RESERVED6,                                       Address offset: 0xC4 - 0xFC */
906   __IO uint32_t PMCR;           /*!< SBS Product Mode & Config Register,              Address offset: 0x100 */
907   __IO uint32_t FPUIMR;         /*!< SBS FPU Interrupt Mask Register,                 Address offset: 0x104 */
908   __IO uint32_t MESR;           /*!< SBS Memory Erase Status Register,                Address offset: 0x108 */
909        uint32_t RESERVED7;      /*!< RESERVED7,                                       Address offset: 0x10C */
910   __IO uint32_t CCCSR;          /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */
911   __IO uint32_t CCVALR;         /*!< SBS Compensation Cell Value Register,            Address offset: 0x114 */
912   __IO uint32_t CCSWCR;         /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */
913   __IO uint32_t RESERVED8;      /*!< RESERVED8,                                       Address offset: 0x11C */
914   __IO uint32_t CFGR2;          /*!< SBS Class B Register,                            Address offset: 0x120 */
915        uint32_t RESERVED9[8];   /*!< RESERVED9,                                       Address offset: 0x124 - 0x140 */
916   __IO uint32_t CNSLCKR;        /*!< SBS CPU Non-secure Lock Register,                Address offset: 0x144 */
917        uint32_t RESERVED10;     /*!< RESERVED10,                                      Address offset: 0x148 */
918   __IO uint32_t ECCNMIR;        /*!< SBS FLITF ECC NMI MASK Register,                 Address offset: 0x14C */
919 } SBS_TypeDef;
920 
921 
922 /**
923   * @brief Universal Serial Bus Full Speed Dual Role Device
924   */
925 typedef struct
926 {
927   __IO uint32_t CHEP0R;          /*!< USB Channel/Endpoint 0 register,      Address offset: 0x00 */
928   __IO uint32_t CHEP1R;          /*!< USB Channel/Endpoint 1 register,      Address offset: 0x04 */
929   __IO uint32_t CHEP2R;          /*!< USB Channel/Endpoint 2 register,      Address offset: 0x08 */
930   __IO uint32_t CHEP3R;          /*!< USB Channel/Endpoint 3 register,      Address offset: 0x0C */
931   __IO uint32_t CHEP4R;          /*!< USB Channel/Endpoint 4 register,      Address offset: 0x10 */
932   __IO uint32_t CHEP5R;          /*!< USB Channel/Endpoint 5 register,      Address offset: 0x14 */
933   __IO uint32_t CHEP6R;          /*!< USB Channel/Endpoint 6 register,      Address offset: 0x18 */
934   __IO uint32_t CHEP7R;          /*!< USB Channel/Endpoint 7 register,      Address offset: 0x1C */
935   __IO uint32_t RESERVED0[8];    /*!< Reserved,                                                  */
936   __IO uint32_t CNTR;            /*!< Control register,                     Address offset: 0x40 */
937   __IO uint32_t ISTR;            /*!< Interrupt status register,            Address offset: 0x44 */
938   __IO uint32_t FNR;             /*!< Frame number register,                Address offset: 0x48 */
939   __IO uint32_t DADDR;           /*!< Device address register,              Address offset: 0x4C */
940   __IO uint32_t RESERVED1;       /*!< Reserved */
941   __IO uint32_t LPMCSR;          /*!< LPM Control and Status register,      Address offset: 0x54 */
942   __IO uint32_t BCDR;            /*!< Battery Charging detector register,   Address offset: 0x58 */
943 } USB_DRD_TypeDef;
944 
945 /**
946   * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table
947   */
948 typedef struct
949 {
950   __IO uint32_t TXBD;             /*!<Transmission buffer address*/
951   __IO uint32_t RXBD;             /*!<Reception buffer address */
952 } USB_DRD_PMABuffDescTypeDef;
953 
954 /**
955   * @brief FD Controller Area Network
956   */
957 typedef struct
958 {
959   __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
960   __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
961        uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
962   __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
963   __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
964   __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
965   __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
966   __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
967   __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
968   __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
969   __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
970   __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
971        uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
972   __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
973   __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
974   __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
975        uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
976   __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
977   __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
978   __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
979   __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
980        uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
981   __IO uint32_t RXGFC;        /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
982   __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x084 */
983   __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x088 */
984        uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
985   __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x090 */
986   __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x094 */
987   __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x098 */
988   __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x09C */
989        uint32_t RESERVED6[8]; /*!< Reserved,                                                                0x0A0 - 0x0BC */
990   __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
991   __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
992   __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0C8 */
993   __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0CC */
994   __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D0 */
995   __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D4 */
996   __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0D8 */
997   __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0DC */
998   __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
999   __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0E4 */
1000   __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0E8 */
1001 } FDCAN_GlobalTypeDef;
1002 
1003 /**
1004   * @brief FD Controller Area Network Configuration
1005   */
1006 typedef struct
1007 {
1008   __IO uint32_t CKDIV;        /*!< FDCAN clock divider register,                            Address offset: 0x100 + 0x000 */
1009        uint32_t RESERVED1[128];/*!< Reserved,                                               0x100 + 0x004 - 0x100 + 0x200 */
1010   __IO uint32_t OPTR;         /*!< FDCAN option register,                                   Address offset: 0x100 + 0x204 */
1011        uint32_t RESERVED2[58];/*!< Reserved,                                                0x100 + 0x208 - 0x100 + 0x2EC */
1012   __IO uint32_t HWCFG;        /*!< FDCAN hardware configuration register,                   Address offset: 0x100 + 0x2F0 */
1013   __IO uint32_t VERR;         /*!< FDCAN IP version register,                               Address offset: 0x100 + 0x2F4 */
1014   __IO uint32_t IPIDR;        /*!< FDCAN IP ID register,                                    Address offset: 0x100 + 0x2F8 */
1015   __IO uint32_t SIDR;         /*!< FDCAN size ID register,                                  Address offset: 0x100 + 0x2FC */
1016 } FDCAN_Config_TypeDef;
1017 
1018 
1019 /**
1020   * @brief ADC
1021   */
1022 typedef struct
1023 {
1024   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
1025   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
1026   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
1027   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
1028   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
1029   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
1030   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
1031        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
1032   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
1033   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
1034   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
1035        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
1036   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
1037   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
1038   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
1039   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
1040   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
1041        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
1042        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
1043   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
1044        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
1045   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
1046   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
1047   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
1048   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
1049        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
1050   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
1051   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
1052   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
1053   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
1054        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
1055   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
1056   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
1057        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
1058        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
1059   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
1060   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
1061        uint32_t RESERVED10[4];/*!< Reserved,                                             0x0B8 - 0x0C4 */
1062   __IO uint32_t OR;           /*!< ADC option register,                           Address offset: 0xC8 */
1063 } ADC_TypeDef;
1064 
1065 typedef struct
1066 {
1067   __IO uint32_t CSR;          /*!< ADC common status register,            Address offset: 0x300 + 0x00 */
1068   uint32_t      RESERVED1;    /*!< Reserved,                              Address offset: 0x300 + 0x04 */
1069   __IO uint32_t CCR;          /*!< ADC common configuration register,     Address offset: 0x300 + 0x08 */
1070   __IO uint32_t CDR;          /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
1071 } ADC_Common_TypeDef;
1072 
1073 
1074 /**
1075   * @brief IWDG
1076   */
1077 typedef struct
1078 {
1079   __IO uint32_t KR;            /*!< IWDG Key register,          Address offset: 0x00 */
1080   __IO uint32_t PR;            /*!< IWDG Prescaler register,    Address offset: 0x04 */
1081   __IO uint32_t RLR;           /*!< IWDG Reload register,       Address offset: 0x08 */
1082   __IO uint32_t SR;            /*!< IWDG Status register,       Address offset: 0x0C */
1083   __IO uint32_t WINR;          /*!< IWDG Window register,       Address offset: 0x10 */
1084   __IO uint32_t EWCR;          /*!< IWDG Early Wakeup register, Address offset: 0x14 */
1085 } IWDG_TypeDef;
1086 
1087 /**
1088   * @brief SPI
1089   */
1090 typedef struct
1091 {
1092   __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
1093   __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
1094   __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
1095   __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
1096   __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
1097   __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
1098   __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
1099   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
1100   __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
1101   uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
1102   __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
1103   uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
1104   __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
1105   __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
1106   __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
1107   __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
1108   __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
1109 } SPI_TypeDef;
1110 
1111 /**
1112   * @brief DTS
1113   */
1114 typedef struct
1115 {
1116   __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */
1117   uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */
1118   __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */
1119   uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */
1120   __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */
1121   __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */
1122   uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */
1123   __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */
1124   __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */
1125   __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */
1126   __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */
1127   __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */
1128 }
1129 DTS_TypeDef;
1130 
1131 /**
1132   * @brief WWDG
1133   */
1134 typedef struct
1135 {
1136   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
1137   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
1138   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
1139 } WWDG_TypeDef;
1140 
1141 /*@}*/ /* end of group STM32H503xx_Peripherals */
1142 
1143 
1144 /* --------  End of section using anonymous unions and disabling warnings  -------- */
1145 #if   defined (__CC_ARM)
1146   #pragma pop
1147 #elif defined (__ICCARM__)
1148   /* leave anonymous unions enabled */
1149 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
1150   #pragma clang diagnostic pop
1151 #elif defined (__GNUC__)
1152   /* anonymous unions are enabled by default */
1153 #elif defined (__TMS470__)
1154   /* anonymous unions are enabled by default */
1155 #elif defined (__TASKING__)
1156   #pragma warning restore
1157 #elif defined (__CSMC__)
1158   /* anonymous unions are enabled by default */
1159 #else
1160   #warning Not supported compiler type
1161 #endif
1162 
1163 
1164 /* =========================================================================================================================== */
1165 /* ================                          Device Specific Peripheral Address Map                           ================ */
1166 /* =========================================================================================================================== */
1167 
1168 
1169 /** @addtogroup STM32H5xx_Peripheral_peripheralAddr
1170   * @{
1171   */
1172 
1173 /* Internal SRAMs size */
1174 
1175 #define SRAM1_SIZE               (0x4000UL)    /*!< SRAM1=16k  */
1176 #define SRAM2_SIZE               (0x4000UL)    /*!< SRAM2=16k  */
1177 #define BKPSRAM_SIZE             (0x0800UL)    /*!< BKPSRAM=2k */
1178 
1179 /* Flash, Peripheral and internal SRAMs base addresses - Non secure */
1180 #define FLASH_BASE_NS            (0x08000000UL) /*!< FLASH (up to 128 KB) non-secure base address       */
1181 #define SRAM1_BASE_NS            (0x20000000UL) /*!< SRAM1 (16 KB) non-secure base address              */
1182 #define SRAM2_BASE_NS            (0x20004000UL) /*!< SRAM2 (16 KB) non-secure base address              */
1183 #define PERIPH_BASE_NS           (0x40000000UL) /*!< Peripheral non-secure base address                 */
1184 
1185 /* Peripheral memory map - Non secure */
1186 #define APB1PERIPH_BASE_NS       PERIPH_BASE_NS
1187 #define APB2PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x00010000UL)
1188 #define AHB1PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x00020000UL)
1189 #define AHB2PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x02020000UL)
1190 #define APB3PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x04000000UL)
1191 #define AHB3PERIPH_BASE_NS       (PERIPH_BASE_NS + 0x04020000UL)
1192 
1193 /*!< APB1 Non secure peripherals */
1194 #define TIM2_BASE_NS             (APB1PERIPH_BASE_NS + 0x0000UL)
1195 #define TIM3_BASE_NS             (APB1PERIPH_BASE_NS + 0x0400UL)
1196 #define TIM6_BASE_NS             (APB1PERIPH_BASE_NS + 0x1000UL)
1197 #define TIM7_BASE_NS             (APB1PERIPH_BASE_NS + 0x1400UL)
1198 #define WWDG_BASE_NS             (APB1PERIPH_BASE_NS + 0x2C00UL)
1199 #define IWDG_BASE_NS             (APB1PERIPH_BASE_NS + 0x3000UL)
1200 #define OPAMP1_BASE_NS           (APB1PERIPH_BASE_NS + 0x3400UL)
1201 #define SPI2_BASE_NS             (APB1PERIPH_BASE_NS + 0x3800UL)
1202 #define SPI3_BASE_NS             (APB1PERIPH_BASE_NS + 0x3C00UL)
1203 #define COMP1_BASE_NS            (APB1PERIPH_BASE_NS + 0x4000UL)
1204 #define USART2_BASE_NS           (APB1PERIPH_BASE_NS + 0x4400UL)
1205 #define USART3_BASE_NS           (APB1PERIPH_BASE_NS + 0x4800UL)
1206 #define I2C1_BASE_NS             (APB1PERIPH_BASE_NS + 0x5400UL)
1207 #define I2C2_BASE_NS             (APB1PERIPH_BASE_NS + 0x5800UL)
1208 #define I3C1_BASE_NS             (APB1PERIPH_BASE_NS + 0x5C00UL)
1209 #define CRS_BASE_NS              (APB1PERIPH_BASE_NS + 0x6000UL)
1210 #define DTS_BASE_NS              (APB1PERIPH_BASE_NS + 0x8C00UL)
1211 #define LPTIM2_BASE_NS           (APB1PERIPH_BASE_NS + 0x9400UL)
1212 #define FDCAN1_BASE_NS           (APB1PERIPH_BASE_NS + 0xA400UL)
1213 #define FDCAN_CONFIG_BASE_NS     (APB1PERIPH_BASE_NS + 0xA500UL)
1214 #define SRAMCAN_BASE_NS          (APB1PERIPH_BASE_NS + 0xAC00UL)
1215 
1216 /*!< APB2 Non secure peripherals */
1217 #define TIM1_BASE_NS             (APB2PERIPH_BASE_NS + 0x2C00UL)
1218 #define SPI1_BASE_NS             (APB2PERIPH_BASE_NS + 0x3000UL)
1219 #define USART1_BASE_NS           (APB2PERIPH_BASE_NS + 0x3800UL)
1220 #define USB_DRD_BASE_NS          (APB2PERIPH_BASE_NS + 0x6000UL)
1221 #define USB_DRD_PMAADDR_NS       (APB2PERIPH_BASE_NS + 0x6400UL)
1222 
1223 /*!< AHB1 Non secure peripherals */
1224 #define GPDMA1_BASE_NS           AHB1PERIPH_BASE_NS
1225 #define GPDMA2_BASE_NS           (AHB1PERIPH_BASE_NS + 0x01000UL)
1226 #define FLASH_R_BASE_NS          (AHB1PERIPH_BASE_NS + 0x02000UL)
1227 #define CRC_BASE_NS              (AHB1PERIPH_BASE_NS + 0x03000UL)
1228 #define RAMCFG_BASE_NS           (AHB1PERIPH_BASE_NS + 0x06000UL)
1229 #define ICACHE_BASE_NS           (AHB1PERIPH_BASE_NS + 0x10400UL)
1230 #define GTZC_TZSC1_BASE_NS       (AHB1PERIPH_BASE_NS + 0x12400UL)
1231 #define GTZC_MPCBB1_BASE_NS      (AHB1PERIPH_BASE_NS + 0x12C00UL)
1232 #define GTZC_MPCBB2_BASE_NS      (AHB1PERIPH_BASE_NS + 0x13000UL)
1233 #define BKPSRAM_BASE_NS          (AHB1PERIPH_BASE_NS + 0x16400UL)
1234 
1235 #define GPDMA1_Channel0_BASE_NS   (GPDMA1_BASE_NS + 0x0050UL)
1236 #define GPDMA1_Channel1_BASE_NS   (GPDMA1_BASE_NS + 0x00D0UL)
1237 #define GPDMA1_Channel2_BASE_NS   (GPDMA1_BASE_NS + 0x0150UL)
1238 #define GPDMA1_Channel3_BASE_NS   (GPDMA1_BASE_NS + 0x01D0UL)
1239 #define GPDMA1_Channel4_BASE_NS   (GPDMA1_BASE_NS + 0x0250UL)
1240 #define GPDMA1_Channel5_BASE_NS   (GPDMA1_BASE_NS + 0x02D0UL)
1241 #define GPDMA1_Channel6_BASE_NS   (GPDMA1_BASE_NS + 0x0350UL)
1242 #define GPDMA1_Channel7_BASE_NS   (GPDMA1_BASE_NS + 0x03D0UL)
1243 #define GPDMA2_Channel0_BASE_NS   (GPDMA2_BASE_NS + 0x0050UL)
1244 #define GPDMA2_Channel1_BASE_NS   (GPDMA2_BASE_NS + 0x00D0UL)
1245 #define GPDMA2_Channel2_BASE_NS   (GPDMA2_BASE_NS + 0x0150UL)
1246 #define GPDMA2_Channel3_BASE_NS   (GPDMA2_BASE_NS + 0x01D0UL)
1247 #define GPDMA2_Channel4_BASE_NS   (GPDMA2_BASE_NS + 0x0250UL)
1248 #define GPDMA2_Channel5_BASE_NS   (GPDMA2_BASE_NS + 0x02D0UL)
1249 #define GPDMA2_Channel6_BASE_NS   (GPDMA2_BASE_NS + 0x0350UL)
1250 #define GPDMA2_Channel7_BASE_NS   (GPDMA2_BASE_NS + 0x03D0UL)
1251 
1252 #define RAMCFG_SRAM1_BASE_NS     (RAMCFG_BASE_NS)
1253 #define RAMCFG_SRAM2_BASE_NS     (RAMCFG_BASE_NS + 0x0040UL)
1254 #define RAMCFG_BKPRAM_BASE_NS    (RAMCFG_BASE_NS + 0x0100UL)
1255 
1256 /*!< AHB2 Non secure peripherals */
1257 #define GPIOA_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00000UL)
1258 #define GPIOB_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00400UL)
1259 #define GPIOC_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00800UL)
1260 #define GPIOD_BASE_NS            (AHB2PERIPH_BASE_NS + 0x00C00UL)
1261 #define GPIOH_BASE_NS            (AHB2PERIPH_BASE_NS + 0x01C00UL)
1262 #define ADC1_BASE_NS             (AHB2PERIPH_BASE_NS + 0x08000UL)
1263 #define ADC12_COMMON_BASE_NS     (AHB2PERIPH_BASE_NS + 0x08300UL)
1264 #define DAC1_BASE_NS             (AHB2PERIPH_BASE_NS + 0x08400UL)
1265 
1266 #define HASH_BASE_NS             (AHB2PERIPH_BASE_NS + 0xA0400UL)
1267 #define HASH_DIGEST_BASE_NS      (AHB2PERIPH_BASE_NS + 0xA0710UL)
1268 #define RNG_BASE_NS              (AHB2PERIPH_BASE_NS + 0xA0800UL)
1269 
1270 
1271 /*!< APB3 Non secure peripherals */
1272 #define SBS_BASE_NS              (APB3PERIPH_BASE_NS + 0x0400UL)
1273 #define LPUART1_BASE_NS          (APB3PERIPH_BASE_NS + 0x2400UL)
1274 #define I3C2_BASE_NS             (APB3PERIPH_BASE_NS + 0x3000UL)
1275 #define LPTIM1_BASE_NS           (APB3PERIPH_BASE_NS + 0x4400UL)
1276 #define RTC_BASE_NS              (APB3PERIPH_BASE_NS + 0x7800UL)
1277 #define TAMP_BASE_NS             (APB3PERIPH_BASE_NS + 0x7C00UL)
1278 
1279 /*!< AHB3 Non secure peripherals */
1280 #define PWR_BASE_NS              (AHB3PERIPH_BASE_NS + 0x0800UL)
1281 #define RCC_BASE_NS              (AHB3PERIPH_BASE_NS + 0x0C00UL)
1282 #define EXTI_BASE_NS             (AHB3PERIPH_BASE_NS + 0x2000UL)
1283 #define DEBUG_BASE_NS            (AHB3PERIPH_BASE_NS + 0x4000UL)
1284 
1285 /* Debug MCU registers base address */
1286 #define DBGMCU_BASE             (0x44024000UL)
1287 
1288 #define PACKAGE_BASE            (0x08FFF80EUL) /*!< Package data register base address     */
1289 #define UID_BASE                (0x08FFF800UL) /*!< Unique device ID register base address */
1290 #define FLASHSIZE_BASE          (0x08FFF80CUL) /*!< Flash size data register base address  */
1291 
1292 
1293 /* Internal Flash OTP Area */
1294 #define FLASH_OTP_BASE          (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */
1295 #define FLASH_OTP_SIZE          (0x800U)       /*!< 2048 bytes OTP (one-time programmable)         */
1296 
1297 /* Flash system Area */
1298 #define FLASH_SYSTEM_BASE_NS    (0x0BF80000UL) /*!< FLASH System non-secure base address  */
1299 #define FLASH_SYSTEM_SIZE       (0x8000U)      /*!< 32 Kbytes system Flash */
1300 
1301 
1302 /*!< USB PMA SIZE */
1303 #define USB_DRD_PMA_SIZE        (2048U)         /*!< USB PMA Size 2Kbyte */
1304 
1305 /*!< Non Secure Service Library */
1306 /************ RSSLIB SAU system Flash region definition constants *************/
1307 #define NSSLIB_SYS_FLASH_NS_PFUNC_START   (0xBF8FE6CUL)
1308 #define NSSLIB_SYS_FLASH_NS_PFUNC_END     (0xBF8FE74UL)
1309 
1310 /************ RSSLIB function return constants ********************************/
1311 #define NSSLIB_ERROR   (0xF5F5F5F5UL)
1312 #define NSSLIB_SUCCESS (0xEAEAEAEAUL)
1313 
1314 /*!< RSSLIB  pointer function structure address definition */
1315 #define NSSLIB_PFUNC_BASE (0xBF8FE6CUL)
1316 #define NSSLIB_PFUNC      ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE)
1317 
1318 /**
1319   * @brief  Prototype of RSSLIB Jump to HDP level2 Function
1320   * @detail This function increments HDP level up to HDP level 2
1321   *         Then it enables the MPU region corresponding the MPU index
1322   *         provided as input parameter. The Vector Table shall be located
1323   *         within this MPU region.
1324   *         Then it jumps to the reset handler present within the
1325   *         Vector table. The function does not return on successful execution.
1326   * @param  pointer on the vector table containing the reset handler the function
1327   *         jumps to.
1328   * @param  MPU region index containing the vector table
1329   *         jumps to.
1330   * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
1331   */
1332 typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);
1333 
1334 /**
1335   * @brief  Prototype of RSSLIB Jump to HDP level3 Function
1336   * @detail This function increments HDP level up to HDP level 3
1337   *         Then it enables the MPU region corresponding the MPU index
1338   *         provided as input parameter. The Vector Table shall be located
1339   *         within this MPU region.
1340   *         Then it jumps to the reset handler present within the
1341   *         Vector table. The function does not return on successful execution.
1342   * @param  pointer on the vector table containing the reset handler the function
1343   *         jumps to.
1344   * @param  MPU region index containing the vector table
1345   *         jumps to.
1346   * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return.
1347   */
1348 typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex);
1349 
1350 /**
1351   * @brief RSSLib secure callable function pointer structure
1352   */
1353 typedef struct
1354 {
1355   __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2;
1356   __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3;
1357 } NSSLIB_pFunc_TypeDef;
1358 
1359 
1360 /** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */
1361 
1362 
1363 /* =========================================================================================================================== */
1364 /* ================                                  Peripheral declaration                                   ================ */
1365 /* =========================================================================================================================== */
1366 
1367 
1368 /** @addtogroup STM32H5xx_Peripheral_declaration
1369   * @{
1370   */
1371 
1372 /*!< APB1 Non secure peripherals */
1373 #define TIM2_NS                ((TIM_TypeDef *)TIM2_BASE_NS)
1374 #define TIM3_NS                ((TIM_TypeDef *)TIM3_BASE_NS)
1375 #define TIM6_NS                ((TIM_TypeDef *)TIM6_BASE_NS)
1376 #define TIM7_NS                ((TIM_TypeDef *)TIM7_BASE_NS)
1377 #define WWDG_NS                ((WWDG_TypeDef *)WWDG_BASE_NS)
1378 #define IWDG_NS                ((IWDG_TypeDef *)IWDG_BASE_NS)
1379 #define OPAMP1_NS              ((OPAMP_TypeDef *)OPAMP1_BASE_NS)
1380 #define SPI2_NS                ((SPI_TypeDef *)SPI2_BASE_NS)
1381 #define SPI3_NS                ((SPI_TypeDef *)SPI3_BASE_NS)
1382 #define COMP1_NS               ((COMP_TypeDef *)COMP1_BASE_NS)
1383 #define USART2_NS              ((USART_TypeDef *)USART2_BASE_NS)
1384 #define USART3_NS              ((USART_TypeDef *)USART3_BASE_NS)
1385 #define I2C1_NS                ((I2C_TypeDef *)I2C1_BASE_NS)
1386 #define I2C2_NS                ((I2C_TypeDef *)I2C2_BASE_NS)
1387 #define I3C1_NS                ((I3C_TypeDef *)I3C1_BASE_NS)
1388 #define CRS_NS                 ((CRS_TypeDef *)CRS_BASE_NS)
1389 #define DTS_NS                 ((DTS_TypeDef *)DTS_BASE_NS)
1390 #define LPTIM2_NS              ((LPTIM_TypeDef *)LPTIM2_BASE_NS)
1391 #define FDCAN1_NS              ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS)
1392 #define FDCAN_CONFIG_NS        ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS)
1393 
1394 /*!< APB2 Non secure peripherals */
1395 #define TIM1_NS                ((TIM_TypeDef *) TIM1_BASE_NS)
1396 #define SPI1_NS                ((SPI_TypeDef *) SPI1_BASE_NS)
1397 #define USART1_NS              ((USART_TypeDef *) USART1_BASE_NS)
1398 #define USB_DRD_FS_NS          ((USB_DRD_TypeDef *) USB_DRD_BASE_NS)
1399 #define USB_DRD_PMA_BUFF_NS    ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS)
1400 
1401 /*!< AHB1 Non secure peripherals */
1402 #define GPDMA1_NS              ((DMA_TypeDef *) GPDMA1_BASE_NS)
1403 #define GPDMA2_NS              ((DMA_TypeDef *) GPDMA2_BASE_NS)
1404 #define FLASH_NS               ((FLASH_TypeDef *) FLASH_R_BASE_NS)
1405 #define CRC_NS                 ((CRC_TypeDef *) CRC_BASE_NS)
1406 #define RAMCFG_SRAM1_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS)
1407 #define RAMCFG_SRAM2_NS        ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS)
1408 #define RAMCFG_BKPRAM_NS       ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS)
1409 #define ICACHE_NS              ((ICACHE_TypeDef *) ICACHE_BASE_NS)
1410 #define GTZC_TZSC1_NS          ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS)
1411 #define GTZC_MPCBB1_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS)
1412 #define GTZC_MPCBB2_NS         ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS)
1413 #define GPDMA1_Channel0_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
1414 #define GPDMA1_Channel1_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
1415 #define GPDMA1_Channel2_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
1416 #define GPDMA1_Channel3_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
1417 #define GPDMA1_Channel4_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
1418 #define GPDMA1_Channel5_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
1419 #define GPDMA1_Channel6_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
1420 #define GPDMA1_Channel7_NS     ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
1421 #define GPDMA2_Channel0_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS)
1422 #define GPDMA2_Channel1_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS)
1423 #define GPDMA2_Channel2_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS)
1424 #define GPDMA2_Channel3_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS)
1425 #define GPDMA2_Channel4_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS)
1426 #define GPDMA2_Channel5_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS)
1427 #define GPDMA2_Channel6_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS)
1428 #define GPDMA2_Channel7_NS     ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS)
1429 
1430 /*!< AHB2 Non secure peripherals */
1431 #define GPIOA_NS               ((GPIO_TypeDef *) GPIOA_BASE_NS)
1432 #define GPIOB_NS               ((GPIO_TypeDef *) GPIOB_BASE_NS)
1433 #define GPIOC_NS               ((GPIO_TypeDef *) GPIOC_BASE_NS)
1434 #define GPIOD_NS               ((GPIO_TypeDef *) GPIOD_BASE_NS)
1435 #define GPIOH_NS               ((GPIO_TypeDef *) GPIOH_BASE_NS)
1436 #define ADC1_NS                ((ADC_TypeDef *) ADC1_BASE_NS)
1437 #define ADC12_COMMON_NS        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
1438 #define DAC1_NS                ((DAC_TypeDef *) DAC1_BASE_NS)
1439 #define HASH_NS                ((HASH_TypeDef *) HASH_BASE_NS)
1440 #define HASH_DIGEST_NS         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
1441 #define RNG_NS                 ((RNG_TypeDef *) RNG_BASE_NS)
1442 
1443 
1444 /*!< APB3 Non secure peripherals */
1445 #define SBS_NS                 ((SBS_TypeDef *) SBS_BASE_NS)
1446 #define LPUART1_NS             ((USART_TypeDef *) LPUART1_BASE_NS)
1447 #define I3C2_NS                ((I3C_TypeDef *) I3C2_BASE_NS)
1448 #define LPTIM1_NS              ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
1449 #define RTC_NS                 ((RTC_TypeDef *) RTC_BASE_NS)
1450 #define TAMP_NS                ((TAMP_TypeDef *) TAMP_BASE_NS)
1451 
1452 /*!< AHB3 Non secure peripherals */
1453 #define PWR_NS                 ((PWR_TypeDef *) PWR_BASE_NS)
1454 #define RCC_NS                 ((RCC_TypeDef *) RCC_BASE_NS)
1455 #define EXTI_NS                ((EXTI_TypeDef *) EXTI_BASE_NS)
1456 
1457 
1458 #define DBGMCU                 ((DBGMCU_TypeDef *) DBGMCU_BASE)
1459 
1460 
1461 /*!< Memory base addresses for Non secure peripherals */
1462 #define FLASH_BASE                     FLASH_BASE_NS
1463 #define FLASH_SYSTEM_BASE              FLASH_SYSTEM_BASE_NS
1464 #define SRAM1_BASE                     SRAM1_BASE_NS
1465 #define SRAM2_BASE                     SRAM2_BASE_NS
1466 #define BKPSRAM_BASE                   BKPSRAM_BASE_NS
1467 
1468 #define PERIPH_BASE                    PERIPH_BASE_NS
1469 #define APB1PERIPH_BASE                APB1PERIPH_BASE_NS
1470 #define APB2PERIPH_BASE                APB2PERIPH_BASE_NS
1471 #define APB3PERIPH_BASE                APB3PERIPH_BASE_NS
1472 #define AHB1PERIPH_BASE                AHB1PERIPH_BASE_NS
1473 #define AHB2PERIPH_BASE                AHB2PERIPH_BASE_NS
1474 #define AHB3PERIPH_BASE                AHB3PERIPH_BASE_NS
1475 
1476 /*!< Instance aliases and base addresses for Non secure peripherals */
1477 #define RCC                            RCC_NS
1478 #define RCC_BASE                       RCC_BASE_NS
1479 
1480 #define DTS                            DTS_NS
1481 #define DTS_BASE                       DTS_BASE_NS
1482 
1483 #define FLASH                          FLASH_NS
1484 #define FLASH_R_BASE                   FLASH_R_BASE_NS
1485 
1486 #define GPDMA1                         GPDMA1_NS
1487 #define GPDMA1_BASE                    GPDMA1_BASE_NS
1488 
1489 #define GPDMA1_Channel0                GPDMA1_Channel0_NS
1490 #define GPDMA1_Channel0_BASE           GPDMA1_Channel0_BASE_NS
1491 
1492 #define GPDMA1_Channel1                GPDMA1_Channel1_NS
1493 #define GPDMA1_Channel1_BASE           GPDMA1_Channel1_BASE_NS
1494 
1495 #define GPDMA1_Channel2                GPDMA1_Channel2_NS
1496 #define GPDMA1_Channel2_BASE           GPDMA1_Channel2_BASE_NS
1497 
1498 #define GPDMA1_Channel3                GPDMA1_Channel3_NS
1499 #define GPDMA1_Channel3_BASE           GPDMA1_Channel3_BASE_NS
1500 
1501 #define GPDMA1_Channel4                GPDMA1_Channel4_NS
1502 #define GPDMA1_Channel4_BASE           GPDMA1_Channel4_BASE_NS
1503 
1504 #define GPDMA1_Channel5                GPDMA1_Channel5_NS
1505 #define GPDMA1_Channel5_BASE           GPDMA1_Channel5_BASE_NS
1506 
1507 #define GPDMA1_Channel6                GPDMA1_Channel6_NS
1508 #define GPDMA1_Channel6_BASE           GPDMA1_Channel6_BASE_NS
1509 
1510 #define GPDMA1_Channel7                GPDMA1_Channel7_NS
1511 #define GPDMA1_Channel7_BASE           GPDMA1_Channel7_BASE_NS
1512 
1513 #define GPDMA2                         GPDMA2_NS
1514 #define GPDMA2_BASE                    GPDMA2_BASE_NS
1515 
1516 #define GPDMA2_Channel0                GPDMA2_Channel0_NS
1517 #define GPDMA2_Channel0_BASE           GPDMA2_Channel0_BASE_NS
1518 
1519 #define GPDMA2_Channel1                GPDMA2_Channel1_NS
1520 #define GPDMA2_Channel1_BASE           GPDMA2_Channel1_BASE_NS
1521 
1522 #define GPDMA2_Channel2                GPDMA2_Channel2_NS
1523 #define GPDMA2_Channel2_BASE           GPDMA2_Channel2_BASE_NS
1524 
1525 #define GPDMA2_Channel3                GPDMA2_Channel3_NS
1526 #define GPDMA2_Channel3_BASE           GPDMA2_Channel3_BASE_NS
1527 
1528 #define GPDMA2_Channel4                GPDMA2_Channel4_NS
1529 #define GPDMA2_Channel4_BASE           GPDMA2_Channel4_BASE_NS
1530 
1531 #define GPDMA2_Channel5                GPDMA2_Channel5_NS
1532 #define GPDMA2_Channel5_BASE           GPDMA2_Channel5_BASE_NS
1533 
1534 #define GPDMA2_Channel6                GPDMA2_Channel6_NS
1535 #define GPDMA2_Channel6_BASE           GPDMA2_Channel6_BASE_NS
1536 
1537 #define GPDMA2_Channel7                GPDMA2_Channel7_NS
1538 #define GPDMA2_Channel7_BASE           GPDMA2_Channel7_BASE_NS
1539 
1540 #define GPIOA                          GPIOA_NS
1541 #define GPIOA_BASE                     GPIOA_BASE_NS
1542 
1543 #define GPIOB                          GPIOB_NS
1544 #define GPIOB_BASE                     GPIOB_BASE_NS
1545 
1546 #define GPIOC                          GPIOC_NS
1547 #define GPIOC_BASE                     GPIOC_BASE_NS
1548 
1549 #define GPIOD                          GPIOD_NS
1550 #define GPIOD_BASE                     GPIOD_BASE_NS
1551 
1552 #define GPIOH                          GPIOH_NS
1553 #define GPIOH_BASE                     GPIOH_BASE_NS
1554 
1555 #define PWR                            PWR_NS
1556 #define PWR_BASE                       PWR_BASE_NS
1557 
1558 #define RAMCFG_SRAM1                   RAMCFG_SRAM1_NS
1559 #define RAMCFG_SRAM1_BASE              RAMCFG_SRAM1_BASE_NS
1560 
1561 #define RAMCFG_SRAM2                   RAMCFG_SRAM2_NS
1562 #define RAMCFG_SRAM2_BASE              RAMCFG_SRAM2_BASE_NS
1563 
1564 #define RAMCFG_BKPRAM                  RAMCFG_BKPRAM_NS
1565 #define RAMCFG_BKPRAM_BASE             RAMCFG_BKPRAM_BASE_NS
1566 
1567 #define EXTI                           EXTI_NS
1568 #define EXTI_BASE                      EXTI_BASE_NS
1569 
1570 #define ICACHE                         ICACHE_NS
1571 #define ICACHE_BASE                    ICACHE_BASE_NS
1572 
1573 #define GTZC_TZSC1                     GTZC_TZSC1_NS
1574 #define GTZC_TZSC1_BASE                GTZC_TZSC1_BASE_NS
1575 
1576 #define GTZC_MPCBB1                    GTZC_MPCBB1_NS
1577 #define GTZC_MPCBB1_BASE               GTZC_MPCBB1_BASE_NS
1578 
1579 #define GTZC_MPCBB2                    GTZC_MPCBB2_NS
1580 #define GTZC_MPCBB2_BASE               GTZC_MPCBB2_BASE_NS
1581 
1582 #define RTC                            RTC_NS
1583 #define RTC_BASE                       RTC_BASE_NS
1584 
1585 #define TAMP                           TAMP_NS
1586 #define TAMP_BASE                      TAMP_BASE_NS
1587 
1588 #define TIM1                           TIM1_NS
1589 #define TIM1_BASE                      TIM1_BASE_NS
1590 
1591 #define TIM2                           TIM2_NS
1592 #define TIM2_BASE                      TIM2_BASE_NS
1593 
1594 #define TIM3                           TIM3_NS
1595 #define TIM3_BASE                      TIM3_BASE_NS
1596 
1597 #define TIM6                           TIM6_NS
1598 #define TIM6_BASE                      TIM6_BASE_NS
1599 
1600 #define TIM7                           TIM7_NS
1601 #define TIM7_BASE                      TIM7_BASE_NS
1602 
1603 #define WWDG                           WWDG_NS
1604 #define WWDG_BASE                      WWDG_BASE_NS
1605 
1606 #define IWDG                           IWDG_NS
1607 #define IWDG_BASE                      IWDG_BASE_NS
1608 
1609 #define OPAMP1                         OPAMP1_NS
1610 #define OPAMP1_BASE                    OPAMP1_BASE_NS
1611 
1612 #define SPI1                           SPI1_NS
1613 #define SPI1_BASE                      SPI1_BASE_NS
1614 
1615 #define SPI2                           SPI2_NS
1616 #define SPI2_BASE                      SPI2_BASE_NS
1617 
1618 #define SPI3                           SPI3_NS
1619 #define SPI3_BASE                      SPI3_BASE_NS
1620 
1621 #define COMP1                          COMP1_NS
1622 #define COMP1_BASE                     COMP1_BASE_NS
1623 
1624 #define USART1                         USART1_NS
1625 #define USART1_BASE                    USART1_BASE_NS
1626 
1627 #define USART2                         USART2_NS
1628 #define USART2_BASE                    USART2_BASE_NS
1629 
1630 #define USART3                         USART3_NS
1631 #define USART3_BASE                    USART3_BASE_NS
1632 
1633 #define I2C1                           I2C1_NS
1634 #define I2C1_BASE                      I2C1_BASE_NS
1635 
1636 #define I2C2                           I2C2_NS
1637 #define I2C2_BASE                      I2C2_BASE_NS
1638 
1639 #define I3C1                           I3C1_NS
1640 #define I3C1_BASE                      I3C1_BASE_NS
1641 
1642 #define I3C2                           I3C2_NS
1643 #define I3C2_BASE                      I3C2_BASE_NS
1644 
1645 #define CRS                            CRS_NS
1646 #define CRS_BASE                       CRS_BASE_NS
1647 
1648 #define FDCAN1                         FDCAN1_NS
1649 #define FDCAN1_BASE                    FDCAN1_BASE_NS
1650 
1651 #define FDCAN_CONFIG                   FDCAN_CONFIG_NS
1652 #define FDCAN_CONFIG_BASE              FDCAN_CONFIG_BASE_NS
1653 #define SRAMCAN_BASE                   SRAMCAN_BASE_NS
1654 
1655 #define DAC1                           DAC1_NS
1656 #define DAC1_BASE                      DAC1_BASE_NS
1657 
1658 #define LPTIM1                         LPTIM1_NS
1659 #define LPTIM1_BASE                    LPTIM1_BASE_NS
1660 
1661 #define LPTIM2                         LPTIM2_NS
1662 #define LPTIM2_BASE                    LPTIM2_BASE_NS
1663 
1664 #define LPUART1                        LPUART1_NS
1665 #define LPUART1_BASE                   LPUART1_BASE_NS
1666 
1667 #define SBS                            SBS_NS
1668 #define SBS_BASE                       SBS_BASE_NS
1669 
1670 #define USB_DRD_FS                     USB_DRD_FS_NS
1671 #define USB_DRD_FS_BASE                USB_DRD_BASE_NS
1672 #define USB_DRD_PMAADDR                USB_DRD_PMAADDR_NS
1673 #define USB_DRD_PMA_BUFF               USB_DRD_PMA_BUFF_NS
1674 
1675 #define CRC                            CRC_NS
1676 #define CRC_BASE                       CRC_BASE_NS
1677 
1678 #define ADC1                           ADC1_NS
1679 #define ADC1_BASE                      ADC1_BASE_NS
1680 
1681 #define ADC12_COMMON                   ADC12_COMMON_NS
1682 #define ADC12_COMMON_BASE              ADC12_COMMON_BASE_NS
1683 
1684 #define HASH                           HASH_NS
1685 #define HASH_BASE                      HASH_BASE_NS
1686 
1687 #define HASH_DIGEST                    HASH_DIGEST_NS
1688 #define HASH_DIGEST_BASE               HASH_DIGEST_BASE_NS
1689 
1690 #define RNG                            RNG_NS
1691 #define RNG_BASE                       RNG_BASE_NS
1692 
1693 
1694 /******************************************************************************/
1695 /*                                                                            */
1696 /*                        Analog to Digital Converter                         */
1697 /*                                                                            */
1698 /******************************************************************************/
1699 /********************  Bit definition for ADC_ISR register  *******************/
1700 #define ADC_ISR_ADRDY_Pos              (0U)
1701 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1702 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1703 #define ADC_ISR_EOSMP_Pos              (1U)
1704 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1705 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1706 #define ADC_ISR_EOC_Pos                (2U)
1707 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1708 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1709 #define ADC_ISR_EOS_Pos                (3U)
1710 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1711 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1712 #define ADC_ISR_OVR_Pos                (4U)
1713 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1714 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1715 #define ADC_ISR_JEOC_Pos               (5U)
1716 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
1717 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1718 #define ADC_ISR_JEOS_Pos               (6U)
1719 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
1720 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1721 #define ADC_ISR_AWD1_Pos               (7U)
1722 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1723 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1724 #define ADC_ISR_AWD2_Pos               (8U)
1725 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1726 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1727 #define ADC_ISR_AWD3_Pos               (9U)
1728 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1729 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1730 #define ADC_ISR_JQOVF_Pos              (10U)
1731 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
1732 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1733 
1734 /********************  Bit definition for ADC_IER register  *******************/
1735 #define ADC_IER_ADRDYIE_Pos            (0U)
1736 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1737 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1738 #define ADC_IER_EOSMPIE_Pos            (1U)
1739 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1740 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1741 #define ADC_IER_EOCIE_Pos              (2U)
1742 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1743 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1744 #define ADC_IER_EOSIE_Pos              (3U)
1745 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1746 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1747 #define ADC_IER_OVRIE_Pos              (4U)
1748 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1749 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1750 #define ADC_IER_JEOCIE_Pos             (5U)
1751 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
1752 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1753 #define ADC_IER_JEOSIE_Pos             (6U)
1754 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
1755 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1756 #define ADC_IER_AWD1IE_Pos             (7U)
1757 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1758 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1759 #define ADC_IER_AWD2IE_Pos             (8U)
1760 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1761 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1762 #define ADC_IER_AWD3IE_Pos             (9U)
1763 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1764 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1765 #define ADC_IER_JQOVFIE_Pos            (10U)
1766 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
1767 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1768 
1769 /********************  Bit definition for ADC_CR register  ********************/
1770 #define ADC_CR_ADEN_Pos                (0U)
1771 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1772 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1773 #define ADC_CR_ADDIS_Pos               (1U)
1774 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1775 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1776 #define ADC_CR_ADSTART_Pos             (2U)
1777 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1778 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1779 #define ADC_CR_JADSTART_Pos            (3U)
1780 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
1781 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1782 #define ADC_CR_ADSTP_Pos               (4U)
1783 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1784 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1785 #define ADC_CR_JADSTP_Pos              (5U)
1786 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
1787 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1788 #define ADC_CR_ADVREGEN_Pos            (28U)
1789 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1790 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1791 #define ADC_CR_DEEPPWD_Pos             (29U)
1792 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
1793 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1794 #define ADC_CR_ADCALDIF_Pos            (30U)
1795 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
1796 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1797 #define ADC_CR_ADCAL_Pos               (31U)
1798 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1799 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1800 
1801 /********************  Bit definition for ADC_CFGR register  ******************/
1802 #define ADC_CFGR_DMAEN_Pos             (0U)
1803 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
1804 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1805 #define ADC_CFGR_DMACFG_Pos            (1U)
1806 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
1807 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1808 
1809 #define ADC_CFGR_RES_Pos               (3U)
1810 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
1811 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1812 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
1813 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
1814 
1815 #define ADC_CFGR_EXTSEL_Pos            (5U)
1816 #define ADC_CFGR_EXTSEL_Msk            (0x1FUL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x000003E0 */
1817 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1818 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000020 */
1819 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
1820 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
1821 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
1822 #define ADC_CFGR_EXTSEL_4              (0x10UL << ADC_CFGR_EXTSEL_Pos)         /*!< 0x00000200 */
1823 
1824 #define ADC_CFGR_EXTEN_Pos             (10U)
1825 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
1826 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1827 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
1828 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
1829 
1830 #define ADC_CFGR_OVRMOD_Pos            (12U)
1831 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
1832 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1833 #define ADC_CFGR_CONT_Pos              (13U)
1834 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
1835 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1836 #define ADC_CFGR_AUTDLY_Pos            (14U)
1837 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
1838 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1839 #define ADC_CFGR_ALIGN_Pos             (15U)
1840 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00008000 */
1841 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
1842 #define ADC_CFGR_DISCEN_Pos            (16U)
1843 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
1844 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1845 
1846 #define ADC_CFGR_DISCNUM_Pos           (17U)
1847 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
1848 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1849 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
1850 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
1851 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
1852 
1853 #define ADC_CFGR_JDISCEN_Pos           (20U)
1854 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
1855 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1856 #define ADC_CFGR_JQM_Pos               (21U)
1857 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
1858 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1859 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1860 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
1861 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1862 #define ADC_CFGR_AWD1EN_Pos            (23U)
1863 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
1864 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1865 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1866 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
1867 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1868 #define ADC_CFGR_JAUTO_Pos             (25U)
1869 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
1870 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1871 
1872 #define ADC_CFGR_AWD1CH_Pos            (26U)
1873 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
1874 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1875 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
1876 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
1877 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
1878 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
1879 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
1880 
1881 #define ADC_CFGR_JQDIS_Pos             (31U)
1882 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
1883 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1884 
1885 /********************  Bit definition for ADC_CFGR2 register  *****************/
1886 #define ADC_CFGR2_ROVSE_Pos            (0U)
1887 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
1888 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1889 #define ADC_CFGR2_JOVSE_Pos            (1U)
1890 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
1891 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1892 
1893 #define ADC_CFGR2_OVSR_Pos             (2U)
1894 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1895 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1896 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1897 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1898 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1899 
1900 #define ADC_CFGR2_OVSS_Pos             (5U)
1901 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1902 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1903 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1904 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1905 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1906 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1907 
1908 #define ADC_CFGR2_TROVS_Pos            (9U)
1909 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
1910 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1911 #define ADC_CFGR2_ROVSM_Pos            (10U)
1912 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
1913 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1914 
1915 #define ADC_CFGR2_GCOMP_Pos            (16U)
1916 #define ADC_CFGR2_GCOMP_Msk            (0x1UL << ADC_CFGR2_GCOMP_Pos)          /*!< 0x00010000 */
1917 #define ADC_CFGR2_GCOMP                ADC_CFGR2_GCOMP_Msk                     /*!< ADC Gain Compensation mode */
1918 
1919 #define ADC_CFGR2_SWTRIG_Pos           (25U)
1920 #define ADC_CFGR2_SWTRIG_Msk           (0x1UL << ADC_CFGR2_SWTRIG_Pos)         /*!< 0x02000000 */
1921 #define ADC_CFGR2_SWTRIG               ADC_CFGR2_SWTRIG_Msk                    /*!< ADC Software Trigger Bit for Sample time control trigger mode */
1922 #define ADC_CFGR2_BULB_Pos             (26U)
1923 #define ADC_CFGR2_BULB_Msk             (0x1UL << ADC_CFGR2_BULB_Pos)           /*!< 0x04000000 */
1924 #define ADC_CFGR2_BULB                 ADC_CFGR2_BULB_Msk                      /*!< ADC Bulb sampling mode */
1925 #define ADC_CFGR2_SMPTRIG_Pos          (27U)
1926 #define ADC_CFGR2_SMPTRIG_Msk          (0x1UL << ADC_CFGR2_SMPTRIG_Pos)        /*!< 0x08000000 */
1927 #define ADC_CFGR2_SMPTRIG              ADC_CFGR2_SMPTRIG_Msk                   /*!< ADC Sample Time Control Trigger mode */
1928 
1929 #define ADC_CFGR2_LFTRIG_Pos           (29U)
1930 #define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
1931 #define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC Low Frequency Trigger */
1932 
1933 /********************  Bit definition for ADC_SMPR1 register  *****************/
1934 #define ADC_SMPR1_SMP0_Pos             (0U)
1935 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
1936 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1937 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
1938 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
1939 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
1940 
1941 #define ADC_SMPR1_SMP1_Pos             (3U)
1942 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
1943 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1944 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
1945 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
1946 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
1947 
1948 #define ADC_SMPR1_SMP2_Pos             (6U)
1949 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
1950 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1951 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
1952 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
1953 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
1954 
1955 #define ADC_SMPR1_SMP3_Pos             (9U)
1956 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
1957 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1958 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
1959 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
1960 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
1961 
1962 #define ADC_SMPR1_SMP4_Pos             (12U)
1963 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
1964 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1965 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
1966 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
1967 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
1968 
1969 #define ADC_SMPR1_SMP5_Pos             (15U)
1970 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
1971 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1972 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
1973 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
1974 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
1975 
1976 #define ADC_SMPR1_SMP6_Pos             (18U)
1977 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
1978 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1979 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
1980 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
1981 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
1982 
1983 #define ADC_SMPR1_SMP7_Pos             (21U)
1984 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
1985 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1986 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
1987 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
1988 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
1989 
1990 #define ADC_SMPR1_SMP8_Pos             (24U)
1991 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
1992 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1993 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
1994 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
1995 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
1996 
1997 #define ADC_SMPR1_SMP9_Pos             (27U)
1998 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
1999 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
2000 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
2001 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
2002 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
2003 
2004 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
2005 #define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
2006 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
2007 
2008 /********************  Bit definition for ADC_SMPR2 register  *****************/
2009 #define ADC_SMPR2_SMP10_Pos            (0U)
2010 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
2011 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
2012 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
2013 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
2014 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
2015 
2016 #define ADC_SMPR2_SMP11_Pos            (3U)
2017 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
2018 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
2019 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
2020 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
2021 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
2022 
2023 #define ADC_SMPR2_SMP12_Pos            (6U)
2024 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
2025 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
2026 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
2027 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
2028 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
2029 
2030 #define ADC_SMPR2_SMP13_Pos            (9U)
2031 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
2032 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
2033 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
2034 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
2035 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
2036 
2037 #define ADC_SMPR2_SMP14_Pos            (12U)
2038 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
2039 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
2040 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
2041 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
2042 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
2043 
2044 #define ADC_SMPR2_SMP15_Pos            (15U)
2045 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
2046 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
2047 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
2048 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
2049 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
2050 
2051 #define ADC_SMPR2_SMP16_Pos            (18U)
2052 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
2053 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
2054 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
2055 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
2056 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
2057 
2058 #define ADC_SMPR2_SMP17_Pos            (21U)
2059 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
2060 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
2061 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
2062 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
2063 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
2064 
2065 #define ADC_SMPR2_SMP18_Pos            (24U)
2066 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
2067 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
2068 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
2069 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
2070 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
2071 
2072 /********************  Bit definition for ADC_TR1 register  *******************/
2073 #define ADC_TR1_LT1_Pos                (0U)
2074 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
2075 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
2076 
2077 #define ADC_TR1_AWDFILT_Pos            (12U)
2078 #define ADC_TR1_AWDFILT_Msk            (0x7UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00007000 */
2079 #define ADC_TR1_AWDFILT                ADC_TR1_AWDFILT_Msk                     /*!< ADC analog watchdog filtering parameter  */
2080 #define ADC_TR1_AWDFILT_0              (0x1UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00001000 */
2081 #define ADC_TR1_AWDFILT_1              (0x2UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00002000 */
2082 #define ADC_TR1_AWDFILT_2              (0x4UL << ADC_TR1_AWDFILT_Pos)          /*!< 0x00004000 */
2083 
2084 #define ADC_TR1_HT1_Pos                (16U)
2085 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
2086 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC analog watchdog 1 threshold high */
2087 
2088 /********************  Bit definition for ADC_TR2 register  *******************/
2089 #define ADC_TR2_LT2_Pos                (0U)
2090 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
2091 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
2092 
2093 #define ADC_TR2_HT2_Pos                (16U)
2094 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
2095 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
2096 
2097 /********************  Bit definition for ADC_TR3 register  *******************/
2098 #define ADC_TR3_LT3_Pos                (0U)
2099 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
2100 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
2101 
2102 #define ADC_TR3_HT3_Pos                (16U)
2103 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
2104 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
2105 
2106 /********************  Bit definition for ADC_SQR1 register  ******************/
2107 #define ADC_SQR1_L_Pos                 (0U)
2108 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
2109 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
2110 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
2111 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
2112 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
2113 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
2114 
2115 #define ADC_SQR1_SQ1_Pos               (6U)
2116 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
2117 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
2118 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
2119 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
2120 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
2121 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
2122 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
2123 
2124 #define ADC_SQR1_SQ2_Pos               (12U)
2125 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
2126 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
2127 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
2128 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
2129 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
2130 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
2131 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
2132 
2133 #define ADC_SQR1_SQ3_Pos               (18U)
2134 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
2135 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
2136 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
2137 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
2138 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
2139 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
2140 #define ADC_SQR1_SQ3_4                 (0x10UL<< ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
2141 
2142 #define ADC_SQR1_SQ4_Pos               (24U)
2143 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
2144 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
2145 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
2146 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
2147 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
2148 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
2149 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
2150 
2151 /********************  Bit definition for ADC_SQR2 register  ******************/
2152 #define ADC_SQR2_SQ5_Pos               (0U)
2153 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
2154 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
2155 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
2156 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
2157 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
2158 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
2159 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
2160 
2161 #define ADC_SQR2_SQ6_Pos               (6U)
2162 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
2163 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
2164 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
2165 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
2166 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
2167 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
2168 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
2169 
2170 #define ADC_SQR2_SQ7_Pos               (12U)
2171 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
2172 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
2173 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
2174 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
2175 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
2176 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
2177 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
2178 
2179 #define ADC_SQR2_SQ8_Pos               (18U)
2180 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
2181 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
2182 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
2183 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
2184 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
2185 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
2186 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
2187 
2188 #define ADC_SQR2_SQ9_Pos               (24U)
2189 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
2190 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
2191 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
2192 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
2193 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
2194 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
2195 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
2196 
2197 /********************  Bit definition for ADC_SQR3 register  ******************/
2198 #define ADC_SQR3_SQ10_Pos              (0U)
2199 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
2200 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
2201 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
2202 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
2203 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
2204 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
2205 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
2206 
2207 #define ADC_SQR3_SQ11_Pos              (6U)
2208 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
2209 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
2210 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
2211 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
2212 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
2213 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
2214 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
2215 
2216 #define ADC_SQR3_SQ12_Pos              (12U)
2217 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
2218 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
2219 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
2220 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
2221 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
2222 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
2223 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
2224 
2225 #define ADC_SQR3_SQ13_Pos              (18U)
2226 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
2227 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
2228 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
2229 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
2230 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
2231 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
2232 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
2233 
2234 #define ADC_SQR3_SQ14_Pos              (24U)
2235 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
2236 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
2237 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
2238 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
2239 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
2240 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
2241 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
2242 
2243 /********************  Bit definition for ADC_SQR4 register  ******************/
2244 #define ADC_SQR4_SQ15_Pos              (0U)
2245 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
2246 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
2247 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
2248 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
2249 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
2250 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
2251 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
2252 
2253 #define ADC_SQR4_SQ16_Pos              (6U)
2254 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
2255 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
2256 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
2257 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
2258 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
2259 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
2260 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
2261 
2262 /********************  Bit definition for ADC_DR register  ********************/
2263 #define ADC_DR_RDATA_Pos               (0U)
2264 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
2265 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
2266 
2267 /********************  Bit definition for ADC_JSQR register  ******************/
2268 #define ADC_JSQR_JL_Pos                (0U)
2269 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
2270 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
2271 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
2272 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
2273 
2274 #define ADC_JSQR_JEXTSEL_Pos           (2U)
2275 #define ADC_JSQR_JEXTSEL_Msk           (0x1FUL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x0000007C */
2276 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
2277 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
2278 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
2279 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
2280 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
2281 #define ADC_JSQR_JEXTSEL_4             (0x10UL << ADC_JSQR_JEXTSEL_Pos)        /*!< 0x00000040 */
2282 
2283 #define ADC_JSQR_JEXTEN_Pos            (7U)
2284 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000180 */
2285 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
2286 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
2287 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000100 */
2288 
2289 #define ADC_JSQR_JSQ1_Pos              (9U)
2290 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00003E00 */
2291 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
2292 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
2293 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
2294 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
2295 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
2296 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00002000 */
2297 
2298 #define ADC_JSQR_JSQ2_Pos              (15U)
2299 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
2300 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
2301 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
2302 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
2303 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
2304 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
2305 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
2306 
2307 #define ADC_JSQR_JSQ3_Pos              (21U)
2308 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x03E00000 */
2309 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
2310 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
2311 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
2312 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
2313 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
2314 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x02000000 */
2315 
2316 #define ADC_JSQR_JSQ4_Pos              (27U)
2317 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0xF8000000 */
2318 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
2319 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
2320 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
2321 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
2322 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
2323 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x80000000 */
2324 
2325 /********************  Bit definition for ADC_OFR1 register  ******************/
2326 #define ADC_OFR1_OFFSET1_Pos           (0U)
2327 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
2328 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
2329 
2330 #define ADC_OFR1_OFFSETPOS_Pos         (24U)
2331 #define ADC_OFR1_OFFSETPOS_Msk         (0x1UL << ADC_OFR1_OFFSETPOS_Pos)       /*!< 0x01000000 */
2332 #define ADC_OFR1_OFFSETPOS             ADC_OFR1_OFFSETPOS_Msk                  /*!< ADC offset number 1 positive */
2333 #define ADC_OFR1_SATEN_Pos             (25U)
2334 #define ADC_OFR1_SATEN_Msk             (0x1UL << ADC_OFR1_SATEN_Pos)           /*!< 0x02000000 */
2335 #define ADC_OFR1_SATEN                 ADC_OFR1_SATEN_Msk                      /*!< ADC offset number 1 saturation enable */
2336 
2337 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
2338 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
2339 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
2340 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
2341 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
2342 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
2343 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
2344 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
2345 
2346 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
2347 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
2348 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
2349 
2350 /********************  Bit definition for ADC_OFR2 register  ******************/
2351 #define ADC_OFR2_OFFSET2_Pos           (0U)
2352 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
2353 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
2354 
2355 #define ADC_OFR2_OFFSETPOS_Pos         (24U)
2356 #define ADC_OFR2_OFFSETPOS_Msk         (0x1UL << ADC_OFR2_OFFSETPOS_Pos)       /*!< 0x01000000 */
2357 #define ADC_OFR2_OFFSETPOS             ADC_OFR2_OFFSETPOS_Msk                  /*!< ADC offset number 2 positive */
2358 #define ADC_OFR2_SATEN_Pos             (25U)
2359 #define ADC_OFR2_SATEN_Msk             (0x1UL << ADC_OFR2_SATEN_Pos)           /*!< 0x02000000 */
2360 #define ADC_OFR2_SATEN                 ADC_OFR2_SATEN_Msk                      /*!< ADC offset number 2 saturation enable */
2361 
2362 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
2363 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
2364 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
2365 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
2366 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
2367 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
2368 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
2369 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
2370 
2371 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
2372 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
2373 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
2374 
2375 /********************  Bit definition for ADC_OFR3 register  ******************/
2376 #define ADC_OFR3_OFFSET3_Pos           (0U)
2377 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
2378 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
2379 
2380 #define ADC_OFR3_OFFSETPOS_Pos         (24U)
2381 #define ADC_OFR3_OFFSETPOS_Msk         (0x1UL << ADC_OFR3_OFFSETPOS_Pos)       /*!< 0x01000000 */
2382 #define ADC_OFR3_OFFSETPOS             ADC_OFR3_OFFSETPOS_Msk                  /*!< ADC offset number 3 positive */
2383 #define ADC_OFR3_SATEN_Pos             (25U)
2384 #define ADC_OFR3_SATEN_Msk             (0x1UL << ADC_OFR3_SATEN_Pos)           /*!< 0x02000000 */
2385 #define ADC_OFR3_SATEN                 ADC_OFR3_SATEN_Msk                      /*!< ADC offset number 3 saturation enable */
2386 
2387 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
2388 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
2389 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
2390 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
2391 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
2392 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
2393 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
2394 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
2395 
2396 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
2397 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
2398 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
2399 
2400 /********************  Bit definition for ADC_OFR4 register  ******************/
2401 #define ADC_OFR4_OFFSET4_Pos           (0U)
2402 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
2403 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
2404 
2405 #define ADC_OFR4_OFFSETPOS_Pos         (24U)
2406 #define ADC_OFR4_OFFSETPOS_Msk         (0x1UL << ADC_OFR4_OFFSETPOS_Pos)       /*!< 0x01000000 */
2407 #define ADC_OFR4_OFFSETPOS             ADC_OFR4_OFFSETPOS_Msk                  /*!< ADC offset number 4 positive */
2408 #define ADC_OFR4_SATEN_Pos             (25U)
2409 #define ADC_OFR4_SATEN_Msk             (0x1UL << ADC_OFR4_SATEN_Pos)           /*!< 0x02000000 */
2410 #define ADC_OFR4_SATEN                 ADC_OFR4_SATEN_Msk                      /*!< ADC offset number 4 saturation enable */
2411 
2412 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
2413 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
2414 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
2415 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
2416 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
2417 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
2418 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
2419 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
2420 
2421 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
2422 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
2423 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
2424 
2425 /********************  Bit definition for ADC_JDR1 register  ******************/
2426 #define ADC_JDR1_JDATA_Pos             (0U)
2427 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
2428 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
2429 
2430 /********************  Bit definition for ADC_JDR2 register  ******************/
2431 #define ADC_JDR2_JDATA_Pos             (0U)
2432 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
2433 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
2434 
2435 /********************  Bit definition for ADC_JDR3 register  ******************/
2436 #define ADC_JDR3_JDATA_Pos             (0U)
2437 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
2438 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
2439 
2440 /********************  Bit definition for ADC_JDR4 register  ******************/
2441 #define ADC_JDR4_JDATA_Pos             (0U)
2442 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
2443 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
2444 
2445 /********************  Bit definition for ADC_AWD2CR register  ****************/
2446 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
2447 #define ADC_AWD2CR_AWD2CH_Msk          (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
2448 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
2449 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
2450 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
2451 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
2452 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
2453 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
2454 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
2455 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
2456 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
2457 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
2458 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
2459 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
2460 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
2461 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
2462 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
2463 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
2464 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
2465 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
2466 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
2467 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
2468 #define ADC_AWD2CR_AWD2CH_19           (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00080000 */
2469 
2470 /********************  Bit definition for ADC_AWD3CR register  ****************/
2471 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
2472 #define ADC_AWD3CR_AWD3CH_Msk          (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
2473 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
2474 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
2475 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
2476 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
2477 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
2478 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
2479 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
2480 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
2481 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
2482 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
2483 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
2484 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
2485 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
2486 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
2487 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
2488 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
2489 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
2490 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
2491 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
2492 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
2493 #define ADC_AWD3CR_AWD2CH_19           (0x80000UL << ADC_AWD3CR_AWD2CH_Pos)    /*!< 0x00080000 */
2494 
2495 /********************  Bit definition for ADC_DIFSEL register  ****************/
2496 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
2497 #define ADC_DIFSEL_DIFSEL_Msk          (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
2498 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
2499 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
2500 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
2501 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
2502 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
2503 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
2504 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
2505 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
2506 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
2507 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
2508 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
2509 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
2510 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
2511 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
2512 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
2513 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
2514 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
2515 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
2516 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
2517 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
2518 #define ADC_DIFSEL_DIFSEL_19           (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00080000 */
2519 
2520 /********************  Bit definition for ADC_CALFACT register  ***************/
2521 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
2522 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
2523 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
2524 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
2525 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
2526 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
2527 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
2528 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
2529 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
2530 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000030 */
2531 
2532 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
2533 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
2534 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
2535 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
2536 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
2537 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
2538 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
2539 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
2540 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
2541 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00300000 */
2542 
2543 /********************  Bit definition for ADC_OR register  *****************/
2544 #define ADC_OR_OP0_Pos       (0U)
2545 #define ADC_OR_OP0_Msk       (0x01UL << ADC_OR_OP0_Pos)                        /*!< 0x00000001 */
2546 #define ADC_OR_OP0           ADC_OR_OP0_Msk                                    /*!< ADC Option bit 0 */
2547 #define ADC_OR_OP1_Pos       (1U)
2548 #define ADC_OR_OP1_Msk       (0x01UL << ADC_OR_OP1_Pos)                        /*!< 0x00000001 */
2549 #define ADC_OR_OP1           ADC_OR_OP1_Msk                                    /*!< ADC Option bit 1 */
2550 
2551 /*************************  ADC Common registers  *****************************/
2552 /********************  Bit definition for ADC_CSR register  *******************/
2553 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2554 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
2555 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2556 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2557 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
2558 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2559 #define ADC_CSR_EOC_MST_Pos            (2U)
2560 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
2561 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2562 #define ADC_CSR_EOS_MST_Pos            (3U)
2563 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
2564 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2565 #define ADC_CSR_OVR_MST_Pos            (4U)
2566 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
2567 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2568 #define ADC_CSR_JEOC_MST_Pos           (5U)
2569 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
2570 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2571 #define ADC_CSR_JEOS_MST_Pos           (6U)
2572 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
2573 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2574 #define ADC_CSR_AWD1_MST_Pos           (7U)
2575 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
2576 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2577 #define ADC_CSR_AWD2_MST_Pos           (8U)
2578 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
2579 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2580 #define ADC_CSR_AWD3_MST_Pos           (9U)
2581 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
2582 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2583 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2584 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
2585 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2586 
2587 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2588 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
2589 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2590 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2591 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
2592 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2593 #define ADC_CSR_EOC_SLV_Pos            (18U)
2594 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
2595 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2596 #define ADC_CSR_EOS_SLV_Pos            (19U)
2597 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
2598 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2599 #define ADC_CSR_OVR_SLV_Pos            (20U)
2600 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
2601 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2602 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2603 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
2604 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2605 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2606 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
2607 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2608 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2609 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
2610 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2611 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2612 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
2613 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2614 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2615 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
2616 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2617 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2618 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
2619 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2620 
2621 /********************  Bit definition for ADC_CCR register  *******************/
2622 #define ADC_CCR_DUAL_Pos               (0U)
2623 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
2624 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2625 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
2626 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
2627 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
2628 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
2629 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
2630 
2631 #define ADC_CCR_DELAY_Pos              (8U)
2632 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
2633 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2634 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
2635 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
2636 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
2637 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
2638 
2639 #define ADC_CCR_DMACFG_Pos             (13U)
2640 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
2641 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2642 
2643 #define ADC_CCR_MDMA_Pos               (14U)
2644 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
2645 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2646 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
2647 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
2648 
2649 #define ADC_CCR_CKMODE_Pos             (16U)
2650 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
2651 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2652 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
2653 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
2654 
2655 #define ADC_CCR_PRESC_Pos              (18U)
2656 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
2657 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2658 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
2659 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
2660 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
2661 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
2662 
2663 #define ADC_CCR_VREFEN_Pos             (22U)
2664 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
2665 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2666 #define ADC_CCR_TSEN_Pos               (23U)
2667 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
2668 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
2669 #define ADC_CCR_VBATEN_Pos             (24U)
2670 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
2671 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
2672 
2673 /********************  Bit definition for ADC_CDR register  *******************/
2674 #define ADC_CDR_RDATA_MST_Pos          (0U)
2675 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
2676 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2677 
2678 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2679 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
2680 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2681 
2682 
2683 /**********************************************************************************************************************/
2684 /*                                                                                                                    */
2685 /*                                            Analog Comparators (COMP)                                               */
2686 /*                                                                                                                    */
2687 /**********************************************************************************************************************/
2688 
2689 /**********************************      Bit definition for COMP_SR register  *****************************************/
2690 #define COMP_SR_C1VAL_Pos            (0U)
2691 #define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)          /*!< 0x00000001                            */
2692 #define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk
2693 
2694 #define COMP_SR_C1IF_Pos             (16U)
2695 #define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)           /*!< 0x00010000                            */
2696 #define COMP_SR_C1IF                 COMP_SR_C1IF_Msk
2697 
2698 /**********************************     Bit definition for COMP_ICFR register *****************************************/
2699 #define COMP_ICFR_CC1IF_Pos          (16U)
2700 #define COMP_ICFR_CC1IF_Msk          (0x1UL << COMP_ICFR_CC1IF_Pos)        /*!< 0x00010000                            */
2701 #define COMP_ICFR_CC1IF              COMP_ICFR_CC1IF_Msk
2702 
2703 /**********************************      Bit definition for COMP_CFGR1 register  **************************************/
2704 #define COMP_CFGR1_EN_Pos            (0U)
2705 #define COMP_CFGR1_EN_Msk            (0x1UL << COMP_CFGR1_EN_Pos)          /*!< 0x00000001                            */
2706 #define COMP_CFGR1_EN                COMP_CFGR1_EN_Msk                     /*!< COMP1 enable bit                      */
2707 
2708 #define COMP_CFGR1_BRGEN_Pos         (1U)
2709 #define COMP_CFGR1_BRGEN_Msk         (0x1UL << COMP_CFGR1_BRGEN_Pos)       /*!< 0x00000002                            */
2710 #define COMP_CFGR1_BRGEN             COMP_CFGR1_BRGEN_Msk                  /*!< COMP1 Scaler bridge enable            */
2711 
2712 #define COMP_CFGR1_SCALEN_Pos        (2U)
2713 #define COMP_CFGR1_SCALEN_Msk        (0x1UL << COMP_CFGR1_SCALEN_Pos)      /*!< 0x00000004                            */
2714 #define COMP_CFGR1_SCALEN            COMP_CFGR1_SCALEN_Msk                 /*!< COMP1 Voltage scaler enable bit       */
2715 
2716 #define COMP_CFGR1_POLARITY_Pos      (3U)
2717 #define COMP_CFGR1_POLARITY_Msk      (0x1UL << COMP_CFGR1_POLARITY_Pos)    /*!< 0x00000008                            */
2718 #define COMP_CFGR1_POLARITY          COMP_CFGR1_POLARITY_Msk               /*!< COMP1 polarity selection bit          */
2719 
2720 #define COMP_CFGR1_ITEN_Pos          (6U)
2721 #define COMP_CFGR1_ITEN_Msk          (0x1UL << COMP_CFGR1_ITEN_Pos)        /*!< 0x00000040                            */
2722 #define COMP_CFGR1_ITEN              COMP_CFGR1_ITEN_Msk                   /*!< COMP1 interrupt enable                */
2723 
2724 #define COMP_CFGR1_HYST_Pos          (8U)
2725 #define COMP_CFGR1_HYST_Msk          (0x3UL << COMP_CFGR1_HYST_Pos)        /*!< 0x00000300                            */
2726 #define COMP_CFGR1_HYST              COMP_CFGR1_HYST_Msk                   /*!< COMP1 hysteresis selection bits       */
2727 #define COMP_CFGR1_HYST_0            (0x1UL << COMP_CFGR1_HYST_Pos)        /*!< 0x00000100                            */
2728 #define COMP_CFGR1_HYST_1            (0x2UL << COMP_CFGR1_HYST_Pos)        /*!< 0x00000200                            */
2729 
2730 #define COMP_CFGR1_PWRMODE_Pos       (12U)
2731 #define COMP_CFGR1_PWRMODE_Msk       (0x3UL << COMP_CFGR1_PWRMODE_Pos)     /*!< 0x00003000                            */
2732 #define COMP_CFGR1_PWRMODE           COMP_CFGR1_PWRMODE_Msk                /*!< COMP1 Power Mode of the comparator    */
2733 #define COMP_CFGR1_PWRMODE_0         (0x1UL << COMP_CFGR1_PWRMODE_Pos)     /*!< 0x00001000                            */
2734 #define COMP_CFGR1_PWRMODE_1         (0x2UL << COMP_CFGR1_PWRMODE_Pos)     /*!< 0x00002000                            */
2735 
2736 #define COMP_CFGR1_INMSEL_Pos        (16U)
2737 #define COMP_CFGR1_INMSEL_Msk        (0xFUL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x000F0000                            */
2738 #define COMP_CFGR1_INMSEL            COMP_CFGR1_INMSEL_Msk                 /*!< COMP1 input minus selection bit       */
2739 #define COMP_CFGR1_INMSEL_0          (0x1UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00010000                            */
2740 #define COMP_CFGR1_INMSEL_1          (0x2UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00020000                            */
2741 #define COMP_CFGR1_INMSEL_2          (0x4UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00040000                            */
2742 #define COMP_CFGR1_INMSEL_3          (0x8UL << COMP_CFGR1_INMSEL_Pos)      /*!< 0x00080000                            */
2743 
2744 #define COMP_CFGR1_INPSEL1_Pos       (20U)
2745 #define COMP_CFGR1_INPSEL1_Msk       (0x1UL << COMP_CFGR1_INPSEL1_Pos)     /*!< 0x00100000                            */
2746 #define COMP_CFGR1_INPSEL1           COMP_CFGR1_INPSEL1_Msk                /*!< COMP1 input plus 1 selection bit      */
2747 
2748 #define COMP_CFGR1_INPSEL2_Pos       (22U)
2749 #define COMP_CFGR1_INPSEL2_Msk       (0x1UL << COMP_CFGR1_INPSEL2_Pos)     /*!< 0x00400000                            */
2750 #define COMP_CFGR1_INPSEL2           COMP_CFGR1_INPSEL2_Msk                /*!< COMP1 input plus 2 selection bit      */
2751 
2752 #define COMP_CFGR1_BLANKING_Pos      (24U)
2753 #define COMP_CFGR1_BLANKING_Msk      (0xFUL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x0F000000                            */
2754 #define COMP_CFGR1_BLANKING          COMP_CFGR1_BLANKING_Msk               /*!< COMP1 blanking source selection bits  */
2755 #define COMP_CFGR1_BLANKING_0        (0x1UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x01000000                            */
2756 #define COMP_CFGR1_BLANKING_1        (0x2UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x02000000                            */
2757 #define COMP_CFGR1_BLANKING_2        (0x4UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x04000000                            */
2758 #define COMP_CFGR1_BLANKING_3        (0x8UL << COMP_CFGR1_BLANKING_Pos)    /*!< 0x08000000                            */
2759 
2760 #define COMP_CFGR1_LOCK_Pos          (31U)
2761 #define COMP_CFGR1_LOCK_Msk          (0x1UL << COMP_CFGR1_LOCK_Pos)        /*!< 0x80000000                            */
2762 #define COMP_CFGR1_LOCK              COMP_CFGR1_LOCK_Msk                   /*!< COMP1 Lock Bit                        */
2763 
2764 /*********************************  Bit definition for COMP_CFGR2 register  *******************************************/
2765 #define COMP_CFGR2_INPSEL0_Pos       (4U)
2766 #define COMP_CFGR2_INPSEL0_Msk       (0x1UL << COMP_CFGR2_INPSEL0_Pos)     /*!< 0x00000010                            */
2767 #define COMP_CFGR2_INPSEL0           COMP_CFGR2_INPSEL0_Msk                /*!< COMP1 input plus 0 selection bit      */
2768 
2769 /**********************************************************************************************************************/
2770 /*                                                                                                                    */
2771 /*                                        Operational Amplifier (OPAMP)                                               */
2772 /*                                                                                                                    */
2773 /**********************************************************************************************************************/
2774 
2775 /**********************************   Bit definition for OPAMP_CSR register   *****************************************/
2776 #define OPAMP_CSR_OPAMPxEN_Pos        (0U)
2777 #define OPAMP_CSR_OPAMPxEN_Msk        (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001                               */
2778 #define OPAMP_CSR_OPAMPxEN            OPAMP_CSR_OPAMPxEN_Msk            /*!< OPAMP enable                             */
2779 
2780 #define OPAMP_CSR_FORCEVP_Pos         (1U)
2781 #define OPAMP_CSR_FORCEVP_Msk         (0x1UL << OPAMP_CSR_FORCEVP_Pos)  /*!< 0x00000002                               */
2782 #define OPAMP_CSR_FORCEVP             OPAMP_CSR_FORCEVP_Msk             /*!< Force internal reference on VP           */
2783 
2784 #define OPAMP_CSR_VPSEL_Pos           (2U)
2785 #define OPAMP_CSR_VPSEL_Msk           (0x3UL << OPAMP_CSR_VPSEL_Pos)    /*!< 0x0000000C                               */
2786 #define OPAMP_CSR_VPSEL               OPAMP_CSR_VPSEL_Msk               /*!< Non inverted input selection             */
2787 #define OPAMP_CSR_VPSEL_0             (0x1UL << OPAMP_CSR_VPSEL_Pos)    /*!< 0x00000004                               */
2788 #define OPAMP_CSR_VPSEL_1             (0x2UL << OPAMP_CSR_VPSEL_Pos)    /*!< 0x00000008                               */
2789 
2790 #define OPAMP_CSR_VMSEL_Pos           (5U)
2791 #define OPAMP_CSR_VMSEL_Msk           (0x3UL << OPAMP_CSR_VMSEL_Pos)    /*!< 0x00000060                               */
2792 #define OPAMP_CSR_VMSEL               OPAMP_CSR_VMSEL_Msk               /*!< Inverting input selection                */
2793 #define OPAMP_CSR_VMSEL_0             (0x1UL << OPAMP_CSR_VMSEL_Pos)    /*!< 0x00000020                               */
2794 #define OPAMP_CSR_VMSEL_1             (0x2UL << OPAMP_CSR_VMSEL_Pos)    /*!< 0x00000040                               */
2795 
2796 #define OPAMP_CSR_OPAHSM_Pos          (8U)
2797 #define OPAMP_CSR_OPAHSM_Msk          (0x1UL << OPAMP_CSR_OPAHSM_Pos)   /*!< 0x00000100                               */
2798 #define OPAMP_CSR_OPAHSM              OPAMP_CSR_OPAHSM_Msk              /*!< high speed mode                          */
2799 
2800 #define OPAMP_CSR_CALON_Pos           (11U)
2801 #define OPAMP_CSR_CALON_Msk           (0x1UL << OPAMP_CSR_CALON_Pos)    /*!< 0x00000800                               */
2802 #define OPAMP_CSR_CALON               OPAMP_CSR_CALON_Msk               /*!< Calibration mode enable                  */
2803 
2804 #define OPAMP_CSR_CALSEL_Pos          (12U)
2805 #define OPAMP_CSR_CALSEL_Msk          (0x3UL << OPAMP_CSR_CALSEL_Pos)   /*!< 0x00003000                               */
2806 #define OPAMP_CSR_CALSEL              OPAMP_CSR_CALSEL_Msk              /*!< Calibration selection                    */
2807 #define OPAMP_CSR_CALSEL_0            (0x1UL << OPAMP_CSR_CALSEL_Pos)   /*!< 0x00001000                               */
2808 #define OPAMP_CSR_CALSEL_1            (0x2UL << OPAMP_CSR_CALSEL_Pos)   /*!< 0x00002000                               */
2809 
2810 #define OPAMP_CSR_PGGAIN_Pos          (14U)
2811 #define OPAMP_CSR_PGGAIN_Msk          (0xFUL << OPAMP_CSR_PGGAIN_Pos)   /*!< 0x0003C000                               */
2812 #define OPAMP_CSR_PGGAIN              OPAMP_CSR_PGGAIN_Msk              /*!< Programmable amplifier gain value        */
2813 #define OPAMP_CSR_PGGAIN_0            (0x1UL << OPAMP_CSR_PGGAIN_Pos)   /*!< 0x00004000                               */
2814 #define OPAMP_CSR_PGGAIN_1            (0x2UL << OPAMP_CSR_PGGAIN_Pos)   /*!< 0x00008000                               */
2815 #define OPAMP_CSR_PGGAIN_2            (0x4UL << OPAMP_CSR_PGGAIN_Pos)   /*!< 0x00010000                               */
2816 #define OPAMP_CSR_PGGAIN_3            (0x8UL << OPAMP_CSR_PGGAIN_Pos)   /*!< 0x00020000                               */
2817 
2818 #define OPAMP_CSR_USERTRIM_Pos        (18U)
2819 #define OPAMP_CSR_USERTRIM_Msk        (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000                               */
2820 #define OPAMP_CSR_USERTRIM            OPAMP_CSR_USERTRIM_Msk            /*!< User trimming enable                     */
2821 
2822 #define OPAMP_CSR_TSTREF_Pos          (29U)
2823 #define OPAMP_CSR_TSTREF_Msk          (0x1UL << OPAMP_CSR_TSTREF_Pos)   /*!< 0x20000000                               */
2824 #define OPAMP_CSR_TSTREF              OPAMP_CSR_TSTREF_Msk              /*!< calibration reference voltage output     */
2825 
2826 #define OPAMP_CSR_CALOUT_Pos          (30U)
2827 #define OPAMP_CSR_CALOUT_Msk          (0x1UL << OPAMP_CSR_CALOUT_Pos)   /*!< 0x40000000                               */
2828 #define OPAMP_CSR_CALOUT              OPAMP_CSR_CALOUT_Msk              /*!< Calibration output                       */
2829 
2830 /**********************************   Bit definition for OPAMP_OTR register  ******************************************/
2831 #define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
2832 #define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F                        */
2833 #define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs  */
2834 
2835 #define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
2836 #define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00                        */
2837 #define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs  */
2838 
2839 /**********************************   Bit definition for OPAMP_HSOTR register   ***************************************/
2840 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)
2841 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F                    */
2842 #define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk             /*!< Trim for NMOS pairs           */
2843 
2844 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)
2845 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00                    */
2846 #define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk             /*!< Trim for PMOS pairs           */
2847 
2848 
2849 /******************************************************************************/
2850 /*                                                                            */
2851 /*                          CRC calculation unit                              */
2852 /*                                                                            */
2853 /******************************************************************************/
2854 /*******************  Bit definition for CRC_DR register  *********************/
2855 #define CRC_DR_DR_Pos                       (0U)
2856 #define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)         /*!< 0xFFFFFFFF */
2857 #define CRC_DR_DR                           CRC_DR_DR_Msk                           /*!< Data register bits */
2858 
2859 /*******************  Bit definition for CRC_IDR register  ********************/
2860 #define CRC_IDR_IDR_Pos                     (0U)
2861 #define CRC_IDR_IDR_Msk                     (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)       /*!< 0xFFFFFFFF */
2862 #define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                         /*!< General-purpose 32-bits data register bits */
2863 
2864 /********************  Bit definition for CRC_CR register  ********************/
2865 #define CRC_CR_RESET_Pos                    (0U)
2866 #define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)             /*!< 0x00000001 */
2867 #define CRC_CR_RESET                        CRC_CR_RESET_Msk                        /*!< RESET the CRC computation unit bit */
2868 #define CRC_CR_POLYSIZE_Pos                 (3U)
2869 #define CRC_CR_POLYSIZE_Msk                 (0x3UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000018 */
2870 #define CRC_CR_POLYSIZE                     CRC_CR_POLYSIZE_Msk                     /*!< Polynomial size bits */
2871 #define CRC_CR_POLYSIZE_0                   (0x1UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000008 */
2872 #define CRC_CR_POLYSIZE_1                   (0x2UL << CRC_CR_POLYSIZE_Pos)          /*!< 0x00000010 */
2873 #define CRC_CR_REV_IN_Pos                   (5U)
2874 #define CRC_CR_REV_IN_Msk                   (0x3UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000060 */
2875 #define CRC_CR_REV_IN                       CRC_CR_REV_IN_Msk                       /*!< REV_IN Reverse Input Data bits */
2876 #define CRC_CR_REV_IN_0                     (0x1UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000020 */
2877 #define CRC_CR_REV_IN_1                     (0x2UL << CRC_CR_REV_IN_Pos)            /*!< 0x00000040 */
2878 #define CRC_CR_REV_OUT_Pos                  (7U)
2879 #define CRC_CR_REV_OUT_Msk                  (0x1UL << CRC_CR_REV_OUT_Pos)           /*!< 0x00000080 */
2880 #define CRC_CR_REV_OUT                      CRC_CR_REV_OUT_Msk                      /*!< REV_OUT Reverse Output Data bits */
2881 
2882 /*******************  Bit definition for CRC_INIT register  *******************/
2883 #define CRC_INIT_INIT_Pos                   (0U)
2884 #define CRC_INIT_INIT_Msk                   (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)     /*!< 0xFFFFFFFF */
2885 #define CRC_INIT_INIT                       CRC_INIT_INIT_Msk                       /*!< Initial CRC value bits */
2886 
2887 /*******************  Bit definition for CRC_POL register  ********************/
2888 #define CRC_POL_POL_Pos                     (0U)
2889 #define CRC_POL_POL_Msk                     (0xFFFFFFFFUL << CRC_POL_POL_Pos)       /*!< 0xFFFFFFFF */
2890 #define CRC_POL_POL                         CRC_POL_POL_Msk                         /*!< Coefficients of the polynomial */
2891 
2892 
2893 /******************************************************************************/
2894 /*                                                                            */
2895 /*                          CRS Clock Recovery System                         */
2896 /******************************************************************************/
2897 /*******************  Bit definition for CRS_CR register  *********************/
2898 #define CRS_CR_SYNCOKIE_Pos                 (0U)
2899 #define CRS_CR_SYNCOKIE_Msk                 (0x1UL << CRS_CR_SYNCOKIE_Pos)          /*!< 0x00000001 */
2900 #define CRS_CR_SYNCOKIE                     CRS_CR_SYNCOKIE_Msk                     /*!< SYNC event OK interrupt enable */
2901 #define CRS_CR_SYNCWARNIE_Pos               (1U)
2902 #define CRS_CR_SYNCWARNIE_Msk               (0x1UL << CRS_CR_SYNCWARNIE_Pos)        /*!< 0x00000002 */
2903 #define CRS_CR_SYNCWARNIE                   CRS_CR_SYNCWARNIE_Msk                   /*!< SYNC warning interrupt enable */
2904 #define CRS_CR_ERRIE_Pos                    (2U)
2905 #define CRS_CR_ERRIE_Msk                    (0x1UL << CRS_CR_ERRIE_Pos)             /*!< 0x00000004 */
2906 #define CRS_CR_ERRIE                        CRS_CR_ERRIE_Msk                        /*!< SYNC error or trimming error interrupt enable */
2907 #define CRS_CR_ESYNCIE_Pos                  (3U)
2908 #define CRS_CR_ESYNCIE_Msk                  (0x1UL << CRS_CR_ESYNCIE_Pos)           /*!< 0x00000008 */
2909 #define CRS_CR_ESYNCIE                      CRS_CR_ESYNCIE_Msk                      /*!< Expected SYNC interrupt enable */
2910 #define CRS_CR_CEN_Pos                      (5U)
2911 #define CRS_CR_CEN_Msk                      (0x1UL << CRS_CR_CEN_Pos)               /*!< 0x00000020 */
2912 #define CRS_CR_CEN                          CRS_CR_CEN_Msk                          /*!< Frequency error counter enable */
2913 #define CRS_CR_AUTOTRIMEN_Pos               (6U)
2914 #define CRS_CR_AUTOTRIMEN_Msk               (0x1UL << CRS_CR_AUTOTRIMEN_Pos)        /*!< 0x00000040 */
2915 #define CRS_CR_AUTOTRIMEN                   CRS_CR_AUTOTRIMEN_Msk                   /*!< Automatic trimming enable */
2916 #define CRS_CR_SWSYNC_Pos                   (7U)
2917 #define CRS_CR_SWSYNC_Msk                   (0x1UL << CRS_CR_SWSYNC_Pos)            /*!< 0x00000080 */
2918 #define CRS_CR_SWSYNC                       CRS_CR_SWSYNC_Msk                       /*!< Generate software SYNC event */
2919 #define CRS_CR_TRIM_Pos                     (8U)
2920 #define CRS_CR_TRIM_Msk                     (0x3FUL << CRS_CR_TRIM_Pos)             /*!< 0x00003F00 */
2921 #define CRS_CR_TRIM                         CRS_CR_TRIM_Msk                         /*!< HSI48 oscillator smooth trimming */
2922 
2923 /*******************  Bit definition for CRS_CFGR register  *********************/
2924 #define CRS_CFGR_RELOAD_Pos                 (0U)
2925 #define CRS_CFGR_RELOAD_Msk                 (0xFFFFUL << CRS_CFGR_RELOAD_Pos)       /*!< 0x0000FFFF */
2926 #define CRS_CFGR_RELOAD                     CRS_CFGR_RELOAD_Msk                     /*!< Counter reload value */
2927 #define CRS_CFGR_FELIM_Pos                  (16U)
2928 #define CRS_CFGR_FELIM_Msk                  (0xFFUL << CRS_CFGR_FELIM_Pos)          /*!< 0x00FF0000 */
2929 #define CRS_CFGR_FELIM                      CRS_CFGR_FELIM_Msk                      /*!< Frequency error limit */
2930 #define CRS_CFGR_SYNCDIV_Pos                (24U)
2931 #define CRS_CFGR_SYNCDIV_Msk                (0x7UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x07000000 */
2932 #define CRS_CFGR_SYNCDIV                    CRS_CFGR_SYNCDIV_Msk                    /*!< SYNC divider */
2933 #define CRS_CFGR_SYNCDIV_0                  (0x1UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x01000000 */
2934 #define CRS_CFGR_SYNCDIV_1                  (0x2UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x02000000 */
2935 #define CRS_CFGR_SYNCDIV_2                  (0x4UL << CRS_CFGR_SYNCDIV_Pos)         /*!< 0x04000000 */
2936 #define CRS_CFGR_SYNCSRC_Pos                (28U)
2937 #define CRS_CFGR_SYNCSRC_Msk                (0x3UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x30000000 */
2938 #define CRS_CFGR_SYNCSRC                    CRS_CFGR_SYNCSRC_Msk                    /*!< SYNC signal source selection */
2939 #define CRS_CFGR_SYNCSRC_0                  (0x1UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x10000000 */
2940 #define CRS_CFGR_SYNCSRC_1                  (0x2UL << CRS_CFGR_SYNCSRC_Pos)         /*!< 0x20000000 */
2941 #define CRS_CFGR_SYNCPOL_Pos                (31U)
2942 #define CRS_CFGR_SYNCPOL_Msk                (0x1UL << CRS_CFGR_SYNCPOL_Pos)         /*!< 0x80000000 */
2943 #define CRS_CFGR_SYNCPOL                    CRS_CFGR_SYNCPOL_Msk                    /*!< SYNC polarity selection */
2944 
2945 /*******************  Bit definition for CRS_ISR register  *********************/
2946 #define CRS_ISR_SYNCOKF_Pos                 (0U)
2947 #define CRS_ISR_SYNCOKF_Msk                 (0x1UL << CRS_ISR_SYNCOKF_Pos)          /*!< 0x00000001 */
2948 #define CRS_ISR_SYNCOKF                     CRS_ISR_SYNCOKF_Msk                     /*!< SYNC event OK flag */
2949 #define CRS_ISR_SYNCWARNF_Pos               (1U)
2950 #define CRS_ISR_SYNCWARNF_Msk               (0x1UL << CRS_ISR_SYNCWARNF_Pos)        /*!< 0x00000002 */
2951 #define CRS_ISR_SYNCWARNF                   CRS_ISR_SYNCWARNF_Msk                   /*!< SYNC warning flag */
2952 #define CRS_ISR_ERRF_Pos                    (2U)
2953 #define CRS_ISR_ERRF_Msk                    (0x1UL << CRS_ISR_ERRF_Pos)             /*!< 0x00000004 */
2954 #define CRS_ISR_ERRF                        CRS_ISR_ERRF_Msk                        /*!< Error flag */
2955 #define CRS_ISR_ESYNCF_Pos                  (3U)
2956 #define CRS_ISR_ESYNCF_Msk                  (0x1UL << CRS_ISR_ESYNCF_Pos)           /*!< 0x00000008 */
2957 #define CRS_ISR_ESYNCF                      CRS_ISR_ESYNCF_Msk                      /*!< Expected SYNC flag */
2958 #define CRS_ISR_SYNCERR_Pos                 (8U)
2959 #define CRS_ISR_SYNCERR_Msk                 (0x1UL << CRS_ISR_SYNCERR_Pos)          /*!< 0x00000100 */
2960 #define CRS_ISR_SYNCERR                     CRS_ISR_SYNCERR_Msk                     /*!< SYNC error */
2961 #define CRS_ISR_SYNCMISS_Pos                (9U)
2962 #define CRS_ISR_SYNCMISS_Msk                (0x1UL << CRS_ISR_SYNCMISS_Pos)         /*!< 0x00000200 */
2963 #define CRS_ISR_SYNCMISS                    CRS_ISR_SYNCMISS_Msk                    /*!< SYNC missed */
2964 #define CRS_ISR_TRIMOVF_Pos                 (10U)
2965 #define CRS_ISR_TRIMOVF_Msk                 (0x1UL << CRS_ISR_TRIMOVF_Pos)          /*!< 0x00000400 */
2966 #define CRS_ISR_TRIMOVF                     CRS_ISR_TRIMOVF_Msk                     /*!< Trimming overflow or underflow */
2967 #define CRS_ISR_FEDIR_Pos                   (15U)
2968 #define CRS_ISR_FEDIR_Msk                   (0x1UL << CRS_ISR_FEDIR_Pos)            /*!< 0x00008000 */
2969 #define CRS_ISR_FEDIR                       CRS_ISR_FEDIR_Msk                       /*!< Frequency error direction */
2970 #define CRS_ISR_FECAP_Pos                   (16U)
2971 #define CRS_ISR_FECAP_Msk                   (0xFFFFUL << CRS_ISR_FECAP_Pos)         /*!< 0xFFFF0000 */
2972 #define CRS_ISR_FECAP                       CRS_ISR_FECAP_Msk                       /*!< Frequency error capture */
2973 
2974 /*******************  Bit definition for CRS_ICR register  *********************/
2975 #define CRS_ICR_SYNCOKC_Pos                 (0U)
2976 #define CRS_ICR_SYNCOKC_Msk                 (0x1UL << CRS_ICR_SYNCOKC_Pos)          /*!< 0x00000001 */
2977 #define CRS_ICR_SYNCOKC                     CRS_ICR_SYNCOKC_Msk                     /*!< SYNC event OK clear flag */
2978 #define CRS_ICR_SYNCWARNC_Pos               (1U)
2979 #define CRS_ICR_SYNCWARNC_Msk               (0x1UL << CRS_ICR_SYNCWARNC_Pos)        /*!< 0x00000002 */
2980 #define CRS_ICR_SYNCWARNC                   CRS_ICR_SYNCWARNC_Msk                   /*!< SYNC warning clear flag */
2981 #define CRS_ICR_ERRC_Pos                    (2U)
2982 #define CRS_ICR_ERRC_Msk                    (0x1UL << CRS_ICR_ERRC_Pos)             /*!< 0x00000004 */
2983 #define CRS_ICR_ERRC                        CRS_ICR_ERRC_Msk                        /*!< Error clear flag */
2984 #define CRS_ICR_ESYNCC_Pos                  (3U)
2985 #define CRS_ICR_ESYNCC_Msk                  (0x1UL << CRS_ICR_ESYNCC_Pos)           /*!< 0x00000008 */
2986 #define CRS_ICR_ESYNCC                      CRS_ICR_ESYNCC_Msk                      /*!< Expected SYNC clear flag */
2987 
2988 
2989 /******************************************************************************/
2990 /*                                                                            */
2991 /*                                    RNG                                     */
2992 /*                                                                            */
2993 /******************************************************************************/
2994 /********************  Bits definition for RNG_CR register  *******************/
2995 #define RNG_CR_RNGEN_Pos                    (2U)
2996 #define RNG_CR_RNGEN_Msk                    (0x1UL << RNG_CR_RNGEN_Pos)             /*!< 0x00000004 */
2997 #define RNG_CR_RNGEN                        RNG_CR_RNGEN_Msk
2998 #define RNG_CR_IE_Pos                       (3U)
2999 #define RNG_CR_IE_Msk                       (0x1UL << RNG_CR_IE_Pos)                /*!< 0x00000008 */
3000 #define RNG_CR_IE                           RNG_CR_IE_Msk
3001 #define RNG_CR_CED_Pos                      (5U)
3002 #define RNG_CR_CED_Msk                      (0x1UL << RNG_CR_CED_Pos)               /*!< 0x00000020 */
3003 #define RNG_CR_CED                          RNG_CR_CED_Msk
3004 #define RNG_CR_ARDIS_Pos                    (7U)
3005 #define RNG_CR_ARDIS_Msk                    (0x1UL << RNG_CR_ARDIS_Pos)
3006 #define RNG_CR_ARDIS                        RNG_CR_ARDIS_Msk
3007 #define RNG_CR_RNG_CONFIG3_Pos              (8U)
3008 #define RNG_CR_RNG_CONFIG3_Msk              (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
3009 #define RNG_CR_RNG_CONFIG3                  RNG_CR_RNG_CONFIG3_Msk
3010 #define RNG_CR_NISTC_Pos                    (12U)
3011 #define RNG_CR_NISTC_Msk                    (0x1UL << RNG_CR_NISTC_Pos)
3012 #define RNG_CR_NISTC                        RNG_CR_NISTC_Msk
3013 #define RNG_CR_RNG_CONFIG2_Pos              (13U)
3014 #define RNG_CR_RNG_CONFIG2_Msk              (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
3015 #define RNG_CR_RNG_CONFIG2                  RNG_CR_RNG_CONFIG2_Msk
3016 #define RNG_CR_CLKDIV_Pos                   (16U)
3017 #define RNG_CR_CLKDIV_Msk                   (0xFUL << RNG_CR_CLKDIV_Pos)
3018 #define RNG_CR_CLKDIV                       RNG_CR_CLKDIV_Msk
3019 #define RNG_CR_CLKDIV_0                     (0x1UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00010000 */
3020 #define RNG_CR_CLKDIV_1                     (0x2UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00020000 */
3021 #define RNG_CR_CLKDIV_2                     (0x4UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00040000 */
3022 #define RNG_CR_CLKDIV_3                     (0x8UL << RNG_CR_CLKDIV_Pos)            /*!< 0x00080000 */
3023 #define RNG_CR_RNG_CONFIG1_Pos              (20U)
3024 #define RNG_CR_RNG_CONFIG1_Msk              (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
3025 #define RNG_CR_RNG_CONFIG1                  RNG_CR_RNG_CONFIG1_Msk
3026 #define RNG_CR_CONDRST_Pos                  (30U)
3027 #define RNG_CR_CONDRST_Msk                  (0x1UL << RNG_CR_CONDRST_Pos)
3028 #define RNG_CR_CONDRST                      RNG_CR_CONDRST_Msk
3029 #define RNG_CR_CONFIGLOCK_Pos               (31U)
3030 #define RNG_CR_CONFIGLOCK_Msk               (0x1UL << RNG_CR_CONFIGLOCK_Pos)
3031 #define RNG_CR_CONFIGLOCK                   RNG_CR_CONFIGLOCK_Msk
3032 
3033 /********************  Bits definition for RNG_SR register  *******************/
3034 #define RNG_SR_DRDY_Pos                     (0U)
3035 #define RNG_SR_DRDY_Msk                     (0x1UL << RNG_SR_DRDY_Pos)              /*!< 0x00000001 */
3036 #define RNG_SR_DRDY                         RNG_SR_DRDY_Msk
3037 #define RNG_SR_CECS_Pos                     (1U)
3038 #define RNG_SR_CECS_Msk                     (0x1UL << RNG_SR_CECS_Pos)              /*!< 0x00000002 */
3039 #define RNG_SR_CECS                         RNG_SR_CECS_Msk
3040 #define RNG_SR_SECS_Pos                     (2U)
3041 #define RNG_SR_SECS_Msk                     (0x1UL << RNG_SR_SECS_Pos)              /*!< 0x00000004 */
3042 #define RNG_SR_SECS                         RNG_SR_SECS_Msk
3043 #define RNG_SR_CEIS_Pos                     (5U)
3044 #define RNG_SR_CEIS_Msk                     (0x1UL << RNG_SR_CEIS_Pos)              /*!< 0x00000020 */
3045 #define RNG_SR_CEIS                         RNG_SR_CEIS_Msk
3046 #define RNG_SR_SEIS_Pos                     (6U)
3047 #define RNG_SR_SEIS_Msk                     (0x1UL << RNG_SR_SEIS_Pos)              /*!< 0x00000040 */
3048 #define RNG_SR_SEIS                         RNG_SR_SEIS_Msk
3049 
3050 /********************  Bits definition for RNG_HTCR register  *******************/
3051 #define RNG_HTCR_HTCFG_Pos                  (0U)
3052 #define RNG_HTCR_HTCFG_Msk                  (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)    /*!< 0xFFFFFFFF */
3053 #define RNG_HTCR_HTCFG                      RNG_HTCR_HTCFG_Msk
3054 
3055 /******************************************************************************/
3056 /*                                                                            */
3057 /*                      Digital to Analog Converter                           */
3058 /*                                                                            */
3059 /******************************************************************************/
3060 #define DAC_CHANNEL2_SUPPORT                                                        /*!< DAC feature available only on specific devices: DAC channel 2 available */
3061 
3062 /********************  Bit definition for DAC_CR register  ********************/
3063 #define DAC_CR_EN1_Pos                      (0U)
3064 #define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)               /*!< 0x00000001 */
3065 #define DAC_CR_EN1                          DAC_CR_EN1_Msk                          /*!<DAC channel1 enable */
3066 #define DAC_CR_TEN1_Pos                     (1U)
3067 #define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)              /*!< 0x00000002 */
3068 #define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                         /*!<DAC channel1 Trigger enable */
3069 #define DAC_CR_TSEL1_Pos                    (2U)
3070 #define DAC_CR_TSEL1_Msk                    (0xFUL << DAC_CR_TSEL1_Pos)             /*!< 0x0000003C */
3071 #define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                        /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
3072 #define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000004 */
3073 #define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000008 */
3074 #define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000010 */
3075 #define DAC_CR_TSEL1_3                      (0x8UL << DAC_CR_TSEL1_Pos)             /*!< 0x00000020 */
3076 #define DAC_CR_WAVE1_Pos                    (6U)
3077 #define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)             /*!< 0x000000C0 */
3078 #define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3079 #define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000040 */
3080 #define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)             /*!< 0x00000080 */
3081 #define DAC_CR_MAMP1_Pos                    (8U)
3082 #define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)             /*!< 0x00000F00 */
3083 #define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3084 #define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000100 */
3085 #define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000200 */
3086 #define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000400 */
3087 #define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)             /*!< 0x00000800 */
3088 #define DAC_CR_DMAEN1_Pos                   (12U)
3089 #define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)            /*!< 0x00001000 */
3090 #define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                       /*!<DAC channel1 DMA enable */
3091 #define DAC_CR_DMAUDRIE1_Pos                (13U)
3092 #define DAC_CR_DMAUDRIE1_Msk                (0x1UL << DAC_CR_DMAUDRIE1_Pos)         /*!< 0x00002000 */
3093 #define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk                    /*!<DAC channel 1 DMA underrun interrupt enable  >*/
3094 #define DAC_CR_CEN1_Pos                     (14U)
3095 #define DAC_CR_CEN1_Msk                     (0x1UL << DAC_CR_CEN1_Pos)              /*!< 0x00004000 */
3096 #define DAC_CR_CEN1                         DAC_CR_CEN1_Msk                         /*!<DAC channel 1 calibration enable >*/
3097 #define DAC_CR_EN2_Pos                      (16U)
3098 #define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)               /*!< 0x00010000 */
3099 #define DAC_CR_EN2                          DAC_CR_EN2_Msk                          /*!<DAC channel2 enable */
3100 #define DAC_CR_TEN2_Pos                     (17U)
3101 #define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)              /*!< 0x00020000 */
3102 #define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                         /*!<DAC channel2 Trigger enable */
3103 #define DAC_CR_TSEL2_Pos                    (18U)
3104 #define DAC_CR_TSEL2_Msk                    (0xFUL << DAC_CR_TSEL2_Pos)             /*!< 0x003C0000 */
3105 #define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                        /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
3106 #define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)             /*!< 0x00040000 */
3107 #define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)             /*!< 0x00080000 */
3108 #define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)             /*!< 0x00100000 */
3109 #define DAC_CR_TSEL2_3                      (0x8UL << DAC_CR_TSEL2_Pos)             /*!< 0x00200000 */
3110 #define DAC_CR_WAVE2_Pos                    (22U)
3111 #define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)             /*!< 0x00C00000 */
3112 #define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3113 #define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)             /*!< 0x00400000 */
3114 #define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)             /*!< 0x00800000 */
3115 #define DAC_CR_MAMP2_Pos                    (24U)
3116 #define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)             /*!< 0x0F000000 */
3117 #define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3118 #define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)             /*!< 0x01000000 */
3119 #define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)             /*!< 0x02000000 */
3120 #define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)             /*!< 0x04000000 */
3121 #define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)             /*!< 0x08000000 */
3122 #define DAC_CR_DMAEN2_Pos                   (28U)
3123 #define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)            /*!< 0x10000000 */
3124 #define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                       /*!<DAC channel2 DMA enabled */
3125 #define DAC_CR_DMAUDRIE2_Pos                (29U)
3126 #define DAC_CR_DMAUDRIE2_Msk                (0x1UL << DAC_CR_DMAUDRIE2_Pos)         /*!< 0x20000000 */
3127 #define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk                    /*!<DAC channel2 DMA underrun interrupt enable  >*/
3128 #define DAC_CR_CEN2_Pos                     (30U)
3129 #define DAC_CR_CEN2_Msk                     (0x1UL << DAC_CR_CEN2_Pos)              /*!< 0x40000000 */
3130 #define DAC_CR_CEN2                         DAC_CR_CEN2_Msk                         /*!<DAC channel2 calibration enable >*/
3131 
3132 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
3133 #define DAC_SWTRIGR_SWTRIG1_Pos             (0U)
3134 #define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)      /*!< 0x00000001 */
3135 #define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk                 /*!<DAC channel1 software trigger */
3136 #define DAC_SWTRIGR_SWTRIG2_Pos             (1U)
3137 #define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)      /*!< 0x00000002 */
3138 #define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk                 /*!<DAC channel2 software trigger */
3139 #define DAC_SWTRIGR_SWTRIGB1_Pos            (16U)
3140 #define DAC_SWTRIGR_SWTRIGB1_Msk            (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)     /*!< 0x00010000 */
3141 #define DAC_SWTRIGR_SWTRIGB1                DAC_SWTRIGR_SWTRIGB1_Msk                /*!<DAC channel1 software trigger B */
3142 #define DAC_SWTRIGR_SWTRIGB2_Pos            (17U)
3143 #define DAC_SWTRIGR_SWTRIGB2_Msk            (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)     /*!< 0x00020000 */
3144 #define DAC_SWTRIGR_SWTRIGB2                DAC_SWTRIGR_SWTRIGB2_Msk                /*!<DAC channel2 software trigger B */
3145 
3146 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
3147 #define DAC_DHR12R1_DACC1DHR_Pos            (0U)
3148 #define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)   /*!< 0x00000FFF */
3149 #define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk                /*!<DAC channel1 12-bit Right aligned data */
3150 #define DAC_DHR12R1_DACC1DHRB_Pos           (16U)
3151 #define DAC_DHR12R1_DACC1DHRB_Msk           (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)  /*!< 0x0FFF0000 */
3152 #define DAC_DHR12R1_DACC1DHRB               DAC_DHR12R1_DACC1DHRB_Msk               /*!<DAC channel1 12-bit Right-aligned data B */
3153 
3154 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
3155 #define DAC_DHR12L1_DACC1DHR_Pos            (4U)
3156 #define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
3157 #define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk                /*!<DAC channel1 12-bit Left aligned data */
3158 #define DAC_DHR12L1_DACC1DHRB_Pos           (20U)
3159 #define DAC_DHR12L1_DACC1DHRB_Msk           (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)  /*!< 0xFFF00000 */
3160 #define DAC_DHR12L1_DACC1DHRB               DAC_DHR12L1_DACC1DHRB_Msk               /*!<DAC channel1 12-bit Left aligned data B */
3161 
3162 /******************  Bit definition for DAC_DHR8R1 register  ******************/
3163 #define DAC_DHR8R1_DACC1DHR_Pos             (0U)
3164 #define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)     /*!< 0x000000FF */
3165 #define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk                 /*!<DAC channel1 8-bit Right aligned data */
3166 #define DAC_DHR8R1_DACC1DHRB_Pos            (8U)
3167 #define DAC_DHR8R1_DACC1DHRB_Msk            (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)    /*!< 0x0000FF00 */
3168 #define DAC_DHR8R1_DACC1DHRB                DAC_DHR8R1_DACC1DHRB_Msk                /*!<DAC channel1 8-bit Right aligned data B */
3169 
3170 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
3171 #define DAC_DHR12R2_DACC2DHR_Pos            (0U)
3172 #define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)   /*!< 0x00000FFF */
3173 #define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk                /*!<DAC channel2 12-bit Right aligned data */
3174 #define DAC_DHR12R2_DACC2DHRB_Pos           (16U)
3175 #define DAC_DHR12R2_DACC2DHRB_Msk           (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)  /*!< 0x0FFF0000 */
3176 #define DAC_DHR12R2_DACC2DHRB               DAC_DHR12R2_DACC2DHRB_Msk               /*!<DAC channel2 12-bit Right-aligned data B */
3177 
3178 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
3179 #define DAC_DHR12L2_DACC2DHR_Pos            (4U)
3180 #define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)   /*!< 0x0000FFF0 */
3181 #define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk                /*!<DAC channel2 12-bit Left aligned data */
3182 #define DAC_DHR12L2_DACC2DHRB_Pos           (20U)
3183 #define DAC_DHR12L2_DACC2DHRB_Msk           (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)  /*!< 0xFFF00000 */
3184 #define DAC_DHR12L2_DACC2DHRB               DAC_DHR12L2_DACC2DHRB_Msk               /*!<DAC channel2 12-bit Left aligned data B */
3185 
3186 /******************  Bit definition for DAC_DHR8R2 register  ******************/
3187 #define DAC_DHR8R2_DACC2DHR_Pos             (0U)
3188 #define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)     /*!< 0x000000FF */
3189 #define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk                 /*!<DAC channel2 8-bit Right aligned data */
3190 #define DAC_DHR8R2_DACC2DHRB_Pos            (8U)
3191 #define DAC_DHR8R2_DACC2DHRB_Msk            (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)    /*!< 0x0000FF00 */
3192 #define DAC_DHR8R2_DACC2DHRB                DAC_DHR8R2_DACC2DHRB_Msk                /*!<DAC channel2 8-bit Right aligned data B */
3193 
3194 /*****************  Bit definition for DAC_DHR12RD register  ******************/
3195 #define DAC_DHR12RD_DACC1DHR_Pos            (0U)
3196 #define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)   /*!< 0x00000FFF */
3197 #define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk                /*!<DAC channel1 12-bit Right aligned data */
3198 #define DAC_DHR12RD_DACC2DHR_Pos            (16U)
3199 #define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)   /*!< 0x0FFF0000 */
3200 #define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk                /*!<DAC channel2 12-bit Right aligned data */
3201 
3202 /*****************  Bit definition for DAC_DHR12LD register  ******************/
3203 #define DAC_DHR12LD_DACC1DHR_Pos            (4U)
3204 #define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)   /*!< 0x0000FFF0 */
3205 #define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk                /*!<DAC channel1 12-bit Left aligned data */
3206 #define DAC_DHR12LD_DACC2DHR_Pos            (20U)
3207 #define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)   /*!< 0xFFF00000 */
3208 #define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk                /*!<DAC channel2 12-bit Left aligned data */
3209 
3210 /******************  Bit definition for DAC_DHR8RD register  ******************/
3211 #define DAC_DHR8RD_DACC1DHR_Pos             (0U)
3212 #define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)     /*!< 0x000000FF */
3213 #define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk                 /*!<DAC channel1 8-bit Right aligned data */
3214 #define DAC_DHR8RD_DACC2DHR_Pos             (8U)
3215 #define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)     /*!< 0x0000FF00 */
3216 #define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk                 /*!<DAC channel2 8-bit Right aligned data */
3217 
3218 /*******************  Bit definition for DAC_DOR1 register  *******************/
3219 #define DAC_DOR1_DACC1DOR_Pos               (0U)
3220 #define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)      /*!< 0x00000FFF */
3221 #define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk                   /*!<DAC channel1 data output */
3222 #define DAC_DOR1_DACC1DORB_Pos              (16U)
3223 #define DAC_DOR1_DACC1DORB_Msk              (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)     /*!< 0x0FFF0000 */
3224 #define DAC_DOR1_DACC1DORB                  DAC_DOR1_DACC1DORB_Msk                  /*!<DAC channel1 data output B */
3225 
3226 /*******************  Bit definition for DAC_DOR2 register  *******************/
3227 #define DAC_DOR2_DACC2DOR_Pos               (0U)
3228 #define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)      /*!< 0x00000FFF */
3229 #define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk                   /*!<DAC channel2 data output */
3230 #define DAC_DOR2_DACC2DORB_Pos              (16U)
3231 #define DAC_DOR2_DACC2DORB_Msk              (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)     /*!< 0x0FFF0000 */
3232 #define DAC_DOR2_DACC2DORB                  DAC_DOR2_DACC2DORB_Msk                  /*!<DAC channel2 data output B */
3233 
3234 /********************  Bit definition for DAC_SR register  ********************/
3235 #define DAC_SR_DAC1RDY_Pos                  (11U)
3236 #define DAC_SR_DAC1RDY_Msk                  (0x1UL << DAC_SR_DAC1RDY_Pos)           /*!< 0x00000800 */
3237 #define DAC_SR_DAC1RDY                      DAC_SR_DAC1RDY_Msk                      /*!<DAC channel 1 ready status bit */
3238 #define DAC_SR_DORSTAT1_Pos                 (12U)
3239 #define DAC_SR_DORSTAT1_Msk                 (0x1UL << DAC_SR_DORSTAT1_Pos)          /*!< 0x00001000 */
3240 #define DAC_SR_DORSTAT1                     DAC_SR_DORSTAT1_Msk                     /*!<DAC channel 1 output register status bit */
3241 #define DAC_SR_DMAUDR1_Pos                  (13U)
3242 #define DAC_SR_DMAUDR1_Msk                  (0x1UL << DAC_SR_DMAUDR1_Pos)           /*!< 0x00002000 */
3243 #define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                      /*!<DAC channel1 DMA underrun flag */
3244 #define DAC_SR_CAL_FLAG1_Pos                (14U)
3245 #define DAC_SR_CAL_FLAG1_Msk                (0x1UL << DAC_SR_CAL_FLAG1_Pos)         /*!< 0x00004000 */
3246 #define DAC_SR_CAL_FLAG1                    DAC_SR_CAL_FLAG1_Msk                    /*!<DAC channel1 calibration offset status */
3247 #define DAC_SR_BWST1_Pos                    (15U)
3248 #define DAC_SR_BWST1_Msk                    (0x1UL << DAC_SR_BWST1_Pos)             /*!< 0x00008000 */
3249 #define DAC_SR_BWST1                        DAC_SR_BWST1_Msk                        /*!<DAC channel1 busy writing sample time flag */
3250 
3251 #define DAC_SR_DAC2RDY_Pos                  (27U)
3252 #define DAC_SR_DAC2RDY_Msk                  (0x1UL << DAC_SR_DAC2RDY_Pos)           /*!< 0x08000000 */
3253 #define DAC_SR_DAC2RDY                      DAC_SR_DAC2RDY_Msk                      /*!<DAC channel 2 ready status bit */
3254 #define DAC_SR_DORSTAT2_Pos                 (28U)
3255 #define DAC_SR_DORSTAT2_Msk                 (0x1UL << DAC_SR_DORSTAT2_Pos)          /*!< 0x10000000 */
3256 #define DAC_SR_DORSTAT2                     DAC_SR_DORSTAT2_Msk                     /*!<DAC channel 2 output register status bit */
3257 #define DAC_SR_DMAUDR2_Pos                  (29U)
3258 #define DAC_SR_DMAUDR2_Msk                  (0x1UL << DAC_SR_DMAUDR2_Pos)           /*!< 0x20000000 */
3259 #define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                      /*!<DAC channel2 DMA underrun flag */
3260 #define DAC_SR_CAL_FLAG2_Pos                (30U)
3261 #define DAC_SR_CAL_FLAG2_Msk                (0x1UL << DAC_SR_CAL_FLAG2_Pos)         /*!< 0x40000000 */
3262 #define DAC_SR_CAL_FLAG2                    DAC_SR_CAL_FLAG2_Msk                    /*!<DAC channel2 calibration offset status */
3263 #define DAC_SR_BWST2_Pos                    (31U)
3264 #define DAC_SR_BWST2_Msk                    (0x1UL << DAC_SR_BWST2_Pos)             /*!< 0x80000000 */
3265 #define DAC_SR_BWST2                        DAC_SR_BWST2_Msk                        /*!<DAC channel2 busy writing sample time flag */
3266 
3267 /*******************  Bit definition for DAC_CCR register  ********************/
3268 #define DAC_CCR_OTRIM1_Pos                  (0U)
3269 #define DAC_CCR_OTRIM1_Msk                  (0x1FUL << DAC_CCR_OTRIM1_Pos)          /*!< 0x0000001F */
3270 #define DAC_CCR_OTRIM1                      DAC_CCR_OTRIM1_Msk                      /*!<DAC channel1 offset trimming value */
3271 #define DAC_CCR_OTRIM2_Pos                  (16U)
3272 #define DAC_CCR_OTRIM2_Msk                  (0x1FUL << DAC_CCR_OTRIM2_Pos)          /*!< 0x001F0000 */
3273 #define DAC_CCR_OTRIM2                      DAC_CCR_OTRIM2_Msk                      /*!<DAC channel2 offset trimming value */
3274 
3275 /*******************  Bit definition for DAC_MCR register  *******************/
3276 #define DAC_MCR_MODE1_Pos                   (0U)
3277 #define DAC_MCR_MODE1_Msk                   (0x7UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000007 */
3278 #define DAC_MCR_MODE1                       DAC_MCR_MODE1_Msk                       /*!<MODE1[2:0] (DAC channel1 mode) */
3279 #define DAC_MCR_MODE1_0                     (0x1UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000001 */
3280 #define DAC_MCR_MODE1_1                     (0x2UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000002 */
3281 #define DAC_MCR_MODE1_2                     (0x4UL << DAC_MCR_MODE1_Pos)            /*!< 0x00000004 */
3282 #define DAC_MCR_DMADOUBLE1_Pos              (8U)
3283 #define DAC_MCR_DMADOUBLE1_Msk              (0x1UL << DAC_MCR_DMADOUBLE1_Pos)       /*!< 0x00000100 */
3284 #define DAC_MCR_DMADOUBLE1                  DAC_MCR_DMADOUBLE1_Msk                  /*!<DAC Channel 1 DMA double data mode */
3285 #define DAC_MCR_SINFORMAT1_Pos              (9U)
3286 #define DAC_MCR_SINFORMAT1_Msk              (0x1UL << DAC_MCR_SINFORMAT1_Pos)       /*!< 0x00000200 */
3287 #define DAC_MCR_SINFORMAT1                  DAC_MCR_SINFORMAT1_Msk                  /*!<DAC Channel 1 enable signed format */
3288 #define DAC_MCR_HFSEL_Pos                   (14U)
3289 #define DAC_MCR_HFSEL_Msk                   (0x3UL << DAC_MCR_HFSEL_Pos)            /*!< 0x0000C000 */
3290 #define DAC_MCR_HFSEL                       DAC_MCR_HFSEL_Msk                       /*!<HFSEL[1:0] (High Frequency interface mode selection) */
3291 #define DAC_MCR_HFSEL_0                     (0x1UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00004000 */
3292 #define DAC_MCR_HFSEL_1                     (0x2UL << DAC_MCR_HFSEL_Pos)            /*!< 0x00008000 */
3293 #define DAC_MCR_MODE2_Pos                   (16U)
3294 #define DAC_MCR_MODE2_Msk                   (0x7UL << DAC_MCR_MODE2_Pos)            /*!< 0x00070000 */
3295 #define DAC_MCR_MODE2                       DAC_MCR_MODE2_Msk                       /*!<MODE2[2:0] (DAC channel2 mode) */
3296 #define DAC_MCR_MODE2_0                     (0x1UL << DAC_MCR_MODE2_Pos)            /*!< 0x00010000 */
3297 #define DAC_MCR_MODE2_1                     (0x2UL << DAC_MCR_MODE2_Pos)            /*!< 0x00020000 */
3298 #define DAC_MCR_MODE2_2                     (0x4UL << DAC_MCR_MODE2_Pos)            /*!< 0x00040000 */
3299 #define DAC_MCR_DMADOUBLE2_Pos              (24U)
3300 #define DAC_MCR_DMADOUBLE2_Msk              (0x1UL << DAC_MCR_DMADOUBLE2_Pos)       /*!< 0x01000000 */
3301 #define DAC_MCR_DMADOUBLE2                  DAC_MCR_DMADOUBLE2_Msk                  /*!<DAC Channel 2 DMA double data mode */
3302 #define DAC_MCR_SINFORMAT2_Pos              (25U)
3303 #define DAC_MCR_SINFORMAT2_Msk              (0x1UL << DAC_MCR_SINFORMAT2_Pos)       /*!< 0x02000000 */
3304 #define DAC_MCR_SINFORMAT2                  DAC_MCR_SINFORMAT2_Msk                  /*!<DAC Channel 2 enable signed format */
3305 
3306 /******************  Bit definition for DAC_SHSR1 register  ******************/
3307 #define DAC_SHSR1_TSAMPLE1_Pos              (0U)
3308 #define DAC_SHSR1_TSAMPLE1_Msk              (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)     /*!< 0x000003FF */
3309 #define DAC_SHSR1_TSAMPLE1                  DAC_SHSR1_TSAMPLE1_Msk                  /*!<DAC channel1 sample time */
3310 
3311 /******************  Bit definition for DAC_SHSR2 register  ******************/
3312 #define DAC_SHSR2_TSAMPLE2_Pos              (0U)
3313 #define DAC_SHSR2_TSAMPLE2_Msk              (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)     /*!< 0x000003FF */
3314 #define DAC_SHSR2_TSAMPLE2                  DAC_SHSR2_TSAMPLE2_Msk                  /*!<DAC channel2 sample time */
3315 
3316 /******************  Bit definition for DAC_SHHR register  ******************/
3317 #define DAC_SHHR_THOLD1_Pos                 (0U)
3318 #define DAC_SHHR_THOLD1_Msk                 (0x3FFUL << DAC_SHHR_THOLD1_Pos)        /*!< 0x000003FF */
3319 #define DAC_SHHR_THOLD1                     DAC_SHHR_THOLD1_Msk                     /*!<DAC channel1 hold time */
3320 #define DAC_SHHR_THOLD2_Pos                 (16U)
3321 #define DAC_SHHR_THOLD2_Msk                 (0x3FFUL << DAC_SHHR_THOLD2_Pos)        /*!< 0x03FF0000 */
3322 #define DAC_SHHR_THOLD2                     DAC_SHHR_THOLD2_Msk                     /*!<DAC channel2 hold time */
3323 
3324 /******************  Bit definition for DAC_SHRR register  ******************/
3325 #define DAC_SHRR_TREFRESH1_Pos              (0U)
3326 #define DAC_SHRR_TREFRESH1_Msk              (0xFFUL << DAC_SHRR_TREFRESH1_Pos)      /*!< 0x000000FF */
3327 #define DAC_SHRR_TREFRESH1                  DAC_SHRR_TREFRESH1_Msk                  /*!<DAC channel1 refresh time */
3328 #define DAC_SHRR_TREFRESH2_Pos              (16U)
3329 #define DAC_SHRR_TREFRESH2_Msk              (0xFFUL << DAC_SHRR_TREFRESH2_Pos)      /*!< 0x00FF0000 */
3330 #define DAC_SHRR_TREFRESH2                  DAC_SHRR_TREFRESH2_Msk                  /*!<DAC channel2 refresh time */
3331 
3332 /******************  Bit definition for DAC_AUTOCR register  ******************/
3333 #define DAC_AUTOCR_AUTOMODE_Pos             (22U)
3334 #define DAC_AUTOCR_AUTOMODE_Msk             (0x1UL << DAC_AUTOCR_AUTOMODE_Pos)      /*!< 0x00400000 */
3335 #define DAC_AUTOCR_AUTOMODE                 DAC_AUTOCR_AUTOMODE_Msk                 /*!< AUTOCR Enable */
3336 
3337 
3338 /******************************************************************************/
3339 /*                                                                            */
3340 /*                                    HASH                                    */
3341 /*                                                                            */
3342 /******************************************************************************/
3343 /******************  Bits definition for HASH_CR register  ********************/
3344 #define HASH_CR_INIT_Pos                    (2U)
3345 #define HASH_CR_INIT_Msk                    (0x1UL << HASH_CR_INIT_Pos)             /*!< 0x00000004 */
3346 #define HASH_CR_INIT                        HASH_CR_INIT_Msk
3347 #define HASH_CR_DMAE_Pos                    (3U)
3348 #define HASH_CR_DMAE_Msk                    (0x1UL << HASH_CR_DMAE_Pos)             /*!< 0x00000008 */
3349 #define HASH_CR_DMAE                        HASH_CR_DMAE_Msk
3350 #define HASH_CR_DATATYPE_Pos                (4U)
3351 #define HASH_CR_DATATYPE_Msk                (0x3UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000030 */
3352 #define HASH_CR_DATATYPE                    HASH_CR_DATATYPE_Msk
3353 #define HASH_CR_DATATYPE_0                  (0x1UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000010 */
3354 #define HASH_CR_DATATYPE_1                  (0x2UL << HASH_CR_DATATYPE_Pos)         /*!< 0x00000020 */
3355 #define HASH_CR_MODE_Pos                    (6U)
3356 #define HASH_CR_MODE_Msk                    (0x1UL << HASH_CR_MODE_Pos)             /*!< 0x00000040 */
3357 #define HASH_CR_MODE                        HASH_CR_MODE_Msk
3358 #define HASH_CR_NBW_Pos                     (8U)
3359 #define HASH_CR_NBW_Msk                     (0xFUL << HASH_CR_NBW_Pos)              /*!< 0x00000F00 */
3360 #define HASH_CR_NBW                         HASH_CR_NBW_Msk
3361 #define HASH_CR_NBW_0                       (0x1UL << HASH_CR_NBW_Pos)              /*!< 0x00000100 */
3362 #define HASH_CR_NBW_1                       (0x2UL << HASH_CR_NBW_Pos)              /*!< 0x00000200 */
3363 #define HASH_CR_NBW_2                       (0x4UL << HASH_CR_NBW_Pos)              /*!< 0x00000400 */
3364 #define HASH_CR_NBW_3                       (0x8UL << HASH_CR_NBW_Pos)              /*!< 0x00000800 */
3365 #define HASH_CR_DINNE_Pos                   (12U)
3366 #define HASH_CR_DINNE_Msk                   (0x1UL << HASH_CR_DINNE_Pos)            /*!< 0x00001000 */
3367 #define HASH_CR_DINNE                       HASH_CR_DINNE_Msk
3368 #define HASH_CR_MDMAT_Pos                   (13U)
3369 #define HASH_CR_MDMAT_Msk                   (0x1UL << HASH_CR_MDMAT_Pos)            /*!< 0x00002000 */
3370 #define HASH_CR_MDMAT                       HASH_CR_MDMAT_Msk
3371 #define HASH_CR_LKEY_Pos                    (16U)
3372 #define HASH_CR_LKEY_Msk                    (0x1UL << HASH_CR_LKEY_Pos)             /*!< 0x00010000 */
3373 #define HASH_CR_LKEY                        HASH_CR_LKEY_Msk
3374 #define HASH_CR_ALGO_Pos                    (17U)
3375 #define HASH_CR_ALGO_Msk                    (0x3UL << HASH_CR_ALGO_Pos)             /*!< 0x00060000 */
3376 #define HASH_CR_ALGO                        HASH_CR_ALGO_Msk
3377 #define HASH_CR_ALGO_0                      (0x1UL << HASH_CR_ALGO_Pos)             /*!< 0x00020000 */
3378 #define HASH_CR_ALGO_1                      (0x2UL << HASH_CR_ALGO_Pos)             /*!< 0x00040000 */
3379 
3380 /******************  Bits definition for HASH_STR register  *******************/
3381 #define HASH_STR_NBLW_Pos                   (0U)
3382 #define HASH_STR_NBLW_Msk                   (0x1FUL << HASH_STR_NBLW_Pos)           /*!< 0x0000001F */
3383 #define HASH_STR_NBLW                       HASH_STR_NBLW_Msk
3384 #define HASH_STR_NBLW_0                     (0x01UL << HASH_STR_NBLW_Pos)           /*!< 0x00000001 */
3385 #define HASH_STR_NBLW_1                     (0x02UL << HASH_STR_NBLW_Pos)           /*!< 0x00000002 */
3386 #define HASH_STR_NBLW_2                     (0x04UL << HASH_STR_NBLW_Pos)           /*!< 0x00000004 */
3387 #define HASH_STR_NBLW_3                     (0x08UL << HASH_STR_NBLW_Pos)           /*!< 0x00000008 */
3388 #define HASH_STR_NBLW_4                     (0x10UL << HASH_STR_NBLW_Pos)           /*!< 0x00000010 */
3389 #define HASH_STR_DCAL_Pos                   (8U)
3390 #define HASH_STR_DCAL_Msk                   (0x1UL << HASH_STR_DCAL_Pos)            /*!< 0x00000100 */
3391 #define HASH_STR_DCAL                       HASH_STR_DCAL_Msk
3392 
3393 /******************  Bits definition for HASH_IMR register  *******************/
3394 #define HASH_IMR_DINIE_Pos                  (0U)
3395 #define HASH_IMR_DINIE_Msk                  (0x1UL << HASH_IMR_DINIE_Pos)           /*!< 0x00000001 */
3396 #define HASH_IMR_DINIE                      HASH_IMR_DINIE_Msk
3397 #define HASH_IMR_DCIE_Pos                   (1U)
3398 #define HASH_IMR_DCIE_Msk                   (0x1UL << HASH_IMR_DCIE_Pos)            /*!< 0x00000002 */
3399 #define HASH_IMR_DCIE                       HASH_IMR_DCIE_Msk
3400 
3401 /******************  Bits definition for HASH_SR register  ********************/
3402 #define HASH_SR_DINIS_Pos                   (0U)
3403 #define HASH_SR_DINIS_Msk                   (0x1UL << HASH_SR_DINIS_Pos)            /*!< 0x00000001 */
3404 #define HASH_SR_DINIS                       HASH_SR_DINIS_Msk
3405 #define HASH_SR_DCIS_Pos                    (1U)
3406 #define HASH_SR_DCIS_Msk                    (0x1UL << HASH_SR_DCIS_Pos)             /*!< 0x00000002 */
3407 #define HASH_SR_DCIS                        HASH_SR_DCIS_Msk
3408 #define HASH_SR_DMAS_Pos                    (2U)
3409 #define HASH_SR_DMAS_Msk                    (0x1UL << HASH_SR_DMAS_Pos)             /*!< 0x00000004 */
3410 #define HASH_SR_DMAS                        HASH_SR_DMAS_Msk
3411 #define HASH_SR_BUSY_Pos                    (3U)
3412 #define HASH_SR_BUSY_Msk                    (0x1UL << HASH_SR_BUSY_Pos)             /*!< 0x00000008 */
3413 #define HASH_SR_BUSY                        HASH_SR_BUSY_Msk
3414 #define HASH_SR_NBWE_Pos                    (16U)
3415 #define HASH_SR_NBWE_Msk                    (0xFUL << HASH_SR_NBWE_Pos)             /*!< 0x000F0000 */
3416 #define HASH_SR_NBWE                        HASH_SR_NBWE_Msk
3417 #define HASH_SR_NBWE_0                      (0x01UL << HASH_SR_NBWE_Pos)            /*!< 0x00010000 */
3418 #define HASH_SR_NBWE_1                      (0x02UL << HASH_SR_NBWE_Pos)            /*!< 0x00020000 */
3419 #define HASH_SR_NBWE_2                      (0x04UL << HASH_SR_NBWE_Pos)            /*!< 0x00040000 */
3420 #define HASH_SR_NBWE_3                      (0x08UL << HASH_SR_NBWE_Pos)            /*!< 0x00080000 */
3421 #define HASH_SR_DINNE_Pos                   (15U)
3422 #define HASH_SR_DINNE_Msk                   (0x1UL << HASH_SR_DINNE_Pos)            /*!< 0x00008000 */
3423 #define HASH_SR_DINNE                       HASH_SR_DINNE_Msk
3424 #define HASH_SR_NBWP_Pos                    (9U)
3425 #define HASH_SR_NBWP_Msk                    (0xFUL << HASH_SR_NBWP_Pos)             /*!< 0x000F0000 */
3426 #define HASH_SR_NBWP                        HASH_SR_NBWP_Msk
3427 #define HASH_SR_NBWP_0                      (0x01UL << HASH_SR_NBWP_Pos)            /*!< 0x000O0200 */
3428 #define HASH_SR_NBWP_1                      (0x02UL << HASH_SR_NBWP_Pos)            /*!< 0x00000400 */
3429 #define HASH_SR_NBWP_2                      (0x04UL << HASH_SR_NBWP_Pos)            /*!< 0x00000800 */
3430 #define HASH_SR_NBWP_3                      (0x08UL << HASH_SR_NBWP_Pos)            /*!< 0x00001000 */
3431 
3432 
3433 /******************************************************************************/
3434 /*                                                                            */
3435 /*                                 Debug MCU                                  */
3436 /*                                                                            */
3437 /******************************************************************************/
3438 /********************  Bit definition for DBGMCU_IDCODE register  *************/
3439 #define DBGMCU_IDCODE_DEV_ID_Pos            (0U)
3440 #define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)   /*!< 0x00000FFF */
3441 #define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk
3442 #define DBGMCU_IDCODE_REV_ID_Pos            (16U)
3443 #define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)  /*!< 0xFFFF0000 */
3444 #define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk
3445 
3446 /********************  Bit definition for DBGMCU_CR register  *****************/
3447 #define DBGMCU_CR_DBG_STOP_Pos              (1U)
3448 #define DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos)       /*!< 0x00000002 */
3449 #define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk
3450 #define DBGMCU_CR_DBG_STANDBY_Pos           (2U)
3451 #define DBGMCU_CR_DBG_STANDBY_Msk           (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)    /*!< 0x00000004 */
3452 #define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk
3453 #define DBGMCU_CR_TRACE_IOEN_Pos            (4U)
3454 #define DBGMCU_CR_TRACE_IOEN_Msk            (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)     /*!< 0x00000010 */
3455 #define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk
3456 #define DBGMCU_CR_TRACE_CLKEN_Pos           (5U)
3457 #define DBGMCU_CR_TRACE_CLKEN_Msk           (0x1UL << DBGMCU_CR_TRACE_CLKEN_Pos)    /*!< 0x00000020 */
3458 #define DBGMCU_CR_TRACE_CLKEN               DBGMCU_CR_TRACE_CLKEN_Msk
3459 #define DBGMCU_CR_TRACE_MODE_Pos            (6U)
3460 #define DBGMCU_CR_TRACE_MODE_Msk            (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x000000C0 */
3461 #define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk
3462 #define DBGMCU_CR_TRACE_MODE_0              (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x00000040 */
3463 #define DBGMCU_CR_TRACE_MODE_1              (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)     /*!< 0x00000080 */
3464 #define DBGMCU_CR_DCRT_Pos                  (16U)
3465 #define DBGMCU_CR_DCRT_Msk                  (0x1UL << DBGMCU_CR_DCRT_Pos)           /*!< 0x00010000 */
3466 #define DBGMCU_CR_DCRT                      DBGMCU_CR_DCRT_Msk
3467 
3468 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
3469 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos   (0U)
3470 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)
3471 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP       DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
3472 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos   (1U)
3473 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)
3474 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP       DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
3475 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos   (4U)
3476 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)
3477 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP       DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
3478 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos   (5U)
3479 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)
3480 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP       DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
3481 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos   (11U)
3482 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)
3483 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP       DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
3484 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos   (12U)
3485 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)
3486 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP       DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
3487 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos   (21U)
3488 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)
3489 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP       DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
3490 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos   (22U)
3491 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)
3492 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP       DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
3493 #define DBGMCU_APB1FZR1_DBG_I3C1_STOP_Pos   (23U)
3494 #define DBGMCU_APB1FZR1_DBG_I3C1_STOP_Msk   (0x1UL << DBGMCU_APB1FZR1_DBG_I3C1_STOP_Pos)
3495 #define DBGMCU_APB1FZR1_DBG_I3C1_STOP       DBGMCU_APB1FZR1_DBG_I3C1_STOP_Msk
3496 
3497 /********************  Bit definition for DBGMCU_APB1FZR2 register  ***********/
3498 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
3499 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)
3500 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP     DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
3501 
3502 /********************  Bit definition for DBGMCU_APB2FZR register  ***********/
3503 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos    (11U)
3504 #define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk    (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)
3505 #define DBGMCU_APB2FZR_DBG_TIM1_STOP        DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
3506 
3507 /********************  Bit definition for DBGMCU_APB3FZR register  ***********/
3508 #define DBGMCU_APB3FZR_DBG_I3C2_STOP_Pos    (12U)
3509 #define DBGMCU_APB3FZR_DBG_I3C2_STOP_Msk    (0x1UL << DBGMCU_APB3FZR_DBG_I3C2_STOP_Pos)
3510 #define DBGMCU_APB3FZR_DBG_I3C2_STOP        DBGMCU_APB3FZR_DBG_I3C2_STOP_Msk
3511 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos  (17U)
3512 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk  (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos)
3513 #define DBGMCU_APB3FZR_DBG_LPTIM1_STOP      DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk
3514 #define DBGMCU_APB3FZR_DBG_RTC_STOP_Pos     (30U)
3515 #define DBGMCU_APB3FZR_DBG_RTC_STOP_Msk     (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos)
3516 #define DBGMCU_APB3FZR_DBG_RTC_STOP         DBGMCU_APB3FZR_DBG_RTC_STOP_Msk
3517 
3518 /********************  Bit definition for DBGMCU_AHB1FZR register  ***********/
3519 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos  (0U)
3520 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos)
3521 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk
3522 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos  (1U)
3523 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos)
3524 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk
3525 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos  (2U)
3526 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos)
3527 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk
3528 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos  (3U)
3529 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos)
3530 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk
3531 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos  (4U)
3532 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos)
3533 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk
3534 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos  (5U)
3535 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos)
3536 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk
3537 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos  (6U)
3538 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos)
3539 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk
3540 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos  (7U)
3541 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos)
3542 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk
3543 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Pos  (8U)
3544 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Pos)
3545 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP_Msk
3546 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Pos  (9U)
3547 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Pos)
3548 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP      DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP_Msk
3549 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Pos (10U)
3550 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Pos)
3551 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP_Msk
3552 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Pos (11U)
3553 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Pos)
3554 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP_Msk
3555 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Pos (12U)
3556 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Pos)
3557 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH12_STOP_Msk
3558 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Pos (13U)
3559 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Pos)
3560 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH13_STOP_Msk
3561 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Pos (14U)
3562 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Pos)
3563 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH14_STOP_Msk
3564 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Pos (15U)
3565 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Pos)
3566 #define DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP     DBGMCU_AHB1FZR_DBG_GPDMA1_CH15_STOP_Msk
3567 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Pos  (16U)
3568 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Msk  (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Pos)
3569 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP      DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP_Msk
3570 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Pos (17U)
3571 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Pos)
3572 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP      DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP_Msk
3573 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Pos (18U)
3574 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Pos)
3575 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP_Msk
3576 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Pos (19U)
3577 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Pos)
3578 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP_Msk
3579 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Pos (20U)
3580 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Pos)
3581 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP_Msk
3582 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Pos (21U)
3583 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Pos)
3584 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP_Msk
3585 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Pos (22U)
3586 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Pos)
3587 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP_Msk
3588 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Pos (23U)
3589 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Pos)
3590 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP_Msk
3591 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Pos (24U)
3592 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Pos)
3593 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP_Msk
3594 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Pos (25U)
3595 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Pos)
3596 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP_Msk
3597 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Pos (26U)
3598 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Pos)
3599 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP_Msk
3600 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Pos (27U)
3601 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Pos)
3602 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP_Msk
3603 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Pos (28U)
3604 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Pos)
3605 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH12_STOP_Msk
3606 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Pos (29U)
3607 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Pos)
3608 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH13_STOP_Msk
3609 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Pos (30U)
3610 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Pos)
3611 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH14_STOP_Msk
3612 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Pos (31U)
3613 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Pos)
3614 #define DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP     DBGMCU_AHB1FZR_DBG_GPDMA2_CH15_STOP_Msk
3615 
3616 /********************  Bit definition for DBGMCU_SR register  ***********/
3617 #define DBGMCU_SR_ACC_PORT_PRES_Pos          (0U)
3618 #define DBGMCU_SR_ACC_PORT_PRES_Msk          (0xFFFFUL << DBGMCU_SR_ACC_PORT_PRES_Pos)   /*!< 0x0000FFFF */
3619 #define DBGMCU_SR_ACC_PORT_PRES              DBGMCU_SR_ACC_PORT_PRES_Msk
3620 #define DBGMCU_SR_ACC_PORT_ENBL_Pos          (16U)
3621 #define DBGMCU_SR_ACC_PORT_ENBL_Msk          (0xFFFFUL << DBGMCU_SR_ACC_PORT_ENBL_Pos)   /*!< 0xFFFF0000 */
3622 #define DBGMCU_SR_ACC_PORT_ENBL              DBGMCU_SR_ACC_PORT_ENBL_Msk
3623 
3624 /********************  Bit definition for DBGMCU_DBG_AUTH_HOST register  ***********/
3625 #define DBGMCU_DBG_AUTH_HOST_Pos             (0U)
3626 #define DBGMCU_DBG_AUTH_HOST_Msk             (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_Pos)  /*!< 0xFFFFFFFF */
3627 #define DBGMCU_DBG_AUTH_HOST                 DBGMCU_DBG_AUTH_HOST_Msk
3628 
3629 /********************  Bit definition for DBGMCU_DBG_AUTH_DEV register  ***********/
3630 #define DBGMCU_DBG_AUTH_DEV_Pos              (0U)
3631 #define DBGMCU_DBG_AUTH_DEV_Msk              (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_Pos)   /*!< 0xFFFFFFFF */
3632 #define DBGMCU_DBG_AUTH_DEV                  DBGMCU_DBG_AUTH_DEV_Msk
3633 
3634 /********************  Bit definition for DBGMCU_DBG_AUTH_ACK register  ***********/
3635 #define DBGMCU_DBG_AUTH_ACK_HOST_Pos         (0U)
3636 #define DBGMCU_DBG_AUTH_ACK_HOST_Msk         (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_Pos)     /*!< 0x00000001 */
3637 #define DBGMCU_DBG_AUTH_ACK_HOST             DBGMCU_DBG_AUTH_ACK_HOST_Msk
3638 #define DBGMCU_DBG_AUTH_ACK_DEV_Pos          (1U)
3639 #define DBGMCU_DBG_AUTH_ACK_DEV_Msk          (0x1UL << DBGMCU_DBG_AUTH_ACK_DEV_Pos)      /*!< 0x00000002 */
3640 #define DBGMCU_DBG_AUTH_ACK_DEV              DBGMCU_DBG_AUTH_ACK_DEV_Msk
3641 
3642 /********************  Bit definition for DBGMCU_PIDR4 register  ************/
3643 #define DBGMCU_PIDR4_JEP106CON_Pos           (0U)
3644 #define DBGMCU_PIDR4_JEP106CON_Msk           (0xFUL << DBGMCU_PIDR4_JEP106CON_Pos)    /*!< 0x0000000F */
3645 #define DBGMCU_PIDR4_JEP106CON               DBGMCU_PIDR4_JEP106CON_Msk
3646 #define DBGMCU_PIDR4_4KCOUNT_Pos             (4U)
3647 #define DBGMCU_PIDR4_4KCOUNT_Msk             (0xFUL << DBGMCU_PIDR4_4KCOUNT_Pos)      /*!< 0x000000F0 */
3648 #define DBGMCU_PIDR4_4KCOUNT                 DBGMCU_PIDR4_4KCOUNT_Msk
3649 
3650 /********************  Bit definition for DBGMCU_PIDR0 register  ************/
3651 #define DBGMCU_PIDR0_PARTNUM_Pos             (0U)
3652 #define DBGMCU_PIDR0_PARTNUM_Msk             (0xFFUL << DBGMCU_PIDR0_PARTNUM_Pos)     /*!< 0x000000FF */
3653 #define DBGMCU_PIDR0_PARTNUM                 DBGMCU_PIDR0_PARTNUM_Msk
3654 
3655 /********************  Bit definition for DBGMCU_PIDR1 register  ************/
3656 #define DBGMCU_PIDR1_PARTNUM_Pos             (0U)
3657 #define DBGMCU_PIDR1_PARTNUM_Msk             (0xFUL << DBGMCU_PIDR1_PARTNUM_Pos)      /*!< 0x0000000F */
3658 #define DBGMCU_PIDR1_PARTNUM                 DBGMCU_PIDR1_PARTNUM_Msk
3659 #define DBGMCU_PIDR1_JEP106ID_Pos            (4U)
3660 #define DBGMCU_PIDR1_JEP106ID_Msk            (0xFUL << DBGMCU_PIDR1_JEP106ID_Pos)     /*!< 0x000000F0 */
3661 #define DBGMCU_PIDR1_JEP106ID                DBGMCU_PIDR1_JEP106ID_Msk
3662 
3663 /********************  Bit definition for DBGMCU_PIDR2 register  ************/
3664 #define DBGMCU_PIDR2_JEP106ID_Pos            (0U)
3665 #define DBGMCU_PIDR2_JEP106ID_Msk            (0x7UL << DBGMCU_PIDR2_JEP106ID_Pos)     /*!< 0x00000007 */
3666 #define DBGMCU_PIDR2_JEP106ID                DBGMCU_PIDR2_JEP106ID_Msk
3667 #define DBGMCU_PIDR2_JEDEC_Pos               (3U)
3668 #define DBGMCU_PIDR2_JEDEC_Msk               (0x1UL << DBGMCU_PIDR2_JEDEC_Pos)        /*!< 0x00000008 */
3669 #define DBGMCU_PIDR2_JEDEC                   DBGMCU_PIDR2_JEDEC_Msk
3670 #define DBGMCU_PIDR2_REVISION_Pos            (4U)
3671 #define DBGMCU_PIDR2_REVISION_Msk            (0xFUL << DBGMCU_PIDR2_REVISION_Pos)     /*!< 0x000000F0 */
3672 #define DBGMCU_PIDR2_REVISION                DBGMCU_PIDR2_REVISION_Msk
3673 
3674 /********************  Bit definition for DBGMCU_PIDR3 register  ************/
3675 #define DBGMCU_PIDR3_CMOD_Pos                (0U)
3676 #define DBGMCU_PIDR3_CMOD_Msk                (0xFUL << DBGMCU_PIDR3_CMOD_Pos)         /*!< 0x0000000F */
3677 #define DBGMCU_PIDR3_CMOD                    DBGMCU_PIDR3_CMOD_Msk
3678 #define DBGMCU_PIDR3_REVAND_Pos              (4U)
3679 #define DBGMCU_PIDR3_REVAND_Msk              (0xFUL << DBGMCU_PIDR3_REVAND_Pos)       /*!< 0x000000F0 */
3680 #define DBGMCU_PIDR3_REVAND                  DBGMCU_PIDR3_REVAND_Msk
3681 
3682 /********************  Bit definition for DBGMCU_CIDR0 register  ************/
3683 #define DBGMCU_CIDR0_PREAMBLE_Pos            (0U)
3684 #define DBGMCU_CIDR0_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR0_PREAMBLE_Pos)    /*!< 0x000000FF */
3685 #define DBGMCU_CIDR0_PREAMBLE                DBGMCU_CIDR0_PREAMBLE_Msk
3686 
3687 /********************  Bit definition for DBGMCU_CIDR1 register  ************/
3688 #define DBGMCU_CIDR1_PREAMBLE_Pos            (0U)
3689 #define DBGMCU_CIDR1_PREAMBLE_Msk            (0xFUL << DBGMCU_CIDR1_PREAMBLE_Pos)     /*!< 0x0000000F */
3690 #define DBGMCU_CIDR1_PREAMBLE                DBGMCU_CIDR1_PREAMBLE_Msk
3691 #define DBGMCU_CIDR1_CLASS_Pos               (4U)
3692 #define DBGMCU_CIDR1_CLASS_Msk               (0xFUL << DBGMCU_CIDR1_CLASS_Pos)        /*!< 0x000000F0 */
3693 #define DBGMCU_CIDR1_CLASS                   DBGMCU_CIDR1_CLASS_Msk
3694 
3695 /********************  Bit definition for DBGMCU_CIDR2 register  ************/
3696 #define DBGMCU_CIDR2_PREAMBLE_Pos            (0U)
3697 #define DBGMCU_CIDR2_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR2_PREAMBLE_Pos)    /*!< 0x000000FF */
3698 #define DBGMCU_CIDR2_PREAMBLE                DBGMCU_CIDR2_PREAMBLE_Msk
3699 
3700 /********************  Bit definition for DBGMCU_CIDR3 register  ************/
3701 #define DBGMCU_CIDR3_PREAMBLE_Pos            (0U)
3702 #define DBGMCU_CIDR3_PREAMBLE_Msk            (0xFFUL << DBGMCU_CIDR3_PREAMBLE_Pos)    /*!< 0x000000FF */
3703 #define DBGMCU_CIDR3_PREAMBLE                DBGMCU_CIDR3_PREAMBLE_Msk
3704 /******************************************************************************/
3705 /*                                                                            */
3706 /*                           DMA Controller (DMA)                             */
3707 /*                                                                            */
3708 /******************************************************************************/
3709 
3710 /*******************  Bit definition for DMA_PRIVCFGR register  ****************/
3711 #define DMA_PRIVCFGR_PRIV0_Pos              (0U)
3712 #define DMA_PRIVCFGR_PRIV0_Msk              (0x1UL << DMA_PRIVCFGR_PRIV0_Pos)       /*!< 0x00000001 */
3713 #define DMA_PRIVCFGR_PRIV0                  DMA_PRIVCFGR_PRIV0_Msk                  /*!< Privileged State of Channel 0  */
3714 #define DMA_PRIVCFGR_PRIV1_Pos              (1U)
3715 #define DMA_PRIVCFGR_PRIV1_Msk              (0x1UL << DMA_PRIVCFGR_PRIV1_Pos)       /*!< 0x00000002 */
3716 #define DMA_PRIVCFGR_PRIV1                  DMA_PRIVCFGR_PRIV1_Msk                  /*!< Privileged State of Channel 1  */
3717 #define DMA_PRIVCFGR_PRIV2_Pos              (2U)
3718 #define DMA_PRIVCFGR_PRIV2_Msk              (0x1UL << DMA_PRIVCFGR_PRIV2_Pos)       /*!< 0x00000004 */
3719 #define DMA_PRIVCFGR_PRIV2                  DMA_PRIVCFGR_PRIV2_Msk                  /*!< Privileged State of Channel 2  */
3720 #define DMA_PRIVCFGR_PRIV3_Pos              (3U)
3721 #define DMA_PRIVCFGR_PRIV3_Msk              (0x1UL << DMA_PRIVCFGR_PRIV3_Pos)       /*!< 0x00000008 */
3722 #define DMA_PRIVCFGR_PRIV3                  DMA_PRIVCFGR_PRIV3_Msk                  /*!< Privileged State of Channel 3  */
3723 #define DMA_PRIVCFGR_PRIV4_Pos              (4U)
3724 #define DMA_PRIVCFGR_PRIV4_Msk              (0x1UL << DMA_PRIVCFGR_PRIV4_Pos)       /*!< 0x00000010 */
3725 #define DMA_PRIVCFGR_PRIV4                  DMA_PRIVCFGR_PRIV4_Msk                  /*!< Privileged State of Channel 4  */
3726 #define DMA_PRIVCFGR_PRIV5_Pos              (5U)
3727 #define DMA_PRIVCFGR_PRIV5_Msk              (0x1UL << DMA_PRIVCFGR_PRIV5_Pos)       /*!< 0x00000020 */
3728 #define DMA_PRIVCFGR_PRIV5                  DMA_PRIVCFGR_PRIV5_Msk                  /*!< Privileged State of Channel 5  */
3729 #define DMA_PRIVCFGR_PRIV6_Pos              (6U)
3730 #define DMA_PRIVCFGR_PRIV6_Msk              (0x1UL << DMA_PRIVCFGR_PRIV6_Pos)       /*!< 0x00000040 */
3731 #define DMA_PRIVCFGR_PRIV6                  DMA_PRIVCFGR_PRIV6_Msk                  /*!< Privileged State of Channel 6  */
3732 #define DMA_PRIVCFGR_PRIV7_Pos              (7U)
3733 #define DMA_PRIVCFGR_PRIV7_Msk              (0x1UL << DMA_PRIVCFGR_PRIV7_Pos)       /*!< 0x00000080 */
3734 #define DMA_PRIVCFGR_PRIV7                  DMA_PRIVCFGR_PRIV7_Msk                  /*!< Privileged State of Channel 7  */
3735 
3736 
3737 /*******************  Bit definition for DMA_MISR register  ****************/
3738 #define DMA_MISR_MIS0_Pos                   (0U)
3739 #define DMA_MISR_MIS0_Msk                   (0x1UL << DMA_MISR_MIS0_Pos)            /*!< 0x00000001 */
3740 #define DMA_MISR_MIS0                       DMA_MISR_MIS0_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 0  */
3741 #define DMA_MISR_MIS1_Pos                   (1U)
3742 #define DMA_MISR_MIS1_Msk                   (0x1UL << DMA_MISR_MIS1_Pos)            /*!< 0x00000002 */
3743 #define DMA_MISR_MIS1                       DMA_MISR_MIS1_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 1  */
3744 #define DMA_MISR_MIS2_Pos                   (2U)
3745 #define DMA_MISR_MIS2_Msk                   (0x1UL << DMA_MISR_MIS2_Pos)            /*!< 0x00000004 */
3746 #define DMA_MISR_MIS2                       DMA_MISR_MIS2_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 2  */
3747 #define DMA_MISR_MIS3_Pos                   (3U)
3748 #define DMA_MISR_MIS3_Msk                   (0x1UL << DMA_MISR_MIS3_Pos)            /*!< 0x00000008 */
3749 #define DMA_MISR_MIS3                       DMA_MISR_MIS3_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 3  */
3750 #define DMA_MISR_MIS4_Pos                   (4U)
3751 #define DMA_MISR_MIS4_Msk                   (0x1UL << DMA_MISR_MIS4_Pos)            /*!< 0x00000010 */
3752 #define DMA_MISR_MIS4                       DMA_MISR_MIS4_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 4  */
3753 #define DMA_MISR_MIS5_Pos                   (5U)
3754 #define DMA_MISR_MIS5_Msk                   (0x1UL << DMA_MISR_MIS5_Pos)            /*!< 0x00000020 */
3755 #define DMA_MISR_MIS5                       DMA_MISR_MIS5_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 5  */
3756 #define DMA_MISR_MIS6_Pos                   (6U)
3757 #define DMA_MISR_MIS6_Msk                   (0x1UL << DMA_MISR_MIS6_Pos)            /*!< 0x00000040 */
3758 #define DMA_MISR_MIS6                       DMA_MISR_MIS6_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 6  */
3759 #define DMA_MISR_MIS7_Pos                   (7U)
3760 #define DMA_MISR_MIS7_Msk                   (0x1UL << DMA_MISR_MIS7_Pos)            /*!< 0x00000080 */
3761 #define DMA_MISR_MIS7                       DMA_MISR_MIS7_Msk                       /*!< Masked Interrupt State of Non-Secure Channel 7  */
3762 
3763 
3764 /*******************  Bit definition for DMA_CLBAR register  ****************/
3765 #define DMA_CLBAR_LBA_Pos                   (16U)
3766 #define DMA_CLBAR_LBA_Msk                   (0xFFFFUL << DMA_CLBAR_LBA_Pos)         /*!< 0xFFFF0000 */
3767 #define DMA_CLBAR_LBA                       DMA_CLBAR_LBA_Msk                       /*!< Linked-list Base Address of DMA channel x */
3768 
3769 /*******************  Bit definition for DMA_CFCR register  *******************/
3770 #define DMA_CFCR_TCF_Pos                    (8U)
3771 #define DMA_CFCR_TCF_Msk                    (0x1UL << DMA_CFCR_TCF_Pos)             /*!< 0x00000100 */
3772 #define DMA_CFCR_TCF                        DMA_CFCR_TCF_Msk                        /*!< Transfer complete flag clear             */
3773 #define DMA_CFCR_HTF_Pos                    (9U)
3774 #define DMA_CFCR_HTF_Msk                    (0x1UL << DMA_CFCR_HTF_Pos)             /*!< 0x00000200 */
3775 #define DMA_CFCR_HTF                        DMA_CFCR_HTF_Msk                        /*!< Half transfer complete flag clear        */
3776 #define DMA_CFCR_DTEF_Pos                   (10U)
3777 #define DMA_CFCR_DTEF_Msk                   (0x1UL << DMA_CFCR_DTEF_Pos)            /*!< 0x00000400 */
3778 #define DMA_CFCR_DTEF                       DMA_CFCR_DTEF_Msk                       /*!< Data transfer error flag clear           */
3779 #define DMA_CFCR_ULEF_Pos                   (11U)
3780 #define DMA_CFCR_ULEF_Msk                   (0x1UL << DMA_CFCR_ULEF_Pos)            /*!< 0x00000800 */
3781 #define DMA_CFCR_ULEF                       DMA_CFCR_ULEF_Msk                       /*!< Update linked-list item error flag clear */
3782 #define DMA_CFCR_USEF_Pos                   (12U)
3783 #define DMA_CFCR_USEF_Msk                   (0x1UL << DMA_CFCR_USEF_Pos)            /*!< 0x00001000 */
3784 #define DMA_CFCR_USEF                       DMA_CFCR_USEF_Msk                       /*!< User setting error flag clear            */
3785 #define DMA_CFCR_SUSPF_Pos                  (13U)
3786 #define DMA_CFCR_SUSPF_Msk                  (0x1UL << DMA_CFCR_SUSPF_Pos)           /*!< 0x00002000 */
3787 #define DMA_CFCR_SUSPF                      DMA_CFCR_SUSPF_Msk                      /*!< Completed suspension flag clear          */
3788 #define DMA_CFCR_TOF_Pos                    (14U)
3789 #define DMA_CFCR_TOF_Msk                    (0x1UL << DMA_CFCR_TOF_Pos)             /*!< 0x00004000 */
3790 #define DMA_CFCR_TOF                        DMA_CFCR_TOF_Msk                        /*!< Trigger overrun flag clear               */
3791 
3792 /*******************  Bit definition for DMA_CSR register  *******************/
3793 #define DMA_CSR_IDLEF_Pos                   (0U)
3794 #define DMA_CSR_IDLEF_Msk                   (0x1UL << DMA_CSR_IDLEF_Pos)            /*!< 0x00000001 */
3795 #define DMA_CSR_IDLEF                       DMA_CSR_IDLEF_Msk                       /*!< Idle flag                          */
3796 #define DMA_CSR_TCF_Pos                     (8U)
3797 #define DMA_CSR_TCF_Msk                     (0x1UL << DMA_CSR_TCF_Pos)              /*!< 0x00000100 */
3798 #define DMA_CSR_TCF                         DMA_CSR_TCF_Msk                         /*!< Transfer complete flag             */
3799 #define DMA_CSR_HTF_Pos                     (9U)
3800 #define DMA_CSR_HTF_Msk                     (0x1UL << DMA_CSR_HTF_Pos)              /*!< 0x00000200 */
3801 #define DMA_CSR_HTF                         DMA_CSR_HTF_Msk                         /*!< Half transfer complete flag        */
3802 #define DMA_CSR_DTEF_Pos                    (10U)
3803 #define DMA_CSR_DTEF_Msk                    (0x1UL << DMA_CSR_DTEF_Pos)             /*!< 0x00000400 */
3804 #define DMA_CSR_DTEF                        DMA_CSR_DTEF_Msk                        /*!< Data transfer error flag           */
3805 #define DMA_CSR_ULEF_Pos                    (11U)
3806 #define DMA_CSR_ULEF_Msk                    (0x1UL << DMA_CSR_ULEF_Pos)             /*!< 0x00000800 */
3807 #define DMA_CSR_ULEF                        DMA_CSR_ULEF_Msk                        /*!< Update linked-list item error flag */
3808 #define DMA_CSR_USEF_Pos                    (12U)
3809 #define DMA_CSR_USEF_Msk                    (0x1UL << DMA_CSR_USEF_Pos)             /*!< 0x00001000 */
3810 #define DMA_CSR_USEF                        DMA_CSR_USEF_Msk                        /*!< User setting error flag            */
3811 #define DMA_CSR_SUSPF_Pos                   (13U)
3812 #define DMA_CSR_SUSPF_Msk                   (0x1UL << DMA_CSR_SUSPF_Pos)            /*!< 0x00002000 */
3813 #define DMA_CSR_SUSPF                       DMA_CSR_SUSPF_Msk                       /*!< User setting error flag            */
3814 #define DMA_CSR_TOF_Pos                     (14U)
3815 #define DMA_CSR_TOF_Msk                     (0x1UL << DMA_CSR_TOF_Pos)              /*!< 0x00004000 */
3816 #define DMA_CSR_TOF                         DMA_CSR_TOF_Msk                         /*!< Trigger overrun flag               */
3817 #define DMA_CSR_FIFOL_Pos                   (16U)
3818 #define DMA_CSR_FIFOL_Msk                   (0xFFUL << DMA_CSR_FIFOL_Pos)           /*!< 0x00FF0000 */
3819 #define DMA_CSR_FIFOL                       DMA_CSR_FIFOL_Msk                       /*!< Monitored FIFO level in bytes      */
3820 
3821 /*******************  Bit definition for DMA_CCR register  ********************/
3822 #define DMA_CCR_EN_Pos                      (0U)
3823 #define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)               /*!< 0x00000001 */
3824 #define DMA_CCR_EN                          DMA_CCR_EN_Msk                          /*!< Channel enable                                 */
3825 #define DMA_CCR_RESET_Pos                   (1U)
3826 #define DMA_CCR_RESET_Msk                   (0x1UL << DMA_CCR_RESET_Pos)            /*!< 0x00000002 */
3827 #define DMA_CCR_RESET                       DMA_CCR_RESET_Msk                       /*!< Channel reset                                  */
3828 #define DMA_CCR_SUSP_Pos                    (2U)
3829 #define DMA_CCR_SUSP_Msk                    (0x1UL << DMA_CCR_SUSP_Pos)             /*!< 0x00000004 */
3830 #define DMA_CCR_SUSP                        DMA_CCR_SUSP_Msk                        /*!< Channel suspend                                */
3831 #define DMA_CCR_TCIE_Pos                    (8U)
3832 #define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)             /*!< 0x00000100 */
3833 #define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                        /*!< Transfer complete interrupt enable             */
3834 #define DMA_CCR_HTIE_Pos                    (9U)
3835 #define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)             /*!< 0x00000200 */
3836 #define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                        /*!< Half transfer complete interrupt enable        */
3837 #define DMA_CCR_DTEIE_Pos                   (10U)
3838 #define DMA_CCR_DTEIE_Msk                   (0x1UL << DMA_CCR_DTEIE_Pos)            /*!< 0x00000400 */
3839 #define DMA_CCR_DTEIE                       DMA_CCR_DTEIE_Msk                       /*!< Data transfer error interrupt enable           */
3840 #define DMA_CCR_ULEIE_Pos                   (11U)
3841 #define DMA_CCR_ULEIE_Msk                   (0x1UL << DMA_CCR_ULEIE_Pos)            /*!< 0x00000800 */
3842 #define DMA_CCR_ULEIE                       DMA_CCR_ULEIE_Msk                       /*!< Update linked-list item error interrupt enable */
3843 #define DMA_CCR_USEIE_Pos                   (12U)
3844 #define DMA_CCR_USEIE_Msk                   (0x1UL << DMA_CCR_USEIE_Pos)            /*!< 0x00001000 */
3845 #define DMA_CCR_USEIE                       DMA_CCR_USEIE_Msk                       /*!< User setting error interrupt enable            */
3846 #define DMA_CCR_SUSPIE_Pos                  (13U)
3847 #define DMA_CCR_SUSPIE_Msk                  (0x1UL << DMA_CCR_SUSPIE_Pos)           /*!< 0x00002000 */
3848 #define DMA_CCR_SUSPIE                      DMA_CCR_SUSPIE_Msk                      /*!< Completed suspension interrupt enable          */
3849 #define DMA_CCR_TOIE_Pos                    (14U)
3850 #define DMA_CCR_TOIE_Msk                    (0x1UL << DMA_CCR_TOIE_Pos)             /*!< 0x00004000 */
3851 #define DMA_CCR_TOIE                        DMA_CCR_TOIE_Msk                        /*!< Trigger overrun interrupt enable               */
3852 #define DMA_CCR_LSM_Pos                     (16U)
3853 #define DMA_CCR_LSM_Msk                     (0x1UL << DMA_CCR_LSM_Pos)              /*!< 0x00010000 */
3854 #define DMA_CCR_LSM                         DMA_CCR_LSM_Msk                         /*!< Link step mode                                 */
3855 #define DMA_CCR_LAP_Pos                     (17U)
3856 #define DMA_CCR_LAP_Msk                     (0x1UL << DMA_CCR_LAP_Pos)              /*!< 0x00020000 */
3857 #define DMA_CCR_LAP                         DMA_CCR_LAP_Msk                         /*!< Linked-list allocated port                     */
3858 #define DMA_CCR_PRIO_Pos                    (22U)
3859 #define DMA_CCR_PRIO_Msk                    (0x3UL << DMA_CCR_PRIO_Pos)             /*!< 0x00C00000 */
3860 #define DMA_CCR_PRIO                        DMA_CCR_PRIO_Msk                        /*!< Priority level                                 */
3861 #define DMA_CCR_PRIO_0                      (0x1UL << DMA_CCR_PRIO_Pos)             /*!< 0x00400000 */
3862 #define DMA_CCR_PRIO_1                      (0x2UL << DMA_CCR_PRIO_Pos)             /*!< 0x00800000 */
3863 
3864 /*******************  Bit definition for DMA_CTR1 register  *******************/
3865 #define DMA_CTR1_SDW_LOG2_Pos               (0U)
3866 #define DMA_CTR1_SDW_LOG2_Msk               (0x3UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< 0x00000003 */
3867 #define DMA_CTR1_SDW_LOG2                   DMA_CTR1_SDW_LOG2_Msk                   /*!< Binary logarithm of the source data width of a burst                    */
3868 #define DMA_CTR1_SDW_LOG2_0                 (0x1UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 0 */
3869 #define DMA_CTR1_SDW_LOG2_1                 (0x2UL << DMA_CTR1_SDW_LOG2_Pos)        /*!< Bit 1 */
3870 #define DMA_CTR1_SINC_Pos                   (3U)
3871 #define DMA_CTR1_SINC_Msk                   (0x1UL << DMA_CTR1_SINC_Pos)            /*!< 0x00000008 */
3872 #define DMA_CTR1_SINC                       DMA_CTR1_SINC_Msk                       /*!< Source incrementing burst                                               */
3873 #define DMA_CTR1_SBL_1_Pos                  (4U)
3874 #define DMA_CTR1_SBL_1_Msk                  (0x3FUL << DMA_CTR1_SBL_1_Pos)          /*!< 0x000003F0 */
3875 #define DMA_CTR1_SBL_1                      DMA_CTR1_SBL_1_Msk                      /*!< Source burst length minus 1                                             */
3876 #define DMA_CTR1_PAM_Pos                    (11U)
3877 #define DMA_CTR1_PAM_Msk                    (0x3UL << DMA_CTR1_PAM_Pos)             /*!< 0x0001800 */
3878 #define DMA_CTR1_PAM                        DMA_CTR1_PAM_Msk                        /*!< Padding / alignment mode                                                */
3879 #define DMA_CTR1_PAM_0                      (0x1UL << DMA_CTR1_PAM_Pos)             /*!< Bit 0 */
3880 #define DMA_CTR1_PAM_1                      (0x2UL << DMA_CTR1_PAM_Pos)             /*!< Bit 1 */
3881 #define DMA_CTR1_SBX_Pos                    (13U)
3882 #define DMA_CTR1_SBX_Msk                    (0x1UL << DMA_CTR1_SBX_Pos)             /*!< 0x00002000 */
3883 #define DMA_CTR1_SBX                        DMA_CTR1_SBX_Msk                        /*!< Source byte exchange within the unaligned half-word of each source word */
3884 #define DMA_CTR1_SAP_Pos                    (14U)
3885 #define DMA_CTR1_SAP_Msk                    (0x1UL << DMA_CTR1_SAP_Pos)             /*!< 0x00004000 */
3886 #define DMA_CTR1_SAP                        DMA_CTR1_SAP_Msk                        /*!< Source allocated port                                                   */
3887 #define DMA_CTR1_DDW_LOG2_Pos               (16U)
3888 #define DMA_CTR1_DDW_LOG2_Msk               (0x3UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< 0x00030000 */
3889 #define DMA_CTR1_DDW_LOG2                   DMA_CTR1_DDW_LOG2_Msk                   /*!< Binary logarithm of the destination data width of a burst               */
3890 #define DMA_CTR1_DDW_LOG2_0                 (0x1UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 0 */
3891 #define DMA_CTR1_DDW_LOG2_1                 (0x2UL << DMA_CTR1_DDW_LOG2_Pos)        /*!< Bit 1 */
3892 #define DMA_CTR1_DINC_Pos                   (19U)
3893 #define DMA_CTR1_DINC_Msk                   (0x1UL << DMA_CTR1_DINC_Pos)            /*!< 0x00080000 */
3894 #define DMA_CTR1_DINC                       DMA_CTR1_DINC_Msk                       /*!< Destination incrementing burst                                          */
3895 #define DMA_CTR1_DBL_1_Pos                  (20U)
3896 #define DMA_CTR1_DBL_1_Msk                  (0x3FUL << DMA_CTR1_DBL_1_Pos)          /*!< 0x03F00000 */
3897 #define DMA_CTR1_DBL_1                      DMA_CTR1_DBL_1_Msk                      /*!< Destination burst length minus 1                                        */
3898 #define DMA_CTR1_DBX_Pos                    (26U)
3899 #define DMA_CTR1_DBX_Msk                    (0x1UL << DMA_CTR1_DBX_Pos)             /*!< 0x04000000 */
3900 #define DMA_CTR1_DBX                        DMA_CTR1_DBX_Msk                        /*!< Destination byte exchange                                               */
3901 #define DMA_CTR1_DHX_Pos                    (27U)
3902 #define DMA_CTR1_DHX_Msk                    (0x1UL << DMA_CTR1_DHX_Pos)             /*!< 0x08000000 */
3903 #define DMA_CTR1_DHX                        DMA_CTR1_DHX_Msk                        /*!< Destination half-word exchange                                          */
3904 #define DMA_CTR1_DAP_Pos                    (30U)
3905 #define DMA_CTR1_DAP_Msk                    (0x1UL << DMA_CTR1_DAP_Pos)             /*!< 0x40000000 */
3906 #define DMA_CTR1_DAP                        DMA_CTR1_DAP_Msk                        /*!< Destination allocated port                                              */
3907 
3908 /******************  Bit definition for DMA_CTR2 register  *******************/
3909 #define DMA_CTR2_REQSEL_Pos                 (0U)
3910 #define DMA_CTR2_REQSEL_Msk                 (0xFFUL << DMA_CTR2_REQSEL_Pos)         /*!< 0x000000FF */
3911 #define DMA_CTR2_REQSEL                     DMA_CTR2_REQSEL_Msk                     /*!< DMA hardware request selection */
3912 #define DMA_CTR2_SWREQ_Pos                  (9U)
3913 #define DMA_CTR2_SWREQ_Msk                  (0x1UL << DMA_CTR2_SWREQ_Pos)           /*!< 0x00000200 */
3914 #define DMA_CTR2_SWREQ                      DMA_CTR2_SWREQ_Msk                      /*!< Software request               */
3915 #define DMA_CTR2_DREQ_Pos                   (10U)
3916 #define DMA_CTR2_DREQ_Msk                   (0x1UL << DMA_CTR2_DREQ_Pos)            /*!< 0x00000400 */
3917 #define DMA_CTR2_DREQ                       DMA_CTR2_DREQ_Msk                       /*!< Destination hardware request   */
3918 #define DMA_CTR2_BREQ_Pos                   (11U)
3919 #define DMA_CTR2_BREQ_Msk                   (0x1UL << DMA_CTR2_BREQ_Pos)            /*!< 0x00000800 */
3920 #define DMA_CTR2_BREQ                       DMA_CTR2_BREQ_Msk                       /*!< Block hardware request         */
3921 #define DMA_CTR2_PFREQ_Pos                  (12U)
3922 #define DMA_CTR2_PFREQ_Msk                  (0x1U << DMA_CTR2_PFREQ_Pos)            /*!< 0x00001000 */
3923 #define DMA_CTR2_PFREQ                      DMA_CTR2_PFREQ_Msk                      /*!< Block hardware request */
3924 #define DMA_CTR2_TRIGM_Pos                  (14U)
3925 #define DMA_CTR2_TRIGM_Msk                  (0x3UL << DMA_CTR2_TRIGM_Pos)           /*!< 0x0000C000 */
3926 #define DMA_CTR2_TRIGM                      DMA_CTR2_TRIGM_Msk                      /*!< Trigger mode                   */
3927 #define DMA_CTR2_TRIGM_0                    (0x1UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 0 */
3928 #define DMA_CTR2_TRIGM_1                    (0x2UL << DMA_CTR2_TRIGM_Pos)           /*!< Bit 1 */
3929 #define DMA_CTR2_TRIGSEL_Pos                (16U)
3930 #define DMA_CTR2_TRIGSEL_Msk                (0x3FUL << DMA_CTR2_TRIGSEL_Pos)        /*!< 0x003F0000 */
3931 #define DMA_CTR2_TRIGSEL                    DMA_CTR2_TRIGSEL_Msk                    /*!< Trigger event input selection  */
3932 #define DMA_CTR2_TRIGPOL_Pos                (24U)
3933 #define DMA_CTR2_TRIGPOL_Msk                (0x3UL << DMA_CTR2_TRIGPOL_Pos)         /*!< 0x03000000 */
3934 #define DMA_CTR2_TRIGPOL                    DMA_CTR2_TRIGPOL_Msk                    /*!< Trigger event polarity         */
3935 #define DMA_CTR2_TRIGPOL_0                  (0x1UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 0 */
3936 #define DMA_CTR2_TRIGPOL_1                  (0x2UL << DMA_CTR2_TRIGPOL_Pos)         /*!< Bit 1 */
3937 #define DMA_CTR2_TCEM_Pos                   (30U)
3938 #define DMA_CTR2_TCEM_Msk                   (0x3UL << DMA_CTR2_TCEM_Pos)            /*!< 0xC0000000 */
3939 #define DMA_CTR2_TCEM                       DMA_CTR2_TCEM_Msk                       /*!< Transfer complete event mode   */
3940 #define DMA_CTR2_TCEM_0                     (0x1UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 0 */
3941 #define DMA_CTR2_TCEM_1                     (0x2UL << DMA_CTR2_TCEM_Pos)            /*!< Bit 1 */
3942 
3943 /******************  Bit definition for DMA_CBR1 register  *******************/
3944 #define DMA_CBR1_BNDT_Pos                   (0U)
3945 #define DMA_CBR1_BNDT_Msk                   (0xFFFFUL << DMA_CBR1_BNDT_Pos)         /*!< 0x0000FFFF */
3946 #define DMA_CBR1_BNDT                       DMA_CBR1_BNDT_Msk                       /*!< Block number of data bytes to transfer from the source */
3947 #define DMA_CBR1_BRC_Pos                    (16U)
3948 #define DMA_CBR1_BRC_Msk                    (0x7FFUL << DMA_CBR1_BRC_Pos)           /*!< 0x07FF0000 */
3949 #define DMA_CBR1_BRC                        DMA_CBR1_BRC_Msk                        /*!< Block repeat counter                                   */
3950 #define DMA_CBR1_SDEC_Pos                   (28U)
3951 #define DMA_CBR1_SDEC_Msk                   (0x1UL << DMA_CBR1_SDEC_Pos)            /*!< 0x10000000 */
3952 #define DMA_CBR1_SDEC                       DMA_CBR1_SDEC_Msk                       /*!< Source address decrement                               */
3953 #define DMA_CBR1_DDEC_Pos                   (29U)
3954 #define DMA_CBR1_DDEC_Msk                   (0x1UL << DMA_CBR1_DDEC_Pos)            /*!< 0x20000000 */
3955 #define DMA_CBR1_DDEC                       DMA_CBR1_DDEC_Msk                       /*!< Destination address decrement                          */
3956 #define DMA_CBR1_BRSDEC_Pos                 (30U)
3957 #define DMA_CBR1_BRSDEC_Msk                 (0x1UL << DMA_CBR1_BRSDEC_Pos)          /*!< 0x40000000 */
3958 #define DMA_CBR1_BRSDEC                     DMA_CBR1_BRSDEC_Msk                     /*!< Block repeat source address decrement                  */
3959 #define DMA_CBR1_BRDDEC_Pos                 (31U)
3960 #define DMA_CBR1_BRDDEC_Msk                 (0x1UL << DMA_CBR1_BRDDEC_Pos)          /*!< 0x80000000 */
3961 #define DMA_CBR1_BRDDEC                     DMA_CBR1_BRDDEC_Msk                     /*!< Block repeat destination address decrement             */
3962 
3963 /******************  Bit definition for DMA_CSAR register  ********************/
3964 #define DMA_CSAR_SA_Pos                     (0U)
3965 #define DMA_CSAR_SA_Msk                     (0xFFFFFFFFUL << DMA_CSAR_SA_Pos)       /*!< 0xFFFFFFFF */
3966 #define DMA_CSAR_SA                         DMA_CSAR_SA_Msk                         /*!< Source Address */
3967 
3968 /******************  Bit definition for DMA_CDAR register  *******************/
3969 #define DMA_CDAR_DA_Pos                     (0U)
3970 #define DMA_CDAR_DA_Msk                     (0xFFFFFFFFUL << DMA_CDAR_DA_Pos)       /*!< 0xFFFFFFFF */
3971 #define DMA_CDAR_DA                         DMA_CDAR_DA_Msk                         /*!< Destination address */
3972 
3973 /******************  Bit definition for DMA_CTR3 register  *******************/
3974 #define DMA_CTR3_SAO_Pos                    (0U)
3975 #define DMA_CTR3_SAO_Msk                    (0x1FFFUL << DMA_CTR3_SAO_Pos)          /*!< 0x00001FFF */
3976 #define DMA_CTR3_SAO                        DMA_CTR3_SAO_Msk                        /*!< Source address offset increment      */
3977 #define DMA_CTR3_DAO_Pos                    (16U)
3978 #define DMA_CTR3_DAO_Msk                    (0x1FFFUL << DMA_CTR3_DAO_Pos)          /*!< 0x1FFF0000 */
3979 #define DMA_CTR3_DAO                        DMA_CTR3_DAO_Msk                        /*!< Destination address offset increment */
3980 
3981 /******************  Bit definition for DMA_CBR2 register  *******************/
3982 #define DMA_CBR2_BRSAO_Pos                  (0U)
3983 #define DMA_CBR2_BRSAO_Msk                  (0xFFFFUL << DMA_CBR2_BRSAO_Pos)        /*!< 0x0000FFFF */
3984 #define DMA_CBR2_BRSAO                      DMA_CBR2_BRSAO_Msk                      /*!< Block repeated source address offset      */
3985 #define DMA_CBR2_BRDAO_Pos                  (16U)
3986 #define DMA_CBR2_BRDAO_Msk                  (0xFFFFUL << DMA_CBR2_BRDAO_Pos)        /*!< 0xFFFF0000 */
3987 #define DMA_CBR2_BRDAO                      DMA_CBR2_BRDAO_Msk                      /*!< Block repeated destination address offset */
3988 
3989 /******************  Bit definition for DMA_CLLR register  *******************/
3990 #define DMA_CLLR_LA_Pos                     (2U)
3991 #define DMA_CLLR_LA_Msk                     (0x3FFFUL << DMA_CLLR_LA_Pos)           /*!< 0x0000FFFC */
3992 #define DMA_CLLR_LA                         DMA_CLLR_LA_Msk                         /*!< Pointer to the next linked-list data structure */
3993 #define DMA_CLLR_ULL_Pos                    (16U)
3994 #define DMA_CLLR_ULL_Msk                    (0x1UL << DMA_CLLR_ULL_Pos)             /*!< 0x00010000 */
3995 #define DMA_CLLR_ULL                        DMA_CLLR_ULL_Msk                        /*!< Update link address register from memory       */
3996 #define DMA_CLLR_UB2_Pos                    (25U)
3997 #define DMA_CLLR_UB2_Msk                    (0x1UL << DMA_CLLR_UB2_Pos)             /*!< 0x02000000 */
3998 #define DMA_CLLR_UB2                        DMA_CLLR_UB2_Msk                        /*!< Update block register 2 from memory            */
3999 #define DMA_CLLR_UT3_Pos                    (26U)
4000 #define DMA_CLLR_UT3_Msk                    (0x1UL << DMA_CLLR_UT3_Pos)             /*!< 0x04000000 */
4001 #define DMA_CLLR_UT3                        DMA_CLLR_UT3_Msk                        /*!< Update transfer register 3 from SRAM           */
4002 #define DMA_CLLR_UDA_Pos                    (27U)
4003 #define DMA_CLLR_UDA_Msk                    (0x1UL << DMA_CLLR_UDA_Pos)             /*!< 0x08000000 */
4004 #define DMA_CLLR_UDA                        DMA_CLLR_UDA_Msk                        /*!< Update destination address register from SRAM  */
4005 #define DMA_CLLR_USA_Pos                    (28U)
4006 #define DMA_CLLR_USA_Msk                    (0x1UL << DMA_CLLR_USA_Pos)             /*!< 0x10000000 */
4007 #define DMA_CLLR_USA                        DMA_CLLR_USA_Msk                        /*!< Update source address register from SRAM       */
4008 #define DMA_CLLR_UB1_Pos                    (29U)
4009 #define DMA_CLLR_UB1_Msk                    (0x1UL << DMA_CLLR_UB1_Pos)             /*!< 0x20000000 */
4010 #define DMA_CLLR_UB1                        DMA_CLLR_UB1_Msk                        /*!< Update block register 1 from SRAM              */
4011 #define DMA_CLLR_UT2_Pos                    (30U)
4012 #define DMA_CLLR_UT2_Msk                    (0x1UL << DMA_CLLR_UT2_Pos)             /*!< 0x40000000 */
4013 #define DMA_CLLR_UT2                        DMA_CLLR_UT2_Msk                        /*!< Update transfer register 2 from SRAM           */
4014 #define DMA_CLLR_UT1_Pos                    (31U)
4015 #define DMA_CLLR_UT1_Msk                    (0x1UL << DMA_CLLR_UT1_Pos)             /*!< 0x80000000 */
4016 #define DMA_CLLR_UT1                        DMA_CLLR_UT1_Msk                        /*!< Update transfer register 1 from SRAM           */
4017 
4018 /******************************************************************************/
4019 /*                                                                            */
4020 /*                    External Interrupt/Event Controller                     */
4021 /*                                                                            */
4022 /******************************************************************************/
4023 /******************  Bit definition for EXTI_RTSR1 register  ******************/
4024 #define EXTI_RTSR1_RT0_Pos                  (0U)
4025 #define EXTI_RTSR1_RT0_Msk                  (0x1UL << EXTI_RTSR1_RT0_Pos)           /*!< 0x00000001 */
4026 #define EXTI_RTSR1_RT0                      EXTI_RTSR1_RT0_Msk                      /*!< Rising trigger configuration for input line 0 */
4027 #define EXTI_RTSR1_RT1_Pos                  (1U)
4028 #define EXTI_RTSR1_RT1_Msk                  (0x1UL << EXTI_RTSR1_RT1_Pos)           /*!< 0x00000002 */
4029 #define EXTI_RTSR1_RT1                      EXTI_RTSR1_RT1_Msk                      /*!< Rising trigger configuration for input line 1 */
4030 #define EXTI_RTSR1_RT2_Pos                  (2U)
4031 #define EXTI_RTSR1_RT2_Msk                  (0x1UL << EXTI_RTSR1_RT2_Pos)           /*!< 0x00000004 */
4032 #define EXTI_RTSR1_RT2                      EXTI_RTSR1_RT2_Msk                      /*!< Rising trigger configuration for input line 2 */
4033 #define EXTI_RTSR1_RT3_Pos                  (3U)
4034 #define EXTI_RTSR1_RT3_Msk                  (0x1UL << EXTI_RTSR1_RT3_Pos)           /*!< 0x00000008 */
4035 #define EXTI_RTSR1_RT3                      EXTI_RTSR1_RT3_Msk                      /*!< Rising trigger configuration for input line 3 */
4036 #define EXTI_RTSR1_RT4_Pos                  (4U)
4037 #define EXTI_RTSR1_RT4_Msk                  (0x1UL << EXTI_RTSR1_RT4_Pos)           /*!< 0x00000010 */
4038 #define EXTI_RTSR1_RT4                      EXTI_RTSR1_RT4_Msk                      /*!< Rising trigger configuration for input line 4 */
4039 #define EXTI_RTSR1_RT5_Pos                  (5U)
4040 #define EXTI_RTSR1_RT5_Msk                  (0x1UL << EXTI_RTSR1_RT5_Pos)           /*!< 0x00000020 */
4041 #define EXTI_RTSR1_RT5                      EXTI_RTSR1_RT5_Msk                      /*!< Rising trigger configuration for input line 5 */
4042 #define EXTI_RTSR1_RT6_Pos                  (6U)
4043 #define EXTI_RTSR1_RT6_Msk                  (0x1UL << EXTI_RTSR1_RT6_Pos)           /*!< 0x00000040 */
4044 #define EXTI_RTSR1_RT6                      EXTI_RTSR1_RT6_Msk                      /*!< Rising trigger configuration for input line 6 */
4045 #define EXTI_RTSR1_RT7_Pos                  (7U)
4046 #define EXTI_RTSR1_RT7_Msk                  (0x1UL << EXTI_RTSR1_RT7_Pos)           /*!< 0x00000080 */
4047 #define EXTI_RTSR1_RT7                      EXTI_RTSR1_RT7_Msk                      /*!< Rising trigger configuration for input line 7 */
4048 #define EXTI_RTSR1_RT8_Pos                  (8U)
4049 #define EXTI_RTSR1_RT8_Msk                  (0x1UL << EXTI_RTSR1_RT8_Pos)           /*!< 0x00000100 */
4050 #define EXTI_RTSR1_RT8                      EXTI_RTSR1_RT8_Msk                      /*!< Rising trigger configuration for input line 8 */
4051 #define EXTI_RTSR1_RT9_Pos                  (9U)
4052 #define EXTI_RTSR1_RT9_Msk                  (0x1UL << EXTI_RTSR1_RT9_Pos)           /*!< 0x00000200 */
4053 #define EXTI_RTSR1_RT9                      EXTI_RTSR1_RT9_Msk                      /*!< Rising trigger configuration for input line 9 */
4054 #define EXTI_RTSR1_RT10_Pos                 (10U)
4055 #define EXTI_RTSR1_RT10_Msk                 (0x1UL << EXTI_RTSR1_RT10_Pos)          /*!< 0x00000400 */
4056 #define EXTI_RTSR1_RT10                     EXTI_RTSR1_RT10_Msk                     /*!< Rising trigger configuration for input line 10 */
4057 #define EXTI_RTSR1_RT11_Pos                 (11U)
4058 #define EXTI_RTSR1_RT11_Msk                 (0x1UL << EXTI_RTSR1_RT11_Pos)          /*!< 0x00000800 */
4059 #define EXTI_RTSR1_RT11                     EXTI_RTSR1_RT11_Msk                     /*!< Rising trigger configuration for input line 11 */
4060 #define EXTI_RTSR1_RT12_Pos                 (12U)
4061 #define EXTI_RTSR1_RT12_Msk                 (0x1UL << EXTI_RTSR1_RT12_Pos)          /*!< 0x00001000 */
4062 #define EXTI_RTSR1_RT12                     EXTI_RTSR1_RT12_Msk                     /*!< Rising trigger configuration for input line 12 */
4063 #define EXTI_RTSR1_RT13_Pos                 (13U)
4064 #define EXTI_RTSR1_RT13_Msk                 (0x1UL << EXTI_RTSR1_RT13_Pos)          /*!< 0x00002000 */
4065 #define EXTI_RTSR1_RT13                     EXTI_RTSR1_RT13_Msk                     /*!< Rising trigger configuration for input line 13 */
4066 #define EXTI_RTSR1_RT14_Pos                 (14U)
4067 #define EXTI_RTSR1_RT14_Msk                 (0x1UL << EXTI_RTSR1_RT14_Pos)          /*!< 0x00004000 */
4068 #define EXTI_RTSR1_RT14                     EXTI_RTSR1_RT14_Msk                     /*!< Rising trigger configuration for input line 14 */
4069 #define EXTI_RTSR1_RT15_Pos                 (15U)
4070 #define EXTI_RTSR1_RT15_Msk                 (0x1UL << EXTI_RTSR1_RT15_Pos)          /*!< 0x00008000 */
4071 #define EXTI_RTSR1_RT15                     EXTI_RTSR1_RT15_Msk                     /*!< Rising trigger configuration for input line 15 */
4072 #define EXTI_RTSR1_RT16_Pos                 (16U)
4073 #define EXTI_RTSR1_RT16_Msk                 (0x1UL << EXTI_RTSR1_RT16_Pos)          /*!< 0x00010000 */
4074 #define EXTI_RTSR1_RT16                     EXTI_RTSR1_RT16_Msk                     /*!< Rising trigger configuration for input line 16 */
4075 
4076 /******************  Bit definition for EXTI_FTSR1 register  ******************/
4077 #define EXTI_FTSR1_FT0_Pos                  (0U)
4078 #define EXTI_FTSR1_FT0_Msk                  (0x1UL << EXTI_FTSR1_FT0_Pos)           /*!< 0x00000001 */
4079 #define EXTI_FTSR1_FT0                      EXTI_FTSR1_FT0_Msk                      /*!< Falling trigger configuration for input line 0 */
4080 #define EXTI_FTSR1_FT1_Pos                  (1U)
4081 #define EXTI_FTSR1_FT1_Msk                  (0x1UL << EXTI_FTSR1_FT1_Pos)           /*!< 0x00000002 */
4082 #define EXTI_FTSR1_FT1                      EXTI_FTSR1_FT1_Msk                      /*!< Falling trigger configuration for input line 1 */
4083 #define EXTI_FTSR1_FT2_Pos                  (2U)
4084 #define EXTI_FTSR1_FT2_Msk                  (0x1UL << EXTI_FTSR1_FT2_Pos)           /*!< 0x00000004 */
4085 #define EXTI_FTSR1_FT2                      EXTI_FTSR1_FT2_Msk                      /*!< Falling trigger configuration for input line 2 */
4086 #define EXTI_FTSR1_FT3_Pos                  (3U)
4087 #define EXTI_FTSR1_FT3_Msk                  (0x1UL << EXTI_FTSR1_FT3_Pos)           /*!< 0x00000008 */
4088 #define EXTI_FTSR1_FT3                      EXTI_FTSR1_FT3_Msk                      /*!< Falling trigger configuration for input line 3 */
4089 #define EXTI_FTSR1_FT4_Pos                  (4U)
4090 #define EXTI_FTSR1_FT4_Msk                  (0x1UL << EXTI_FTSR1_FT4_Pos)           /*!< 0x00000010 */
4091 #define EXTI_FTSR1_FT4                      EXTI_FTSR1_FT4_Msk                      /*!< Falling trigger configuration for input line 4 */
4092 #define EXTI_FTSR1_FT5_Pos                  (5U)
4093 #define EXTI_FTSR1_FT5_Msk                  (0x1UL << EXTI_FTSR1_FT5_Pos)           /*!< 0x00000020 */
4094 #define EXTI_FTSR1_FT5                      EXTI_FTSR1_FT5_Msk                      /*!< Falling trigger configuration for input line 5 */
4095 #define EXTI_FTSR1_FT6_Pos                  (6U)
4096 #define EXTI_FTSR1_FT6_Msk                  (0x1UL << EXTI_FTSR1_FT6_Pos)           /*!< 0x00000040 */
4097 #define EXTI_FTSR1_FT6                      EXTI_FTSR1_FT6_Msk                      /*!< Falling trigger configuration for input line 6 */
4098 #define EXTI_FTSR1_FT7_Pos                  (7U)
4099 #define EXTI_FTSR1_FT7_Msk                  (0x1UL << EXTI_FTSR1_FT7_Pos)           /*!< 0x00000080 */
4100 #define EXTI_FTSR1_FT7                      EXTI_FTSR1_FT7_Msk                      /*!< Falling trigger configuration for input line 7 */
4101 #define EXTI_FTSR1_FT8_Pos                  (8U)
4102 #define EXTI_FTSR1_FT8_Msk                  (0x1UL << EXTI_FTSR1_FT8_Pos)           /*!< 0x00000100 */
4103 #define EXTI_FTSR1_FT8                      EXTI_FTSR1_FT8_Msk                      /*!< Falling trigger configuration for input line 8 */
4104 #define EXTI_FTSR1_FT9_Pos                  (9U)
4105 #define EXTI_FTSR1_FT9_Msk                  (0x1UL << EXTI_FTSR1_FT9_Pos)           /*!< 0x00000200 */
4106 #define EXTI_FTSR1_FT9                      EXTI_FTSR1_FT9_Msk                      /*!< Falling trigger configuration for input line 9 */
4107 #define EXTI_FTSR1_FT10_Pos                 (10U)
4108 #define EXTI_FTSR1_FT10_Msk                 (0x1UL << EXTI_FTSR1_FT10_Pos)          /*!< 0x00000400 */
4109 #define EXTI_FTSR1_FT10                     EXTI_FTSR1_FT10_Msk                     /*!< Falling trigger configuration for input line 10 */
4110 #define EXTI_FTSR1_FT11_Pos                 (11U)
4111 #define EXTI_FTSR1_FT11_Msk                 (0x1UL << EXTI_FTSR1_FT11_Pos)          /*!< 0x00000800 */
4112 #define EXTI_FTSR1_FT11                     EXTI_FTSR1_FT11_Msk                     /*!< Falling trigger configuration for input line 11 */
4113 #define EXTI_FTSR1_FT12_Pos                 (12U)
4114 #define EXTI_FTSR1_FT12_Msk                 (0x1UL << EXTI_FTSR1_FT12_Pos)          /*!< 0x00001000 */
4115 #define EXTI_FTSR1_FT12                     EXTI_FTSR1_FT12_Msk                     /*!< Falling trigger configuration for input line 12 */
4116 #define EXTI_FTSR1_FT13_Pos                 (13U)
4117 #define EXTI_FTSR1_FT13_Msk                 (0x1UL << EXTI_FTSR1_FT13_Pos)          /*!< 0x00002000 */
4118 #define EXTI_FTSR1_FT13                     EXTI_FTSR1_FT13_Msk                     /*!< Falling trigger configuration for input line 13 */
4119 #define EXTI_FTSR1_FT14_Pos                 (14U)
4120 #define EXTI_FTSR1_FT14_Msk                 (0x1UL << EXTI_FTSR1_FT14_Pos)          /*!< 0x00004000 */
4121 #define EXTI_FTSR1_FT14                     EXTI_FTSR1_FT14_Msk                     /*!< Falling trigger configuration for input line 14 */
4122 #define EXTI_FTSR1_FT15_Pos                 (15U)
4123 #define EXTI_FTSR1_FT15_Msk                 (0x1UL << EXTI_FTSR1_FT15_Pos)          /*!< 0x00008000 */
4124 #define EXTI_FTSR1_FT15                     EXTI_FTSR1_FT15_Msk                     /*!< Falling trigger configuration for input line 15 */
4125 #define EXTI_FTSR1_FT16_Pos                 (16U)
4126 #define EXTI_FTSR1_FT16_Msk                 (0x1UL << EXTI_FTSR1_FT16_Pos)          /*!< 0x00010000 */
4127 #define EXTI_FTSR1_FT16                     EXTI_FTSR1_FT16_Msk                     /*!< Falling trigger configuration for input line 16 */
4128 
4129 /******************  Bit definition for EXTI_SWIER1 register  *****************/
4130 #define EXTI_SWIER1_SWI0_Pos                (0U)
4131 #define EXTI_SWIER1_SWI0_Msk                (0x1UL << EXTI_SWIER1_SWI0_Pos)         /*!< 0x00000001 */
4132 #define EXTI_SWIER1_SWI0                    EXTI_SWIER1_SWI0_Msk                    /*!< Software Interrupt on line 0 */
4133 #define EXTI_SWIER1_SWI1_Pos                (1U)
4134 #define EXTI_SWIER1_SWI1_Msk                (0x1UL << EXTI_SWIER1_SWI1_Pos)         /*!< 0x00000002 */
4135 #define EXTI_SWIER1_SWI1                    EXTI_SWIER1_SWI1_Msk                    /*!< Software Interrupt on line 1 */
4136 #define EXTI_SWIER1_SWI2_Pos                (2U)
4137 #define EXTI_SWIER1_SWI2_Msk                (0x1UL << EXTI_SWIER1_SWI2_Pos)         /*!< 0x00000004 */
4138 #define EXTI_SWIER1_SWI2                    EXTI_SWIER1_SWI2_Msk                    /*!< Software Interrupt on line 2 */
4139 #define EXTI_SWIER1_SWI3_Pos                (3U)
4140 #define EXTI_SWIER1_SWI3_Msk                (0x1UL << EXTI_SWIER1_SWI3_Pos)         /*!< 0x00000008 */
4141 #define EXTI_SWIER1_SWI3                    EXTI_SWIER1_SWI3_Msk                    /*!< Software Interrupt on line 3 */
4142 #define EXTI_SWIER1_SWI4_Pos                (4U)
4143 #define EXTI_SWIER1_SWI4_Msk                (0x1UL << EXTI_SWIER1_SWI4_Pos)         /*!< 0x00000010 */
4144 #define EXTI_SWIER1_SWI4                    EXTI_SWIER1_SWI4_Msk                    /*!< Software Interrupt on line 4 */
4145 #define EXTI_SWIER1_SWI5_Pos                (5U)
4146 #define EXTI_SWIER1_SWI5_Msk                (0x1UL << EXTI_SWIER1_SWI5_Pos)         /*!< 0x00000020 */
4147 #define EXTI_SWIER1_SWI5                    EXTI_SWIER1_SWI5_Msk                    /*!< Software Interrupt on line 5 */
4148 #define EXTI_SWIER1_SWI6_Pos                (6U)
4149 #define EXTI_SWIER1_SWI6_Msk                (0x1UL << EXTI_SWIER1_SWI6_Pos)         /*!< 0x00000040 */
4150 #define EXTI_SWIER1_SWI6                    EXTI_SWIER1_SWI6_Msk                    /*!< Software Interrupt on line 6 */
4151 #define EXTI_SWIER1_SWI7_Pos                (7U)
4152 #define EXTI_SWIER1_SWI7_Msk                (0x1UL << EXTI_SWIER1_SWI7_Pos)         /*!< 0x00000080 */
4153 #define EXTI_SWIER1_SWI7                    EXTI_SWIER1_SWI7_Msk                    /*!< Software Interrupt on line 7 */
4154 #define EXTI_SWIER1_SWI8_Pos                (8U)
4155 #define EXTI_SWIER1_SWI8_Msk                (0x1UL << EXTI_SWIER1_SWI8_Pos)         /*!< 0x00000100 */
4156 #define EXTI_SWIER1_SWI8                    EXTI_SWIER1_SWI8_Msk                    /*!< Software Interrupt on line 8 */
4157 #define EXTI_SWIER1_SWI9_Pos                (9U)
4158 #define EXTI_SWIER1_SWI9_Msk                (0x1UL << EXTI_SWIER1_SWI9_Pos)         /*!< 0x00000200 */
4159 #define EXTI_SWIER1_SWI9                    EXTI_SWIER1_SWI9_Msk                    /*!< Software Interrupt on line 9 */
4160 #define EXTI_SWIER1_SWI10_Pos               (10U)
4161 #define EXTI_SWIER1_SWI10_Msk               (0x1UL << EXTI_SWIER1_SWI10_Pos)        /*!< 0x00000400 */
4162 #define EXTI_SWIER1_SWI10                   EXTI_SWIER1_SWI10_Msk                   /*!< Software Interrupt on line 10 */
4163 #define EXTI_SWIER1_SWI11_Pos               (11U)
4164 #define EXTI_SWIER1_SWI11_Msk               (0x1UL << EXTI_SWIER1_SWI11_Pos)        /*!< 0x00000800 */
4165 #define EXTI_SWIER1_SWI11                   EXTI_SWIER1_SWI11_Msk                   /*!< Software Interrupt on line 11 */
4166 #define EXTI_SWIER1_SWI12_Pos               (12U)
4167 #define EXTI_SWIER1_SWI12_Msk               (0x1UL << EXTI_SWIER1_SWI12_Pos)        /*!< 0x00001000 */
4168 #define EXTI_SWIER1_SWI12                   EXTI_SWIER1_SWI12_Msk                   /*!< Software Interrupt on line 12 */
4169 #define EXTI_SWIER1_SWI13_Pos               (13U)
4170 #define EXTI_SWIER1_SWI13_Msk               (0x1UL << EXTI_SWIER1_SWI13_Pos)        /*!< 0x00002000 */
4171 #define EXTI_SWIER1_SWI13                   EXTI_SWIER1_SWI13_Msk                   /*!< Software Interrupt on line 13 */
4172 #define EXTI_SWIER1_SWI14_Pos               (14U)
4173 #define EXTI_SWIER1_SWI14_Msk               (0x1UL << EXTI_SWIER1_SWI14_Pos)        /*!< 0x00004000 */
4174 #define EXTI_SWIER1_SWI14                   EXTI_SWIER1_SWI14_Msk                   /*!< Software Interrupt on line 14 */
4175 #define EXTI_SWIER1_SWI15_Pos               (15U)
4176 #define EXTI_SWIER1_SWI15_Msk               (0x1UL << EXTI_SWIER1_SWI15_Pos)        /*!< 0x00008000 */
4177 #define EXTI_SWIER1_SWI15                   EXTI_SWIER1_SWI15_Msk                   /*!< Software Interrupt on line 15 */
4178 #define EXTI_SWIER1_SWI16_Pos               (16U)
4179 #define EXTI_SWIER1_SWI16_Msk               (0x1UL << EXTI_SWIER1_SWI16_Pos)        /*!< 0x00010000 */
4180 #define EXTI_SWIER1_SWI16                   EXTI_SWIER1_SWI16_Msk                   /*!< Software Interrupt on line 16 */
4181 
4182 
4183 /*******************  Bit definition for EXTI_RPR1 register  ******************/
4184 #define EXTI_RPR1_RPIF0_Pos                 (0U)
4185 #define EXTI_RPR1_RPIF0_Msk                 (0x1UL << EXTI_RPR1_RPIF0_Pos)          /*!< 0x00000001 */
4186 #define EXTI_RPR1_RPIF0                     EXTI_RPR1_RPIF0_Msk                     /*!< Rising Pending Interrupt Flag on line 0 */
4187 #define EXTI_RPR1_RPIF1_Pos                 (1U)
4188 #define EXTI_RPR1_RPIF1_Msk                 (0x1UL << EXTI_RPR1_RPIF1_Pos)          /*!< 0x00000002 */
4189 #define EXTI_RPR1_RPIF1                     EXTI_RPR1_RPIF1_Msk                     /*!< Rising Pending Interrupt Flag on line 1 */
4190 #define EXTI_RPR1_RPIF2_Pos                 (2U)
4191 #define EXTI_RPR1_RPIF2_Msk                 (0x1UL << EXTI_RPR1_RPIF2_Pos)          /*!< 0x00000004 */
4192 #define EXTI_RPR1_RPIF2                     EXTI_RPR1_RPIF2_Msk                     /*!< Rising Pending Interrupt Flag on line 2 */
4193 #define EXTI_RPR1_RPIF3_Pos                 (3U)
4194 #define EXTI_RPR1_RPIF3_Msk                 (0x1UL << EXTI_RPR1_RPIF3_Pos)          /*!< 0x00000008 */
4195 #define EXTI_RPR1_RPIF3                     EXTI_RPR1_RPIF3_Msk                     /*!< Rising Pending Interrupt Flag on line 3 */
4196 #define EXTI_RPR1_RPIF4_Pos                 (4U)
4197 #define EXTI_RPR1_RPIF4_Msk                 (0x1UL << EXTI_RPR1_RPIF4_Pos)          /*!< 0x00000010 */
4198 #define EXTI_RPR1_RPIF4                     EXTI_RPR1_RPIF4_Msk                     /*!< Rising Pending Interrupt Flag on line 4 */
4199 #define EXTI_RPR1_RPIF5_Pos                 (5U)
4200 #define EXTI_RPR1_RPIF5_Msk                 (0x1UL << EXTI_RPR1_RPIF5_Pos)          /*!< 0x00000020 */
4201 #define EXTI_RPR1_RPIF5                     EXTI_RPR1_RPIF5_Msk                     /*!< Rising Pending Interrupt Flag on line 5 */
4202 #define EXTI_RPR1_RPIF6_Pos                 (6U)
4203 #define EXTI_RPR1_RPIF6_Msk                 (0x1UL << EXTI_RPR1_RPIF6_Pos)          /*!< 0x00000040 */
4204 #define EXTI_RPR1_RPIF6                     EXTI_RPR1_RPIF6_Msk                     /*!< Rising Pending Interrupt Flag on line 6 */
4205 #define EXTI_RPR1_RPIF7_Pos                 (7U)
4206 #define EXTI_RPR1_RPIF7_Msk                 (0x1UL << EXTI_RPR1_RPIF7_Pos)          /*!< 0x00000080 */
4207 #define EXTI_RPR1_RPIF7                     EXTI_RPR1_RPIF7_Msk                     /*!< Rising Pending Interrupt Flag on line 7 */
4208 #define EXTI_RPR1_RPIF8_Pos                 (8U)
4209 #define EXTI_RPR1_RPIF8_Msk                 (0x1UL << EXTI_RPR1_RPIF8_Pos)          /*!< 0x00000100 */
4210 #define EXTI_RPR1_RPIF8                     EXTI_RPR1_RPIF8_Msk                     /*!< Rising Pending Interrupt Flag on line 8 */
4211 #define EXTI_RPR1_RPIF9_Pos                 (9U)
4212 #define EXTI_RPR1_RPIF9_Msk                 (0x1UL << EXTI_RPR1_RPIF9_Pos)          /*!< 0x00000200 */
4213 #define EXTI_RPR1_RPIF9                     EXTI_RPR1_RPIF9_Msk                     /*!< Rising Pending Interrupt Flag on line 9 */
4214 #define EXTI_RPR1_RPIF10_Pos                (10U)
4215 #define EXTI_RPR1_RPIF10_Msk                (0x1UL << EXTI_RPR1_RPIF10_Pos)         /*!< 0x00000400 */
4216 #define EXTI_RPR1_RPIF10                    EXTI_RPR1_RPIF10_Msk                    /*!< Rising Pending Interrupt Flag on line 10 */
4217 #define EXTI_RPR1_RPIF11_Pos                (11U)
4218 #define EXTI_RPR1_RPIF11_Msk                (0x1UL << EXTI_RPR1_RPIF11_Pos)         /*!< 0x00000800 */
4219 #define EXTI_RPR1_RPIF11                    EXTI_RPR1_RPIF11_Msk                    /*!< Rising Pending Interrupt Flag on line 11 */
4220 #define EXTI_RPR1_RPIF12_Pos                (12U)
4221 #define EXTI_RPR1_RPIF12_Msk                (0x1UL << EXTI_RPR1_RPIF12_Pos)         /*!< 0x00001000 */
4222 #define EXTI_RPR1_RPIF12                    EXTI_RPR1_RPIF12_Msk                    /*!< Rising Pending Interrupt Flag on line 12 */
4223 #define EXTI_RPR1_RPIF13_Pos                (13U)
4224 #define EXTI_RPR1_RPIF13_Msk                (0x1UL << EXTI_RPR1_RPIF13_Pos)         /*!< 0x00002000 */
4225 #define EXTI_RPR1_RPIF13                    EXTI_RPR1_RPIF13_Msk                    /*!< Rising Pending Interrupt Flag on line 13 */
4226 #define EXTI_RPR1_RPIF14_Pos                (14U)
4227 #define EXTI_RPR1_RPIF14_Msk                (0x1UL << EXTI_RPR1_RPIF14_Pos)         /*!< 0x00004000 */
4228 #define EXTI_RPR1_RPIF14                    EXTI_RPR1_RPIF14_Msk                    /*!< Rising Pending Interrupt Flag on line 14 */
4229 #define EXTI_RPR1_RPIF15_Pos                (15U)
4230 #define EXTI_RPR1_RPIF15_Msk                (0x1UL << EXTI_RPR1_RPIF15_Pos)         /*!< 0x00008000 */
4231 #define EXTI_RPR1_RPIF15                    EXTI_RPR1_RPIF15_Msk                    /*!< Rising Pending Interrupt Flag on line 15 */
4232 #define EXTI_RPR1_RPIF16_Pos                (16U)
4233 #define EXTI_RPR1_RPIF16_Msk                (0x1UL << EXTI_RPR1_RPIF16_Pos)         /*!< 0x00010000 */
4234 #define EXTI_RPR1_RPIF16                    EXTI_RPR1_RPIF16_Msk                    /*!< Rising Pending Interrupt Flag on line 16 */
4235 
4236 /*******************  Bit definition for EXTI_FPR1 register  ******************/
4237 #define EXTI_FPR1_FPIF0_Pos                 (0U)
4238 #define EXTI_FPR1_FPIF0_Msk                 (0x1UL << EXTI_FPR1_FPIF0_Pos)          /*!< 0x00000001 */
4239 #define EXTI_FPR1_FPIF0                     EXTI_FPR1_FPIF0_Msk                     /*!< Falling Pending Interrupt Flag on line 0 */
4240 #define EXTI_FPR1_FPIF1_Pos                 (1U)
4241 #define EXTI_FPR1_FPIF1_Msk                 (0x1UL << EXTI_FPR1_FPIF1_Pos)          /*!< 0x00000002 */
4242 #define EXTI_FPR1_FPIF1                     EXTI_FPR1_FPIF1_Msk                     /*!< Falling Pending Interrupt Flag on line 1 */
4243 #define EXTI_FPR1_FPIF2_Pos                 (2U)
4244 #define EXTI_FPR1_FPIF2_Msk                 (0x1UL << EXTI_FPR1_FPIF2_Pos)          /*!< 0x00000004 */
4245 #define EXTI_FPR1_FPIF2                     EXTI_FPR1_FPIF2_Msk                     /*!< Falling Pending Interrupt Flag on line 2 */
4246 #define EXTI_FPR1_FPIF3_Pos                 (3U)
4247 #define EXTI_FPR1_FPIF3_Msk                 (0x1UL << EXTI_FPR1_FPIF3_Pos)          /*!< 0x00000008 */
4248 #define EXTI_FPR1_FPIF3                     EXTI_FPR1_FPIF3_Msk                     /*!< Falling Pending Interrupt Flag on line 3 */
4249 #define EXTI_FPR1_FPIF4_Pos                 (4U)
4250 #define EXTI_FPR1_FPIF4_Msk                 (0x1UL << EXTI_FPR1_FPIF4_Pos)          /*!< 0x00000010 */
4251 #define EXTI_FPR1_FPIF4                     EXTI_FPR1_FPIF4_Msk                     /*!< Falling Pending Interrupt Flag on line 4 */
4252 #define EXTI_FPR1_FPIF5_Pos                 (5U)
4253 #define EXTI_FPR1_FPIF5_Msk                 (0x1UL << EXTI_FPR1_FPIF5_Pos)          /*!< 0x00000020 */
4254 #define EXTI_FPR1_FPIF5                     EXTI_FPR1_FPIF5_Msk                     /*!< Falling Pending Interrupt Flag on line 5 */
4255 #define EXTI_FPR1_FPIF6_Pos                 (6U)
4256 #define EXTI_FPR1_FPIF6_Msk                 (0x1UL << EXTI_FPR1_FPIF6_Pos)          /*!< 0x00000040 */
4257 #define EXTI_FPR1_FPIF6                     EXTI_FPR1_FPIF6_Msk                     /*!< Falling Pending Interrupt Flag on line 6 */
4258 #define EXTI_FPR1_FPIF7_Pos                 (7U)
4259 #define EXTI_FPR1_FPIF7_Msk                 (0x1UL << EXTI_FPR1_FPIF7_Pos)          /*!< 0x00000080 */
4260 #define EXTI_FPR1_FPIF7                     EXTI_FPR1_FPIF7_Msk                     /*!< Falling Pending Interrupt Flag on line 7 */
4261 #define EXTI_FPR1_FPIF8_Pos                 (8U)
4262 #define EXTI_FPR1_FPIF8_Msk                 (0x1UL << EXTI_FPR1_FPIF8_Pos)          /*!< 0x00000100 */
4263 #define EXTI_FPR1_FPIF8                     EXTI_FPR1_FPIF8_Msk                     /*!< Falling Pending Interrupt Flag on line 8 */
4264 #define EXTI_FPR1_FPIF9_Pos                 (9U)
4265 #define EXTI_FPR1_FPIF9_Msk                 (0x1UL << EXTI_FPR1_FPIF9_Pos)          /*!< 0x00000200 */
4266 #define EXTI_FPR1_FPIF9                     EXTI_FPR1_FPIF9_Msk                     /*!< Falling Pending Interrupt Flag on line 9 */
4267 #define EXTI_FPR1_FPIF10_Pos                (10U)
4268 #define EXTI_FPR1_FPIF10_Msk                (0x1UL << EXTI_FPR1_FPIF10_Pos)         /*!< 0x00000400 */
4269 #define EXTI_FPR1_FPIF10                    EXTI_FPR1_FPIF10_Msk                    /*!< Falling Pending Interrupt Flag on line 10 */
4270 #define EXTI_FPR1_FPIF11_Pos                (11U)
4271 #define EXTI_FPR1_FPIF11_Msk                (0x1UL << EXTI_FPR1_FPIF11_Pos)         /*!< 0x00000800 */
4272 #define EXTI_FPR1_FPIF11                    EXTI_FPR1_FPIF11_Msk                    /*!< Falling Pending Interrupt Flag on line 11 */
4273 #define EXTI_FPR1_FPIF12_Pos                (12U)
4274 #define EXTI_FPR1_FPIF12_Msk                (0x1UL << EXTI_FPR1_FPIF12_Pos)         /*!< 0x00001000 */
4275 #define EXTI_FPR1_FPIF12                    EXTI_FPR1_FPIF12_Msk                    /*!< Falling Pending Interrupt Flag on line 12 */
4276 #define EXTI_FPR1_FPIF13_Pos                (13U)
4277 #define EXTI_FPR1_FPIF13_Msk                (0x1UL << EXTI_FPR1_FPIF13_Pos)         /*!< 0x00002000 */
4278 #define EXTI_FPR1_FPIF13                    EXTI_FPR1_FPIF13_Msk                    /*!< Falling Pending Interrupt Flag on line 13 */
4279 #define EXTI_FPR1_FPIF14_Pos                (14U)
4280 #define EXTI_FPR1_FPIF14_Msk                (0x1UL << EXTI_FPR1_FPIF14_Pos)         /*!< 0x00004000 */
4281 #define EXTI_FPR1_FPIF14                    EXTI_FPR1_FPIF14_Msk                    /*!< Falling Pending Interrupt Flag on line 14 */
4282 #define EXTI_FPR1_FPIF15_Pos                (15U)
4283 #define EXTI_FPR1_FPIF15_Msk                (0x1UL << EXTI_FPR1_FPIF15_Pos)         /*!< 0x00008000 */
4284 #define EXTI_FPR1_FPIF15                    EXTI_FPR1_FPIF15_Msk                    /*!< Falling Pending Interrupt Flag on line 15 */
4285 #define EXTI_FPR1_FPIF16_Pos                (16U)
4286 #define EXTI_FPR1_FPIF16_Msk                (0x1UL << EXTI_FPR1_FPIF16_Pos)         /*!< 0x00010000 */
4287 #define EXTI_FPR1_FPIF16                    EXTI_FPR1_FPIF16_Msk                    /*!< Falling Pending Interrupt Flag on line 16 */
4288 
4289 /*******************  Bit definition for EXTI_SECENR1 register  ******************/
4290 #define EXTI_SECENR1_SEC0_Pos              (0U)
4291 #define EXTI_SECENR1_SEC0_Msk              (0x1UL << EXTI_SECENR1_SEC0_Pos)       /*!< 0x00000001 */
4292 #define EXTI_SECENR1_SEC0                  EXTI_SECENR1_SEC0_Msk                  /*!< Security enable on line 0 */
4293 #define EXTI_SECENR1_SEC1_Pos              (1U)
4294 #define EXTI_SECENR1_SEC1_Msk              (0x1UL << EXTI_SECENR1_SEC1_Pos)       /*!< 0x00000002 */
4295 #define EXTI_SECENR1_SEC1                  EXTI_SECENR1_SEC1_Msk                  /*!< Security enable on line 1 */
4296 #define EXTI_SECENR1_SEC2_Pos              (2U)
4297 #define EXTI_SECENR1_SEC2_Msk              (0x1UL << EXTI_SECENR1_SEC2_Pos)       /*!< 0x00000004 */
4298 #define EXTI_SECENR1_SEC2                  EXTI_SECENR1_SEC2_Msk                  /*!< Security enable on line 2 */
4299 #define EXTI_SECENR1_SEC3_Pos              (3U)
4300 #define EXTI_SECENR1_SEC3_Msk              (0x1UL << EXTI_SECENR1_SEC3_Pos)       /*!< 0x00000008 */
4301 #define EXTI_SECENR1_SEC3                  EXTI_SECENR1_SEC3_Msk                  /*!< Security enable on line 3 */
4302 #define EXTI_SECENR1_SEC4_Pos              (4U)
4303 #define EXTI_SECENR1_SEC4_Msk              (0x1UL << EXTI_SECENR1_SEC4_Pos)       /*!< 0x00000010 */
4304 #define EXTI_SECENR1_SEC4                  EXTI_SECENR1_SEC4_Msk                  /*!< Security enable on line 4 */
4305 #define EXTI_SECENR1_SEC5_Pos              (5U)
4306 #define EXTI_SECENR1_SEC5_Msk              (0x1UL << EXTI_SECENR1_SEC5_Pos)       /*!< 0x00000020 */
4307 #define EXTI_SECENR1_SEC5                  EXTI_SECENR1_SEC5_Msk                  /*!< Security enable on line 5 */
4308 #define EXTI_SECENR1_SEC6_Pos              (6U)
4309 #define EXTI_SECENR1_SEC6_Msk              (0x1UL << EXTI_SECENR1_SEC6_Pos)       /*!< 0x00000040 */
4310 #define EXTI_SECENR1_SEC6                  EXTI_SECENR1_SEC6_Msk                  /*!< Security enable on line 6 */
4311 #define EXTI_SECENR1_SEC7_Pos              (7U)
4312 #define EXTI_SECENR1_SEC7_Msk              (0x1UL << EXTI_SECENR1_SEC7_Pos)       /*!< 0x00000080 */
4313 #define EXTI_SECENR1_SEC7                  EXTI_SECENR1_SEC7_Msk                  /*!< Security enable on line 7 */
4314 #define EXTI_SECENR1_SEC8_Pos              (8U)
4315 #define EXTI_SECENR1_SEC8_Msk              (0x1UL << EXTI_SECENR1_SEC8_Pos)       /*!< 0x00000100 */
4316 #define EXTI_SECENR1_SEC8                  EXTI_SECENR1_SEC8_Msk                  /*!< Security enable on line 8 */
4317 #define EXTI_SECENR1_SEC9_Pos              (9U)
4318 #define EXTI_SECENR1_SEC9_Msk              (0x1UL << EXTI_SECENR1_SEC9_Pos)       /*!< 0x00000200 */
4319 #define EXTI_SECENR1_SEC9                  EXTI_SECENR1_SEC9_Msk                  /*!< Security enable on line 9 */
4320 #define EXTI_SECENR1_SEC10_Pos             (10U)
4321 #define EXTI_SECENR1_SEC10_Msk             (0x1UL << EXTI_SECENR1_SEC10_Pos)      /*!< 0x00000400 */
4322 #define EXTI_SECENR1_SEC10                 EXTI_SECENR1_SEC10_Msk                 /*!< Security enable on line 10 */
4323 #define EXTI_SECENR1_SEC11_Pos             (11U)
4324 #define EXTI_SECENR1_SEC11_Msk             (0x1UL << EXTI_SECENR1_SEC11_Pos)      /*!< 0x00000800 */
4325 #define EXTI_SECENR1_SEC11                 EXTI_SECENR1_SEC11_Msk                 /*!< Security enable on line 11 */
4326 #define EXTI_SECENR1_SEC12_Pos             (12U)
4327 #define EXTI_SECENR1_SEC12_Msk             (0x1UL << EXTI_SECENR1_SEC12_Pos)      /*!< 0x00001000 */
4328 #define EXTI_SECENR1_SEC12                 EXTI_SECENR1_SEC12_Msk                 /*!< Security enable on line 12 */
4329 #define EXTI_SECENR1_SEC13_Pos             (13U)
4330 #define EXTI_SECENR1_SEC13_Msk             (0x1UL << EXTI_SECENR1_SEC13_Pos)      /*!< 0x00002000 */
4331 #define EXTI_SECENR1_SEC13                 EXTI_SECENR1_SEC13_Msk                 /*!< Security enable on line 13 */
4332 #define EXTI_SECENR1_SEC14_Pos             (14U)
4333 #define EXTI_SECENR1_SEC14_Msk             (0x1UL << EXTI_SECENR1_SEC14_Pos)      /*!< 0x00004000 */
4334 #define EXTI_SECENR1_SEC14                 EXTI_SECENR1_SEC14_Msk                 /*!< Security enable on line 14 */
4335 #define EXTI_SECENR1_SEC15_Pos             (15U)
4336 #define EXTI_SECENR1_SEC15_Msk             (0x1UL << EXTI_SECENR1_SEC15_Pos)      /*!< 0x00008000 */
4337 #define EXTI_SECENR1_SEC15                 EXTI_SECENR1_SEC15_Msk                 /*!< Security enable on line 15 */
4338 #define EXTI_SECENR1_SEC16_Pos             (16U)
4339 #define EXTI_SECENR1_SEC16_Msk             (0x1UL << EXTI_SECENR1_SEC16_Pos)      /*!< 0x00010000 */
4340 #define EXTI_SECENR1_SEC16                 EXTI_SECENR1_SEC16_Msk                 /*!< Security enable on line 16 */
4341 #define EXTI_SECENR1_SEC17_Pos             (17U)
4342 #define EXTI_SECENR1_SEC17_Msk             (0x1UL << EXTI_SECENR1_SEC17_Pos)      /*!< 0x00020000 */
4343 #define EXTI_SECENR1_SEC17                 EXTI_SECENR1_SEC17_Msk                 /*!< Security enable on line 17 */
4344 #define EXTI_SECENR1_SEC18_Pos             (18U)
4345 #define EXTI_SECENR1_SEC18_Msk             (0x1UL << EXTI_SECENR1_SEC18_Pos)      /*!< 0x00040000 */
4346 #define EXTI_SECENR1_SEC18                 EXTI_SECENR1_SEC18_Msk                 /*!< Security enable on line 18 */
4347 #define EXTI_SECENR1_SEC19_Pos             (19U)
4348 #define EXTI_SECENR1_SEC19_Msk             (0x1UL << EXTI_SECENR1_SEC19_Pos)      /*!< 0x00080000 */
4349 #define EXTI_SECENR1_SEC19                 EXTI_SECENR1_SEC19_Msk                 /*!< Security enable on line 19 */
4350 #define EXTI_SECENR1_SEC20_Pos             (20U)
4351 #define EXTI_SECENR1_SEC20_Msk             (0x1UL << EXTI_SECENR1_SEC20_Pos)      /*!< 0x00100000 */
4352 #define EXTI_SECENR1_SEC20                 EXTI_SECENR1_SEC20_Msk                 /*!< Security enable on line 20 */
4353 #define EXTI_SECENR1_SEC21_Pos             (21U)
4354 #define EXTI_SECENR1_SEC21_Msk             (0x1UL << EXTI_SECENR1_SEC21_Pos)      /*!< 0x00200000 */
4355 #define EXTI_SECENR1_SEC21                 EXTI_SECENR1_SEC21_Msk                 /*!< Security enable on line 21 */
4356 #define EXTI_SECENR1_SEC22_Pos             (22U)
4357 #define EXTI_SECENR1_SEC22_Msk             (0x1UL << EXTI_SECENR1_SEC22_Pos)      /*!< 0x00400000 */
4358 #define EXTI_SECENR1_SEC22                 EXTI_SECENR1_SEC22_Msk                 /*!< Security enable on line 22 */
4359 #define EXTI_SECENR1_SEC23_Pos             (23U)
4360 #define EXTI_SECENR1_SEC23_Msk             (0x1UL << EXTI_SECENR1_SEC23_Pos)      /*!< 0x00800000 */
4361 #define EXTI_SECENR1_SEC23                 EXTI_SECENR1_SEC23_Msk                 /*!< Security enable on line 23 */
4362 #define EXTI_SECENR1_SEC24_Pos             (24U)
4363 #define EXTI_SECENR1_SEC24_Msk             (0x1UL << EXTI_SECENR1_SEC24_Pos)      /*!< 0x01000000 */
4364 #define EXTI_SECENR1_SEC24                 EXTI_SECENR1_SEC24_Msk                 /*!< Security enable on line 24 */
4365 #define EXTI_SECENR1_SEC25_Pos             (25U)
4366 #define EXTI_SECENR1_SEC25_Msk             (0x1UL << EXTI_SECENR1_SEC25_Pos)      /*!< 0x02000000 */
4367 #define EXTI_SECENR1_SEC25                 EXTI_SECENR1_SEC25_Msk                 /*!< Security enable on line 25 */
4368 #define EXTI_SECENR1_SEC26_Pos             (26U)
4369 #define EXTI_SECENR1_SEC26_Msk             (0x1UL << EXTI_SECENR1_SEC26_Pos)      /*!< 0x04000000 */
4370 #define EXTI_SECENR1_SEC26                 EXTI_SECENR1_SEC26_Msk                 /*!< Security enable on line 26 */
4371 #define EXTI_SECENR1_SEC27_Pos             (27U)
4372 #define EXTI_SECENR1_SEC27_Msk             (0x1UL << EXTI_SECENR1_SEC27_Pos)      /*!< 0x08000000 */
4373 #define EXTI_SECENR1_SEC27                 EXTI_SECENR1_SEC27_Msk                 /*!< Security enable on line 27 */
4374 #define EXTI_SECENR1_SEC28_Pos             (28U)
4375 #define EXTI_SECENR1_SEC28_Msk             (0x1UL << EXTI_SECENR1_SEC28_Pos)      /*!< 0x10000000 */
4376 #define EXTI_SECENR1_SEC28                 EXTI_SECENR1_SEC28_Msk                 /*!< Security enable on line 28 */
4377 #define EXTI_SECENR1_SEC29_Pos             (29U)
4378 #define EXTI_SECENR1_SEC29_Msk             (0x1UL << EXTI_SECENR1_SEC29_Pos)      /*!< 0x20000000 */
4379 #define EXTI_SECENR1_SEC29                 EXTI_SECENR1_SEC29_Msk                 /*!< Security enable on line 29 */
4380 #define EXTI_SECENR1_SEC30_Pos             (30U)
4381 #define EXTI_SECENR1_SEC30_Msk             (0x1UL << EXTI_SECENR1_SEC30_Pos)      /*!< 0x40000000 */
4382 #define EXTI_SECENR1_SEC30                 EXTI_SECENR1_SEC30_Msk                 /*!< Security enable on line 30 */
4383 #define EXTI_SECENR1_SEC31_Pos             (31U)
4384 #define EXTI_SECENR1_SEC31_Msk             (0x1UL << EXTI_SECENR1_SEC31_Pos)      /*!< 0x80000000 */
4385 #define EXTI_SECENR1_SEC31                 EXTI_SECENR1_SEC31_Msk                 /*!< Security enable on line 31 */
4386 
4387 
4388 /*******************  Bit definition for EXTI_PRIVENR1 register  ******************/
4389 #define EXTI_PRIVENR1_PRIV0_Pos             (0U)
4390 #define EXTI_PRIVENR1_PRIV0_Msk             (0x1UL << EXTI_PRIVENR1_PRIV0_Pos)      /*!< 0x00000001 */
4391 #define EXTI_PRIVENR1_PRIV0                 EXTI_PRIVENR1_PRIV0_Msk                 /*!< Privilege enable on line 0 */
4392 #define EXTI_PRIVENR1_PRIV1_Pos             (1U)
4393 #define EXTI_PRIVENR1_PRIV1_Msk             (0x1UL << EXTI_PRIVENR1_PRIV1_Pos)      /*!< 0x00000002 */
4394 #define EXTI_PRIVENR1_PRIV1                 EXTI_PRIVENR1_PRIV1_Msk                 /*!< Privilege enable on line 1 */
4395 #define EXTI_PRIVENR1_PRIV2_Pos             (2U)
4396 #define EXTI_PRIVENR1_PRIV2_Msk             (0x1UL << EXTI_PRIVENR1_PRIV2_Pos)      /*!< 0x00000004 */
4397 #define EXTI_PRIVENR1_PRIV2                 EXTI_PRIVENR1_PRIV2_Msk                 /*!< Privilege enable on line 2 */
4398 #define EXTI_PRIVENR1_PRIV3_Pos             (3U)
4399 #define EXTI_PRIVENR1_PRIV3_Msk             (0x1UL << EXTI_PRIVENR1_PRIV3_Pos)      /*!< 0x00000008 */
4400 #define EXTI_PRIVENR1_PRIV3                 EXTI_PRIVENR1_PRIV3_Msk                 /*!< Privilege enable on line 3 */
4401 #define EXTI_PRIVENR1_PRIV4_Pos             (4U)
4402 #define EXTI_PRIVENR1_PRIV4_Msk             (0x1UL << EXTI_PRIVENR1_PRIV4_Pos)      /*!< 0x00000010 */
4403 #define EXTI_PRIVENR1_PRIV4                 EXTI_PRIVENR1_PRIV4_Msk                 /*!< Privilege enable on line 4 */
4404 #define EXTI_PRIVENR1_PRIV5_Pos             (5U)
4405 #define EXTI_PRIVENR1_PRIV5_Msk             (0x1UL << EXTI_PRIVENR1_PRIV5_Pos)      /*!< 0x00000020 */
4406 #define EXTI_PRIVENR1_PRIV5                 EXTI_PRIVENR1_PRIV5_Msk                 /*!< Privilege enable on line 5 */
4407 #define EXTI_PRIVENR1_PRIV6_Pos             (6U)
4408 #define EXTI_PRIVENR1_PRIV6_Msk             (0x1UL << EXTI_PRIVENR1_PRIV6_Pos)      /*!< 0x00000040 */
4409 #define EXTI_PRIVENR1_PRIV6                 EXTI_PRIVENR1_PRIV6_Msk                 /*!< Privilege enable on line 6 */
4410 #define EXTI_PRIVENR1_PRIV7_Pos             (7U)
4411 #define EXTI_PRIVENR1_PRIV7_Msk             (0x1UL << EXTI_PRIVENR1_PRIV7_Pos)      /*!< 0x00000080 */
4412 #define EXTI_PRIVENR1_PRIV7                 EXTI_PRIVENR1_PRIV7_Msk                 /*!< Privilege enable on line 7 */
4413 #define EXTI_PRIVENR1_PRIV8_Pos             (8U)
4414 #define EXTI_PRIVENR1_PRIV8_Msk             (0x1UL << EXTI_PRIVENR1_PRIV8_Pos)      /*!< 0x00000100 */
4415 #define EXTI_PRIVENR1_PRIV8                 EXTI_PRIVENR1_PRIV8_Msk                 /*!< Privilege enable on line 8 */
4416 #define EXTI_PRIVENR1_PRIV9_Pos             (9U)
4417 #define EXTI_PRIVENR1_PRIV9_Msk             (0x1UL << EXTI_PRIVENR1_PRIV9_Pos)      /*!< 0x00000200 */
4418 #define EXTI_PRIVENR1_PRIV9                 EXTI_PRIVENR1_PRIV9_Msk                 /*!< Privilege enable on line 9 */
4419 #define EXTI_PRIVENR1_PRIV10_Pos            (10U)
4420 #define EXTI_PRIVENR1_PRIV10_Msk            (0x1UL << EXTI_PRIVENR1_PRIV10_Pos)     /*!< 0x00000400 */
4421 #define EXTI_PRIVENR1_PRIV10                EXTI_PRIVENR1_PRIV10_Msk                /*!< Privilege enable on line 10 */
4422 #define EXTI_PRIVENR1_PRIV11_Pos            (11U)
4423 #define EXTI_PRIVENR1_PRIV11_Msk            (0x1UL << EXTI_PRIVENR1_PRIV11_Pos)     /*!< 0x00000800 */
4424 #define EXTI_PRIVENR1_PRIV11                EXTI_PRIVENR1_PRIV11_Msk                /*!< Privilege enable on line 11 */
4425 #define EXTI_PRIVENR1_PRIV12_Pos            (12U)
4426 #define EXTI_PRIVENR1_PRIV12_Msk            (0x1UL << EXTI_PRIVENR1_PRIV12_Pos)     /*!< 0x00001000 */
4427 #define EXTI_PRIVENR1_PRIV12                EXTI_PRIVENR1_PRIV12_Msk                /*!< Privilege enable on line 12 */
4428 #define EXTI_PRIVENR1_PRIV13_Pos            (13U)
4429 #define EXTI_PRIVENR1_PRIV13_Msk            (0x1UL << EXTI_PRIVENR1_PRIV13_Pos)     /*!< 0x00002000 */
4430 #define EXTI_PRIVENR1_PRIV13                EXTI_PRIVENR1_PRIV13_Msk                /*!< Privilege enable on line 13 */
4431 #define EXTI_PRIVENR1_PRIV14_Pos            (14U)
4432 #define EXTI_PRIVENR1_PRIV14_Msk            (0x1UL << EXTI_PRIVENR1_PRIV14_Pos)     /*!< 0x00004000 */
4433 #define EXTI_PRIVENR1_PRIV14                EXTI_PRIVENR1_PRIV14_Msk                /*!< Privilege enable on line 14 */
4434 #define EXTI_PRIVENR1_PRIV15_Pos            (15U)
4435 #define EXTI_PRIVENR1_PRIV15_Msk            (0x1UL << EXTI_PRIVENR1_PRIV15_Pos)     /*!< 0x00008000 */
4436 #define EXTI_PRIVENR1_PRIV15                EXTI_PRIVENR1_PRIV15_Msk                /*!< Privilege enable on line 15 */
4437 #define EXTI_PRIVENR1_PRIV16_Pos            (16U)
4438 #define EXTI_PRIVENR1_PRIV16_Msk            (0x1UL << EXTI_PRIVENR1_PRIV16_Pos)     /*!< 0x00010000 */
4439 #define EXTI_PRIVENR1_PRIV16                EXTI_PRIVENR1_PRIV16_Msk                /*!< Privilege enable on line 16 */
4440 #define EXTI_PRIVENR1_PRIV17_Pos            (17U)
4441 #define EXTI_PRIVENR1_PRIV17_Msk            (0x1UL << EXTI_PRIVENR1_PRIV17_Pos)     /*!< 0x00020000 */
4442 #define EXTI_PRIVENR1_PRIV17                EXTI_PRIVENR1_PRIV17_Msk                /*!< Privilege enable on line 17 */
4443 #define EXTI_PRIVENR1_PRIV18_Pos            (18U)
4444 #define EXTI_PRIVENR1_PRIV18_Msk            (0x1UL << EXTI_PRIVENR1_PRIV18_Pos)     /*!< 0x00040000 */
4445 #define EXTI_PRIVENR1_PRIV18                EXTI_PRIVENR1_PRIV18_Msk                /*!< Privilege enable on line 18 */
4446 #define EXTI_PRIVENR1_PRIV19_Pos            (19U)
4447 #define EXTI_PRIVENR1_PRIV19_Msk            (0x1UL << EXTI_PRIVENR1_PRIV19_Pos)     /*!< 0x00080000 */
4448 #define EXTI_PRIVENR1_PRIV19                EXTI_PRIVENR1_PRIV19_Msk                /*!< Privilege enable on line 19 */
4449 #define EXTI_PRIVENR1_PRIV20_Pos            (20U)
4450 #define EXTI_PRIVENR1_PRIV20_Msk            (0x1UL << EXTI_PRIVENR1_PRIV20_Pos)     /*!< 0x00100000 */
4451 #define EXTI_PRIVENR1_PRIV20                EXTI_PRIVENR1_PRIV20_Msk                /*!< Privilege enable on line 20 */
4452 #define EXTI_PRIVENR1_PRIV21_Pos            (21U)
4453 #define EXTI_PRIVENR1_PRIV21_Msk            (0x1UL << EXTI_PRIVENR1_PRIV21_Pos)     /*!< 0x00200000 */
4454 #define EXTI_PRIVENR1_PRIV21                EXTI_PRIVENR1_PRIV21_Msk                /*!< Privilege enable on line 21 */
4455 #define EXTI_PRIVENR1_PRIV22_Pos            (22U)
4456 #define EXTI_PRIVENR1_PRIV22_Msk            (0x1UL << EXTI_PRIVENR1_PRIV22_Pos)     /*!< 0x00400000 */
4457 #define EXTI_PRIVENR1_PRIV22                EXTI_PRIVENR1_PRIV22_Msk                /*!< Privilege enable on line 22 */
4458 #define EXTI_PRIVENR1_PRIV23_Pos            (23U)
4459 #define EXTI_PRIVENR1_PRIV23_Msk            (0x1UL << EXTI_PRIVENR1_PRIV23_Pos)     /*!< 0x00800000 */
4460 #define EXTI_PRIVENR1_PRIV23                EXTI_PRIVENR1_PRIV23_Msk                /*!< Privilege enable on line 23 */
4461 #define EXTI_PRIVENR1_PRIV24_Pos            (24U)
4462 #define EXTI_PRIVENR1_PRIV24_Msk            (0x1UL << EXTI_PRIVENR1_PRIV24_Pos)     /*!< 0x01000000 */
4463 #define EXTI_PRIVENR1_PRIV24                EXTI_PRIVENR1_PRIV24_Msk                /*!< Privilege enable on line 24 */
4464 #define EXTI_PRIVENR1_PRIV25_Pos            (25U)
4465 #define EXTI_PRIVENR1_PRIV25_Msk            (0x1UL << EXTI_PRIVENR1_PRIV25_Pos)      /*!< 0x02000000 */
4466 #define EXTI_PRIVENR1_PRIV25                EXTI_PRIVENR1_PRIV25_Msk                 /*!< Privilege enable on line 25 */
4467 #define EXTI_PRIVENR1_PRIV26_Pos            (26U)
4468 #define EXTI_PRIVENR1_PRIV26_Msk            (0x1UL << EXTI_PRIVENR1_PRIV26_Pos)      /*!< 0x04000000 */
4469 #define EXTI_PRIVENR1_PRIV26                EXTI_PRIVENR1_PRIV26_Msk                 /*!< Privilege enable on line 26 */
4470 #define EXTI_PRIVENR1_PRIV27_Pos            (27U)
4471 #define EXTI_PRIVENR1_PRIV27_Msk            (0x1UL << EXTI_PRIVENR1_PRIV27_Pos)      /*!< 0x08000000 */
4472 #define EXTI_PRIVENR1_PRIV27                EXTI_PRIVENR1_PRIV27_Msk                 /*!< Privilege enable on line 27 */
4473 #define EXTI_PRIVENR1_PRIV28_Pos            (28U)
4474 #define EXTI_PRIVENR1_PRIV28_Msk            (0x1UL << EXTI_PRIVENR1_PRIV28_Pos)      /*!< 0x10000000 */
4475 #define EXTI_PRIVENR1_PRIV28                EXTI_PRIVENR1_PRIV28_Msk                 /*!< Privilege enable on line 28 */
4476 #define EXTI_PRIVENR1_PRIV29_Pos            (29U)
4477 #define EXTI_PRIVENR1_PRIV29_Msk            (0x1UL << EXTI_PRIVENR1_PRIV29_Pos)      /*!< 0x20000000 */
4478 #define EXTI_PRIVENR1_PRIV29                EXTI_PRIVENR1_PRIV29_Msk                 /*!< Privilege enable on line 29 */
4479 #define EXTI_PRIVENR1_PRIV30_Pos            (30U)
4480 #define EXTI_PRIVENR1_PRIV30_Msk            (0x1UL << EXTI_PRIVENR1_PRIV30_Pos)      /*!< 0x40000000 */
4481 #define EXTI_PRIVENR1_PRIV30                EXTI_PRIVENR1_PRIV30_Msk                 /*!< Privilege enable on line 30 */
4482 #define EXTI_PRIVENR1_PRIV31_Pos            (31U)
4483 #define EXTI_PRIVENR1_PRIV31_Msk            (0x1UL << EXTI_PRIVENR1_PRIV31_Pos)      /*!< 0x80000000 */
4484 #define EXTI_PRIVENR1_PRIV31                EXTI_PRIVENR1_PRIV31_Msk                 /*!< Privilege enable on line 31 */
4485 
4486 /******************  Bit definition for EXTI_RTSR2 register  *******************/
4487 #define EXTI_RTSR2_TR_Pos                   (14U)
4488 #define EXTI_RTSR2_TR_Msk                   (0x244UL << EXTI_RTSR2_TR_Pos)              /*!< 0x00244000 */
4489 #define EXTI_RTSR2_TR                       EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */
4490 #define EXTI_RTSR2_TR46_Pos                 (14U)
4491 #define EXTI_RTSR2_TR46_Msk                 (0x1UL << EXTI_RTSR2_TR46_Pos)              /*!< 0x00004000 */
4492 #define EXTI_RTSR2_TR46                     EXTI_RTSR2_TR46_Msk                         /*!< Rising trigger event configuration bit of line 46 */
4493 #define EXTI_RTSR2_TR50_Pos                 (18U)
4494 #define EXTI_RTSR2_TR50_Msk                 (0x1UL << EXTI_RTSR2_TR50_Pos)              /*!< 0x00040000 */
4495 #define EXTI_RTSR2_TR50                     EXTI_RTSR2_TR50_Msk                         /*!< Rising trigger event configuration bit of line 50 */
4496 #define EXTI_RTSR2_TR53_Pos                 (21U)
4497 #define EXTI_RTSR2_TR53_Msk                 (0x1UL << EXTI_RTSR2_TR53_Pos)              /*!< 0x00200000 */
4498 #define EXTI_RTSR2_TR53                     EXTI_RTSR2_TR53_Msk                         /*!< Rising trigger event configuration bit of line 53 */
4499 
4500 /******************  Bit definition for EXTI_FTSR2 register  *******************/
4501 #define EXTI_FTSR2_TR_Pos                   (14U)
4502 #define EXTI_FTSR2_TR_Msk                   (0x244 << EXTI_FTSR2_TR_Pos)                /*!< 0x00244000 */
4503 #define EXTI_FTSR2_TR                       EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */
4504 #define EXTI_FTSR2_TR46_Pos                 (14U)
4505 #define EXTI_FTSR2_TR46_Msk                 (0x1UL << EXTI_FTSR2_TR46_Pos)              /*!< 0x00004000 */
4506 #define EXTI_FTSR2_TR46                     EXTI_FTSR2_TR46_Msk                         /*!< Falling trigger event configuration bit of line 46 */
4507 #define EXTI_FTSR2_TR50_Pos                 (18U)
4508 #define EXTI_FTSR2_TR50_Msk                 (0x1UL << EXTI_FTSR2_TR50_Pos)              /*!< 0x00040000 */
4509 #define EXTI_FTSR2_TR50                     EXTI_FTSR2_TR50_Msk                         /*!< Falling trigger event configuration bit of line 50 */
4510 #define EXTI_FTSR2_TR53_Pos                 (21U)
4511 #define EXTI_FTSR2_TR53_Msk                 (0x1UL << EXTI_FTSR2_TR53_Pos)              /*!< 0x00200000 */
4512 #define EXTI_FTSR2_TR53                     EXTI_FTSR2_TR53_Msk                         /*!< Falling trigger event configuration bit of line 53 */
4513 
4514 /******************  Bit definition for EXTI_SWIER2 register  ******************/
4515 #define EXTI_SWIER2_SWIER46_Pos            (14U)
4516 #define EXTI_SWIER2_SWIER46_Msk            (0x1UL << EXTI_SWIER2_SWIER46_Pos)          /*!< 0x00004000 */
4517 #define EXTI_SWIER2_SWIER46                EXTI_SWIER2_SWIER46_Msk                     /*!< Software Interrupt on line 46 */
4518 #define EXTI_SWIER2_SWIER50_Pos            (18U)
4519 #define EXTI_SWIER2_SWIER50_Msk            (0x1UL << EXTI_SWIER2_SWIER50_Pos)          /*!< 0x00040000 */
4520 #define EXTI_SWIER2_SWIER50                EXTI_SWIER2_SWIER50_Msk                     /*!< Software Interrupt on line 50 */
4521 #define EXTI_SWIER2_SWIER53_Pos            (21U)
4522 #define EXTI_SWIER2_SWIER53_Msk            (0x1UL << EXTI_SWIER2_SWIER53_Pos)          /*!< 0x00200000 */
4523 #define EXTI_SWIER2_SWIER53                EXTI_SWIER2_SWIER53_Msk                     /*!< Software Interrupt on line 53 */
4524 
4525 /******************  Bit definition for EXTI_RPR2 register  *******************/
4526 #define EXTI_RPR2_RPIF_Pos                   (14U)
4527 #define EXTI_RPR2_RPIF_Msk                   (0x244UL << EXTI_RPR2_RPIF_Pos)        /*!< 0x00244000 */
4528 #define EXTI_RPR2_RPIF                       EXTI_RPR2_RPIF_Msk                     /*!< Rising pending edge configuration bits */
4529 #define EXTI_RPR2_RPIF46_Pos                 (14U)
4530 #define EXTI_RPR2_RPIF46_Msk                 (0x1UL << EXTI_RPR2_RPIF46_Pos)        /*!< 0x00004000 */
4531 #define EXTI_RPR2_RPIF46                     EXTI_RPR2_RPIF46_Msk                   /*!< Rising pending edge configuration bit of line 46 */
4532 #define EXTI_RPR2_RPIF50_Pos                 (18U)
4533 #define EXTI_RPR2_RPIF50_Msk                 (0x1UL << EXTI_RPR2_RPIF50_Pos)        /*!< 0x00040000 */
4534 #define EXTI_RPR2_RPIF50                     EXTI_RPR2_RPIF50_Msk                   /*!< Rising pending edge configuration bit of line 50 */
4535 #define EXTI_RPR2_RPIF53_Pos                 (21U)
4536 #define EXTI_RPR2_RPIF53_Msk                 (0x1UL << EXTI_RPR2_RPIF53_Pos)        /*!< 0x00200000 */
4537 #define EXTI_RPR2_RPIF53                     EXTI_RPR2_RPIF53_Msk                   /*!< Rising pending edge configuration bit of line 53 */
4538 
4539 /******************  Bit definition for EXTI_FPR2 register  *******************/
4540 #define EXTI_FPR2_FPIF_Pos                   (14U)
4541 #define EXTI_FPR2_FPIF_Msk                   (0x244UL << EXTI_FPR2_FPIF_Pos)        /*!< 0x00244000 */
4542 #define EXTI_FPR2_FPIF                       EXTI_FPR2_FPIF_Msk                     /*!< Rising falling edge configuration bits */
4543 #define EXTI_FPR2_FPIF46_Pos                 (14U)
4544 #define EXTI_FPR2_FPIF46_Msk                 (0x1UL << EXTI_FPR2_FPIF46_Pos)        /*!< 0x00004000 */
4545 #define EXTI_FPR2_FPIF46                     EXTI_FPR2_FPIF46_Msk                   /*!< Rising falling edge configuration bit of line 46 */
4546 #define EXTI_FPR2_FPIF50_Pos                 (18U)
4547 #define EXTI_FPR2_FPIF50_Msk                 (0x1UL << EXTI_FPR2_FPIF50_Pos)        /*!< 0x00040000 */
4548 #define EXTI_FPR2_FPIF50                     EXTI_FPR2_FPIF50_Msk                   /*!< Rising falling edge configuration bit of line 50 */
4549 #define EXTI_FPR2_FPIF53_Pos                 (21U)
4550 #define EXTI_FPR2_FPIF53_Msk                 (0x1UL << EXTI_FPR2_FPIF53_Pos)        /*!< 0x00200000 */
4551 #define EXTI_FPR2_FPIF53                     EXTI_FPR2_FPIF53_Msk                   /*!< Rising falling edge configuration bit of line 53 */
4552 
4553 /*******************  Bit definition for EXTI_SECENR2 register  ******************/
4554 #define EXTI_SECENR2_SEC32_Pos              (0U)
4555 #define EXTI_SECENR2_SEC32_Msk              (0x1UL << EXTI_SECENR2_SEC32_Pos)       /*!< 0x00000001 */
4556 #define EXTI_SECENR2_SEC32                  EXTI_SECENR2_SEC32_Msk                  /*!< Security enable on line 32 */
4557 #define EXTI_SECENR2_SEC33_Pos              (1U)
4558 #define EXTI_SECENR2_SEC33_Msk              (0x1UL << EXTI_SECENR2_SEC33_Pos)       /*!< 0x00000002 */
4559 #define EXTI_SECENR2_SEC33                  EXTI_SECENR2_SEC33_Msk                  /*!< Security enable on line 33 */
4560 #define EXTI_SECENR2_SEC34_Pos              (2U)
4561 #define EXTI_SECENR2_SEC34_Msk              (0x1UL << EXTI_SECENR2_SEC34_Pos)       /*!< 0x00000004 */
4562 #define EXTI_SECENR2_SEC34                  EXTI_SECENR2_SEC34_Msk                  /*!< Security enable on line 2 */
4563 #define EXTI_SECENR2_SEC35_Pos              (3U)
4564 #define EXTI_SECENR2_SEC35_Msk              (0x1UL << EXTI_SECENR2_SEC35_Pos)       /*!< 0x00000008 */
4565 #define EXTI_SECENR2_SEC35                  EXTI_SECENR2_SEC35_Msk                  /*!< Security enable on line 3 */
4566 #define EXTI_SECENR2_SEC36_Pos              (4U)
4567 #define EXTI_SECENR2_SEC36_Msk              (0x1UL << EXTI_SECENR2_SEC36_Pos)       /*!< 0x00000010 */
4568 #define EXTI_SECENR2_SEC36                  EXTI_SECENR2_SEC36_Msk                  /*!< Security enable on line 4 */
4569 #define EXTI_SECENR2_SEC37_Pos              (5U)
4570 #define EXTI_SECENR2_SEC37_Msk              (0x1UL << EXTI_SECENR2_SEC37_Pos)       /*!< 0x00000020 */
4571 #define EXTI_SECENR2_SEC37                  EXTI_SECENR2_SEC37_Msk                  /*!< Security enable on line 5 */
4572 #define EXTI_SECENR2_SEC38_Pos              (6U)
4573 #define EXTI_SECENR2_SEC38_Msk              (0x1UL << EXTI_SECENR2_SEC38_Pos)       /*!< 0x00000040 */
4574 #define EXTI_SECENR2_SEC38                  EXTI_SECENR2_SEC38_Msk                  /*!< Security enable on line 6 */
4575 #define EXTI_SECENR2_SEC39_Pos              (7U)
4576 #define EXTI_SECENR2_SEC39_Msk              (0x1UL << EXTI_SECENR2_SEC39_Pos)       /*!< 0x00000080 */
4577 #define EXTI_SECENR2_SEC39                  EXTI_SECENR2_SEC39_Msk                  /*!< Security enable on line 7 */
4578 #define EXTI_SECENR2_SEC40_Pos              (8U)
4579 #define EXTI_SECENR2_SEC40_Msk              (0x1UL << EXTI_SECENR2_SEC40_Pos)       /*!< 0x00000100 */
4580 #define EXTI_SECENR2_SEC40                  EXTI_SECENR2_SEC40_Msk                  /*!< Security enable on line 8 */
4581 #define EXTI_SECENR2_SEC41_Pos              (9U)
4582 #define EXTI_SECENR2_SEC41_Msk              (0x1UL << EXTI_SECENR2_SEC41_Pos)       /*!< 0x00000200 */
4583 #define EXTI_SECENR2_SEC41                  EXTI_SECENR2_SEC41_Msk                  /*!< Security enable on line 9 */
4584 #define EXTI_SECENR2_SEC42_Pos             (10U)
4585 #define EXTI_SECENR2_SEC42_Msk             (0x1UL << EXTI_SECENR2_SEC42_Pos)        /*!< 0x00000400 */
4586 #define EXTI_SECENR2_SEC42                 EXTI_SECENR2_SEC42_Msk                   /*!< Security enable on line 10 */
4587 #define EXTI_SECENR2_SEC43_Pos             (11U)
4588 #define EXTI_SECENR2_SEC43_Msk             (0x1UL << EXTI_SECENR2_SEC43_Pos)        /*!< 0x00000800 */
4589 #define EXTI_SECENR2_SEC43                 EXTI_SECENR2_SEC43_Msk                   /*!< Security enable on line 11 */
4590 #define EXTI_SECENR2_SEC44_Pos             (12U)
4591 #define EXTI_SECENR2_SEC44_Msk             (0x1UL << EXTI_SECENR2_SEC44_Pos)        /*!< 0x00001000 */
4592 #define EXTI_SECENR2_SEC44                 EXTI_SECENR2_SEC44_Msk                   /*!< Security enable on line 12 */
4593 #define EXTI_SECENR2_SEC45_Pos             (13U)
4594 #define EXTI_SECENR2_SEC45_Msk             (0x1UL << EXTI_SECENR2_SEC45_Pos)        /*!< 0x00002000 */
4595 #define EXTI_SECENR2_SEC45                 EXTI_SECENR2_SEC45_Msk                   /*!< Security enable on line 13 */
4596 #define EXTI_SECENR2_SEC46_Pos             (14U)
4597 #define EXTI_SECENR2_SEC46_Msk             (0x1UL << EXTI_SECENR2_SEC46_Pos)        /*!< 0x00004000 */
4598 #define EXTI_SECENR2_SEC46                 EXTI_SECENR2_SEC46_Msk                   /*!< Security enable on line 14 */
4599 #define EXTI_SECENR2_SEC47_Pos             (15U)
4600 #define EXTI_SECENR2_SEC47_Msk             (0x1UL << EXTI_SECENR2_SEC47_Pos)        /*!< 0x00008000 */
4601 #define EXTI_SECENR2_SEC47                 EXTI_SECENR2_SEC47_Msk                   /*!< Security enable on line 15 */
4602 #define EXTI_SECENR2_SEC48_Pos             (16U)
4603 #define EXTI_SECENR2_SEC48_Msk             (0x1UL << EXTI_SECENR2_SEC48_Pos)        /*!< 0x00010000 */
4604 #define EXTI_SECENR2_SEC48                 EXTI_SECENR2_SEC48_Msk                   /*!< Security enable on line 16 */
4605 #define EXTI_SECENR2_SEC49_Pos             (17U)
4606 #define EXTI_SECENR2_SEC49_Msk             (0x1UL << EXTI_SECENR2_SEC49_Pos)        /*!< 0x00020000 */
4607 #define EXTI_SECENR2_SEC49                 EXTI_SECENR2_SEC49_Msk                   /*!< Security enable on line 17 */
4608 #define EXTI_SECENR2_SEC50_Pos             (18U)
4609 #define EXTI_SECENR2_SEC50_Msk             (0x1UL << EXTI_SECENR2_SEC50_Pos)        /*!< 0x00040000 */
4610 #define EXTI_SECENR2_SEC50                 EXTI_SECENR2_SEC50_Msk                   /*!< Security enable on line 18 */
4611 #define EXTI_SECENR2_SEC51_Pos             (19U)
4612 #define EXTI_SECENR2_SEC51_Msk             (0x1UL << EXTI_SECENR2_SEC51_Pos)        /*!< 0x00080000 */
4613 #define EXTI_SECENR2_SEC51                 EXTI_SECENR2_SEC51_Msk                   /*!< Security enable on line 19 */
4614 #define EXTI_SECENR2_SEC52_Pos             (20U)
4615 #define EXTI_SECENR2_SEC52_Msk             (0x1UL << EXTI_SECENR2_SEC52_Pos)        /*!< 0x00100000 */
4616 #define EXTI_SECENR2_SEC52                 EXTI_SECENR2_SEC52_Msk                   /*!< Security enable on line 20 */
4617 #define EXTI_SECENR2_SEC53_Pos             (21U)
4618 #define EXTI_SECENR2_SEC53_Msk             (0x1UL << EXTI_SECENR2_SEC53_Pos)        /*!< 0x00200000 */
4619 #define EXTI_SECENR2_SEC53                 EXTI_SECENR2_SEC53_Msk                   /*!< Security enable on line 21 */
4620 #define EXTI_SECENR2_SEC54_Pos             (22U)
4621 #define EXTI_SECENR2_SEC54_Msk             (0x1UL << EXTI_SECENR2_SEC54_Pos)        /*!< 0x00400000 */
4622 #define EXTI_SECENR2_SEC54                 EXTI_SECENR2_SEC54_Msk                   /*!< Security enable on line 22 */
4623 #define EXTI_SECENR2_SEC55_Pos             (23U)
4624 #define EXTI_SECENR2_SEC55_Msk             (0x1UL << EXTI_SECENR2_SEC55_Pos)        /*!< 0x00800000 */
4625 #define EXTI_SECENR2_SEC55                 EXTI_SECENR2_SEC55_Msk                   /*!< Security enable on line 23 */
4626 #define EXTI_SECENR2_SEC56_Pos             (24U)
4627 #define EXTI_SECENR2_SEC56_Msk             (0x1UL << EXTI_SECENR2_SEC56_Pos)        /*!< 0x01000000 */
4628 #define EXTI_SECENR2_SEC56                 EXTI_SECENR2_SEC56_Msk                   /*!< Security enable on line 24 */
4629 #define EXTI_SECENR2_SEC57_Pos             (25U)
4630 #define EXTI_SECENR2_SEC57_Msk             (0x1UL << EXTI_SECENR2_SEC57_Pos)        /*!< 0x02000000 */
4631 #define EXTI_SECENR2_SEC57                 EXTI_SECENR2_SEC57_Msk                   /*!< Security enable on line 25 */
4632 
4633 /*******************  Bit definition for EXTI_PRIVENR2 register  ******************/
4634 #define EXTI_PRIVENR2_PRIV32_Pos              (0U)
4635 #define EXTI_PRIVENR2_PRIV32_Msk              (0x1UL << EXTI_PRIVENR2_PRIV32_Pos)       /*!< 0x00000001 */
4636 #define EXTI_PRIVENR2_PRIV32                  EXTI_PRIVENR2_PRIV32_Msk                  /*!< Security enable on line 32 */
4637 #define EXTI_PRIVENR2_PRIV33_Pos              (1U)
4638 #define EXTI_PRIVENR2_PRIV33_Msk              (0x1UL << EXTI_PRIVENR2_PRIV33_Pos)       /*!< 0x00000002 */
4639 #define EXTI_PRIVENR2_PRIV33                  EXTI_PRIVENR2_PRIV33_Msk                  /*!< Security enable on line 33 */
4640 #define EXTI_PRIVENR2_PRIV34_Pos              (2U)
4641 #define EXTI_PRIVENR2_PRIV34_Msk              (0x1UL << EXTI_PRIVENR2_PRIV34_Pos)       /*!< 0x00000004 */
4642 #define EXTI_PRIVENR2_PRIV34                  EXTI_PRIVENR2_PRIV34_Msk                  /*!< Security enable on line 2 */
4643 #define EXTI_PRIVENR2_PRIV35_Pos              (3U)
4644 #define EXTI_PRIVENR2_PRIV35_Msk              (0x1UL << EXTI_PRIVENR2_PRIV35_Pos)       /*!< 0x00000008 */
4645 #define EXTI_PRIVENR2_PRIV35                  EXTI_PRIVENR2_PRIV35_Msk                  /*!< Security enable on line 3 */
4646 #define EXTI_PRIVENR2_PRIV36_Pos              (4U)
4647 #define EXTI_PRIVENR2_PRIV36_Msk              (0x1UL << EXTI_PRIVENR2_PRIV36_Pos)       /*!< 0x00000010 */
4648 #define EXTI_PRIVENR2_PRIV36                  EXTI_PRIVENR2_PRIV36_Msk                  /*!< Security enable on line 4 */
4649 #define EXTI_PRIVENR2_PRIV37_Pos              (5U)
4650 #define EXTI_PRIVENR2_PRIV37_Msk              (0x1UL << EXTI_PRIVENR2_PRIV37_Pos)       /*!< 0x00000020 */
4651 #define EXTI_PRIVENR2_PRIV37                  EXTI_PRIVENR2_PRIV37_Msk                  /*!< Security enable on line 5 */
4652 #define EXTI_PRIVENR2_PRIV38_Pos              (6U)
4653 #define EXTI_PRIVENR2_PRIV38_Msk              (0x1UL << EXTI_PRIVENR2_PRIV38_Pos)       /*!< 0x00000040 */
4654 #define EXTI_PRIVENR2_PRIV38                  EXTI_PRIVENR2_PRIV38_Msk                  /*!< Security enable on line 6 */
4655 #define EXTI_PRIVENR2_PRIV39_Pos              (7U)
4656 #define EXTI_PRIVENR2_PRIV39_Msk              (0x1UL << EXTI_PRIVENR2_PRIV39_Pos)       /*!< 0x00000080 */
4657 #define EXTI_PRIVENR2_PRIV39                  EXTI_PRIVENR2_PRIV39_Msk                  /*!< Security enable on line 7 */
4658 #define EXTI_PRIVENR2_PRIV40_Pos              (8U)
4659 #define EXTI_PRIVENR2_PRIV40_Msk              (0x1UL << EXTI_PRIVENR2_PRIV40_Pos)       /*!< 0x00000100 */
4660 #define EXTI_PRIVENR2_PRIV40                  EXTI_PRIVENR2_PRIV40_Msk                  /*!< Security enable on line 8 */
4661 #define EXTI_PRIVENR2_PRIV41_Pos              (9U)
4662 #define EXTI_PRIVENR2_PRIV41_Msk              (0x1UL << EXTI_PRIVENR2_PRIV41_Pos)       /*!< 0x00000200 */
4663 #define EXTI_PRIVENR2_PRIV41                  EXTI_PRIVENR2_PRIV41_Msk                  /*!< Security enable on line 9 */
4664 #define EXTI_PRIVENR2_PRIV42_Pos             (10U)
4665 #define EXTI_PRIVENR2_PRIV42_Msk             (0x1UL << EXTI_PRIVENR2_PRIV42_Pos)        /*!< 0x00000400 */
4666 #define EXTI_PRIVENR2_PRIV42                 EXTI_PRIVENR2_PRIV42_Msk                   /*!< Security enable on line 10 */
4667 #define EXTI_PRIVENR2_PRIV43_Pos             (11U)
4668 #define EXTI_PRIVENR2_PRIV43_Msk             (0x1UL << EXTI_PRIVENR2_PRIV43_Pos)        /*!< 0x00000800 */
4669 #define EXTI_PRIVENR2_PRIV43                 EXTI_PRIVENR2_PRIV43_Msk                   /*!< Security enable on line 11 */
4670 #define EXTI_PRIVENR2_PRIV44_Pos             (12U)
4671 #define EXTI_PRIVENR2_PRIV44_Msk             (0x1UL << EXTI_PRIVENR2_PRIV44_Pos)        /*!< 0x00001000 */
4672 #define EXTI_PRIVENR2_PRIV44                 EXTI_PRIVENR2_PRIV44_Msk                   /*!< Security enable on line 12 */
4673 #define EXTI_PRIVENR2_PRIV45_Pos             (13U)
4674 #define EXTI_PRIVENR2_PRIV45_Msk             (0x1UL << EXTI_PRIVENR2_PRIV45_Pos)        /*!< 0x00002000 */
4675 #define EXTI_PRIVENR2_PRIV45                 EXTI_PRIVENR2_PRIV45_Msk                   /*!< Security enable on line 13 */
4676 #define EXTI_PRIVENR2_PRIV46_Pos             (14U)
4677 #define EXTI_PRIVENR2_PRIV46_Msk             (0x1UL << EXTI_PRIVENR2_PRIV46_Pos)        /*!< 0x00004000 */
4678 #define EXTI_PRIVENR2_PRIV46                 EXTI_PRIVENR2_PRIV46_Msk                   /*!< Security enable on line 14 */
4679 #define EXTI_PRIVENR2_PRIV47_Pos             (15U)
4680 #define EXTI_PRIVENR2_PRIV47_Msk             (0x1UL << EXTI_PRIVENR2_PRIV47_Pos)        /*!< 0x00008000 */
4681 #define EXTI_PRIVENR2_PRIV47                 EXTI_PRIVENR2_PRIV47_Msk                   /*!< Security enable on line 15 */
4682 #define EXTI_PRIVENR2_PRIV48_Pos             (16U)
4683 #define EXTI_PRIVENR2_PRIV48_Msk             (0x1UL << EXTI_PRIVENR2_PRIV48_Pos)        /*!< 0x00010000 */
4684 #define EXTI_PRIVENR2_PRIV48                 EXTI_PRIVENR2_PRIV48_Msk                   /*!< Security enable on line 16 */
4685 #define EXTI_PRIVENR2_PRIV49_Pos             (17U)
4686 #define EXTI_PRIVENR2_PRIV49_Msk             (0x1UL << EXTI_PRIVENR2_PRIV49_Pos)        /*!< 0x00020000 */
4687 #define EXTI_PRIVENR2_PRIV49                 EXTI_PRIVENR2_PRIV49_Msk                   /*!< Security enable on line 17 */
4688 #define EXTI_PRIVENR2_PRIV50_Pos             (18U)
4689 #define EXTI_PRIVENR2_PRIV50_Msk             (0x1UL << EXTI_PRIVENR2_PRIV50_Pos)        /*!< 0x00040000 */
4690 #define EXTI_PRIVENR2_PRIV50                 EXTI_PRIVENR2_PRIV50_Msk                   /*!< Security enable on line 18 */
4691 #define EXTI_PRIVENR2_PRIV51_Pos             (19U)
4692 #define EXTI_PRIVENR2_PRIV51_Msk             (0x1UL << EXTI_PRIVENR2_PRIV51_Pos)        /*!< 0x00080000 */
4693 #define EXTI_PRIVENR2_PRIV51                 EXTI_PRIVENR2_PRIV51_Msk                   /*!< Security enable on line 19 */
4694 #define EXTI_PRIVENR2_PRIV52_Pos             (20U)
4695 #define EXTI_PRIVENR2_PRIV52_Msk             (0x1UL << EXTI_PRIVENR2_PRIV52_Pos)        /*!< 0x00100000 */
4696 #define EXTI_PRIVENR2_PRIV52                 EXTI_PRIVENR2_PRIV52_Msk                   /*!< Security enable on line 20 */
4697 #define EXTI_PRIVENR2_PRIV53_Pos             (21U)
4698 #define EXTI_PRIVENR2_PRIV53_Msk             (0x1UL << EXTI_PRIVENR2_PRIV53_Pos)        /*!< 0x00200000 */
4699 #define EXTI_PRIVENR2_PRIV53                 EXTI_PRIVENR2_PRIV53_Msk                   /*!< Security enable on line 21 */
4700 #define EXTI_PRIVENR2_PRIV54_Pos             (22U)
4701 #define EXTI_PRIVENR2_PRIV54_Msk             (0x1UL << EXTI_PRIVENR2_PRIV54_Pos)        /*!< 0x00400000 */
4702 #define EXTI_PRIVENR2_PRIV54                 EXTI_PRIVENR2_PRIV54_Msk                   /*!< Security enable on line 22 */
4703 #define EXTI_PRIVENR2_PRIV55_Pos             (23U)
4704 #define EXTI_PRIVENR2_PRIV55_Msk             (0x1UL << EXTI_PRIVENR2_PRIV55_Pos)        /*!< 0x00800000 */
4705 #define EXTI_PRIVENR2_PRIV55                 EXTI_PRIVENR2_PRIV55_Msk                   /*!< Security enable on line 23 */
4706 #define EXTI_PRIVENR2_PRIV56_Pos             (24U)
4707 #define EXTI_PRIVENR2_PRIV56_Msk             (0x1UL << EXTI_PRIVENR2_PRIV56_Pos)        /*!< 0x01000000 */
4708 #define EXTI_PRIVENR2_PRIV56                 EXTI_PRIVENR2_PRIV56_Msk                   /*!< Security enable on line 24 */
4709 #define EXTI_PRIVENR2_PRIV57_Pos             (25U)
4710 #define EXTI_PRIVENR2_PRIV57_Msk             (0x1UL << EXTI_PRIVENR2_PRIV57_Pos)        /*!< 0x02000000 */
4711 #define EXTI_PRIVENR2_PRIV57                 EXTI_PRIVENR2_PRIV57_Msk                   /*!< Security enable on line 25 */
4712 
4713 /*****************  Bit definition for EXTI_EXTICR1 register  **************/
4714 #define EXTI_EXTICR1_EXTI0_Pos              (0U)
4715 #define EXTI_EXTICR1_EXTI0_Msk              (0xFUL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000007 */
4716 #define EXTI_EXTICR1_EXTI0                  EXTI_EXTICR1_EXTI0_Msk                  /*!< EXTI 0 configuration */
4717 #define EXTI_EXTICR1_EXTI0_0                (0x1UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000001 */
4718 #define EXTI_EXTICR1_EXTI0_1                (0x2UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000002 */
4719 #define EXTI_EXTICR1_EXTI0_2                (0x4UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000004 */
4720 #define EXTI_EXTICR1_EXTI0_3                (0x8UL << EXTI_EXTICR1_EXTI0_Pos)       /*!< 0x00000008 */
4721 #define EXTI_EXTICR1_EXTI1_Pos              (8U)
4722 #define EXTI_EXTICR1_EXTI1_Msk              (0xFUL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000700 */
4723 #define EXTI_EXTICR1_EXTI1                  EXTI_EXTICR1_EXTI1_Msk                  /*!< EXTI 1 configuration */
4724 #define EXTI_EXTICR1_EXTI1_0                (0x1UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000100 */
4725 #define EXTI_EXTICR1_EXTI1_1                (0x2UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000200 */
4726 #define EXTI_EXTICR1_EXTI1_2                (0x4UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000400 */
4727 #define EXTI_EXTICR1_EXTI1_3                (0x8UL << EXTI_EXTICR1_EXTI1_Pos)       /*!< 0x00000800 */
4728 #define EXTI_EXTICR1_EXTI2_Pos              (16U)
4729 #define EXTI_EXTICR1_EXTI2_Msk              (0xFUL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00070000 */
4730 #define EXTI_EXTICR1_EXTI2                  EXTI_EXTICR1_EXTI2_Msk                  /*!< EXTI 2 configuration */
4731 #define EXTI_EXTICR1_EXTI2_0                (0x1UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00010000 */
4732 #define EXTI_EXTICR1_EXTI2_1                (0x2UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00020000 */
4733 #define EXTI_EXTICR1_EXTI2_2                (0x4UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00040000 */
4734 #define EXTI_EXTICR1_EXTI2_3                (0x8UL << EXTI_EXTICR1_EXTI2_Pos)       /*!< 0x00080000 */
4735 #define EXTI_EXTICR1_EXTI3_Pos              (24U)
4736 #define EXTI_EXTICR1_EXTI3_Msk              (0xFUL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x07000000 */
4737 #define EXTI_EXTICR1_EXTI3                  EXTI_EXTICR1_EXTI3_Msk                  /*!< EXTI 3 configuration */
4738 #define EXTI_EXTICR1_EXTI3_0                (0x1UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x01000000 */
4739 #define EXTI_EXTICR1_EXTI3_1                (0x2UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x02000000 */
4740 #define EXTI_EXTICR1_EXTI3_2                (0x4UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x04000000 */
4741 #define EXTI_EXTICR1_EXTI3_3                (0x8UL << EXTI_EXTICR1_EXTI3_Pos)       /*!< 0x08000000 */
4742 
4743 /*****************  Bit definition for EXTI_EXTICR2 register  **************/
4744 #define EXTI_EXTICR2_EXTI4_Pos              (0U)
4745 #define EXTI_EXTICR2_EXTI4_Msk              (0xFUL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000007 */
4746 #define EXTI_EXTICR2_EXTI4                  EXTI_EXTICR2_EXTI4_Msk                  /*!< EXTI 4 configuration */
4747 #define EXTI_EXTICR2_EXTI4_0                (0x1UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000001 */
4748 #define EXTI_EXTICR2_EXTI4_1                (0x2UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000002 */
4749 #define EXTI_EXTICR2_EXTI4_2                (0x4UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000004 */
4750 #define EXTI_EXTICR2_EXTI4_3                (0x8UL << EXTI_EXTICR2_EXTI4_Pos)       /*!< 0x00000008 */
4751 #define EXTI_EXTICR2_EXTI5_Pos              (8U)
4752 #define EXTI_EXTICR2_EXTI5_Msk              (0xFUL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000700 */
4753 #define EXTI_EXTICR2_EXTI5                  EXTI_EXTICR2_EXTI5_Msk                  /*!< EXTI 5 configuration */
4754 #define EXTI_EXTICR2_EXTI5_0                (0x1UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000100 */
4755 #define EXTI_EXTICR2_EXTI5_1                (0x2UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000200 */
4756 #define EXTI_EXTICR2_EXTI5_2                (0x4UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000400 */
4757 #define EXTI_EXTICR2_EXTI5_3                (0x8UL << EXTI_EXTICR2_EXTI5_Pos)       /*!< 0x00000800 */
4758 #define EXTI_EXTICR2_EXTI6_Pos              (16U)
4759 #define EXTI_EXTICR2_EXTI6_Msk              (0xFUL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00070000 */
4760 #define EXTI_EXTICR2_EXTI6                  EXTI_EXTICR2_EXTI6_Msk                  /*!< EXTI 6 configuration */
4761 #define EXTI_EXTICR2_EXTI6_0                (0x1UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00010000 */
4762 #define EXTI_EXTICR2_EXTI6_1                (0x2UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00020000 */
4763 #define EXTI_EXTICR2_EXTI6_2                (0x4UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00040000 */
4764 #define EXTI_EXTICR2_EXTI6_3                (0x8UL << EXTI_EXTICR2_EXTI6_Pos)       /*!< 0x00080000 */
4765 #define EXTI_EXTICR2_EXTI7_Pos              (24U)
4766 #define EXTI_EXTICR2_EXTI7_Msk              (0xFUL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x07000000 */
4767 #define EXTI_EXTICR2_EXTI7                  EXTI_EXTICR2_EXTI7_Msk                  /*!< EXTI 7 configuration */
4768 #define EXTI_EXTICR2_EXTI7_0                (0x1UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x01000000 */
4769 #define EXTI_EXTICR2_EXTI7_1                (0x2UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x02000000 */
4770 #define EXTI_EXTICR2_EXTI7_2                (0x4UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x04000000 */
4771 #define EXTI_EXTICR2_EXTI7_3                (0x8UL << EXTI_EXTICR2_EXTI7_Pos)       /*!< 0x08000000 */
4772 
4773 /*****************  Bit definition for EXTI_EXTICR3 register  **************/
4774 #define EXTI_EXTICR3_EXTI8_Pos              (0U)
4775 #define EXTI_EXTICR3_EXTI8_Msk              (0xFUL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000007 */
4776 #define EXTI_EXTICR3_EXTI8                  EXTI_EXTICR3_EXTI8_Msk                  /*!< EXTI 8 configuration */
4777 #define EXTI_EXTICR3_EXTI8_0                (0x1UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000001 */
4778 #define EXTI_EXTICR3_EXTI8_1                (0x2UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000002 */
4779 #define EXTI_EXTICR3_EXTI8_2                (0x4UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000004 */
4780 #define EXTI_EXTICR3_EXTI8_3                (0x8UL << EXTI_EXTICR3_EXTI8_Pos)       /*!< 0x00000008 */
4781 #define EXTI_EXTICR3_EXTI9_Pos              (8U)
4782 #define EXTI_EXTICR3_EXTI9_Msk              (0xFUL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000700 */
4783 #define EXTI_EXTICR3_EXTI9                  EXTI_EXTICR3_EXTI9_Msk                  /*!< EXTI 9 configuration */
4784 #define EXTI_EXTICR3_EXTI9_0                (0x1UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000100 */
4785 #define EXTI_EXTICR3_EXTI9_1                (0x2UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000200 */
4786 #define EXTI_EXTICR3_EXTI9_2                (0x4UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000400 */
4787 #define EXTI_EXTICR3_EXTI9_3                (0x8UL << EXTI_EXTICR3_EXTI9_Pos)       /*!< 0x00000800 */
4788 #define EXTI_EXTICR3_EXTI10_Pos             (16U)
4789 #define EXTI_EXTICR3_EXTI10_Msk             (0xFUL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00070000 */
4790 #define EXTI_EXTICR3_EXTI10                 EXTI_EXTICR3_EXTI10_Msk                 /*!< EXTI 10 configuration */
4791 #define EXTI_EXTICR3_EXTI10_0               (0x1UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00010000 */
4792 #define EXTI_EXTICR3_EXTI10_1               (0x2UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00020000 */
4793 #define EXTI_EXTICR3_EXTI10_2               (0x4UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00040000 */
4794 #define EXTI_EXTICR3_EXTI10_3               (0x8UL << EXTI_EXTICR3_EXTI10_Pos)      /*!< 0x00080000 */
4795 #define EXTI_EXTICR3_EXTI11_Pos             (24U)
4796 #define EXTI_EXTICR3_EXTI11_Msk             (0xFUL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x07000000 */
4797 #define EXTI_EXTICR3_EXTI11                 EXTI_EXTICR3_EXTI11_Msk                 /*!< EXTI 11 configuration */
4798 #define EXTI_EXTICR3_EXTI11_0               (0x1UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x01000000 */
4799 #define EXTI_EXTICR3_EXTI11_1               (0x2UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x02000000 */
4800 #define EXTI_EXTICR3_EXTI11_2               (0x4UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x04000000 */
4801 #define EXTI_EXTICR3_EXTI11_3               (0x8UL << EXTI_EXTICR3_EXTI11_Pos)      /*!< 0x08000000 */
4802 
4803 /*****************  Bit definition for EXTI_EXTICR4 register  **************/
4804 #define EXTI_EXTICR4_EXTI12_Pos             (0U)
4805 #define EXTI_EXTICR4_EXTI12_Msk             (0xFUL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000007 */
4806 #define EXTI_EXTICR4_EXTI12                 EXTI_EXTICR4_EXTI12_Msk                 /*!< EXTI 12 configuration */
4807 #define EXTI_EXTICR4_EXTI12_0               (0x1UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000001 */
4808 #define EXTI_EXTICR4_EXTI12_1               (0x2UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000002 */
4809 #define EXTI_EXTICR4_EXTI12_2               (0x4UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000004 */
4810 #define EXTI_EXTICR4_EXTI12_3               (0x8UL << EXTI_EXTICR4_EXTI12_Pos)      /*!< 0x00000008 */
4811 #define EXTI_EXTICR4_EXTI13_Pos             (8U)
4812 #define EXTI_EXTICR4_EXTI13_Msk             (0xFUL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000700 */
4813 #define EXTI_EXTICR4_EXTI13                 EXTI_EXTICR4_EXTI13_Msk                 /*!< EXTI 13 configuration */
4814 #define EXTI_EXTICR4_EXTI13_0               (0x1UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000100 */
4815 #define EXTI_EXTICR4_EXTI13_1               (0x2UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000200 */
4816 #define EXTI_EXTICR4_EXTI13_2               (0x4UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000400 */
4817 #define EXTI_EXTICR4_EXTI13_3               (0x8UL << EXTI_EXTICR4_EXTI13_Pos)      /*!< 0x00000800 */
4818 #define EXTI_EXTICR4_EXTI14_Pos             (16U)
4819 #define EXTI_EXTICR4_EXTI14_Msk             (0xFUL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00070000 */
4820 #define EXTI_EXTICR4_EXTI14                 EXTI_EXTICR4_EXTI14_Msk                 /*!< EXTI 14 configuration */
4821 #define EXTI_EXTICR4_EXTI14_0               (0x1UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00010000 */
4822 #define EXTI_EXTICR4_EXTI14_1               (0x2UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00020000 */
4823 #define EXTI_EXTICR4_EXTI14_2               (0x4UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00040000 */
4824 #define EXTI_EXTICR4_EXTI14_3               (0x8UL << EXTI_EXTICR4_EXTI14_Pos)      /*!< 0x00080000 */
4825 #define EXTI_EXTICR4_EXTI15_Pos             (24U)
4826 #define EXTI_EXTICR4_EXTI15_Msk             (0xFUL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x07000000 */
4827 #define EXTI_EXTICR4_EXTI15                 EXTI_EXTICR4_EXTI15_Msk                 /*!< EXTI 15 configuration */
4828 #define EXTI_EXTICR4_EXTI15_0               (0x1UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x01000000 */
4829 #define EXTI_EXTICR4_EXTI15_1               (0x2UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x02000000 */
4830 #define EXTI_EXTICR4_EXTI15_2               (0x4UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x04000000 */
4831 #define EXTI_EXTICR4_EXTI15_3               (0x8UL << EXTI_EXTICR4_EXTI15_Pos)      /*!< 0x08000000 */
4832 
4833 /*******************  Bit definition for EXTI_IMR1 register  ******************/
4834 #define EXTI_IMR1_IM_Pos                    (0U)
4835 #define EXTI_IMR1_IM_Msk                    (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)      /*!< 0xFFFFFFFF */
4836 #define EXTI_IMR1_IM                        EXTI_IMR1_IM_Msk                        /*!< Interrupt Mask */
4837 #define EXTI_IMR1_IM0_Pos                   (0U)
4838 #define EXTI_IMR1_IM0_Msk                   (0x1UL << EXTI_IMR1_IM0_Pos)            /*!< 0x00000001 */
4839 #define EXTI_IMR1_IM0                       EXTI_IMR1_IM0_Msk                       /*!< Interrupt Mask on line 0 */
4840 #define EXTI_IMR1_IM1_Pos                   (1U)
4841 #define EXTI_IMR1_IM1_Msk                   (0x1UL << EXTI_IMR1_IM1_Pos)            /*!< 0x00000002 */
4842 #define EXTI_IMR1_IM1                       EXTI_IMR1_IM1_Msk                       /*!< Interrupt Mask on line 1 */
4843 #define EXTI_IMR1_IM2_Pos                   (2U)
4844 #define EXTI_IMR1_IM2_Msk                   (0x1UL << EXTI_IMR1_IM2_Pos)            /*!< 0x00000004 */
4845 #define EXTI_IMR1_IM2                       EXTI_IMR1_IM2_Msk                       /*!< Interrupt Mask on line 2 */
4846 #define EXTI_IMR1_IM3_Pos                   (3U)
4847 #define EXTI_IMR1_IM3_Msk                   (0x1UL << EXTI_IMR1_IM3_Pos)            /*!< 0x00000008 */
4848 #define EXTI_IMR1_IM3                       EXTI_IMR1_IM3_Msk                       /*!< Interrupt Mask on line 3 */
4849 #define EXTI_IMR1_IM4_Pos                   (4U)
4850 #define EXTI_IMR1_IM4_Msk                   (0x1UL << EXTI_IMR1_IM4_Pos)            /*!< 0x00000010 */
4851 #define EXTI_IMR1_IM4                       EXTI_IMR1_IM4_Msk                       /*!< Interrupt Mask on line 4 */
4852 #define EXTI_IMR1_IM5_Pos                   (5U)
4853 #define EXTI_IMR1_IM5_Msk                   (0x1UL << EXTI_IMR1_IM5_Pos)            /*!< 0x00000020 */
4854 #define EXTI_IMR1_IM5                       EXTI_IMR1_IM5_Msk                       /*!< Interrupt Mask on line 5 */
4855 #define EXTI_IMR1_IM6_Pos                   (6U)
4856 #define EXTI_IMR1_IM6_Msk                   (0x1UL << EXTI_IMR1_IM6_Pos)            /*!< 0x00000040 */
4857 #define EXTI_IMR1_IM6                       EXTI_IMR1_IM6_Msk                       /*!< Interrupt Mask on line 6 */
4858 #define EXTI_IMR1_IM7_Pos                   (7U)
4859 #define EXTI_IMR1_IM7_Msk                   (0x1UL << EXTI_IMR1_IM7_Pos)            /*!< 0x00000080 */
4860 #define EXTI_IMR1_IM7                       EXTI_IMR1_IM7_Msk                       /*!< Interrupt Mask on line 7 */
4861 #define EXTI_IMR1_IM8_Pos                   (8U)
4862 #define EXTI_IMR1_IM8_Msk                   (0x1UL << EXTI_IMR1_IM8_Pos)            /*!< 0x00000100 */
4863 #define EXTI_IMR1_IM8                       EXTI_IMR1_IM8_Msk                       /*!< Interrupt Mask on line 8 */
4864 #define EXTI_IMR1_IM9_Pos                   (9U)
4865 #define EXTI_IMR1_IM9_Msk                   (0x1UL << EXTI_IMR1_IM9_Pos)            /*!< 0x00000200 */
4866 #define EXTI_IMR1_IM9                       EXTI_IMR1_IM9_Msk                       /*!< Interrupt Mask on line 9 */
4867 #define EXTI_IMR1_IM10_Pos                  (10U)
4868 #define EXTI_IMR1_IM10_Msk                  (0x1UL << EXTI_IMR1_IM10_Pos)           /*!< 0x00000400 */
4869 #define EXTI_IMR1_IM10                      EXTI_IMR1_IM10_Msk                      /*!< Interrupt Mask on line 10 */
4870 #define EXTI_IMR1_IM11_Pos                  (11U)
4871 #define EXTI_IMR1_IM11_Msk                  (0x1UL << EXTI_IMR1_IM11_Pos)           /*!< 0x00000800 */
4872 #define EXTI_IMR1_IM11                      EXTI_IMR1_IM11_Msk                      /*!< Interrupt Mask on line 11 */
4873 #define EXTI_IMR1_IM12_Pos                  (12U)
4874 #define EXTI_IMR1_IM12_Msk                  (0x1UL << EXTI_IMR1_IM12_Pos)           /*!< 0x00001000 */
4875 #define EXTI_IMR1_IM12                      EXTI_IMR1_IM12_Msk                      /*!< Interrupt Mask on line 12 */
4876 #define EXTI_IMR1_IM13_Pos                  (13U)
4877 #define EXTI_IMR1_IM13_Msk                  (0x1UL << EXTI_IMR1_IM13_Pos)           /*!< 0x00002000 */
4878 #define EXTI_IMR1_IM13                      EXTI_IMR1_IM13_Msk                      /*!< Interrupt Mask on line 13 */
4879 #define EXTI_IMR1_IM14_Pos                  (14U)
4880 #define EXTI_IMR1_IM14_Msk                  (0x1UL << EXTI_IMR1_IM14_Pos)           /*!< 0x00004000 */
4881 #define EXTI_IMR1_IM14                      EXTI_IMR1_IM14_Msk                      /*!< Interrupt Mask on line 14 */
4882 #define EXTI_IMR1_IM15_Pos                  (15U)
4883 #define EXTI_IMR1_IM15_Msk                  (0x1UL << EXTI_IMR1_IM15_Pos)           /*!< 0x00008000 */
4884 #define EXTI_IMR1_IM15                      EXTI_IMR1_IM15_Msk                      /*!< Interrupt Mask on line 15 */
4885 #define EXTI_IMR1_IM16_Pos                  (16U)
4886 #define EXTI_IMR1_IM16_Msk                  (0x1UL << EXTI_IMR1_IM16_Pos)           /*!< 0x00010000 */
4887 #define EXTI_IMR1_IM16                      EXTI_IMR1_IM16_Msk                      /*!< Interrupt Mask on line 16 */
4888 #define EXTI_IMR1_IM17_Pos                  (17U)
4889 #define EXTI_IMR1_IM17_Msk                  (0x1UL << EXTI_IMR1_IM17_Pos)           /*!< 0x00020000 */
4890 #define EXTI_IMR1_IM17                      EXTI_IMR1_IM17_Msk                      /*!< Interrupt Mask on line 17 */
4891 #define EXTI_IMR1_IM18_Pos                  (18U)
4892 #define EXTI_IMR1_IM18_Msk                  (0x1UL << EXTI_IMR1_IM18_Pos)           /*!< 0x00040000 */
4893 #define EXTI_IMR1_IM18                      EXTI_IMR1_IM18_Msk                      /*!< Interrupt Mask on line 18 */
4894 #define EXTI_IMR1_IM19_Pos                  (19U)
4895 #define EXTI_IMR1_IM19_Msk                  (0x1UL << EXTI_IMR1_IM19_Pos)           /*!< 0x00080000 */
4896 #define EXTI_IMR1_IM19                      EXTI_IMR1_IM19_Msk                      /*!< Interrupt Mask on line 19 */
4897 #define EXTI_IMR1_IM20_Pos                  (20U)
4898 #define EXTI_IMR1_IM20_Msk                  (0x1UL << EXTI_IMR1_IM20_Pos)           /*!< 0x00100000 */
4899 #define EXTI_IMR1_IM20                      EXTI_IMR1_IM20_Msk                      /*!< Interrupt Mask on line 20 */
4900 #define EXTI_IMR1_IM21_Pos                  (21U)
4901 #define EXTI_IMR1_IM21_Msk                  (0x1UL << EXTI_IMR1_IM21_Pos)           /*!< 0x00200000 */
4902 #define EXTI_IMR1_IM21                      EXTI_IMR1_IM21_Msk                      /*!< Interrupt Mask on line 21 */
4903 #define EXTI_IMR1_IM22_Pos                  (22U)
4904 #define EXTI_IMR1_IM22_Msk                  (0x1UL << EXTI_IMR1_IM22_Pos)           /*!< 0x00400000 */
4905 #define EXTI_IMR1_IM22                      EXTI_IMR1_IM22_Msk                      /*!< Interrupt Mask on line 22 */
4906 #define EXTI_IMR1_IM23_Pos                  (23U)
4907 #define EXTI_IMR1_IM23_Msk                  (0x1UL << EXTI_IMR1_IM23_Pos)           /*!< 0x00800000 */
4908 #define EXTI_IMR1_IM23                      EXTI_IMR1_IM23_Msk                      /*!< Interrupt Mask on line 23 */
4909 #define EXTI_IMR1_IM24_Pos                  (24U)
4910 #define EXTI_IMR1_IM24_Msk                  (0x1UL << EXTI_IMR1_IM24_Pos)           /*!< 0x01000000 */
4911 #define EXTI_IMR1_IM24                      EXTI_IMR1_IM24_Msk                      /*!< Interrupt Mask on line 24 */
4912 #define EXTI_IMR1_IM25_Pos                  (25U)
4913 #define EXTI_IMR1_IM25_Msk                  (0x1UL << EXTI_IMR1_IM25_Pos)           /*!< 0x02000000 */
4914 #define EXTI_IMR1_IM25                      EXTI_IMR1_IM25_Msk                      /*!< Interrupt Mask on line 25 */
4915 #define EXTI_IMR1_IM26_Pos                  (26U)
4916 #define EXTI_IMR1_IM26_Msk                  (0x1UL << EXTI_IMR1_IM26_Pos)           /*!< 0x04000000 */
4917 #define EXTI_IMR1_IM26                      EXTI_IMR1_IM26_Msk                      /*!< Interrupt Mask on line 26 */
4918 #define EXTI_IMR1_IM27_Pos                  (27U)
4919 #define EXTI_IMR1_IM27_Msk                  (0x1UL << EXTI_IMR1_IM27_Pos)           /*!< 0x08000000 */
4920 #define EXTI_IMR1_IM27                      EXTI_IMR1_IM27_Msk                      /*!< Interrupt Mask on line 27 */
4921 #define EXTI_IMR1_IM28_Pos                  (28U)
4922 #define EXTI_IMR1_IM28_Msk                  (0x1UL << EXTI_IMR1_IM28_Pos)           /*!< 0x10000000 */
4923 #define EXTI_IMR1_IM28                      EXTI_IMR1_IM28_Msk                      /*!< Interrupt Mask on line 28 */
4924 #define EXTI_IMR1_IM29_Pos                  (29U)
4925 #define EXTI_IMR1_IM29_Msk                  (0x1UL << EXTI_IMR1_IM29_Pos)           /*!< 0x20000000 */
4926 #define EXTI_IMR1_IM29                      EXTI_IMR1_IM29_Msk                      /*!< Interrupt Mask on line 29 */
4927 #define EXTI_IMR1_IM30_Pos                  (30U)
4928 #define EXTI_IMR1_IM30_Msk                  (0x1UL << EXTI_IMR1_IM30_Pos)           /*!< 0x40000000 */
4929 #define EXTI_IMR1_IM30                      EXTI_IMR1_IM30_Msk                      /*!< Interrupt Mask on line 30 */
4930 #define EXTI_IMR1_IM31_Pos                  (31U)
4931 #define EXTI_IMR1_IM31_Msk                  (0x1UL << EXTI_IMR1_IM31_Pos)           /*!< 0x80000000 */
4932 #define EXTI_IMR1_IM31                      EXTI_IMR1_IM31_Msk                      /*!< Interrupt Mask on line 31 */
4933 
4934 /*******************  Bit definition for EXTI_EMR1 register  ******************/
4935 #define EXTI_EMR1_EM_Pos                    (0U)
4936 #define EXTI_EMR1_EM_Msk                    (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)      /*!< 0xFFFFFFFF */
4937 #define EXTI_EMR1_EM                        EXTI_EMR1_EM_Msk                        /*!< Event Mask */
4938 #define EXTI_EMR1_EM0_Pos                   (0U)
4939 #define EXTI_EMR1_EM0_Msk                   (0x1UL << EXTI_EMR1_EM0_Pos)            /*!< 0x00000001 */
4940 #define EXTI_EMR1_EM0                       EXTI_EMR1_EM0_Msk                       /*!< Event Mask on line 0 */
4941 #define EXTI_EMR1_EM1_Pos                   (1U)
4942 #define EXTI_EMR1_EM1_Msk                   (0x1UL << EXTI_EMR1_EM1_Pos)            /*!< 0x00000002 */
4943 #define EXTI_EMR1_EM1                       EXTI_EMR1_EM1_Msk                       /*!< Event Mask on line 1 */
4944 #define EXTI_EMR1_EM2_Pos                   (2U)
4945 #define EXTI_EMR1_EM2_Msk                   (0x1UL << EXTI_EMR1_EM2_Pos)            /*!< 0x00000004 */
4946 #define EXTI_EMR1_EM2                       EXTI_EMR1_EM2_Msk                       /*!< Event Mask on line 2 */
4947 #define EXTI_EMR1_EM3_Pos                   (3U)
4948 #define EXTI_EMR1_EM3_Msk                   (0x1UL << EXTI_EMR1_EM3_Pos)            /*!< 0x00000008 */
4949 #define EXTI_EMR1_EM3                       EXTI_EMR1_EM3_Msk                       /*!< Event Mask on line 3 */
4950 #define EXTI_EMR1_EM4_Pos                   (4U)
4951 #define EXTI_EMR1_EM4_Msk                   (0x1UL << EXTI_EMR1_EM4_Pos)            /*!< 0x00000010 */
4952 #define EXTI_EMR1_EM4                       EXTI_EMR1_EM4_Msk                       /*!< Event Mask on line 4 */
4953 #define EXTI_EMR1_EM5_Pos                   (5U)
4954 #define EXTI_EMR1_EM5_Msk                   (0x1UL << EXTI_EMR1_EM5_Pos)            /*!< 0x00000020 */
4955 #define EXTI_EMR1_EM5                       EXTI_EMR1_EM5_Msk                       /*!< Event Mask on line 5 */
4956 #define EXTI_EMR1_EM6_Pos                   (6U)
4957 #define EXTI_EMR1_EM6_Msk                   (0x1UL << EXTI_EMR1_EM6_Pos)            /*!< 0x00000040 */
4958 #define EXTI_EMR1_EM6                       EXTI_EMR1_EM6_Msk                       /*!< Event Mask on line 6 */
4959 #define EXTI_EMR1_EM7_Pos                   (7U)
4960 #define EXTI_EMR1_EM7_Msk                   (0x1UL << EXTI_EMR1_EM7_Pos)            /*!< 0x00000080 */
4961 #define EXTI_EMR1_EM7                       EXTI_EMR1_EM7_Msk                       /*!< Event Mask on line 7 */
4962 #define EXTI_EMR1_EM8_Pos                   (8U)
4963 #define EXTI_EMR1_EM8_Msk                   (0x1UL << EXTI_EMR1_EM8_Pos)            /*!< 0x00000100 */
4964 #define EXTI_EMR1_EM8                       EXTI_EMR1_EM8_Msk                       /*!< Event Mask on line 8 */
4965 #define EXTI_EMR1_EM9_Pos                   (9U)
4966 #define EXTI_EMR1_EM9_Msk                   (0x1UL << EXTI_EMR1_EM9_Pos)            /*!< 0x00000200 */
4967 #define EXTI_EMR1_EM9                       EXTI_EMR1_EM9_Msk                       /*!< Event Mask on line 9 */
4968 #define EXTI_EMR1_EM10_Pos                  (10U)
4969 #define EXTI_EMR1_EM10_Msk                  (0x1UL << EXTI_EMR1_EM10_Pos)           /*!< 0x00000400 */
4970 #define EXTI_EMR1_EM10                      EXTI_EMR1_EM10_Msk                      /*!< Event Mask on line 10 */
4971 #define EXTI_EMR1_EM11_Pos                  (11U)
4972 #define EXTI_EMR1_EM11_Msk                  (0x1UL << EXTI_EMR1_EM11_Pos)           /*!< 0x00000800 */
4973 #define EXTI_EMR1_EM11                      EXTI_EMR1_EM11_Msk                      /*!< Event Mask on line 11 */
4974 #define EXTI_EMR1_EM12_Pos                  (12U)
4975 #define EXTI_EMR1_EM12_Msk                  (0x1UL << EXTI_EMR1_EM12_Pos)           /*!< 0x00001000 */
4976 #define EXTI_EMR1_EM12                      EXTI_EMR1_EM12_Msk                      /*!< Event Mask on line 12 */
4977 #define EXTI_EMR1_EM13_Pos                  (13U)
4978 #define EXTI_EMR1_EM13_Msk                  (0x1UL << EXTI_EMR1_EM13_Pos)           /*!< 0x00002000 */
4979 #define EXTI_EMR1_EM13                      EXTI_EMR1_EM13_Msk                      /*!< Event Mask on line 13 */
4980 #define EXTI_EMR1_EM14_Pos                  (14U)
4981 #define EXTI_EMR1_EM14_Msk                  (0x1UL << EXTI_EMR1_EM14_Pos)           /*!< 0x00004000 */
4982 #define EXTI_EMR1_EM14                      EXTI_EMR1_EM14_Msk                      /*!< Event Mask on line 14 */
4983 #define EXTI_EMR1_EM15_Pos                  (15U)
4984 #define EXTI_EMR1_EM15_Msk                  (0x1UL << EXTI_EMR1_EM15_Pos)           /*!< 0x00008000 */
4985 #define EXTI_EMR1_EM15                      EXTI_EMR1_EM15_Msk                      /*!< Event Mask on line 15 */
4986 #define EXTI_EMR1_EM16_Pos                  (16U)
4987 #define EXTI_EMR1_EM16_Msk                  (0x1UL << EXTI_EMR1_EM16_Pos)           /*!< 0x00010000 */
4988 #define EXTI_EMR1_EM16                      EXTI_EMR1_EM16_Msk                      /*!< Event Mask on line 16 */
4989 #define EXTI_EMR1_EM17_Pos                  (17U)
4990 #define EXTI_EMR1_EM17_Msk                  (0x1UL << EXTI_EMR1_EM17_Pos)           /*!< 0x00020000 */
4991 #define EXTI_EMR1_EM17                      EXTI_EMR1_EM17_Msk                      /*!< Event Mask on line 17 */
4992 #define EXTI_EMR1_EM18_Pos                  (18U)
4993 #define EXTI_EMR1_EM18_Msk                  (0x1UL << EXTI_EMR1_EM18_Pos)           /*!< 0x00040000 */
4994 #define EXTI_EMR1_EM18                      EXTI_EMR1_EM18_Msk                      /*!< Event Mask on line 18 */
4995 #define EXTI_EMR1_EM19_Pos                  (19U)
4996 #define EXTI_EMR1_EM19_Msk                  (0x1UL << EXTI_EMR1_EM19_Pos)           /*!< 0x00080000 */
4997 #define EXTI_EMR1_EM19                      EXTI_EMR1_EM19_Msk                      /*!< Event Mask on line 19 */
4998 #define EXTI_EMR1_EM20_Pos                  (20U)
4999 #define EXTI_EMR1_EM20_Msk                  (0x1UL << EXTI_EMR1_EM20_Pos)           /*!< 0x00100000 */
5000 #define EXTI_EMR1_EM20                      EXTI_EMR1_EM20_Msk                      /*!< Event Mask on line 20 */
5001 #define EXTI_EMR1_EM21_Pos                  (21U)
5002 #define EXTI_EMR1_EM21_Msk                  (0x1UL << EXTI_EMR1_EM21_Pos)           /*!< 0x00200000 */
5003 #define EXTI_EMR1_EM21                      EXTI_EMR1_EM21_Msk                      /*!< Event Mask on line 21 */
5004 #define EXTI_EMR1_EM22_Pos                  (22U)
5005 #define EXTI_EMR1_EM22_Msk                  (0x1UL << EXTI_EMR1_EM22_Pos)           /*!< 0x00400000 */
5006 #define EXTI_EMR1_EM22                      EXTI_EMR1_EM22_Msk                      /*!< Event Mask on line 22 */
5007 #define EXTI_EMR1_EM23_Pos                  (23U)
5008 #define EXTI_EMR1_EM23_Msk                  (0x1UL << EXTI_EMR1_EM23_Pos)           /*!< 0x00800000 */
5009 #define EXTI_EMR1_EM23                      EXTI_EMR1_EM23_Msk                      /*!< Event Mask on line 23 */
5010 #define EXTI_EMR1_EM24_Pos                  (24U)
5011 #define EXTI_EMR1_EM24_Msk                  (0x1UL << EXTI_EMR1_EM24_Pos)           /*!< 0x01000000 */
5012 #define EXTI_EMR1_EM24                      EXTI_EMR1_EM24_Msk                      /*!< Event Mask on line 24 */
5013 #define EXTI_EMR1_EM25_Pos                  (25U)
5014 #define EXTI_EMR1_EM25_Msk                  (0x1UL << EXTI_EMR1_EM25_Pos)           /*!< 0x02000000 */
5015 #define EXTI_EMR1_EM25                      EXTI_EMR1_EM25_Msk                      /*!< Event Mask on line 25 */
5016 #define EXTI_EMR1_EM26_Pos                  (26U)
5017 #define EXTI_EMR1_EM26_Msk                  (0x1UL << EXTI_EMR1_EM26_Pos)           /*!< 0x04000000 */
5018 #define EXTI_EMR1_EM26                      EXTI_EMR1_EM26_Msk                      /*!< Event Mask on line 26 */
5019 #define EXTI_EMR1_EM27_Pos                  (27U)
5020 #define EXTI_EMR1_EM27_Msk                  (0x1UL << EXTI_EMR1_EM27_Pos)           /*!< 0x08000000 */
5021 #define EXTI_EMR1_EM27                      EXTI_EMR1_EM27_Msk                      /*!< Event Mask on line 27 */
5022 #define EXTI_EMR1_EM28_Pos                  (28U)
5023 #define EXTI_EMR1_EM28_Msk                  (0x1UL << EXTI_EMR1_EM28_Pos)           /*!< 0x10000000 */
5024 #define EXTI_EMR1_EM28                      EXTI_EMR1_EM28_Msk                      /*!< Event Mask on line 28 */
5025 #define EXTI_EMR1_EM29_Pos                  (29U)
5026 #define EXTI_EMR1_EM29_Msk                  (0x1UL << EXTI_EMR1_EM29_Pos)           /*!< 0x20000000 */
5027 #define EXTI_EMR1_EM29                      EXTI_EMR1_EM29_Msk                      /*!< Event Mask on line 29 */
5028 #define EXTI_EMR1_EM30_Pos                  (30U)
5029 #define EXTI_EMR1_EM30_Msk                  (0x1UL << EXTI_EMR1_EM30_Pos)           /*!< 0x40000000 */
5030 #define EXTI_EMR1_EM30                      EXTI_EMR1_EM30_Msk                      /*!< Event Mask on line 30 */
5031 #define EXTI_EMR1_EM31_Pos                  (31U)
5032 #define EXTI_EMR1_EM31_Msk                  (0x1UL << EXTI_EMR1_EM31_Pos)           /*!< 0x80000000 */
5033 #define EXTI_EMR1_EM31                      EXTI_EMR1_EM31_Msk                      /*!< Event Mask on line 31 */
5034 
5035 /*******************  Bit definition for EXTI_IMR2 register  *******************/
5036 #define EXTI_IMR2_IM_Pos                    (0U)
5037 #define EXTI_IMR2_IM_Msk                    (0x003FFFFFUL << EXTI_IMR2_IM_Pos)      /*!< 0x003FFFFF */
5038 #define EXTI_IMR2_IM                        EXTI_IMR2_IM_Msk                        /*!< Interrupt Mask */
5039 #define EXTI_IMR2_IM32_Pos                  (0U)
5040 #define EXTI_IMR2_IM32_Msk                  (0x1UL << EXTI_IMR2_IM32_Pos)           /*!< 0x00000001 */
5041 #define EXTI_IMR2_IM32                      EXTI_IMR2_IM32_Msk                      /*!< Interrupt Mask on line 32 */
5042 #define EXTI_IMR2_IM33_Pos                  (1U)
5043 #define EXTI_IMR2_IM33_Msk                  (0x1UL << EXTI_IMR2_IM33_Pos)           /*!< 0x00000002 */
5044 #define EXTI_IMR2_IM33                      EXTI_IMR2_IM33_Msk                      /*!< Interrupt Mask on line 33 */
5045 #define EXTI_IMR2_IM34_Pos                  (2U)
5046 #define EXTI_IMR2_IM34_Msk                  (0x1UL << EXTI_IMR2_IM34_Pos)           /*!< 0x00000004 */
5047 #define EXTI_IMR2_IM34                      EXTI_IMR2_IM34_Msk                      /*!< Interrupt Mask on line 34 */
5048 #define EXTI_IMR2_IM35_Pos                  (3U)
5049 #define EXTI_IMR2_IM35_Msk                  (0x1UL << EXTI_IMR2_IM35_Pos)           /*!< 0x00000008 */
5050 #define EXTI_IMR2_IM35                      EXTI_IMR2_IM35_Msk                      /*!< Interrupt Mask on line 35 */
5051 #define EXTI_IMR2_IM36_Pos                  (4U)
5052 #define EXTI_IMR2_IM36_Msk                  (0x1UL << EXTI_IMR2_IM36_Pos)           /*!< 0x00000010 */
5053 #define EXTI_IMR2_IM36                      EXTI_IMR2_IM36_Msk                      /*!< Interrupt Mask on line 36 */
5054 #define EXTI_IMR2_IM37_Pos                  (5U)
5055 #define EXTI_IMR2_IM37_Msk                  (0x1UL << EXTI_IMR2_IM37_Pos)           /*!< 0x00000020 */
5056 #define EXTI_IMR2_IM37                      EXTI_IMR2_IM37_Msk                      /*!< Interrupt Mask on line 37 */
5057 #define EXTI_IMR2_IM38_Pos                  (6U)
5058 #define EXTI_IMR2_IM38_Msk                  (0x1UL << EXTI_IMR2_IM38_Pos)           /*!< 0x00000040 */
5059 #define EXTI_IMR2_IM38                      EXTI_IMR2_IM38_Msk                      /*!< Interrupt Mask on line 38 */
5060 #define EXTI_IMR2_IM39_Pos                  (7U)
5061 #define EXTI_IMR2_IM39_Msk                  (0x1UL << EXTI_IMR2_IM39_Pos)           /*!< 0x00000080 */
5062 #define EXTI_IMR2_IM39                      EXTI_IMR2_IM39_Msk                      /*!< Interrupt Mask on line 39 */
5063 #define EXTI_IMR2_IM40_Pos                  (8U)
5064 #define EXTI_IMR2_IM40_Msk                  (0x1UL << EXTI_IMR2_IM40_Pos)           /*!< 0x00000100 */
5065 #define EXTI_IMR2_IM40                      EXTI_IMR2_IM40_Msk                      /*!< Interrupt Mask on line 40 */
5066 #define EXTI_IMR2_IM41_Pos                  (9U)
5067 #define EXTI_IMR2_IM41_Msk                  (0x1UL << EXTI_IMR2_IM41_Pos)           /*!< 0x00000200 */
5068 #define EXTI_IMR2_IM41                      EXTI_IMR2_IM41_Msk                      /*!< Interrupt Mask on line 41 */
5069 #define EXTI_IMR2_IM42_Pos                  (10U)
5070 #define EXTI_IMR2_IM42_Msk                  (0x1UL << EXTI_IMR2_IM42_Pos)           /*!< 0x00000400 */
5071 #define EXTI_IMR2_IM42                      EXTI_IMR2_IM42_Msk                      /*!< Interrupt Mask on line 42 */
5072 #define EXTI_IMR2_IM43_Pos                  (11U)
5073 #define EXTI_IMR2_IM43_Msk                  (0x1UL << EXTI_IMR2_IM43_Pos)           /*!< 0x00000800 */
5074 #define EXTI_IMR2_IM43                      EXTI_IMR2_IM43_Msk                      /*!< Interrupt Mask on line 43 */
5075 #define EXTI_IMR2_IM44_Pos                  (12U)
5076 #define EXTI_IMR2_IM44_Msk                  (0x1UL << EXTI_IMR2_IM44_Pos)           /*!< 0x00001000 */
5077 #define EXTI_IMR2_IM44                      EXTI_IMR2_IM44_Msk                      /*!< Interrupt Mask on line 44 */
5078 #define EXTI_IMR2_IM46_Pos                  (14U)
5079 #define EXTI_IMR2_IM46_Msk                  (0x1UL << EXTI_IMR2_IM46_Pos)           /*!< 0x00004000 */
5080 #define EXTI_IMR2_IM46                      EXTI_IMR2_IM46_Msk                      /*!< Interrupt Mask on line 46 */
5081 #define EXTI_IMR2_IM47_Pos                  (15U)
5082 #define EXTI_IMR2_IM47_Msk                  (0x1UL << EXTI_IMR2_IM47_Pos)           /*!< 0x00008000 */
5083 #define EXTI_IMR2_IM47                      EXTI_IMR2_IM47_Msk                      /*!< Interrupt Mask on line 47 */
5084 #define EXTI_IMR2_IM48_Pos                  (16U)
5085 #define EXTI_IMR2_IM48_Msk                  (0x1UL << EXTI_IMR2_IM48_Pos)           /*!< 0x00010000 */
5086 #define EXTI_IMR2_IM48                      EXTI_IMR2_IM48_Msk                      /*!< Interrupt Mask on line 48 */
5087 #define EXTI_IMR2_IM49_Pos                  (17U)
5088 #define EXTI_IMR2_IM49_Msk                  (0x1UL << EXTI_IMR2_IM49_Pos)           /*!< 0x00020000 */
5089 #define EXTI_IMR2_IM49                      EXTI_IMR2_IM49_Msk                      /*!< Interrupt Mask on line 49 */
5090 #define EXTI_IMR2_IM50_Pos                  (18U)
5091 #define EXTI_IMR2_IM50_Msk                  (0x1UL << EXTI_IMR2_IM50_Pos)           /*!< 0x00040000 */
5092 #define EXTI_IMR2_IM50                      EXTI_IMR2_IM50_Msk                      /*!< Interrupt Mask on line 50 */
5093 #define EXTI_IMR2_IM51_Pos                  (19U)
5094 #define EXTI_IMR2_IM51_Msk                  (0x1UL << EXTI_IMR2_IM51_Pos)           /*!< 0x00080000 */
5095 #define EXTI_IMR2_IM51                      EXTI_IMR2_IM51_Msk                      /*!< Interrupt Mask on line 51 */
5096 #define EXTI_IMR2_IM52_Pos                  (20U)
5097 #define EXTI_IMR2_IM52_Msk                  (0x1UL << EXTI_IMR2_IM52_Pos)           /*!< 0x00100000 */
5098 #define EXTI_IMR2_IM52                      EXTI_IMR2_IM52_Msk                      /*!< Interrupt Mask on line 52 */
5099 #define EXTI_IMR2_IM53_Pos                  (21U)
5100 #define EXTI_IMR2_IM53_Msk                  (0x1UL << EXTI_IMR2_IM53_Pos)           /*!< 0x00200000 */
5101 #define EXTI_IMR2_IM53                      EXTI_IMR2_IM53_Msk                      /*!< Interrupt Mask on line 53 */
5102 #define EXTI_IMR2_IM54_Pos                  (22U)
5103 #define EXTI_IMR2_IM54_Msk                  (0x1UL << EXTI_IMR2_IM54_Pos)           /*!< 0x00400000 */
5104 #define EXTI_IMR2_IM54                      EXTI_IMR2_IM54_Msk                      /*!< Interrupt Mask on line 54 */
5105 #define EXTI_IMR2_IM55_Pos                  (23U)
5106 #define EXTI_IMR2_IM55_Msk                  (0x1UL << EXTI_IMR2_IM55_Pos)           /*!< 0x00800000 */
5107 #define EXTI_IMR2_IM55                      EXTI_IMR2_IM55_Msk                      /*!< Interrupt Mask on line 55 */
5108 #define EXTI_IMR2_IM56_Pos                  (24U)
5109 #define EXTI_IMR2_IM56_Msk                  (0x1UL << EXTI_IMR2_IM56_Pos)           /*!< 0x01000000 */
5110 #define EXTI_IMR2_IM56                      EXTI_IMR2_IM56_Msk                      /*!< Interrupt Mask on line 56 */
5111 #define EXTI_IMR2_IM57_Pos                  (25U)
5112 #define EXTI_IMR2_IM57_Msk                  (0x1UL << EXTI_IMR2_IM57_Pos)           /*!< 0x02000000 */
5113 #define EXTI_IMR2_IM57                      EXTI_IMR2_IM57_Msk                      /*!< Interrupt Mask on line 57 */
5114 
5115 
5116 /*******************  Bit definition for EXTI_EMR2 register  *******************/
5117 #define EXTI_EMR2_EM_Pos                    (0U)
5118 #define EXTI_EMR2_EM_Msk                    (0x03FFFFFFUL << EXTI_EMR2_EM_Pos)      /*!< 0x03FFFFFF */
5119 #define EXTI_EMR2_EM                        EXTI_EMR2_EM_Msk                        /*!< Event Mask */
5120 #define EXTI_EMR2_EM32_Pos                  (0U)
5121 #define EXTI_EMR2_EM32_Msk                  (0x1UL << EXTI_EMR2_EM32_Pos)           /*!< 0x00000001 */
5122 #define EXTI_EMR2_EM32                      EXTI_EMR2_EM32_Msk                      /*!< Event Mask on line 32*/
5123 #define EXTI_EMR2_EM33_Pos                  (1U)
5124 #define EXTI_EMR2_EM33_Msk                  (0x1UL << EXTI_EMR2_EM33_Pos)           /*!< 0x00000002 */
5125 #define EXTI_EMR2_EM33                      EXTI_EMR2_EM33_Msk                      /*!< Event Mask on line 33*/
5126 #define EXTI_EMR2_EM34_Pos                  (2U)
5127 #define EXTI_EMR2_EM34_Msk                  (0x1UL << EXTI_EMR2_EM34_Pos)           /*!< 0x00000004 */
5128 #define EXTI_EMR2_EM34                      EXTI_EMR2_EM34_Msk                      /*!< Event Mask on line 34*/
5129 #define EXTI_EMR2_EM35_Pos                  (3U)
5130 #define EXTI_EMR2_EM35_Msk                  (0x1UL << EXTI_EMR2_EM35_Pos)           /*!< 0x00000008 */
5131 #define EXTI_EMR2_EM35                      EXTI_EMR2_EM35_Msk                      /*!< Event Mask on line 35*/
5132 #define EXTI_EMR2_EM36_Pos                  (4U)
5133 #define EXTI_EMR2_EM36_Msk                  (0x1UL << EXTI_EMR2_EM36_Pos)           /*!< 0x00000010 */
5134 #define EXTI_EMR2_EM36                      EXTI_EMR2_EM36_Msk                      /*!< Event Mask on line 36*/
5135 #define EXTI_EMR2_EM37_Pos                  (5U)
5136 #define EXTI_EMR2_EM37_Msk                  (0x1UL << EXTI_EMR2_EM37_Pos)           /*!< 0x00000020 */
5137 #define EXTI_EMR2_EM37                      EXTI_EMR2_EM37_Msk                      /*!< Event Mask on line 37*/
5138 #define EXTI_EMR2_EM38_Pos                  (6U)
5139 #define EXTI_EMR2_EM38_Msk                  (0x1UL << EXTI_EMR2_EM38_Pos)           /*!< 0x00000040 */
5140 #define EXTI_EMR2_EM38                      EXTI_EMR2_EM38_Msk                      /*!< Event Mask on line 38*/
5141 #define EXTI_EMR2_EM39_Pos                  (7U)
5142 #define EXTI_EMR2_EM39_Msk                  (0x1UL << EXTI_EMR2_EM39_Pos)           /*!< 0x00000080 */
5143 #define EXTI_EMR2_EM39                      EXTI_EMR2_EM39_Msk                      /*!< Event Mask on line 39*/
5144 #define EXTI_EMR2_EM40_Pos                  (8U)
5145 #define EXTI_EMR2_EM40_Msk                  (0x1UL << EXTI_EMR2_EM40_Pos)           /*!< 0x00000100 */
5146 #define EXTI_EMR2_EM40                      EXTI_EMR2_EM40_Msk                      /*!< Event Mask on line 40*/
5147 #define EXTI_EMR2_EM41_Pos                  (9U)
5148 #define EXTI_EMR2_EM41_Msk                  (0x1UL << EXTI_EMR2_EM41_Pos)           /*!< 0x00000200 */
5149 #define EXTI_EMR2_EM41                      EXTI_EMR2_EM41_Msk                      /*!< Event Mask on line 41*/
5150 #define EXTI_EMR2_EM42_Pos                  (10U)
5151 #define EXTI_EMR2_EM42_Msk                  (0x1UL << EXTI_EMR2_EM42_Pos)           /*!< 0x00000400 */
5152 #define EXTI_EMR2_EM42                      EXTI_EMR2_EM42_Msk                      /*!< Event Mask on line 42 */
5153 #define EXTI_EMR2_EM43_Pos                  (11U)
5154 #define EXTI_EMR2_EM43_Msk                  (0x1UL << EXTI_EMR2_EM43_Pos)           /*!< 0x00000800 */
5155 #define EXTI_EMR2_EM43                      EXTI_EMR2_EM43_Msk                      /*!< Event Mask on line 43 */
5156 #define EXTI_EMR2_EM44_Pos                  (12U)
5157 #define EXTI_EMR2_EM44_Msk                  (0x1UL << EXTI_EMR2_EM44_Pos)           /*!< 0x00001000 */
5158 #define EXTI_EMR2_EM44                      EXTI_EMR2_EM44_Msk                      /*!< Event Mask on line 44 */
5159 #define EXTI_EMR2_EM46_Pos                  (14U)
5160 #define EXTI_EMR2_EM46_Msk                  (0x1UL << EXTI_EMR2_EM46_Pos)           /*!< 0x00004000 */
5161 #define EXTI_EMR2_EM46                      EXTI_EMR2_EM46_Msk                      /*!< Event Mask on line 46 */
5162 #define EXTI_EMR2_EM47_Pos                  (15U)
5163 #define EXTI_EMR2_EM47_Msk                  (0x1UL << EXTI_EMR2_EM47_Pos)           /*!< 0x00008000 */
5164 #define EXTI_EMR2_EM47                      EXTI_EMR2_EM47_Msk                      /*!< Event Mask on line 47 */
5165 #define EXTI_EMR2_EM48_Pos                  (16U)
5166 #define EXTI_EMR2_EM48_Msk                  (0x1UL << EXTI_EMR2_EM48_Pos)           /*!< 0x00010000 */
5167 #define EXTI_EMR2_EM48                      EXTI_EMR2_EM48_Msk                      /*!< Event Mask on line 48 */
5168 #define EXTI_EMR2_EM49_Pos                  (17U)
5169 #define EXTI_EMR2_EM49_Msk                  (0x1UL << EXTI_EMR2_EM49_Pos)           /*!< 0x00020000 */
5170 #define EXTI_EMR2_EM49                      EXTI_EMR2_EM49_Msk                      /*!< Event Mask on line 49 */
5171 #define EXTI_EMR2_EM50_Pos                  (18U)
5172 #define EXTI_EMR2_EM50_Msk                  (0x1UL << EXTI_EMR2_EM50_Pos)           /*!< 0x00040000 */
5173 #define EXTI_EMR2_EM50                      EXTI_EMR2_EM50_Msk                      /*!< Event Mask on line 50 */
5174 #define EXTI_EMR2_EM51_Pos                  (19U)
5175 #define EXTI_EMR2_EM51_Msk                  (0x1UL << EXTI_EMR2_EM51_Pos)           /*!< 0x00080000 */
5176 #define EXTI_EMR2_EM51                      EXTI_EMR2_EM51_Msk                      /*!< Event Mask on line 51 */
5177 #define EXTI_EMR2_EM52_Pos                  (20U)
5178 #define EXTI_EMR2_EM52_Msk                  (0x1UL << EXTI_EMR2_EM52_Pos)           /*!< 0x00100000 */
5179 #define EXTI_EMR2_EM52                      EXTI_EMR2_EM52_Msk                      /*!< Event Mask on line 52 */
5180 #define EXTI_EMR2_EM53_Pos                  (21U)
5181 #define EXTI_EMR2_EM53_Msk                  (0x1UL << EXTI_EMR2_EM53_Pos)           /*!< 0x00200000 */
5182 #define EXTI_EMR2_EM53                      EXTI_EMR2_EM53_Msk                      /*!< Event Mask on line 53 */
5183 #define EXTI_EMR2_EM54_Pos                  (22U)
5184 #define EXTI_EMR2_EM54_Msk                  (0x1UL << EXTI_EMR2_EM54_Pos)           /*!< 0x00400000 */
5185 #define EXTI_EMR2_EM54                      EXTI_EMR2_EM54_Msk                      /*!< Event Mask on line 54 */
5186 #define EXTI_EMR2_EM55_Pos                  (23U)
5187 #define EXTI_EMR2_EM55_Msk                  (0x1UL << EXTI_EMR2_EM55_Pos)           /*!< 0x00800000 */
5188 #define EXTI_EMR2_EM55                      EXTI_EMR2_EM55_Msk                      /*!< Event Mask on line 55 */
5189 #define EXTI_EMR2_EM56_Pos                  (24U)
5190 #define EXTI_EMR2_EM56_Msk                  (0x1UL << EXTI_EMR2_EM56_Pos)           /*!< 0x01000000 */
5191 #define EXTI_EMR2_EM56                      EXTI_EMR2_EM56_Msk                      /*!< Event Mask on line 56 */
5192 #define EXTI_EMR2_EM57_Pos                  (25U)
5193 #define EXTI_EMR2_EM57_Msk                  (0x1UL << EXTI_EMR2_EM57_Pos)           /*!< 0x02000000 */
5194 #define EXTI_EMR2_EM57                      EXTI_EMR2_EM57_Msk                      /*!< Event Mask on line 57 */
5195 
5196 /******************************************************************************/
5197 /*                                                                            */
5198 /*                 Flexible Datarate Controller Area Network                  */
5199 /*                                                                            */
5200 /******************************************************************************/
5201 /*!<FDCAN control and status registers */
5202 /*****************  Bit definition for FDCAN_CREL register  *******************/
5203 #define FDCAN_CREL_DAY_Pos                  (0U)
5204 #define FDCAN_CREL_DAY_Msk                  (0xFFUL << FDCAN_CREL_DAY_Pos)          /*!< 0x000000FF */
5205 #define FDCAN_CREL_DAY                      FDCAN_CREL_DAY_Msk                      /*!<Timestamp Day                           */
5206 #define FDCAN_CREL_MON_Pos                  (8U)
5207 #define FDCAN_CREL_MON_Msk                  (0xFFUL << FDCAN_CREL_MON_Pos)          /*!< 0x0000FF00 */
5208 #define FDCAN_CREL_MON                      FDCAN_CREL_MON_Msk                      /*!<Timestamp Month                         */
5209 #define FDCAN_CREL_YEAR_Pos                 (16U)
5210 #define FDCAN_CREL_YEAR_Msk                 (0xFUL << FDCAN_CREL_YEAR_Pos)          /*!< 0x000F0000 */
5211 #define FDCAN_CREL_YEAR                     FDCAN_CREL_YEAR_Msk                     /*!<Timestamp Year                          */
5212 #define FDCAN_CREL_SUBSTEP_Pos              (20U)
5213 #define FDCAN_CREL_SUBSTEP_Msk              (0xFUL << FDCAN_CREL_SUBSTEP_Pos)       /*!< 0x00F00000 */
5214 #define FDCAN_CREL_SUBSTEP                  FDCAN_CREL_SUBSTEP_Msk                  /*!<Sub-step of Core release                */
5215 #define FDCAN_CREL_STEP_Pos                 (24U)
5216 #define FDCAN_CREL_STEP_Msk                 (0xFUL << FDCAN_CREL_STEP_Pos)          /*!< 0x0F000000 */
5217 #define FDCAN_CREL_STEP                     FDCAN_CREL_STEP_Msk                     /*!<Step of Core release                    */
5218 #define FDCAN_CREL_REL_Pos                  (28U)
5219 #define FDCAN_CREL_REL_Msk                  (0xFUL << FDCAN_CREL_REL_Pos)           /*!< 0xF0000000 */
5220 #define FDCAN_CREL_REL                      FDCAN_CREL_REL_Msk                      /*!<Core release                            */
5221 
5222 /*****************  Bit definition for FDCAN_ENDN register  *******************/
5223 #define FDCAN_ENDN_ETV_Pos                  (0U)
5224 #define FDCAN_ENDN_ETV_Msk                  (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)    /*!< 0xFFFFFFFF */
5225 #define FDCAN_ENDN_ETV                      FDCAN_ENDN_ETV_Msk                      /*!<Endianness Test Value                   */
5226 
5227 /*****************  Bit definition for FDCAN_DBTP register  *******************/
5228 #define FDCAN_DBTP_DSJW_Pos                 (0U)
5229 #define FDCAN_DBTP_DSJW_Msk                 (0xFUL << FDCAN_DBTP_DSJW_Pos)          /*!< 0x0000000F */
5230 #define FDCAN_DBTP_DSJW                     FDCAN_DBTP_DSJW_Msk                     /*!<Synchronization Jump Width              */
5231 #define FDCAN_DBTP_DTSEG2_Pos               (4U)
5232 #define FDCAN_DBTP_DTSEG2_Msk               (0xFUL << FDCAN_DBTP_DTSEG2_Pos)        /*!< 0x000000F0 */
5233 #define FDCAN_DBTP_DTSEG2                   FDCAN_DBTP_DTSEG2_Msk                   /*!<Data time segment after sample point    */
5234 #define FDCAN_DBTP_DTSEG1_Pos               (8U)
5235 #define FDCAN_DBTP_DTSEG1_Msk               (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)       /*!< 0x00001F00 */
5236 #define FDCAN_DBTP_DTSEG1                   FDCAN_DBTP_DTSEG1_Msk                   /*!<Data time segment before sample point   */
5237 #define FDCAN_DBTP_DBRP_Pos                 (16U)
5238 #define FDCAN_DBTP_DBRP_Msk                 (0x1FUL << FDCAN_DBTP_DBRP_Pos)         /*!< 0x001F0000 */
5239 #define FDCAN_DBTP_DBRP                     FDCAN_DBTP_DBRP_Msk                     /*!<Data BIt Rate Prescaler                 */
5240 #define FDCAN_DBTP_TDC_Pos                  (23U)
5241 #define FDCAN_DBTP_TDC_Msk                  (0x1UL << FDCAN_DBTP_TDC_Pos)           /*!< 0x00800000 */
5242 #define FDCAN_DBTP_TDC                      FDCAN_DBTP_TDC_Msk                      /*!<Transceiver Delay Compensation          */
5243 
5244 /*****************  Bit definition for FDCAN_TEST register  *******************/
5245 #define FDCAN_TEST_LBCK_Pos                 (4U)
5246 #define FDCAN_TEST_LBCK_Msk                 (0x1UL << FDCAN_TEST_LBCK_Pos)          /*!< 0x00000010 */
5247 #define FDCAN_TEST_LBCK                     FDCAN_TEST_LBCK_Msk                     /*!<Loop Back mode                           */
5248 #define FDCAN_TEST_TX_Pos                   (5U)
5249 #define FDCAN_TEST_TX_Msk                   (0x3UL << FDCAN_TEST_TX_Pos)            /*!< 0x00000060 */
5250 #define FDCAN_TEST_TX                       FDCAN_TEST_TX_Msk                       /*!<Control of Transmit Pin                  */
5251 #define FDCAN_TEST_RX_Pos                   (7U)
5252 #define FDCAN_TEST_RX_Msk                   (0x1UL << FDCAN_TEST_RX_Pos)            /*!< 0x00000080 */
5253 #define FDCAN_TEST_RX                       FDCAN_TEST_RX_Msk                       /*!<Receive Pin                              */
5254 
5255 /*****************  Bit definition for FDCAN_RWD register  ********************/
5256 #define FDCAN_RWD_WDC_Pos                   (0U)
5257 #define FDCAN_RWD_WDC_Msk                   (0xFFUL << FDCAN_RWD_WDC_Pos)           /*!< 0x000000FF */
5258 #define FDCAN_RWD_WDC                       FDCAN_RWD_WDC_Msk                       /*!<Watchdog configuration                   */
5259 #define FDCAN_RWD_WDV_Pos                   (8U)
5260 #define FDCAN_RWD_WDV_Msk                   (0xFFUL << FDCAN_RWD_WDV_Pos)           /*!< 0x0000FF00 */
5261 #define FDCAN_RWD_WDV                       FDCAN_RWD_WDV_Msk                       /*!<Watchdog value                           */
5262 
5263 /*****************  Bit definition for FDCAN_CCCR register  ********************/
5264 #define FDCAN_CCCR_INIT_Pos                 (0U)
5265 #define FDCAN_CCCR_INIT_Msk                 (0x1UL << FDCAN_CCCR_INIT_Pos)          /*!< 0x00000001 */
5266 #define FDCAN_CCCR_INIT                     FDCAN_CCCR_INIT_Msk                     /*!<Initialization                           */
5267 #define FDCAN_CCCR_CCE_Pos                  (1U)
5268 #define FDCAN_CCCR_CCE_Msk                  (0x1UL << FDCAN_CCCR_CCE_Pos)           /*!< 0x00000002 */
5269 #define FDCAN_CCCR_CCE                      FDCAN_CCCR_CCE_Msk                      /*!<Configuration Change Enable              */
5270 #define FDCAN_CCCR_ASM_Pos                  (2U)
5271 #define FDCAN_CCCR_ASM_Msk                  (0x1UL << FDCAN_CCCR_ASM_Pos)           /*!< 0x00000004 */
5272 #define FDCAN_CCCR_ASM                      FDCAN_CCCR_ASM_Msk                      /*!<ASM Restricted Operation Mode            */
5273 #define FDCAN_CCCR_CSA_Pos                  (3U)
5274 #define FDCAN_CCCR_CSA_Msk                  (0x1UL << FDCAN_CCCR_CSA_Pos)           /*!< 0x00000008 */
5275 #define FDCAN_CCCR_CSA                      FDCAN_CCCR_CSA_Msk                      /*!<Clock Stop Acknowledge                   */
5276 #define FDCAN_CCCR_CSR_Pos                  (4U)
5277 #define FDCAN_CCCR_CSR_Msk                  (0x1UL << FDCAN_CCCR_CSR_Pos)           /*!< 0x00000010 */
5278 #define FDCAN_CCCR_CSR                      FDCAN_CCCR_CSR_Msk                      /*!<Clock Stop Request                       */
5279 #define FDCAN_CCCR_MON_Pos                  (5U)
5280 #define FDCAN_CCCR_MON_Msk                  (0x1UL << FDCAN_CCCR_MON_Pos)           /*!< 0x00000020 */
5281 #define FDCAN_CCCR_MON                      FDCAN_CCCR_MON_Msk                      /*!<Bus Monitoring Mode                      */
5282 #define FDCAN_CCCR_DAR_Pos                  (6U)
5283 #define FDCAN_CCCR_DAR_Msk                  (0x1UL << FDCAN_CCCR_DAR_Pos)           /*!< 0x00000040 */
5284 #define FDCAN_CCCR_DAR                      FDCAN_CCCR_DAR_Msk                      /*!<Disable Automatic Retransmission         */
5285 #define FDCAN_CCCR_TEST_Pos                 (7U)
5286 #define FDCAN_CCCR_TEST_Msk                 (0x1UL << FDCAN_CCCR_TEST_Pos)          /*!< 0x00000080 */
5287 #define FDCAN_CCCR_TEST                     FDCAN_CCCR_TEST_Msk                     /*!<Test Mode Enable                         */
5288 #define FDCAN_CCCR_FDOE_Pos                 (8U)
5289 #define FDCAN_CCCR_FDOE_Msk                 (0x1UL << FDCAN_CCCR_FDOE_Pos)          /*!< 0x00000100 */
5290 #define FDCAN_CCCR_FDOE                     FDCAN_CCCR_FDOE_Msk                     /*!<FD Operation Enable                      */
5291 #define FDCAN_CCCR_BRSE_Pos                 (9U)
5292 #define FDCAN_CCCR_BRSE_Msk                 (0x1UL << FDCAN_CCCR_BRSE_Pos)          /*!< 0x00000200 */
5293 #define FDCAN_CCCR_BRSE                     FDCAN_CCCR_BRSE_Msk                     /*!<FDCAN Bit Rate Switching                 */
5294 #define FDCAN_CCCR_PXHD_Pos                 (12U)
5295 #define FDCAN_CCCR_PXHD_Msk                 (0x1UL << FDCAN_CCCR_PXHD_Pos)          /*!< 0x00001000 */
5296 #define FDCAN_CCCR_PXHD                     FDCAN_CCCR_PXHD_Msk                     /*!<Protocol Exception Handling Disable      */
5297 #define FDCAN_CCCR_EFBI_Pos                 (13U)
5298 #define FDCAN_CCCR_EFBI_Msk                 (0x1UL << FDCAN_CCCR_EFBI_Pos)          /*!< 0x00002000 */
5299 #define FDCAN_CCCR_EFBI                     FDCAN_CCCR_EFBI_Msk                     /*!<Edge Filtering during Bus Integration    */
5300 #define FDCAN_CCCR_TXP_Pos                  (14U)
5301 #define FDCAN_CCCR_TXP_Msk                  (0x1UL << FDCAN_CCCR_TXP_Pos)           /*!< 0x00004000 */
5302 #define FDCAN_CCCR_TXP                      FDCAN_CCCR_TXP_Msk                      /*!<Two CAN bit times Pause                  */
5303 #define FDCAN_CCCR_NISO_Pos                 (15U)
5304 #define FDCAN_CCCR_NISO_Msk                 (0x1UL << FDCAN_CCCR_NISO_Pos)          /*!< 0x00008000 */
5305 #define FDCAN_CCCR_NISO                     FDCAN_CCCR_NISO_Msk                     /*!<Non ISO Operation                        */
5306 
5307 /*****************  Bit definition for FDCAN_NBTP register  ******************* */
5308 #define FDCAN_NBTP_NTSEG2_Pos               (0U)
5309 #define FDCAN_NBTP_NTSEG2_Msk               (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)       /*!< 0x0000007F */
5310 #define FDCAN_NBTP_NTSEG2                   FDCAN_NBTP_NTSEG2_Msk                   /*!<Nominal Time segment after sample point  */
5311 #define FDCAN_NBTP_NTSEG1_Pos               (8U)
5312 #define FDCAN_NBTP_NTSEG1_Msk               (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)       /*!< 0x0000FF00 */
5313 #define FDCAN_NBTP_NTSEG1                   FDCAN_NBTP_NTSEG1_Msk                   /*!<Nominal Time segment before sample point */
5314 #define FDCAN_NBTP_NBRP_Pos                 (16U)
5315 #define FDCAN_NBTP_NBRP_Msk                 (0x1FFUL << FDCAN_NBTP_NBRP_Pos)        /*!< 0x01FF0000 */
5316 #define FDCAN_NBTP_NBRP                     FDCAN_NBTP_NBRP_Msk                     /*!<Bit Rate Prescaler                       */
5317 #define FDCAN_NBTP_NSJW_Pos                 (25U)
5318 #define FDCAN_NBTP_NSJW_Msk                 (0x7FUL << FDCAN_NBTP_NSJW_Pos)         /*!< 0xFE000000 */
5319 #define FDCAN_NBTP_NSJW                     FDCAN_NBTP_NSJW_Msk                     /*!<Nominal (Re)Synchronization Jump Width   */
5320 
5321 /*****************  Bit definition for FDCAN_TSCC register  ********************/
5322 #define FDCAN_TSCC_TSS_Pos                  (0U)
5323 #define FDCAN_TSCC_TSS_Msk                  (0x3UL << FDCAN_TSCC_TSS_Pos)           /*!< 0x00000003 */
5324 #define FDCAN_TSCC_TSS                      FDCAN_TSCC_TSS_Msk                      /*!<Timestamp Select                         */
5325 #define FDCAN_TSCC_TCP_Pos                  (16U)
5326 #define FDCAN_TSCC_TCP_Msk                  (0xFUL << FDCAN_TSCC_TCP_Pos)           /*!< 0x000F0000 */
5327 #define FDCAN_TSCC_TCP                      FDCAN_TSCC_TCP_Msk                      /*!<Timestamp Counter Prescaler              */
5328 
5329 /*****************  Bit definition for FDCAN_TSCV register  ********************/
5330 #define FDCAN_TSCV_TSC_Pos                  (0U)
5331 #define FDCAN_TSCV_TSC_Msk                  (0xFFFFUL << FDCAN_TSCV_TSC_Pos)        /*!< 0x0000FFFF */
5332 #define FDCAN_TSCV_TSC                      FDCAN_TSCV_TSC_Msk                      /*!<Timestamp Counter                        */
5333 
5334 /*****************  Bit definition for FDCAN_TOCC register  ********************/
5335 #define FDCAN_TOCC_ETOC_Pos                 (0U)
5336 #define FDCAN_TOCC_ETOC_Msk                 (0x1UL << FDCAN_TOCC_ETOC_Pos)          /*!< 0x00000001 */
5337 #define FDCAN_TOCC_ETOC                     FDCAN_TOCC_ETOC_Msk                     /*!<Enable Timeout Counter                   */
5338 #define FDCAN_TOCC_TOS_Pos                  (1U)
5339 #define FDCAN_TOCC_TOS_Msk                  (0x3UL << FDCAN_TOCC_TOS_Pos)           /*!< 0x00000006 */
5340 #define FDCAN_TOCC_TOS                      FDCAN_TOCC_TOS_Msk                      /*!<Timeout Select                           */
5341 #define FDCAN_TOCC_TOP_Pos                  (16U)
5342 #define FDCAN_TOCC_TOP_Msk                  (0xFFFFUL << FDCAN_TOCC_TOP_Pos)        /*!< 0xFFFF0000 */
5343 #define FDCAN_TOCC_TOP                      FDCAN_TOCC_TOP_Msk                      /*!<Timeout Period                           */
5344 
5345 /*****************  Bit definition for FDCAN_TOCV register  ******************* */
5346 #define FDCAN_TOCV_TOC_Pos                  (0U)
5347 #define FDCAN_TOCV_TOC_Msk                  (0xFFFFUL << FDCAN_TOCV_TOC_Pos)        /*!< 0x0000FFFF */
5348 #define FDCAN_TOCV_TOC                      FDCAN_TOCV_TOC_Msk                      /*!<Timeout Counter                          */
5349 
5350 /*****************  Bit definition for FDCAN_ECR register  ******************** */
5351 #define FDCAN_ECR_TEC_Pos                   (0U)
5352 #define FDCAN_ECR_TEC_Msk                   (0xFFUL << FDCAN_ECR_TEC_Pos)           /*!< 0x000000FF */
5353 #define FDCAN_ECR_TEC                       FDCAN_ECR_TEC_Msk                       /*!<Transmit Error Counter                   */
5354 #define FDCAN_ECR_REC_Pos                   (8U)
5355 #define FDCAN_ECR_REC_Msk                   (0x7FUL << FDCAN_ECR_REC_Pos)           /*!< 0x00007F00 */
5356 #define FDCAN_ECR_REC                       FDCAN_ECR_REC_Msk                       /*!<Receive Error Counter                    */
5357 #define FDCAN_ECR_RP_Pos                    (15U)
5358 #define FDCAN_ECR_RP_Msk                    (0x1UL << FDCAN_ECR_RP_Pos)             /*!< 0x00008000 */
5359 #define FDCAN_ECR_RP                        FDCAN_ECR_RP_Msk                        /*!<Receive Error Passive                    */
5360 #define FDCAN_ECR_CEL_Pos                   (16U)
5361 #define FDCAN_ECR_CEL_Msk                   (0xFFUL << FDCAN_ECR_CEL_Pos)           /*!< 0x00FF0000 */
5362 #define FDCAN_ECR_CEL                       FDCAN_ECR_CEL_Msk                       /*!<CAN Error Logging                        */
5363 
5364 /*****************  Bit definition for FDCAN_PSR register  ******************** */
5365 #define FDCAN_PSR_LEC_Pos                   (0U)
5366 #define FDCAN_PSR_LEC_Msk                   (0x7UL << FDCAN_PSR_LEC_Pos)            /*!< 0x00000007 */
5367 #define FDCAN_PSR_LEC                       FDCAN_PSR_LEC_Msk                       /*!<Last Error Code                          */
5368 #define FDCAN_PSR_ACT_Pos                   (3U)
5369 #define FDCAN_PSR_ACT_Msk                   (0x3UL << FDCAN_PSR_ACT_Pos)            /*!< 0x00000018 */
5370 #define FDCAN_PSR_ACT                       FDCAN_PSR_ACT_Msk                       /*!<Activity                                 */
5371 #define FDCAN_PSR_EP_Pos                    (5U)
5372 #define FDCAN_PSR_EP_Msk                    (0x1UL << FDCAN_PSR_EP_Pos)             /*!< 0x00000020 */
5373 #define FDCAN_PSR_EP                        FDCAN_PSR_EP_Msk                        /*!<Error Passive                            */
5374 #define FDCAN_PSR_EW_Pos                    (6U)
5375 #define FDCAN_PSR_EW_Msk                    (0x1UL << FDCAN_PSR_EW_Pos)             /*!< 0x00000040 */
5376 #define FDCAN_PSR_EW                        FDCAN_PSR_EW_Msk                        /*!<Warning Status                           */
5377 #define FDCAN_PSR_BO_Pos                    (7U)
5378 #define FDCAN_PSR_BO_Msk                    (0x1UL << FDCAN_PSR_BO_Pos)             /*!< 0x00000080 */
5379 #define FDCAN_PSR_BO                        FDCAN_PSR_BO_Msk                        /*!<Bus_Off Status                           */
5380 #define FDCAN_PSR_DLEC_Pos                  (8U)
5381 #define FDCAN_PSR_DLEC_Msk                  (0x7UL << FDCAN_PSR_DLEC_Pos)           /*!< 0x00000700 */
5382 #define FDCAN_PSR_DLEC                      FDCAN_PSR_DLEC_Msk                      /*!<Data Last Error Code                     */
5383 #define FDCAN_PSR_RESI_Pos                  (11U)
5384 #define FDCAN_PSR_RESI_Msk                  (0x1UL << FDCAN_PSR_RESI_Pos)           /*!< 0x00000800 */
5385 #define FDCAN_PSR_RESI                      FDCAN_PSR_RESI_Msk                      /*!<ESI flag of last received FDCAN Message  */
5386 #define FDCAN_PSR_RBRS_Pos                  (12U)
5387 #define FDCAN_PSR_RBRS_Msk                  (0x1UL << FDCAN_PSR_RBRS_Pos)           /*!< 0x00001000 */
5388 #define FDCAN_PSR_RBRS                      FDCAN_PSR_RBRS_Msk                      /*!<BRS flag of last received FDCAN Message  */
5389 #define FDCAN_PSR_REDL_Pos                  (13U)
5390 #define FDCAN_PSR_REDL_Msk                  (0x1UL << FDCAN_PSR_REDL_Pos)           /*!< 0x00002000 */
5391 #define FDCAN_PSR_REDL                      FDCAN_PSR_REDL_Msk                      /*!<Received FDCAN Message                   */
5392 #define FDCAN_PSR_PXE_Pos                   (14U)
5393 #define FDCAN_PSR_PXE_Msk                   (0x1UL << FDCAN_PSR_PXE_Pos)            /*!< 0x00004000 */
5394 #define FDCAN_PSR_PXE                       FDCAN_PSR_PXE_Msk                       /*!<Protocol Exception Event                 */
5395 #define FDCAN_PSR_TDCV_Pos                  (16U)
5396 #define FDCAN_PSR_TDCV_Msk                  (0x7FUL << FDCAN_PSR_TDCV_Pos)          /*!< 0x007F0000 */
5397 #define FDCAN_PSR_TDCV                      FDCAN_PSR_TDCV_Msk                      /*!<Transmitter Delay Compensation Value     */
5398 
5399 /*****************  Bit definition for FDCAN_TDCR register  ******************* */
5400 #define FDCAN_TDCR_TDCF_Pos                 (0U)
5401 #define FDCAN_TDCR_TDCF_Msk                 (0x7FUL << FDCAN_TDCR_TDCF_Pos)         /*!< 0x0000007F */
5402 #define FDCAN_TDCR_TDCF                     FDCAN_TDCR_TDCF_Msk                     /*!<Transmitter Delay Compensation Filter    */
5403 #define FDCAN_TDCR_TDCO_Pos                 (8U)
5404 #define FDCAN_TDCR_TDCO_Msk                 (0x7FUL << FDCAN_TDCR_TDCO_Pos)         /*!< 0x00007F00 */
5405 #define FDCAN_TDCR_TDCO                     FDCAN_TDCR_TDCO_Msk                     /*!<Transmitter Delay Compensation Offset    */
5406 
5407 /*****************  Bit definition for FDCAN_IR register  ********************* */
5408 #define FDCAN_IR_RF0N_Pos                   (0U)
5409 #define FDCAN_IR_RF0N_Msk                   (0x1UL << FDCAN_IR_RF0N_Pos)            /*!< 0x00000001 */
5410 #define FDCAN_IR_RF0N                       FDCAN_IR_RF0N_Msk                       /*!<Rx FIFO 0 New Message                    */
5411 #define FDCAN_IR_RF0F_Pos                   (1U)
5412 #define FDCAN_IR_RF0F_Msk                   (0x1UL << FDCAN_IR_RF0F_Pos)            /*!< 0x00000002 */
5413 #define FDCAN_IR_RF0F                       FDCAN_IR_RF0F_Msk                       /*!<Rx FIFO 0 Full                           */
5414 #define FDCAN_IR_RF0L_Pos                   (2U)
5415 #define FDCAN_IR_RF0L_Msk                   (0x1UL << FDCAN_IR_RF0L_Pos)            /*!< 0x00000004 */
5416 #define FDCAN_IR_RF0L                       FDCAN_IR_RF0L_Msk                       /*!<Rx FIFO 0 Message Lost                   */
5417 #define FDCAN_IR_RF1N_Pos                   (3U)
5418 #define FDCAN_IR_RF1N_Msk                   (0x1UL << FDCAN_IR_RF1N_Pos)            /*!< 0x00000008 */
5419 #define FDCAN_IR_RF1N                       FDCAN_IR_RF1N_Msk                       /*!<Rx FIFO 1 New Message                    */
5420 #define FDCAN_IR_RF1F_Pos                   (4U)
5421 #define FDCAN_IR_RF1F_Msk                   (0x1UL << FDCAN_IR_RF1F_Pos)            /*!< 0x00000010 */
5422 #define FDCAN_IR_RF1F                       FDCAN_IR_RF1F_Msk                       /*!<Rx FIFO 1 Full                           */
5423 #define FDCAN_IR_RF1L_Pos                   (5U)
5424 #define FDCAN_IR_RF1L_Msk                   (0x1UL << FDCAN_IR_RF1L_Pos)            /*!< 0x00000020 */
5425 #define FDCAN_IR_RF1L                       FDCAN_IR_RF1L_Msk                       /*!<Rx FIFO 1 Message Lost                   */
5426 #define FDCAN_IR_HPM_Pos                    (6U)
5427 #define FDCAN_IR_HPM_Msk                    (0x1UL << FDCAN_IR_HPM_Pos)             /*!< 0x00000040 */
5428 #define FDCAN_IR_HPM                        FDCAN_IR_HPM_Msk                        /*!<High Priority Message                    */
5429 #define FDCAN_IR_TC_Pos                     (7U)
5430 #define FDCAN_IR_TC_Msk                     (0x1UL << FDCAN_IR_TC_Pos)              /*!< 0x00000080 */
5431 #define FDCAN_IR_TC                         FDCAN_IR_TC_Msk                         /*!<Transmission Completed                   */
5432 #define FDCAN_IR_TCF_Pos                    (8U)
5433 #define FDCAN_IR_TCF_Msk                    (0x1UL << FDCAN_IR_TCF_Pos)             /*!< 0x00000100 */
5434 #define FDCAN_IR_TCF                        FDCAN_IR_TCF_Msk                        /*!<Transmission Cancellation Finished       */
5435 #define FDCAN_IR_TFE_Pos                    (9U)
5436 #define FDCAN_IR_TFE_Msk                    (0x1UL << FDCAN_IR_TFE_Pos)             /*!< 0x00000200 */
5437 #define FDCAN_IR_TFE                        FDCAN_IR_TFE_Msk                        /*!<Tx FIFO Empty                            */
5438 #define FDCAN_IR_TEFN_Pos                   (10U)
5439 #define FDCAN_IR_TEFN_Msk                   (0x1UL << FDCAN_IR_TEFN_Pos)            /*!< 0x00000400 */
5440 #define FDCAN_IR_TEFN                       FDCAN_IR_TEFN_Msk                       /*!<Tx Event FIFO New Entry                  */
5441 #define FDCAN_IR_TEFF_Pos                   (11U)
5442 #define FDCAN_IR_TEFF_Msk                   (0x1UL << FDCAN_IR_TEFF_Pos)            /*!< 0x00000800 */
5443 #define FDCAN_IR_TEFF                       FDCAN_IR_TEFF_Msk                       /*!<Tx Event FIFO Full                       */
5444 #define FDCAN_IR_TEFL_Pos                   (12U)
5445 #define FDCAN_IR_TEFL_Msk                   (0x1UL << FDCAN_IR_TEFL_Pos)            /*!< 0x00001000 */
5446 #define FDCAN_IR_TEFL                       FDCAN_IR_TEFL_Msk                       /*!<Tx Event FIFO Element Lost               */
5447 #define FDCAN_IR_TSW_Pos                    (13U)
5448 #define FDCAN_IR_TSW_Msk                    (0x1UL << FDCAN_IR_TSW_Pos)             /*!< 0x00002000 */
5449 #define FDCAN_IR_TSW                        FDCAN_IR_TSW_Msk                        /*!<Timestamp Wraparound                     */
5450 #define FDCAN_IR_MRAF_Pos                   (14U)
5451 #define FDCAN_IR_MRAF_Msk                   (0x1UL << FDCAN_IR_MRAF_Pos)            /*!< 0x00004000 */
5452 #define FDCAN_IR_MRAF                       FDCAN_IR_MRAF_Msk                       /*!<Message RAM Access Failure               */
5453 #define FDCAN_IR_TOO_Pos                    (15U)
5454 #define FDCAN_IR_TOO_Msk                    (0x1UL << FDCAN_IR_TOO_Pos)             /*!< 0x00008000 */
5455 #define FDCAN_IR_TOO                        FDCAN_IR_TOO_Msk                        /*!<Timeout Occurred                         */
5456 #define FDCAN_IR_ELO_Pos                    (16U)
5457 #define FDCAN_IR_ELO_Msk                    (0x1UL << FDCAN_IR_ELO_Pos)             /*!< 0x00010000 */
5458 #define FDCAN_IR_ELO                        FDCAN_IR_ELO_Msk                        /*!<Error Logging Overflow                   */
5459 #define FDCAN_IR_EP_Pos                     (17U)
5460 #define FDCAN_IR_EP_Msk                     (0x1UL << FDCAN_IR_EP_Pos)              /*!< 0x00020000 */
5461 #define FDCAN_IR_EP                         FDCAN_IR_EP_Msk                         /*!<Error Passive                            */
5462 #define FDCAN_IR_EW_Pos                     (18U)
5463 #define FDCAN_IR_EW_Msk                     (0x1UL << FDCAN_IR_EW_Pos)              /*!< 0x00040000 */
5464 #define FDCAN_IR_EW                         FDCAN_IR_EW_Msk                         /*!<Warning Status                           */
5465 #define FDCAN_IR_BO_Pos                     (19U)
5466 #define FDCAN_IR_BO_Msk                     (0x1UL << FDCAN_IR_BO_Pos)              /*!< 0x00080000 */
5467 #define FDCAN_IR_BO                         FDCAN_IR_BO_Msk                         /*!<Bus_Off Status                           */
5468 #define FDCAN_IR_WDI_Pos                    (20U)
5469 #define FDCAN_IR_WDI_Msk                    (0x1UL << FDCAN_IR_WDI_Pos)             /*!< 0x00100000 */
5470 #define FDCAN_IR_WDI                        FDCAN_IR_WDI_Msk                        /*!<Watchdog Interrupt                       */
5471 #define FDCAN_IR_PEA_Pos                    (21U)
5472 #define FDCAN_IR_PEA_Msk                    (0x1UL << FDCAN_IR_PEA_Pos)             /*!< 0x00200000 */
5473 #define FDCAN_IR_PEA                        FDCAN_IR_PEA_Msk                        /*!<Protocol Error in Arbitration Phase      */
5474 #define FDCAN_IR_PED_Pos                    (22U)
5475 #define FDCAN_IR_PED_Msk                    (0x1UL << FDCAN_IR_PED_Pos)             /*!< 0x00400000 */
5476 #define FDCAN_IR_PED                        FDCAN_IR_PED_Msk                        /*!<Protocol Error in Data Phase             */
5477 #define FDCAN_IR_ARA_Pos                    (23U)
5478 #define FDCAN_IR_ARA_Msk                    (0x1UL << FDCAN_IR_ARA_Pos)             /*!< 0x00800000 */
5479 #define FDCAN_IR_ARA                        FDCAN_IR_ARA_Msk                        /*!<Access to Reserved Address               */
5480 
5481 /*****************  Bit definition for FDCAN_IE register  ********************* */
5482 #define FDCAN_IE_RF0NE_Pos                  (0U)
5483 #define FDCAN_IE_RF0NE_Msk                  (0x1UL << FDCAN_IE_RF0NE_Pos)           /*!< 0x00000001 */
5484 #define FDCAN_IE_RF0NE                      FDCAN_IE_RF0NE_Msk                      /*!<Rx FIFO 0 New Message Enable             */
5485 #define FDCAN_IE_RF0FE_Pos                  (1U)
5486 #define FDCAN_IE_RF0FE_Msk                  (0x1UL << FDCAN_IE_RF0FE_Pos)           /*!< 0x00000002 */
5487 #define FDCAN_IE_RF0FE                      FDCAN_IE_RF0FE_Msk                      /*!<Rx FIFO 0 Full Enable                    */
5488 #define FDCAN_IE_RF0LE_Pos                  (2U)
5489 #define FDCAN_IE_RF0LE_Msk                  (0x1UL << FDCAN_IE_RF0LE_Pos)           /*!< 0x00000004 */
5490 #define FDCAN_IE_RF0LE                      FDCAN_IE_RF0LE_Msk                      /*!<Rx FIFO 0 Message Lost Enable            */
5491 #define FDCAN_IE_RF1NE_Pos                  (3U)
5492 #define FDCAN_IE_RF1NE_Msk                  (0x1UL << FDCAN_IE_RF1NE_Pos)           /*!< 0x00000008 */
5493 #define FDCAN_IE_RF1NE                      FDCAN_IE_RF1NE_Msk                      /*!<Rx FIFO 1 New Message Enable             */
5494 #define FDCAN_IE_RF1FE_Pos                  (4U)
5495 #define FDCAN_IE_RF1FE_Msk                  (0x1UL << FDCAN_IE_RF1FE_Pos)           /*!< 0x00000010 */
5496 #define FDCAN_IE_RF1FE                      FDCAN_IE_RF1FE_Msk                      /*!<Rx FIFO 1 Full Enable                    */
5497 #define FDCAN_IE_RF1LE_Pos                  (5U)
5498 #define FDCAN_IE_RF1LE_Msk                  (0x1UL << FDCAN_IE_RF1LE_Pos)           /*!< 0x00000020 */
5499 #define FDCAN_IE_RF1LE                      FDCAN_IE_RF1LE_Msk                      /*!<Rx FIFO 1 Message Lost Enable            */
5500 #define FDCAN_IE_HPME_Pos                   (6U)
5501 #define FDCAN_IE_HPME_Msk                   (0x1UL << FDCAN_IE_HPME_Pos)            /*!< 0x00000040 */
5502 #define FDCAN_IE_HPME                       FDCAN_IE_HPME_Msk                       /*!<High Priority Message Enable             */
5503 #define FDCAN_IE_TCE_Pos                    (7U)
5504 #define FDCAN_IE_TCE_Msk                    (0x1UL << FDCAN_IE_TCE_Pos)             /*!< 0x00000080 */
5505 #define FDCAN_IE_TCE                        FDCAN_IE_TCE_Msk                        /*!<Transmission Completed Enable            */
5506 #define FDCAN_IE_TCFE_Pos                   (8U)
5507 #define FDCAN_IE_TCFE_Msk                   (0x1UL << FDCAN_IE_TCFE_Pos)            /*!< 0x00000100 */
5508 #define FDCAN_IE_TCFE                       FDCAN_IE_TCFE_Msk                       /*!<Transmission Cancellation Finished Enable*/
5509 #define FDCAN_IE_TFEE_Pos                   (9U)
5510 #define FDCAN_IE_TFEE_Msk                   (0x1UL << FDCAN_IE_TFEE_Pos)            /*!< 0x00000200 */
5511 #define FDCAN_IE_TFEE                       FDCAN_IE_TFEE_Msk                       /*!<Tx FIFO Empty Enable                     */
5512 #define FDCAN_IE_TEFNE_Pos                  (10U)
5513 #define FDCAN_IE_TEFNE_Msk                  (0x1UL << FDCAN_IE_TEFNE_Pos)           /*!< 0x00000400 */
5514 #define FDCAN_IE_TEFNE                      FDCAN_IE_TEFNE_Msk                      /*!<Tx Event FIFO New Entry Enable           */
5515 #define FDCAN_IE_TEFFE_Pos                  (11U)
5516 #define FDCAN_IE_TEFFE_Msk                  (0x1UL << FDCAN_IE_TEFFE_Pos)           /*!< 0x00000800 */
5517 #define FDCAN_IE_TEFFE                      FDCAN_IE_TEFFE_Msk                      /*!<Tx Event FIFO Full Enable                */
5518 #define FDCAN_IE_TEFLE_Pos                  (12U)
5519 #define FDCAN_IE_TEFLE_Msk                  (0x1UL << FDCAN_IE_TEFLE_Pos)           /*!< 0x00001000 */
5520 #define FDCAN_IE_TEFLE                      FDCAN_IE_TEFLE_Msk                      /*!<Tx Event FIFO Element Lost Enable        */
5521 #define FDCAN_IE_TSWE_Pos                   (13U)
5522 #define FDCAN_IE_TSWE_Msk                   (0x1UL << FDCAN_IE_TSWE_Pos)            /*!< 0x00002000 */
5523 #define FDCAN_IE_TSWE                       FDCAN_IE_TSWE_Msk                       /*!<Timestamp Wraparound Enable              */
5524 #define FDCAN_IE_MRAFE_Pos                  (14U)
5525 #define FDCAN_IE_MRAFE_Msk                  (0x1UL << FDCAN_IE_MRAFE_Pos)           /*!< 0x00004000 */
5526 #define FDCAN_IE_MRAFE                      FDCAN_IE_MRAFE_Msk                      /*!<Message RAM Access Failure Enable        */
5527 #define FDCAN_IE_TOOE_Pos                   (15U)
5528 #define FDCAN_IE_TOOE_Msk                   (0x1UL << FDCAN_IE_TOOE_Pos)            /*!< 0x00008000 */
5529 #define FDCAN_IE_TOOE                       FDCAN_IE_TOOE_Msk                       /*!<Timeout Occurred Enable                  */
5530 #define FDCAN_IE_ELOE_Pos                   (16U)
5531 #define FDCAN_IE_ELOE_Msk                   (0x1UL << FDCAN_IE_ELOE_Pos)            /*!< 0x00010000 */
5532 #define FDCAN_IE_ELOE                       FDCAN_IE_ELOE_Msk                       /*!<Error Logging Overflow Enable            */
5533 #define FDCAN_IE_EPE_Pos                    (17U)
5534 #define FDCAN_IE_EPE_Msk                    (0x1UL << FDCAN_IE_EPE_Pos)             /*!< 0x00020000 */
5535 #define FDCAN_IE_EPE                        FDCAN_IE_EPE_Msk                        /*!<Error Passive Enable                     */
5536 #define FDCAN_IE_EWE_Pos                    (18U)
5537 #define FDCAN_IE_EWE_Msk                    (0x1UL << FDCAN_IE_EWE_Pos)             /*!< 0x00040000 */
5538 #define FDCAN_IE_EWE                        FDCAN_IE_EWE_Msk                        /*!<Warning Status Enable                    */
5539 #define FDCAN_IE_BOE_Pos                    (19U)
5540 #define FDCAN_IE_BOE_Msk                    (0x1UL << FDCAN_IE_BOE_Pos)             /*!< 0x00080000 */
5541 #define FDCAN_IE_BOE                        FDCAN_IE_BOE_Msk                        /*!<Bus_Off Status Enable                    */
5542 #define FDCAN_IE_WDIE_Pos                   (20U)
5543 #define FDCAN_IE_WDIE_Msk                   (0x1UL << FDCAN_IE_WDIE_Pos)            /*!< 0x00100000 */
5544 #define FDCAN_IE_WDIE                       FDCAN_IE_WDIE_Msk                       /*!<Watchdog Interrupt Enable                */
5545 #define FDCAN_IE_PEAE_Pos                   (21U)
5546 #define FDCAN_IE_PEAE_Msk                   (0x1UL << FDCAN_IE_PEAE_Pos)            /*!< 0x00200000 */
5547 #define FDCAN_IE_PEAE                       FDCAN_IE_PEAE_Msk                       /*!<Protocol Error in Arbitration Phase Enable*/
5548 #define FDCAN_IE_PEDE_Pos                   (22U)
5549 #define FDCAN_IE_PEDE_Msk                   (0x1UL << FDCAN_IE_PEDE_Pos)            /*!< 0x00400000 */
5550 #define FDCAN_IE_PEDE                       FDCAN_IE_PEDE_Msk                       /*!<Protocol Error in Data Phase Enable      */
5551 #define FDCAN_IE_ARAE_Pos                   (23U)
5552 #define FDCAN_IE_ARAE_Msk                   (0x1UL << FDCAN_IE_ARAE_Pos)            /*!< 0x00800000 */
5553 #define FDCAN_IE_ARAE                       FDCAN_IE_ARAE_Msk                       /*!<Access to Reserved Address Enable        */
5554 
5555 /*****************  Bit definition for FDCAN_ILS register  ******************** **/
5556 #define FDCAN_ILS_RXFIFO0_Pos               (0U)
5557 #define FDCAN_ILS_RXFIFO0_Msk               (0x1UL << FDCAN_ILS_RXFIFO0_Pos)        /*!< 0x00000001 */
5558 #define FDCAN_ILS_RXFIFO0                   FDCAN_ILS_RXFIFO0_Msk                   /*!<Rx FIFO 0 Message Lost
5559                                                                                         Rx FIFO 0 is Full
5560                                                                                         Rx FIFO 0 Has New Message                */
5561 #define FDCAN_ILS_RXFIFO1_Pos               (1U)
5562 #define FDCAN_ILS_RXFIFO1_Msk               (0x1UL << FDCAN_ILS_RXFIFO1_Pos)        /*!< 0x00000002 */
5563 #define FDCAN_ILS_RXFIFO1                   FDCAN_ILS_RXFIFO1_Msk                   /*!<Rx FIFO 1 Message Lost
5564                                                                                         Rx FIFO 1 is Full
5565                                                                                         Rx FIFO 1 Has New Message                */
5566 #define FDCAN_ILS_SMSG_Pos                  (2U)
5567 #define FDCAN_ILS_SMSG_Msk                  (0x1UL << FDCAN_ILS_SMSG_Pos)           /*!< 0x00000004 */
5568 #define FDCAN_ILS_SMSG                      FDCAN_ILS_SMSG_Msk                      /*!<Transmission Cancellation Finished
5569                                                                                         Transmission Completed
5570                                                                                         High Priority Message                    */
5571 #define FDCAN_ILS_TFERR_Pos                 (3U)
5572 #define FDCAN_ILS_TFERR_Msk                 (0x1UL << FDCAN_ILS_TFERR_Pos)          /*!< 0x00000008 */
5573 #define FDCAN_ILS_TFERR                     FDCAN_ILS_TFERR_Msk                     /*!<Tx Event FIFO Element Lost
5574                                                                                         Tx Event FIFO Full
5575                                                                                         Tx Event FIFO New Entry
5576                                                                                         Tx FIFO Empty Interrupt Line             */
5577 #define FDCAN_ILS_MISC_Pos                  (4U)
5578 #define FDCAN_ILS_MISC_Msk                  (0x1UL << FDCAN_ILS_MISC_Pos)           /*!< 0x00000010 */
5579 #define FDCAN_ILS_MISC                      FDCAN_ILS_MISC_Msk                      /*!<Timeout Occurred
5580                                                                                         Message RAM Access Failure
5581                                                                                         Timestamp Wraparound                    */
5582 #define FDCAN_ILS_BERR_Pos                  (5U)
5583 #define FDCAN_ILS_BERR_Msk                  (0x1UL << FDCAN_ILS_BERR_Pos)           /*!< 0x00000020 */
5584 #define FDCAN_ILS_BERR                      FDCAN_ILS_BERR_Msk                      /*!<Error Passive
5585                                                                                         Error Logging Overflow                   */
5586 #define FDCAN_ILS_PERR_Pos                  (6U)
5587 #define FDCAN_ILS_PERR_Msk                  (0x1UL << FDCAN_ILS_PERR_Pos)           /*!< 0x00000040 */
5588 #define FDCAN_ILS_PERR                      FDCAN_ILS_PERR_Msk                      /*!<Access to Reserved Address Line
5589                                                                                         Protocol Error in Data Phase Line
5590                                                                                         Protocol Error in Arbitration Phase Line
5591                                                                                         Watchdog Interrupt Line
5592                                                                                         Bus_Off Status
5593                                                                                         Warning Status                           */
5594 
5595 /*****************  Bit definition for FDCAN_ILE register  ******************** **/
5596 #define FDCAN_ILE_EINT0_Pos                 (0U)
5597 #define FDCAN_ILE_EINT0_Msk                 (0x1UL << FDCAN_ILE_EINT0_Pos)          /*!< 0x00000001 */
5598 #define FDCAN_ILE_EINT0                     FDCAN_ILE_EINT0_Msk                     /*!<Enable Interrupt Line 0                  */
5599 #define FDCAN_ILE_EINT1_Pos                 (1U)
5600 #define FDCAN_ILE_EINT1_Msk                 (0x1UL << FDCAN_ILE_EINT1_Pos)          /*!< 0x00000002 */
5601 #define FDCAN_ILE_EINT1                     FDCAN_ILE_EINT1_Msk                     /*!<Enable Interrupt Line 1                  */
5602 
5603 /*****************  Bit definition for FDCAN_RXGFC register  ****************** **/
5604 #define FDCAN_RXGFC_RRFE_Pos                (0U)
5605 #define FDCAN_RXGFC_RRFE_Msk                (0x1UL << FDCAN_RXGFC_RRFE_Pos)         /*!< 0x00000001 */
5606 #define FDCAN_RXGFC_RRFE                    FDCAN_RXGFC_RRFE_Msk                    /*!<Reject Remote Frames Extended            */
5607 #define FDCAN_RXGFC_RRFS_Pos                (1U)
5608 #define FDCAN_RXGFC_RRFS_Msk                (0x1UL << FDCAN_RXGFC_RRFS_Pos)         /*!< 0x00000002 */
5609 #define FDCAN_RXGFC_RRFS                    FDCAN_RXGFC_RRFS_Msk                    /*!<Reject Remote Frames Standard            */
5610 #define FDCAN_RXGFC_ANFE_Pos                (2U)
5611 #define FDCAN_RXGFC_ANFE_Msk                (0x3UL << FDCAN_RXGFC_ANFE_Pos)         /*!< 0x0000000C */
5612 #define FDCAN_RXGFC_ANFE                    FDCAN_RXGFC_ANFE_Msk                    /*!<Accept Non-matching Frames Extended      */
5613 #define FDCAN_RXGFC_ANFS_Pos                (4U)
5614 #define FDCAN_RXGFC_ANFS_Msk                (0x3UL << FDCAN_RXGFC_ANFS_Pos)         /*!< 0x00000030 */
5615 #define FDCAN_RXGFC_ANFS                    FDCAN_RXGFC_ANFS_Msk                    /*!<Accept Non-matching Frames Standard      */
5616 #define FDCAN_RXGFC_F1OM_Pos                (8U)
5617 #define FDCAN_RXGFC_F1OM_Msk                (0x1UL << FDCAN_RXGFC_F1OM_Pos)         /*!< 0x00000100 */
5618 #define FDCAN_RXGFC_F1OM                    FDCAN_RXGFC_F1OM_Msk                    /*!<FIFO 1 operation mode                    */
5619 #define FDCAN_RXGFC_F0OM_Pos                (9U)
5620 #define FDCAN_RXGFC_F0OM_Msk                (0x1UL << FDCAN_RXGFC_F0OM_Pos)         /*!< 0x00000200 */
5621 #define FDCAN_RXGFC_F0OM                    FDCAN_RXGFC_F0OM_Msk                    /*!<FIFO 0 operation mode                    */
5622 #define FDCAN_RXGFC_LSS_Pos                 (16U)
5623 #define FDCAN_RXGFC_LSS_Msk                 (0x1FUL << FDCAN_RXGFC_LSS_Pos)         /*!< 0x001F0000 */
5624 #define FDCAN_RXGFC_LSS                     FDCAN_RXGFC_LSS_Msk                     /*!<List Size Standard                       */
5625 #define FDCAN_RXGFC_LSE_Pos                 (24U)
5626 #define FDCAN_RXGFC_LSE_Msk                 (0xFUL << FDCAN_RXGFC_LSE_Pos)          /*!< 0x0F000000 */
5627 #define FDCAN_RXGFC_LSE                     FDCAN_RXGFC_LSE_Msk                     /*!<List Size Extended                       */
5628 
5629 /*****************  Bit definition for FDCAN_XIDAM register  ****************** **/
5630 #define FDCAN_XIDAM_EIDM_Pos                (0U)
5631 #define FDCAN_XIDAM_EIDM_Msk                (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)  /*!< 0x1FFFFFFF */
5632 #define FDCAN_XIDAM_EIDM                    FDCAN_XIDAM_EIDM_Msk                    /*!<Extended ID Mask                         */
5633 
5634 /*****************  Bit definition for FDCAN_HPMS register  ******************* **/
5635 #define FDCAN_HPMS_BIDX_Pos                 (0U)
5636 #define FDCAN_HPMS_BIDX_Msk                 (0x7UL << FDCAN_HPMS_BIDX_Pos)          /*!< 0x00000007 */
5637 #define FDCAN_HPMS_BIDX                     FDCAN_HPMS_BIDX_Msk                     /*!<Buffer Index                             */
5638 #define FDCAN_HPMS_MSI_Pos                  (6U)
5639 #define FDCAN_HPMS_MSI_Msk                  (0x3UL << FDCAN_HPMS_MSI_Pos)           /*!< 0x000000C0 */
5640 #define FDCAN_HPMS_MSI                      FDCAN_HPMS_MSI_Msk                      /*!<Message Storage Indicator                */
5641 #define FDCAN_HPMS_FIDX_Pos                 (8U)
5642 #define FDCAN_HPMS_FIDX_Msk                 (0x1FUL << FDCAN_HPMS_FIDX_Pos)         /*!< 0x00001F00 */
5643 #define FDCAN_HPMS_FIDX                     FDCAN_HPMS_FIDX_Msk                     /*!<Filter Index                             */
5644 #define FDCAN_HPMS_FLST_Pos                 (15U)
5645 #define FDCAN_HPMS_FLST_Msk                 (0x1UL << FDCAN_HPMS_FLST_Pos)          /*!< 0x00008000 */
5646 #define FDCAN_HPMS_FLST                     FDCAN_HPMS_FLST_Msk                     /*!<Filter List                              */
5647 
5648 /*****************  Bit definition for FDCAN_RXF0S register  ****************** **/
5649 #define FDCAN_RXF0S_F0FL_Pos                (0U)
5650 #define FDCAN_RXF0S_F0FL_Msk                (0xFUL << FDCAN_RXF0S_F0FL_Pos)         /*!< 0x0000000F */
5651 #define FDCAN_RXF0S_F0FL                    FDCAN_RXF0S_F0FL_Msk                    /*!<Rx FIFO 0 Fill Level                     */
5652 #define FDCAN_RXF0S_F0GI_Pos                (8U)
5653 #define FDCAN_RXF0S_F0GI_Msk                (0x3UL << FDCAN_RXF0S_F0GI_Pos)         /*!< 0x00000300 */
5654 #define FDCAN_RXF0S_F0GI                    FDCAN_RXF0S_F0GI_Msk                    /*!<Rx FIFO 0 Get Index                      */
5655 #define FDCAN_RXF0S_F0PI_Pos                (16U)
5656 #define FDCAN_RXF0S_F0PI_Msk                (0x3UL << FDCAN_RXF0S_F0PI_Pos)         /*!< 0x00030000 */
5657 #define FDCAN_RXF0S_F0PI                    FDCAN_RXF0S_F0PI_Msk                    /*!<Rx FIFO 0 Put Index                      */
5658 #define FDCAN_RXF0S_F0F_Pos                 (24U)
5659 #define FDCAN_RXF0S_F0F_Msk                 (0x1UL << FDCAN_RXF0S_F0F_Pos)          /*!< 0x01000000 */
5660 #define FDCAN_RXF0S_F0F                     FDCAN_RXF0S_F0F_Msk                     /*!<Rx FIFO 0 Full                           */
5661 #define FDCAN_RXF0S_RF0L_Pos                (25U)
5662 #define FDCAN_RXF0S_RF0L_Msk                (0x1UL << FDCAN_RXF0S_RF0L_Pos)         /*!< 0x02000000 */
5663 #define FDCAN_RXF0S_RF0L                    FDCAN_RXF0S_RF0L_Msk                    /*!<Rx FIFO 0 Message Lost                   */
5664 
5665 /*****************  Bit definition for FDCAN_RXF0A register  ****************** **/
5666 #define FDCAN_RXF0A_F0AI_Pos                (0U)
5667 #define FDCAN_RXF0A_F0AI_Msk                (0x7UL << FDCAN_RXF0A_F0AI_Pos)         /*!< 0x00000007 */
5668 #define FDCAN_RXF0A_F0AI                    FDCAN_RXF0A_F0AI_Msk                    /*!<Rx FIFO 0 Acknowledge Index              */
5669 
5670 /*****************  Bit definition for FDCAN_RXF1S register  ****************** **/
5671 #define FDCAN_RXF1S_F1FL_Pos                (0U)
5672 #define FDCAN_RXF1S_F1FL_Msk                (0xFUL << FDCAN_RXF1S_F1FL_Pos)         /*!< 0x0000000F */
5673 #define FDCAN_RXF1S_F1FL                    FDCAN_RXF1S_F1FL_Msk                    /*!<Rx FIFO 1 Fill Level                     */
5674 #define FDCAN_RXF1S_F1GI_Pos                (8U)
5675 #define FDCAN_RXF1S_F1GI_Msk                (0x3UL << FDCAN_RXF1S_F1GI_Pos)         /*!< 0x00000300 */
5676 #define FDCAN_RXF1S_F1GI                    FDCAN_RXF1S_F1GI_Msk                    /*!<Rx FIFO 1 Get Index                      */
5677 #define FDCAN_RXF1S_F1PI_Pos                (16U)
5678 #define FDCAN_RXF1S_F1PI_Msk                (0x3UL << FDCAN_RXF1S_F1PI_Pos)         /*!< 0x00030000 */
5679 #define FDCAN_RXF1S_F1PI                    FDCAN_RXF1S_F1PI_Msk                    /*!<Rx FIFO 1 Put Index                      */
5680 #define FDCAN_RXF1S_F1F_Pos                 (24U)
5681 #define FDCAN_RXF1S_F1F_Msk                 (0x1UL << FDCAN_RXF1S_F1F_Pos)          /*!< 0x01000000 */
5682 #define FDCAN_RXF1S_F1F                     FDCAN_RXF1S_F1F_Msk                     /*!<Rx FIFO 1 Full                           */
5683 #define FDCAN_RXF1S_RF1L_Pos                (25U)
5684 #define FDCAN_RXF1S_RF1L_Msk                (0x1UL << FDCAN_RXF1S_RF1L_Pos)         /*!< 0x02000000 */
5685 #define FDCAN_RXF1S_RF1L                    FDCAN_RXF1S_RF1L_Msk                    /*!<Rx FIFO 1 Message Lost                   */
5686 
5687 /*****************  Bit definition for FDCAN_RXF1A register  ****************** **/
5688 #define FDCAN_RXF1A_F1AI_Pos                (0U)
5689 #define FDCAN_RXF1A_F1AI_Msk                (0x7UL << FDCAN_RXF1A_F1AI_Pos)         /*!< 0x00000007 */
5690 #define FDCAN_RXF1A_F1AI                    FDCAN_RXF1A_F1AI_Msk                    /*!<Rx FIFO 1 Acknowledge Index              */
5691 
5692 /*****************  Bit definition for FDCAN_TXBC register  ******************* **/
5693 #define FDCAN_TXBC_TFQM_Pos                 (24U)
5694 #define FDCAN_TXBC_TFQM_Msk                 (0x1UL << FDCAN_TXBC_TFQM_Pos)          /*!< 0x01000000 */
5695 #define FDCAN_TXBC_TFQM                     FDCAN_TXBC_TFQM_Msk                     /*!<Tx FIFO/Queue Mode                       */
5696 
5697 /*****************  Bit definition for FDCAN_TXFQS register  ****************** ***/
5698 #define FDCAN_TXFQS_TFFL_Pos                (0U)
5699 #define FDCAN_TXFQS_TFFL_Msk                (0x7UL << FDCAN_TXFQS_TFFL_Pos)         /*!< 0x00000007 */
5700 #define FDCAN_TXFQS_TFFL                    FDCAN_TXFQS_TFFL_Msk                    /*!<Tx FIFO Free Level                       */
5701 #define FDCAN_TXFQS_TFGI_Pos                (8U)
5702 #define FDCAN_TXFQS_TFGI_Msk                (0x3UL << FDCAN_TXFQS_TFGI_Pos)         /*!< 0x00000300 */
5703 #define FDCAN_TXFQS_TFGI                    FDCAN_TXFQS_TFGI_Msk                    /*!<Tx FIFO Get Index                        */
5704 #define FDCAN_TXFQS_TFQPI_Pos               (16U)
5705 #define FDCAN_TXFQS_TFQPI_Msk               (0x3UL << FDCAN_TXFQS_TFQPI_Pos)        /*!< 0x00030000 */
5706 #define FDCAN_TXFQS_TFQPI                   FDCAN_TXFQS_TFQPI_Msk                   /*!<Tx FIFO/Queue Put Index                  */
5707 #define FDCAN_TXFQS_TFQF_Pos                (21U)
5708 #define FDCAN_TXFQS_TFQF_Msk                (0x1UL << FDCAN_TXFQS_TFQF_Pos)         /*!< 0x00200000 */
5709 #define FDCAN_TXFQS_TFQF                    FDCAN_TXFQS_TFQF_Msk                    /*!<Tx FIFO/Queue Full                       */
5710 
5711 /*****************  Bit definition for FDCAN_TXBRP register  ****************** ***/
5712 #define FDCAN_TXBRP_TRP_Pos                 (0U)
5713 #define FDCAN_TXBRP_TRP_Msk                 (0x7UL << FDCAN_TXBRP_TRP_Pos)          /*!< 0x00000007 */
5714 #define FDCAN_TXBRP_TRP                     FDCAN_TXBRP_TRP_Msk                     /*!<Transmission Request Pending             */
5715 
5716 /*****************  Bit definition for FDCAN_TXBAR register  ****************** ***/
5717 #define FDCAN_TXBAR_AR_Pos                  (0U)
5718 #define FDCAN_TXBAR_AR_Msk                  (0x7UL << FDCAN_TXBAR_AR_Pos)           /*!< 0x00000007 */
5719 #define FDCAN_TXBAR_AR                      FDCAN_TXBAR_AR_Msk                      /*!<Add Request                              */
5720 
5721 /*****************  Bit definition for FDCAN_TXBCR register  ****************** ***/
5722 #define FDCAN_TXBCR_CR_Pos                  (0U)
5723 #define FDCAN_TXBCR_CR_Msk                  (0x7UL << FDCAN_TXBCR_CR_Pos)           /*!< 0x00000007 */
5724 #define FDCAN_TXBCR_CR                      FDCAN_TXBCR_CR_Msk                      /*!<Cancellation Request                     */
5725 
5726 /*****************  Bit definition for FDCAN_TXBTO register  ****************** ***/
5727 #define FDCAN_TXBTO_TO_Pos                  (0U)
5728 #define FDCAN_TXBTO_TO_Msk                  (0x7UL << FDCAN_TXBTO_TO_Pos)           /*!< 0x00000007 */
5729 #define FDCAN_TXBTO_TO                      FDCAN_TXBTO_TO_Msk                      /*!<Transmission Occurred                    */
5730 
5731 /*****************  Bit definition for FDCAN_TXBCF register  ****************** ***/
5732 #define FDCAN_TXBCF_CF_Pos                  (0U)
5733 #define FDCAN_TXBCF_CF_Msk                  (0x7UL << FDCAN_TXBCF_CF_Pos)           /*!< 0x00000007 */
5734 #define FDCAN_TXBCF_CF                      FDCAN_TXBCF_CF_Msk                      /*!<Cancellation Finished                    */
5735 
5736 /*****************  Bit definition for FDCAN_TXBTIE register  ***************** ***/
5737 #define FDCAN_TXBTIE_TIE_Pos                (0U)
5738 #define FDCAN_TXBTIE_TIE_Msk                (0x7UL << FDCAN_TXBTIE_TIE_Pos)         /*!< 0x00000007 */
5739 #define FDCAN_TXBTIE_TIE                    FDCAN_TXBTIE_TIE_Msk                    /*!<Transmission Interrupt Enable            */
5740 
5741 /*****************  Bit definition for FDCAN_ TXBCIE register  **************** ***/
5742 #define FDCAN_TXBCIE_CFIE_Pos               (0U)
5743 #define FDCAN_TXBCIE_CFIE_Msk               (0x7UL << FDCAN_TXBCIE_CFIE_Pos)        /*!< 0x00000007 */
5744 #define FDCAN_TXBCIE_CFIE                   FDCAN_TXBCIE_CFIE_Msk                   /*!<Cancellation Finished Interrupt Enable   */
5745 
5746 /*****************  Bit definition for FDCAN_TXEFS register  ****************** ***/
5747 #define FDCAN_TXEFS_EFFL_Pos                (0U)
5748 #define FDCAN_TXEFS_EFFL_Msk                (0x7UL << FDCAN_TXEFS_EFFL_Pos)         /*!< 0x00000007 */
5749 #define FDCAN_TXEFS_EFFL                    FDCAN_TXEFS_EFFL_Msk                    /*!<Event FIFO Fill Level                    */
5750 #define FDCAN_TXEFS_EFGI_Pos                (8U)
5751 #define FDCAN_TXEFS_EFGI_Msk                (0x3UL << FDCAN_TXEFS_EFGI_Pos)         /*!< 0x00000300 */
5752 #define FDCAN_TXEFS_EFGI                    FDCAN_TXEFS_EFGI_Msk                    /*!<Event FIFO Get Index                     */
5753 #define FDCAN_TXEFS_EFPI_Pos                (16U)
5754 #define FDCAN_TXEFS_EFPI_Msk                (0x3UL << FDCAN_TXEFS_EFPI_Pos)         /*!< 0x00030000 */
5755 #define FDCAN_TXEFS_EFPI                    FDCAN_TXEFS_EFPI_Msk                    /*!<Event FIFO Put Index                     */
5756 #define FDCAN_TXEFS_EFF_Pos                 (24U)
5757 #define FDCAN_TXEFS_EFF_Msk                 (0x1UL << FDCAN_TXEFS_EFF_Pos)          /*!< 0x01000000 */
5758 #define FDCAN_TXEFS_EFF                     FDCAN_TXEFS_EFF_Msk                     /*!<Event FIFO Full                          */
5759 #define FDCAN_TXEFS_TEFL_Pos                (25U)
5760 #define FDCAN_TXEFS_TEFL_Msk                (0x1UL << FDCAN_TXEFS_TEFL_Pos)         /*!< 0x02000000 */
5761 #define FDCAN_TXEFS_TEFL                    FDCAN_TXEFS_TEFL_Msk                    /*!<Tx Event FIFO Element Lost               */
5762 
5763 /*****************  Bit definition for FDCAN_TXEFA register  ****************** ***/
5764 #define FDCAN_TXEFA_EFAI_Pos                (0U)
5765 #define FDCAN_TXEFA_EFAI_Msk                (0x3UL << FDCAN_TXEFA_EFAI_Pos)         /*!< 0x00000003 */
5766 #define FDCAN_TXEFA_EFAI                    FDCAN_TXEFA_EFAI_Msk                    /*!<Event FIFO Acknowledge Index             */
5767 
5768 /*!<FDCAN config registers */
5769 /*****************  Bit definition for FDCAN_CKDIV register  ****************** ***/
5770 #define FDCAN_CKDIV_PDIV_Pos                (0U)
5771 #define FDCAN_CKDIV_PDIV_Msk                (0xFUL << FDCAN_CKDIV_PDIV_Pos)         /*!< 0x0000000F */
5772 #define FDCAN_CKDIV_PDIV                    FDCAN_CKDIV_PDIV_Msk                    /*!<Input Clock Divider                      */
5773 /******************************************************************************/
5774 /*                                                                            */
5775 /*                                    FLASH                                   */
5776 /*                                                                            */
5777 /******************************************************************************/
5778 #define FLASH_LATENCY_DEFAULT               FLASH_ACR_LATENCY_3WS                   /* FLASH Three Latency cycle */
5779 #define FLASH_BLOCKBASED_NB_REG             (1U)                                    /*!< 1 Block-based registers for each Flash bank */
5780 #define FLASH_SIZE_DEFAULT                  (0x20000U)                              /*!< FLASH Size */
5781 #define FLASH_SECTOR_NB                     (8U)                                    /*!< Flash Sector number */
5782 #define FLASH_SIZE                          ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \
5783                                             ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \
5784                                             (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U)))
5785 #define FLASH_BANK_SIZE                     (FLASH_SIZE >> 1U)                      /*!< FLASH Bank Size */
5786 #define FLASH_SECTOR_SIZE                   0x2000U                                 /*!< Flash Sector Size: 8 KB */
5787 
5788 /*******************  Bits definition for FLASH_ACR register  *****************/
5789 #define FLASH_ACR_LATENCY_Pos               (0U)
5790 #define FLASH_ACR_LATENCY_Msk               (0xFUL << FLASH_ACR_LATENCY_Pos)        /*!< 0x0000000F */
5791 #define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk                   /*!< Latency    */
5792 #define FLASH_ACR_LATENCY_0WS               (0x00000000U)
5793 #define FLASH_ACR_LATENCY_1WS               (0x00000001U)
5794 #define FLASH_ACR_LATENCY_2WS               (0x00000002U)
5795 #define FLASH_ACR_LATENCY_3WS               (0x00000003U)
5796 #define FLASH_ACR_LATENCY_4WS               (0x00000004U)
5797 #define FLASH_ACR_LATENCY_5WS               (0x00000005U)
5798 #define FLASH_ACR_LATENCY_6WS               (0x00000006U)
5799 #define FLASH_ACR_LATENCY_7WS               (0x00000007U)
5800 #define FLASH_ACR_LATENCY_8WS               (0x00000008U)
5801 #define FLASH_ACR_LATENCY_9WS               (0x00000009U)
5802 #define FLASH_ACR_LATENCY_10WS              (0x0000000AU)
5803 #define FLASH_ACR_LATENCY_11WS              (0x0000000BU)
5804 #define FLASH_ACR_LATENCY_12WS              (0x0000000CU)
5805 #define FLASH_ACR_LATENCY_13WS              (0x0000000DU)
5806 #define FLASH_ACR_LATENCY_14WS              (0x0000000EU)
5807 #define FLASH_ACR_LATENCY_15WS              (0x0000000FU)
5808 #define FLASH_ACR_WRHIGHFREQ_Pos            (4U)
5809 #define FLASH_ACR_WRHIGHFREQ_Msk            (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)     /*!< 0x00000030 */
5810 #define FLASH_ACR_WRHIGHFREQ                FLASH_ACR_WRHIGHFREQ_Msk                /*!< Flash signal delay */
5811 #define FLASH_ACR_WRHIGHFREQ_0              (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)     /*!< 0x00000010 */
5812 #define FLASH_ACR_WRHIGHFREQ_1              (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)     /*!< 0x00000020 */
5813 #define FLASH_ACR_PRFTEN_Pos                (8U)
5814 #define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)         /*!< 0x00000100 */
5815 #define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk                    /*!< Prefetch enable */
5816 
5817 /*******************  Bits definition for FLASH_OPSR register  ***************/
5818 #define FLASH_OPSR_ADDR_OP_Pos              (0U)
5819 #define FLASH_OPSR_ADDR_OP_Msk              (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos)   /*!< 0x000FFFFF */
5820 #define FLASH_OPSR_ADDR_OP                  FLASH_OPSR_ADDR_OP_Msk                  /*!< Interrupted operation address */
5821 #define FLASH_OPSR_BK_OP_Pos                (22U)
5822 #define FLASH_OPSR_BK_OP_Msk                (0x1UL << FLASH_OPSR_BK_OP_Pos)         /*!< 0x00400000 */
5823 #define FLASH_OPSR_BK_OP                    FLASH_OPSR_BK_OP_Msk                    /*!< Interrupted operation bank */
5824 #define FLASH_OPSR_SYSF_OP_Pos              (23U)
5825 #define FLASH_OPSR_SYSF_OP_Msk              (0x1UL << FLASH_OPSR_SYSF_OP_Pos)       /*!< 0x00800000 */
5826 #define FLASH_OPSR_SYSF_OP                  FLASH_OPSR_SYSF_OP_Msk                  /*!< Operation in System Flash interrupted */
5827 #define FLASH_OPSR_OTP_OP_Pos               (24U)
5828 #define FLASH_OPSR_OTP_OP_Msk               (0x1UL << FLASH_OPSR_OTP_OP_Pos)        /*!< 0x01000000 */
5829 #define FLASH_OPSR_OTP_OP                   FLASH_OPSR_OTP_OP_Msk                   /*!< Operation in OTP area interrupted */
5830 #define FLASH_OPSR_CODE_OP_Pos              (29U)
5831 #define FLASH_OPSR_CODE_OP_Msk              (0x7UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0xE0000000 */
5832 #define FLASH_OPSR_CODE_OP                  FLASH_OPSR_CODE_OP_Msk                  /*!< Flash memory operation code */
5833 #define FLASH_OPSR_CODE_OP_0                (0x1UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x20000000 */
5834 #define FLASH_OPSR_CODE_OP_1                (0x2UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x40000000 */
5835 #define FLASH_OPSR_CODE_OP_2                (0x4UL << FLASH_OPSR_CODE_OP_Pos)       /*!< 0x80000000 */
5836 
5837 /*******************  Bits definition for FLASH_OPTCR register  *******************/
5838 #define FLASH_OPTCR_OPTLOCK_Pos             (0U)
5839 #define FLASH_OPTCR_OPTLOCK_Msk             (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)      /*!< 0x00000001 */
5840 #define FLASH_OPTCR_OPTLOCK                 FLASH_OPTCR_OPTLOCK_Msk                 /*!< FLASH_OPTCR lock option configuration bit */
5841 #define FLASH_OPTCR_OPTSTART_Pos            (1U)
5842 #define FLASH_OPTCR_OPTSTART_Msk            (0x1UL << FLASH_OPTCR_OPTSTART_Pos)     /*!< 0x00000002 */
5843 #define FLASH_OPTCR_OPTSTART                FLASH_OPTCR_OPTSTART_Msk                /*!< Option byte start change option configuration bit */
5844 #define FLASH_OPTCR_SWAP_BANK_Pos           (31U)
5845 #define FLASH_OPTCR_SWAP_BANK_Msk           (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos)    /*!< 0x80000000 */
5846 #define FLASH_OPTCR_SWAP_BANK               FLASH_OPTCR_SWAP_BANK_Msk               /*!< Bank swapping option configuration bit */
5847 
5848 /*******************  Bits definition for FLASH_SR register  ***********************/
5849 #define FLASH_SR_BSY_Pos                    (0U)
5850 #define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)             /*!< 0x00000001 */
5851 #define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                        /*!< Busy flag */
5852 #define FLASH_SR_WBNE_Pos                   (1U)
5853 #define FLASH_SR_WBNE_Msk                   (0x1UL << FLASH_SR_WBNE_Pos)            /*!< 0x00000002 */
5854 #define FLASH_SR_WBNE                       FLASH_SR_WBNE_Msk                       /*!< Write buffer not empty flag */
5855 #define FLASH_SR_DBNE_Pos                   (3U)
5856 #define FLASH_SR_DBNE_Msk                   (0x1UL << FLASH_SR_DBNE_Pos)            /*!< 0x00000008 */
5857 #define FLASH_SR_DBNE                       FLASH_SR_DBNE_Msk                       /*!< Data buffer not empty flag */
5858 #define FLASH_SR_EOP_Pos                    (16U)
5859 #define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)             /*!< 0x00010000 */
5860 #define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                        /*!< End-of-program flag */
5861 #define FLASH_SR_WRPERR_Pos                 (17U)
5862 #define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)          /*!< 0x00020000 */
5863 #define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk                     /*!< Write protection error flag */
5864 #define FLASH_SR_PGSERR_Pos                 (18U)
5865 #define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)          /*!< 0x00040000 */
5866 #define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk                     /*!< Programming sequence error flag */
5867 #define FLASH_SR_STRBERR_Pos                (19U)
5868 #define FLASH_SR_STRBERR_Msk                (0x1UL << FLASH_SR_STRBERR_Pos)         /*!< 0x00080000 */
5869 #define FLASH_SR_STRBERR                    FLASH_SR_STRBERR_Msk                    /*!< Strobe error flag */
5870 #define FLASH_SR_INCERR_Pos                 (20U)
5871 #define FLASH_SR_INCERR_Msk                 (0x1UL << FLASH_SR_INCERR_Pos)          /*!< 0x00100000 */
5872 #define FLASH_SR_INCERR                     FLASH_SR_INCERR_Msk                     /*!< Inconsistency error flag */
5873 #define FLASH_SR_OPTCHANGEERR_Pos           (23U)
5874 #define FLASH_SR_OPTCHANGEERR_Msk           (0x1UL << FLASH_SR_OPTCHANGEERR_Pos)    /*!< 0x00800000 */
5875 #define FLASH_SR_OPTCHANGEERR               FLASH_SR_OPTCHANGEERR_Msk               /*!< Option byte change error flag */
5876 
5877 /*******************  Bits definition for FLASH_CR register  ***********************/
5878 #define FLASH_CR_LOCK_Pos                   (0U)
5879 #define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)            /*!< 0x00000001 */
5880 #define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                       /*!< Configuration lock bit */
5881 #define FLASH_CR_PG_Pos                     (1U)
5882 #define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)              /*!< 0x00000002 */
5883 #define FLASH_CR_PG                         FLASH_CR_PG_Msk                         /*!< Programming control bit */
5884 #define FLASH_CR_SER_Pos                    (2U)
5885 #define FLASH_CR_SER_Msk                    (0x1UL << FLASH_CR_SER_Pos)             /*!< 0x00000004 */
5886 #define FLASH_CR_SER                        FLASH_CR_SER_Msk                        /*!< Sector erase request */
5887 #define FLASH_CR_BER_Pos                    (3U)
5888 #define FLASH_CR_BER_Msk                    (0x1UL << FLASH_CR_BER_Pos)             /*!< 0x00000008 */
5889 #define FLASH_CR_BER                        FLASH_CR_BER_Msk                        /*!< Bank erase request */
5890 #define FLASH_CR_FW_Pos                     (4U)
5891 #define FLASH_CR_FW_Msk                     (0x1UL << FLASH_CR_FW_Pos)              /*!< 0x00000010 */
5892 #define FLASH_CR_FW                         FLASH_CR_FW_Msk                         /*!< Write forcing control bit */
5893 #define FLASH_CR_START_Pos                  (5U)
5894 #define FLASH_CR_START_Msk                  (0x1UL << FLASH_CR_START_Pos)           /*!< 0x00000020 */
5895 #define FLASH_CR_START                      FLASH_CR_START_Msk                      /*!< Erase start control bit */
5896 #define FLASH_CR_SNB_Pos                    (6U)
5897 #define FLASH_CR_SNB_Msk                    (0x7FUL << FLASH_CR_SNB_Pos)            /*!< 0x00001FC0 */
5898 #define FLASH_CR_SNB                        FLASH_CR_SNB_Msk                        /*!< Sector erase selection number */
5899 #define FLASH_CR_SNB_0                      (0x01UL << FLASH_CR_SNB_Pos)            /*!< 0x00000040 */
5900 #define FLASH_CR_SNB_1                      (0x02UL << FLASH_CR_SNB_Pos)            /*!< 0x00000080 */
5901 #define FLASH_CR_SNB_2                      (0x04UL << FLASH_CR_SNB_Pos)            /*!< 0x00000100 */
5902 #define FLASH_CR_SNB_3                      (0x08UL << FLASH_CR_SNB_Pos)            /*!< 0x00000200 */
5903 #define FLASH_CR_SNB_4                      (0x10UL << FLASH_CR_SNB_Pos)            /*!< 0x00000400 */
5904 #define FLASH_CR_SNB_5                      (0x20UL << FLASH_CR_SNB_Pos)            /*!< 0x00000800 */
5905 #define FLASH_CR_SNB_6                      (0x40UL << FLASH_CR_SNB_Pos)            /*!< 0x00001000 */
5906 #define FLASH_CR_MER_Pos                    (15U)
5907 #define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)             /*!< 0x00008000 */
5908 #define FLASH_CR_MER                        FLASH_CR_MER_Msk                        /*!< Mass erase */
5909 #define FLASH_CR_EOPIE_Pos                  (16U)
5910 #define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)           /*!< 0x00010000 */
5911 #define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                      /*!< End-of-operation interrupt control bit */
5912 #define FLASH_CR_WRPERRIE_Pos               (17U)
5913 #define FLASH_CR_WRPERRIE_Msk               (0x1UL << FLASH_CR_WRPERRIE_Pos)        /*!< 0x00020000 */
5914 #define FLASH_CR_WRPERRIE                   FLASH_CR_WRPERRIE_Msk                   /*!< Write protection error interrupt enable bit */
5915 #define FLASH_CR_PGSERRIE_Pos               (18U)
5916 #define FLASH_CR_PGSERRIE_Msk               (0x1UL << FLASH_CR_PGSERRIE_Pos)        /*!< 0x00040000 */
5917 #define FLASH_CR_PGSERRIE                   FLASH_CR_PGSERRIE_Msk                   /*!< Programming sequence error interrupt enable bit */
5918 #define FLASH_CR_STRBERRIE_Pos              (19U)
5919 #define FLASH_CR_STRBERRIE_Msk              (0x1UL << FLASH_CR_STRBERRIE_Pos)       /*!< 0x00080000 */
5920 #define FLASH_CR_STRBERRIE                  FLASH_CR_STRBERRIE_Msk                  /*!< Strobe error interrupt enable bit */
5921 #define FLASH_CR_INCERRIE_Pos               (20U)
5922 #define FLASH_CR_INCERRIE_Msk               (0x1UL << FLASH_CR_INCERRIE_Pos)        /*!< 0x00100000 */
5923 #define FLASH_CR_INCERRIE                   FLASH_CR_INCERRIE_Msk                   /*!< Inconsistency error interrupt enable bit */
5924 #define FLASH_CR_OPTCHANGEERRIE_Pos         (23U)
5925 #define FLASH_CR_OPTCHANGEERRIE_Msk         (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos)  /*!< 0x00800000 */
5926 #define FLASH_CR_OPTCHANGEERRIE             FLASH_CR_OPTCHANGEERRIE_Msk             /*!< Option byte change error interrupt enable bit */
5927 #define FLASH_CR_INV_Pos                    (29U)
5928 #define FLASH_CR_INV_Msk                    (0x1UL << FLASH_CR_INV_Pos)             /*!< 0x20000000 */
5929 #define FLASH_CR_INV                        FLASH_CR_INV_Msk                        /*!< Flash Security State Invert */
5930 #define FLASH_CR_BKSEL_Pos                  (31U)
5931 #define FLASH_CR_BKSEL_Msk                  (0x1UL << FLASH_CR_BKSEL_Pos)           /*!< 0x10000000 */
5932 #define FLASH_CR_BKSEL                      FLASH_CR_BKSEL_Msk                      /*!< Bank selector */
5933 
5934 /*******************  Bits definition for FLASH_CCR register  *******************/
5935 #define FLASH_CCR_CLR_EOP_Pos               (16U)
5936 #define FLASH_CCR_CLR_EOP_Msk               (0x1UL << FLASH_CCR_CLR_EOP_Pos)        /*!< 0x00010000 */
5937 #define FLASH_CCR_CLR_EOP                   FLASH_CCR_CLR_EOP_Msk                   /*!< EOP flag clear bit */
5938 #define FLASH_CCR_CLR_WRPERR_Pos            (17U)
5939 #define FLASH_CCR_CLR_WRPERR_Msk            (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)     /*!< 0x00020000 */
5940 #define FLASH_CCR_CLR_WRPERR                FLASH_CCR_CLR_WRPERR_Msk                /*!< WRPERR flag clear bit */
5941 #define FLASH_CCR_CLR_PGSERR_Pos            (18U)
5942 #define FLASH_CCR_CLR_PGSERR_Msk            (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)     /*!< 0x00040000 */
5943 #define FLASH_CCR_CLR_PGSERR                FLASH_CCR_CLR_PGSERR_Msk                /*!< PGSERR flag clear bit */
5944 #define FLASH_CCR_CLR_STRBERR_Pos           (19U)
5945 #define FLASH_CCR_CLR_STRBERR_Msk           (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)    /*!< 0x00080000 */
5946 #define FLASH_CCR_CLR_STRBERR               FLASH_CCR_CLR_STRBERR_Msk               /*!< STRBERR flag clear bit */
5947 #define FLASH_CCR_CLR_INCERR_Pos            (20U)
5948 #define FLASH_CCR_CLR_INCERR_Msk            (0x1UL << FLASH_CCR_CLR_INCERR_Pos)     /*!< 0x00100000 */
5949 #define FLASH_CCR_CLR_INCERR                FLASH_CCR_CLR_INCERR_Msk                /*!< INCERR flag clear bit */
5950 #define FLASH_CCR_CLR_OPTCHANGEERR_Pos      (23U)
5951 #define FLASH_CCR_CLR_OPTCHANGEERR_Msk      (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */
5952 #define FLASH_CCR_CLR_OPTCHANGEERR          FLASH_CCR_CLR_OPTCHANGEERR_Msk            /*!< Option byte change error clear bit */
5953 
5954 /******************  Bits definition for FLASH_PRIVCFGR register  ***********/
5955 #define FLASH_PRIVCFGR_NSPRIV_Pos           (1U)
5956 #define FLASH_PRIVCFGR_NSPRIV_Msk           (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos)    /*!< 0x00000002 */
5957 #define FLASH_PRIVCFGR_NSPRIV               FLASH_PRIVCFGR_NSPRIV_Msk               /*!< Privilege protection for non-secure registers */
5958 
5959 
5960 /******************  Bits definition for FLASH_HDPEXTR register  *****************/
5961 #define FLASH_HDPEXTR_HDP1_EXT_Pos          (0U)
5962 #define FLASH_HDPEXTR_HDP1_EXT_Msk          (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos)  /*!< 0x0000007F */
5963 #define FLASH_HDPEXTR_HDP1_EXT              FLASH_HDPEXTR_HDP1_EXT_Msk              /*!< HDP area extension in 8kB sectors in bank 1 */
5964 #define FLASH_HDPEXTR_HDP2_EXT_Pos          (16U)
5965 #define FLASH_HDPEXTR_HDP2_EXT_Msk          (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos)  /*!< 0x007F0000 */
5966 #define FLASH_HDPEXTR_HDP2_EXT              FLASH_HDPEXTR_HDP2_EXT_Msk              /*!< HDP area extension in 8kB sectors in bank 2 */
5967 
5968 /*******************  Bits definition for FLASH_OPTSR register  ***************/
5969 #define FLASH_OPTSR_BOR_LEV_Pos             (0U)
5970 #define FLASH_OPTSR_BOR_LEV_Msk             (0x3UL << FLASH_OPTSR_BOR_LEV_Pos)      /*!< 0x00000003 */
5971 #define FLASH_OPTSR_BOR_LEV                 FLASH_OPTSR_BOR_LEV_Msk                 /*!< Brownout level option bit */
5972 #define FLASH_OPTSR_BOR_LEV_0               (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)      /*!< 0x00000001 */
5973 #define FLASH_OPTSR_BOR_LEV_1               (0x2UL << FLASH_OPTSR_BOR_LEV_Pos)      /*!< 0x00000002 */
5974 #define FLASH_OPTSR_BORH_EN_Pos             (2U)
5975 #define FLASH_OPTSR_BORH_EN_Msk             (0x1UL << FLASH_OPTSR_BORH_EN_Pos)      /*!< 0x00000004 */
5976 #define FLASH_OPTSR_BORH_EN                 FLASH_OPTSR_BORH_EN_Msk                 /*!< Brownout high enable configuration bit */
5977 #define FLASH_OPTSR_IWDG_SW_Pos             (3U)
5978 #define FLASH_OPTSR_IWDG_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG_SW_Pos)      /*!< 0x00000008 */
5979 #define FLASH_OPTSR_IWDG_SW                 FLASH_OPTSR_IWDG_SW_Msk                 /*!< IWDG control mode option bit */
5980 #define FLASH_OPTSR_WWDG_SW_Pos             (4U)
5981 #define FLASH_OPTSR_WWDG_SW_Msk             (0x1UL << FLASH_OPTSR_WWDG_SW_Pos)      /*!< 0x00000010 */
5982 #define FLASH_OPTSR_WWDG_SW                 FLASH_OPTSR_WWDG_SW_Msk                 /*!< WWDG control mode option bit */
5983 #define FLASH_OPTSR_NRST_STOP_Pos           (6U)
5984 #define FLASH_OPTSR_NRST_STOP_Msk           (0x1UL << FLASH_OPTSR_NRST_STOP_Pos)    /*!< 0x00000040 */
5985 #define FLASH_OPTSR_NRST_STOP               FLASH_OPTSR_NRST_STOP_Msk               /*!< Stop mode entry reset option bit */
5986 #define FLASH_OPTSR_NRST_STDBY_Pos          (7U)
5987 #define FLASH_OPTSR_NRST_STDBY_Msk          (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos)   /*!< 0x00000080 */
5988 #define FLASH_OPTSR_NRST_STDBY              FLASH_OPTSR_NRST_STDBY_Msk              /*!< Standby mode entry reset option bit */
5989 #define FLASH_OPTSR_PRODUCT_STATE_Pos       (8U)
5990 #define FLASH_OPTSR_PRODUCT_STATE_Msk       (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */
5991 #define FLASH_OPTSR_PRODUCT_STATE           FLASH_OPTSR_PRODUCT_STATE_Msk             /*!< Life state code option byte */
5992 #define FLASH_OPTSR_IO_VDD_HSLV_Pos         (16U)
5993 #define FLASH_OPTSR_IO_VDD_HSLV_Msk         (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos)  /*!< 0x00010000 */
5994 #define FLASH_OPTSR_IO_VDD_HSLV             FLASH_OPTSR_IO_VDD_HSLV_Msk             /*!< VDD I/O high-speed at low-voltage option bit */
5995 #define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos      (17U)
5996 #define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk      (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */
5997 #define FLASH_OPTSR_IO_VDDIO2_HSLV          FLASH_OPTSR_IO_VDDIO2_HSLV_Msk            /*!< VDDIO2 I/O high-speed at low-voltage option bit */
5998 #define FLASH_OPTSR_IWDG_STOP_Pos           (20U)
5999 #define FLASH_OPTSR_IWDG_STOP_Msk           (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos)    /*!< 0x00100000 */
6000 #define FLASH_OPTSR_IWDG_STOP               FLASH_OPTSR_IWDG_STOP_Msk               /*!< Independent watchdog counter freeze in Stop mode */
6001 #define FLASH_OPTSR_IWDG_STDBY_Pos          (21U)
6002 #define FLASH_OPTSR_IWDG_STDBY_Msk          (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos)   /*!< 0x00200000 */
6003 #define FLASH_OPTSR_IWDG_STDBY              FLASH_OPTSR_IWDG_STDBY_Msk              /*!< Independent watchdog counter freeze in Standby mode */
6004 #define FLASH_OPTSR_SWAP_BANK_Pos           (31U)
6005 #define FLASH_OPTSR_SWAP_BANK_Msk           (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos)    /*!< 0x80000000 */
6006 #define FLASH_OPTSR_SWAP_BANK               FLASH_OPTSR_SWAP_BANK_Msk               /*!< Bank swapping option bit */
6007 
6008 /*******************  Bits definition for FLASH_EPOCHR register  ***************/
6009 #define FLASH_EPOCHR_EPOCH_Pos              (0U)
6010 #define FLASH_EPOCHR_EPOCH_Msk              (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos)  /*!< 0x00FFFFFF */
6011 #define FLASH_EPOCHR_EPOCH                  FLASH_EPOCHR_EPOCH_Msk                  /*!< EPOCH counter */
6012 
6013 /*******************  Bits definition for FLASH_OPTSR2 register  ***************/
6014 #define FLASH_OPTSR2_SRAM2_RST_Pos          (3U)
6015 #define FLASH_OPTSR2_SRAM2_RST_Msk          (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos)   /*!< 0x00000008 */
6016 #define FLASH_OPTSR2_SRAM2_RST              FLASH_OPTSR2_SRAM2_RST_Msk              /*!< SRAM2 erased when a system reset occurs*/
6017 #define FLASH_OPTSR2_BKPRAM_ECC_Pos         (4U)
6018 #define FLASH_OPTSR2_BKPRAM_ECC_Msk         (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos)  /*!< 0x00000010 */
6019 #define FLASH_OPTSR2_BKPRAM_ECC             FLASH_OPTSR2_BKPRAM_ECC_Msk             /*!< Backup RAM ECC detection and correction enable */
6020 #define FLASH_OPTSR2_SRAM2_ECC_Pos          (6U)
6021 #define FLASH_OPTSR2_SRAM2_ECC_Msk          (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos)   /*!< 0x00000040 */
6022 #define FLASH_OPTSR2_SRAM2_ECC              FLASH_OPTSR2_SRAM2_ECC_Msk              /*!< SRAM2 ECC detection and correction disable */
6023 #define FLASH_OPTSR2_SRAM1_RST_Pos          (9U)
6024 #define FLASH_OPTSR2_SRAM1_RST_Msk          (0x1UL << FLASH_OPTSR2_SRAM1_RST_Pos)    /*!< 0x00000200 */
6025 #define FLASH_OPTSR2_SRAM1_RST              FLASH_OPTSR2_SRAM1_RST_Msk               /*!< SRAM1 erase upon a system reset */
6026 #define FLASH_OPTSR2_SRAM1_ECC_Pos          (10U)
6027 #define FLASH_OPTSR2_SRAM1_ECC_Msk          (0x1UL << FLASH_OPTSR2_SRAM1_ECC_Pos)    /*!< 0x00000400 */
6028 #define FLASH_OPTSR2_SRAM1_ECC              FLASH_OPTSR2_SRAM1_ECC_Msk               /*!< SRAM1 ECC detection and correction disable */
6029 
6030 /****************  Bits definition for FLASH_BOOTR register  **********************/
6031 #define FLASH_BOOTR_BOOT_LOCK_Pos           (0U)
6032 #define FLASH_BOOTR_BOOT_LOCK_Msk           (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos)   /*!< 0x000000FF */
6033 #define FLASH_BOOTR_BOOT_LOCK               FLASH_BOOTR_BOOT_LOCK_Msk               /*!< Boot Lock */
6034 #define FLASH_BOOTR_BOOTADD_Pos             (8U)
6035 #define FLASH_BOOTR_BOOTADD_Msk             (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */
6036 #define FLASH_BOOTR_BOOTADD                 FLASH_BOOTR_BOOTADD_Msk                 /*!< Boot address */
6037 
6038 /****************  Bits definition for FLASH_PRIVBBR register  *******************/
6039 #define FLASH_PRIVBBR_PRIVBB_Pos            (0U)
6040 #define FLASH_PRIVBBR_PRIVBB_Msk            (0x000000FFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0x000000FF */
6041 #define FLASH_PRIVBBR_PRIVBB                FLASH_PRIVBBR_PRIVBB_Msk                   /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */
6042 
6043 
6044 /*****************  Bits definition for FLASH_WRPR register  *********************/
6045 #define FLASH_WRPR_WRPSG_Pos                (0U)
6046 #define FLASH_WRPR_WRPSG_Msk                (0x000000FFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x000000FF */
6047 #define FLASH_WRPR_WRPSG                    FLASH_WRPR_WRPSG_Msk  /*!< Sector group protection option status */
6048 
6049 
6050 /*****************  Bits definition for FLASH_HDPR register  ********************/
6051 #define FLASH_HDPR_HDP_STRT_Pos             (0U)
6052 #define FLASH_HDPR_HDP_STRT_Msk             (0x07UL << FLASH_HDPR_HDP_STRT_Pos)     /*!< 0x00000007 */
6053 #define FLASH_HDPR_HDP_STRT                 FLASH_HDPR_HDP_STRT_Msk                 /*!< Start sector of hide protection area */
6054 #define FLASH_HDPR_HDP_END_Pos              (16U)
6055 #define FLASH_HDPR_HDP_END_Msk              (0x07UL << FLASH_HDPR_HDP_END_Pos)      /*!< 0x00070000 */
6056 #define FLASH_HDPR_HDP_END                  FLASH_HDPR_HDP_END_Msk                  /*!< End sector of hide protection area */
6057 
6058 /*******************  Bits definition for FLASH_ECCR register  ***************/
6059 #define FLASH_ECCR_ADDR_ECC_Pos             (0U)
6060 #define FLASH_ECCR_ADDR_ECC_Msk             (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos)   /*!< 0x0000FFFF */
6061 #define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk                 /*!< ECC fail address */
6062 #define FLASH_ECCR_BK_ECC_Pos               (22U)
6063 #define FLASH_ECCR_BK_ECC_Msk               (0x1UL << FLASH_ECCR_BK_ECC_Pos)        /*!< 0x00400000 */
6064 #define FLASH_ECCR_BK_ECC                   FLASH_ECCR_BK_ECC_Msk                   /*!< ECC fail bank */
6065 #define FLASH_ECCR_SYSF_ECC_Pos             (23U)
6066 #define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)      /*!< 0x00800000 */
6067 #define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk                 /*!< System Flash ECC fail */
6068 #define FLASH_ECCR_OTP_ECC_Pos              (24U)
6069 #define FLASH_ECCR_OTP_ECC_Msk              (0x1UL << FLASH_ECCR_OTP_ECC_Pos)       /*!< 0x01000000 */
6070 #define FLASH_ECCR_OTP_ECC                  FLASH_ECCR_OTP_ECC_Msk                  /*!< Flash OTP ECC fail */
6071 #define FLASH_ECCR_ECCIE_Pos                (25U)
6072 #define FLASH_ECCR_ECCIE_Msk                (0x1UL << FLASH_ECCR_ECCIE_Pos)         /*!< 0x02000000 */
6073 #define FLASH_ECCR_ECCIE                    FLASH_ECCR_ECCIE_Msk                    /*!< ECC correction interrupt enable */
6074 #define FLASH_ECCR_ECCC_Pos                 (30U)
6075 #define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)          /*!< 0x40000000 */
6076 #define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk                     /*!< ECC correction */
6077 #define FLASH_ECCR_ECCD_Pos                 (31U)
6078 #define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)          /*!< 0x80000000 */
6079 #define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk                     /*!< ECC detection */
6080 
6081 /*******************  Bits definition for FLASH_ECCDR register  ***************/
6082 #define FLASH_ECCDR_FAIL_DATA_Pos           (0U)
6083 #define FLASH_ECCDR_FAIL_DATA_Msk           (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */
6084 #define FLASH_ECCDR_FAIL_DATA               FLASH_ECCDR_FAIL_DATA_Msk               /*!< ECC fail data */
6085 
6086 
6087 /******************************************************************************/
6088 /*                                                                            */
6089 /*                       General Purpose IOs (GPIO)                           */
6090 /*                                                                            */
6091 /******************************************************************************/
6092 /******************  Bits definition for GPIO_MODER register  *****************/
6093 #define GPIO_MODER_MODE0_Pos                (0U)
6094 #define GPIO_MODER_MODE0_Msk                (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
6095 #define GPIO_MODER_MODE0                    GPIO_MODER_MODE0_Msk
6096 #define GPIO_MODER_MODE0_0                  (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
6097 #define GPIO_MODER_MODE0_1                  (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
6098 #define GPIO_MODER_MODE1_Pos                (2U)
6099 #define GPIO_MODER_MODE1_Msk                (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
6100 #define GPIO_MODER_MODE1                    GPIO_MODER_MODE1_Msk
6101 #define GPIO_MODER_MODE1_0                  (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
6102 #define GPIO_MODER_MODE1_1                  (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
6103 #define GPIO_MODER_MODE2_Pos                (4U)
6104 #define GPIO_MODER_MODE2_Msk                (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
6105 #define GPIO_MODER_MODE2                    GPIO_MODER_MODE2_Msk
6106 #define GPIO_MODER_MODE2_0                  (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
6107 #define GPIO_MODER_MODE2_1                  (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
6108 #define GPIO_MODER_MODE3_Pos                (6U)
6109 #define GPIO_MODER_MODE3_Msk                (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
6110 #define GPIO_MODER_MODE3                    GPIO_MODER_MODE3_Msk
6111 #define GPIO_MODER_MODE3_0                  (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
6112 #define GPIO_MODER_MODE3_1                  (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
6113 #define GPIO_MODER_MODE4_Pos                (8U)
6114 #define GPIO_MODER_MODE4_Msk                (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
6115 #define GPIO_MODER_MODE4                    GPIO_MODER_MODE4_Msk
6116 #define GPIO_MODER_MODE4_0                  (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
6117 #define GPIO_MODER_MODE4_1                  (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
6118 #define GPIO_MODER_MODE5_Pos                (10U)
6119 #define GPIO_MODER_MODE5_Msk                (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
6120 #define GPIO_MODER_MODE5                    GPIO_MODER_MODE5_Msk
6121 #define GPIO_MODER_MODE5_0                  (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
6122 #define GPIO_MODER_MODE5_1                  (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
6123 #define GPIO_MODER_MODE6_Pos                (12U)
6124 #define GPIO_MODER_MODE6_Msk                (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
6125 #define GPIO_MODER_MODE6                    GPIO_MODER_MODE6_Msk
6126 #define GPIO_MODER_MODE6_0                  (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
6127 #define GPIO_MODER_MODE6_1                  (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
6128 #define GPIO_MODER_MODE7_Pos                (14U)
6129 #define GPIO_MODER_MODE7_Msk                (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
6130 #define GPIO_MODER_MODE7                    GPIO_MODER_MODE7_Msk
6131 #define GPIO_MODER_MODE7_0                  (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
6132 #define GPIO_MODER_MODE7_1                  (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
6133 #define GPIO_MODER_MODE8_Pos                (16U)
6134 #define GPIO_MODER_MODE8_Msk                (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
6135 #define GPIO_MODER_MODE8                    GPIO_MODER_MODE8_Msk
6136 #define GPIO_MODER_MODE8_0                  (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
6137 #define GPIO_MODER_MODE8_1                  (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
6138 #define GPIO_MODER_MODE9_Pos                (18U)
6139 #define GPIO_MODER_MODE9_Msk                (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
6140 #define GPIO_MODER_MODE9                    GPIO_MODER_MODE9_Msk
6141 #define GPIO_MODER_MODE9_0                  (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
6142 #define GPIO_MODER_MODE9_1                  (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
6143 #define GPIO_MODER_MODE10_Pos               (20U)
6144 #define GPIO_MODER_MODE10_Msk               (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
6145 #define GPIO_MODER_MODE10                   GPIO_MODER_MODE10_Msk
6146 #define GPIO_MODER_MODE10_0                 (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
6147 #define GPIO_MODER_MODE10_1                 (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
6148 #define GPIO_MODER_MODE11_Pos               (22U)
6149 #define GPIO_MODER_MODE11_Msk               (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
6150 #define GPIO_MODER_MODE11                   GPIO_MODER_MODE11_Msk
6151 #define GPIO_MODER_MODE11_0                 (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
6152 #define GPIO_MODER_MODE11_1                 (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
6153 #define GPIO_MODER_MODE12_Pos               (24U)
6154 #define GPIO_MODER_MODE12_Msk               (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
6155 #define GPIO_MODER_MODE12                   GPIO_MODER_MODE12_Msk
6156 #define GPIO_MODER_MODE12_0                 (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
6157 #define GPIO_MODER_MODE12_1                 (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
6158 #define GPIO_MODER_MODE13_Pos               (26U)
6159 #define GPIO_MODER_MODE13_Msk               (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
6160 #define GPIO_MODER_MODE13                   GPIO_MODER_MODE13_Msk
6161 #define GPIO_MODER_MODE13_0                 (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
6162 #define GPIO_MODER_MODE13_1                 (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
6163 #define GPIO_MODER_MODE14_Pos               (28U)
6164 #define GPIO_MODER_MODE14_Msk               (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
6165 #define GPIO_MODER_MODE14                   GPIO_MODER_MODE14_Msk
6166 #define GPIO_MODER_MODE14_0                 (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
6167 #define GPIO_MODER_MODE14_1                 (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
6168 #define GPIO_MODER_MODE15_Pos               (30U)
6169 #define GPIO_MODER_MODE15_Msk               (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
6170 #define GPIO_MODER_MODE15                   GPIO_MODER_MODE15_Msk
6171 #define GPIO_MODER_MODE15_0                 (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
6172 #define GPIO_MODER_MODE15_1                 (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
6173 
6174 /******************  Bits definition for GPIO_OTYPER register  ****************/
6175 #define GPIO_OTYPER_OT0_Pos                 (0U)
6176 #define GPIO_OTYPER_OT0_Msk                 (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
6177 #define GPIO_OTYPER_OT0                     GPIO_OTYPER_OT0_Msk
6178 #define GPIO_OTYPER_OT1_Pos                 (1U)
6179 #define GPIO_OTYPER_OT1_Msk                 (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
6180 #define GPIO_OTYPER_OT1                     GPIO_OTYPER_OT1_Msk
6181 #define GPIO_OTYPER_OT2_Pos                 (2U)
6182 #define GPIO_OTYPER_OT2_Msk                 (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
6183 #define GPIO_OTYPER_OT2                     GPIO_OTYPER_OT2_Msk
6184 #define GPIO_OTYPER_OT3_Pos                 (3U)
6185 #define GPIO_OTYPER_OT3_Msk                 (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
6186 #define GPIO_OTYPER_OT3                     GPIO_OTYPER_OT3_Msk
6187 #define GPIO_OTYPER_OT4_Pos                 (4U)
6188 #define GPIO_OTYPER_OT4_Msk                 (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
6189 #define GPIO_OTYPER_OT4                     GPIO_OTYPER_OT4_Msk
6190 #define GPIO_OTYPER_OT5_Pos                 (5U)
6191 #define GPIO_OTYPER_OT5_Msk                 (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
6192 #define GPIO_OTYPER_OT5                     GPIO_OTYPER_OT5_Msk
6193 #define GPIO_OTYPER_OT6_Pos                 (6U)
6194 #define GPIO_OTYPER_OT6_Msk                 (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
6195 #define GPIO_OTYPER_OT6                     GPIO_OTYPER_OT6_Msk
6196 #define GPIO_OTYPER_OT7_Pos                 (7U)
6197 #define GPIO_OTYPER_OT7_Msk                 (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
6198 #define GPIO_OTYPER_OT7                     GPIO_OTYPER_OT7_Msk
6199 #define GPIO_OTYPER_OT8_Pos                 (8U)
6200 #define GPIO_OTYPER_OT8_Msk                 (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
6201 #define GPIO_OTYPER_OT8                     GPIO_OTYPER_OT8_Msk
6202 #define GPIO_OTYPER_OT9_Pos                 (9U)
6203 #define GPIO_OTYPER_OT9_Msk                 (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
6204 #define GPIO_OTYPER_OT9                     GPIO_OTYPER_OT9_Msk
6205 #define GPIO_OTYPER_OT10_Pos                (10U)
6206 #define GPIO_OTYPER_OT10_Msk                (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
6207 #define GPIO_OTYPER_OT10                    GPIO_OTYPER_OT10_Msk
6208 #define GPIO_OTYPER_OT11_Pos                (11U)
6209 #define GPIO_OTYPER_OT11_Msk                (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
6210 #define GPIO_OTYPER_OT11                    GPIO_OTYPER_OT11_Msk
6211 #define GPIO_OTYPER_OT12_Pos                (12U)
6212 #define GPIO_OTYPER_OT12_Msk                (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
6213 #define GPIO_OTYPER_OT12                    GPIO_OTYPER_OT12_Msk
6214 #define GPIO_OTYPER_OT13_Pos                (13U)
6215 #define GPIO_OTYPER_OT13_Msk                (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
6216 #define GPIO_OTYPER_OT13                    GPIO_OTYPER_OT13_Msk
6217 #define GPIO_OTYPER_OT14_Pos                (14U)
6218 #define GPIO_OTYPER_OT14_Msk                (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
6219 #define GPIO_OTYPER_OT14                    GPIO_OTYPER_OT14_Msk
6220 #define GPIO_OTYPER_OT15_Pos                (15U)
6221 #define GPIO_OTYPER_OT15_Msk                (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
6222 #define GPIO_OTYPER_OT15                    GPIO_OTYPER_OT15_Msk
6223 
6224 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
6225 #define GPIO_OSPEEDR_OSPEED0_Pos            (0U)
6226 #define GPIO_OSPEEDR_OSPEED0_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
6227 #define GPIO_OSPEEDR_OSPEED0                GPIO_OSPEEDR_OSPEED0_Msk
6228 #define GPIO_OSPEEDR_OSPEED0_0              (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
6229 #define GPIO_OSPEEDR_OSPEED0_1              (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
6230 #define GPIO_OSPEEDR_OSPEED1_Pos            (2U)
6231 #define GPIO_OSPEEDR_OSPEED1_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
6232 #define GPIO_OSPEEDR_OSPEED1                GPIO_OSPEEDR_OSPEED1_Msk
6233 #define GPIO_OSPEEDR_OSPEED1_0              (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
6234 #define GPIO_OSPEEDR_OSPEED1_1              (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
6235 #define GPIO_OSPEEDR_OSPEED2_Pos            (4U)
6236 #define GPIO_OSPEEDR_OSPEED2_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
6237 #define GPIO_OSPEEDR_OSPEED2                GPIO_OSPEEDR_OSPEED2_Msk
6238 #define GPIO_OSPEEDR_OSPEED2_0              (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
6239 #define GPIO_OSPEEDR_OSPEED2_1              (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
6240 #define GPIO_OSPEEDR_OSPEED3_Pos            (6U)
6241 #define GPIO_OSPEEDR_OSPEED3_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
6242 #define GPIO_OSPEEDR_OSPEED3                GPIO_OSPEEDR_OSPEED3_Msk
6243 #define GPIO_OSPEEDR_OSPEED3_0              (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
6244 #define GPIO_OSPEEDR_OSPEED3_1              (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
6245 #define GPIO_OSPEEDR_OSPEED4_Pos            (8U)
6246 #define GPIO_OSPEEDR_OSPEED4_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
6247 #define GPIO_OSPEEDR_OSPEED4                GPIO_OSPEEDR_OSPEED4_Msk
6248 #define GPIO_OSPEEDR_OSPEED4_0              (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
6249 #define GPIO_OSPEEDR_OSPEED4_1              (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
6250 #define GPIO_OSPEEDR_OSPEED5_Pos            (10U)
6251 #define GPIO_OSPEEDR_OSPEED5_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
6252 #define GPIO_OSPEEDR_OSPEED5                GPIO_OSPEEDR_OSPEED5_Msk
6253 #define GPIO_OSPEEDR_OSPEED5_0              (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
6254 #define GPIO_OSPEEDR_OSPEED5_1              (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
6255 #define GPIO_OSPEEDR_OSPEED6_Pos            (12U)
6256 #define GPIO_OSPEEDR_OSPEED6_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
6257 #define GPIO_OSPEEDR_OSPEED6                GPIO_OSPEEDR_OSPEED6_Msk
6258 #define GPIO_OSPEEDR_OSPEED6_0              (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
6259 #define GPIO_OSPEEDR_OSPEED6_1              (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
6260 #define GPIO_OSPEEDR_OSPEED7_Pos            (14U)
6261 #define GPIO_OSPEEDR_OSPEED7_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
6262 #define GPIO_OSPEEDR_OSPEED7                GPIO_OSPEEDR_OSPEED7_Msk
6263 #define GPIO_OSPEEDR_OSPEED7_0              (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
6264 #define GPIO_OSPEEDR_OSPEED7_1              (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
6265 #define GPIO_OSPEEDR_OSPEED8_Pos            (16U)
6266 #define GPIO_OSPEEDR_OSPEED8_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
6267 #define GPIO_OSPEEDR_OSPEED8                GPIO_OSPEEDR_OSPEED8_Msk
6268 #define GPIO_OSPEEDR_OSPEED8_0              (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
6269 #define GPIO_OSPEEDR_OSPEED8_1              (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
6270 #define GPIO_OSPEEDR_OSPEED9_Pos            (18U)
6271 #define GPIO_OSPEEDR_OSPEED9_Msk            (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
6272 #define GPIO_OSPEEDR_OSPEED9                GPIO_OSPEEDR_OSPEED9_Msk
6273 #define GPIO_OSPEEDR_OSPEED9_0              (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
6274 #define GPIO_OSPEEDR_OSPEED9_1              (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
6275 #define GPIO_OSPEEDR_OSPEED10_Pos           (20U)
6276 #define GPIO_OSPEEDR_OSPEED10_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
6277 #define GPIO_OSPEEDR_OSPEED10               GPIO_OSPEEDR_OSPEED10_Msk
6278 #define GPIO_OSPEEDR_OSPEED10_0             (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
6279 #define GPIO_OSPEEDR_OSPEED10_1             (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
6280 #define GPIO_OSPEEDR_OSPEED11_Pos           (22U)
6281 #define GPIO_OSPEEDR_OSPEED11_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
6282 #define GPIO_OSPEEDR_OSPEED11               GPIO_OSPEEDR_OSPEED11_Msk
6283 #define GPIO_OSPEEDR_OSPEED11_0             (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
6284 #define GPIO_OSPEEDR_OSPEED11_1             (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
6285 #define GPIO_OSPEEDR_OSPEED12_Pos           (24U)
6286 #define GPIO_OSPEEDR_OSPEED12_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
6287 #define GPIO_OSPEEDR_OSPEED12               GPIO_OSPEEDR_OSPEED12_Msk
6288 #define GPIO_OSPEEDR_OSPEED12_0             (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
6289 #define GPIO_OSPEEDR_OSPEED12_1             (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
6290 #define GPIO_OSPEEDR_OSPEED13_Pos           (26U)
6291 #define GPIO_OSPEEDR_OSPEED13_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
6292 #define GPIO_OSPEEDR_OSPEED13               GPIO_OSPEEDR_OSPEED13_Msk
6293 #define GPIO_OSPEEDR_OSPEED13_0             (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
6294 #define GPIO_OSPEEDR_OSPEED13_1             (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
6295 #define GPIO_OSPEEDR_OSPEED14_Pos           (28U)
6296 #define GPIO_OSPEEDR_OSPEED14_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
6297 #define GPIO_OSPEEDR_OSPEED14               GPIO_OSPEEDR_OSPEED14_Msk
6298 #define GPIO_OSPEEDR_OSPEED14_0             (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
6299 #define GPIO_OSPEEDR_OSPEED14_1             (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
6300 #define GPIO_OSPEEDR_OSPEED15_Pos           (30U)
6301 #define GPIO_OSPEEDR_OSPEED15_Msk           (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
6302 #define GPIO_OSPEEDR_OSPEED15               GPIO_OSPEEDR_OSPEED15_Msk
6303 #define GPIO_OSPEEDR_OSPEED15_0             (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
6304 #define GPIO_OSPEEDR_OSPEED15_1             (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
6305 
6306 /******************  Bits definition for GPIO_PUPDR register  *****************/
6307 #define GPIO_PUPDR_PUPD0_Pos                (0U)
6308 #define GPIO_PUPDR_PUPD0_Msk                (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
6309 #define GPIO_PUPDR_PUPD0                    GPIO_PUPDR_PUPD0_Msk
6310 #define GPIO_PUPDR_PUPD0_0                  (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
6311 #define GPIO_PUPDR_PUPD0_1                  (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
6312 #define GPIO_PUPDR_PUPD1_Pos                (2U)
6313 #define GPIO_PUPDR_PUPD1_Msk                (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
6314 #define GPIO_PUPDR_PUPD1                    GPIO_PUPDR_PUPD1_Msk
6315 #define GPIO_PUPDR_PUPD1_0                  (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
6316 #define GPIO_PUPDR_PUPD1_1                  (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
6317 #define GPIO_PUPDR_PUPD2_Pos                (4U)
6318 #define GPIO_PUPDR_PUPD2_Msk                (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
6319 #define GPIO_PUPDR_PUPD2                    GPIO_PUPDR_PUPD2_Msk
6320 #define GPIO_PUPDR_PUPD2_0                  (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
6321 #define GPIO_PUPDR_PUPD2_1                  (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
6322 #define GPIO_PUPDR_PUPD3_Pos                (6U)
6323 #define GPIO_PUPDR_PUPD3_Msk                (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
6324 #define GPIO_PUPDR_PUPD3                    GPIO_PUPDR_PUPD3_Msk
6325 #define GPIO_PUPDR_PUPD3_0                  (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
6326 #define GPIO_PUPDR_PUPD3_1                  (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
6327 #define GPIO_PUPDR_PUPD4_Pos                (8U)
6328 #define GPIO_PUPDR_PUPD4_Msk                (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
6329 #define GPIO_PUPDR_PUPD4                    GPIO_PUPDR_PUPD4_Msk
6330 #define GPIO_PUPDR_PUPD4_0                  (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
6331 #define GPIO_PUPDR_PUPD4_1                  (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
6332 #define GPIO_PUPDR_PUPD5_Pos                (10U)
6333 #define GPIO_PUPDR_PUPD5_Msk                (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
6334 #define GPIO_PUPDR_PUPD5                    GPIO_PUPDR_PUPD5_Msk
6335 #define GPIO_PUPDR_PUPD5_0                  (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
6336 #define GPIO_PUPDR_PUPD5_1                  (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
6337 #define GPIO_PUPDR_PUPD6_Pos                (12U)
6338 #define GPIO_PUPDR_PUPD6_Msk                (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
6339 #define GPIO_PUPDR_PUPD6                    GPIO_PUPDR_PUPD6_Msk
6340 #define GPIO_PUPDR_PUPD6_0                  (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
6341 #define GPIO_PUPDR_PUPD6_1                  (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
6342 #define GPIO_PUPDR_PUPD7_Pos                (14U)
6343 #define GPIO_PUPDR_PUPD7_Msk                (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
6344 #define GPIO_PUPDR_PUPD7                    GPIO_PUPDR_PUPD7_Msk
6345 #define GPIO_PUPDR_PUPD7_0                  (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
6346 #define GPIO_PUPDR_PUPD7_1                  (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
6347 #define GPIO_PUPDR_PUPD8_Pos                (16U)
6348 #define GPIO_PUPDR_PUPD8_Msk                (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
6349 #define GPIO_PUPDR_PUPD8                    GPIO_PUPDR_PUPD8_Msk
6350 #define GPIO_PUPDR_PUPD8_0                  (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
6351 #define GPIO_PUPDR_PUPD8_1                  (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
6352 #define GPIO_PUPDR_PUPD9_Pos                (18U)
6353 #define GPIO_PUPDR_PUPD9_Msk                (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
6354 #define GPIO_PUPDR_PUPD9                    GPIO_PUPDR_PUPD9_Msk
6355 #define GPIO_PUPDR_PUPD9_0                  (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
6356 #define GPIO_PUPDR_PUPD9_1                  (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
6357 #define GPIO_PUPDR_PUPD10_Pos               (20U)
6358 #define GPIO_PUPDR_PUPD10_Msk               (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
6359 #define GPIO_PUPDR_PUPD10                   GPIO_PUPDR_PUPD10_Msk
6360 #define GPIO_PUPDR_PUPD10_0                 (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
6361 #define GPIO_PUPDR_PUPD10_1                 (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
6362 #define GPIO_PUPDR_PUPD11_Pos               (22U)
6363 #define GPIO_PUPDR_PUPD11_Msk               (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
6364 #define GPIO_PUPDR_PUPD11                   GPIO_PUPDR_PUPD11_Msk
6365 #define GPIO_PUPDR_PUPD11_0                 (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
6366 #define GPIO_PUPDR_PUPD11_1                 (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
6367 #define GPIO_PUPDR_PUPD12_Pos               (24U)
6368 #define GPIO_PUPDR_PUPD12_Msk               (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
6369 #define GPIO_PUPDR_PUPD12                   GPIO_PUPDR_PUPD12_Msk
6370 #define GPIO_PUPDR_PUPD12_0                 (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
6371 #define GPIO_PUPDR_PUPD12_1                 (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
6372 #define GPIO_PUPDR_PUPD13_Pos               (26U)
6373 #define GPIO_PUPDR_PUPD13_Msk               (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
6374 #define GPIO_PUPDR_PUPD13                   GPIO_PUPDR_PUPD13_Msk
6375 #define GPIO_PUPDR_PUPD13_0                 (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
6376 #define GPIO_PUPDR_PUPD13_1                 (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
6377 #define GPIO_PUPDR_PUPD14_Pos               (28U)
6378 #define GPIO_PUPDR_PUPD14_Msk               (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
6379 #define GPIO_PUPDR_PUPD14                   GPIO_PUPDR_PUPD14_Msk
6380 #define GPIO_PUPDR_PUPD14_0                 (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
6381 #define GPIO_PUPDR_PUPD14_1                 (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
6382 #define GPIO_PUPDR_PUPD15_Pos               (30U)
6383 #define GPIO_PUPDR_PUPD15_Msk               (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
6384 #define GPIO_PUPDR_PUPD15                   GPIO_PUPDR_PUPD15_Msk
6385 #define GPIO_PUPDR_PUPD15_0                 (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
6386 #define GPIO_PUPDR_PUPD15_1                 (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
6387 
6388 /******************  Bits definition for GPIO_IDR register  *******************/
6389 #define GPIO_IDR_ID0_Pos                    (0U)
6390 #define GPIO_IDR_ID0_Msk                    (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
6391 #define GPIO_IDR_ID0                        GPIO_IDR_ID0_Msk
6392 #define GPIO_IDR_ID1_Pos                    (1U)
6393 #define GPIO_IDR_ID1_Msk                    (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
6394 #define GPIO_IDR_ID1                        GPIO_IDR_ID1_Msk
6395 #define GPIO_IDR_ID2_Pos                    (2U)
6396 #define GPIO_IDR_ID2_Msk                    (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
6397 #define GPIO_IDR_ID2                        GPIO_IDR_ID2_Msk
6398 #define GPIO_IDR_ID3_Pos                    (3U)
6399 #define GPIO_IDR_ID3_Msk                    (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
6400 #define GPIO_IDR_ID3                        GPIO_IDR_ID3_Msk
6401 #define GPIO_IDR_ID4_Pos                    (4U)
6402 #define GPIO_IDR_ID4_Msk                    (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
6403 #define GPIO_IDR_ID4                        GPIO_IDR_ID4_Msk
6404 #define GPIO_IDR_ID5_Pos                    (5U)
6405 #define GPIO_IDR_ID5_Msk                    (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
6406 #define GPIO_IDR_ID5                        GPIO_IDR_ID5_Msk
6407 #define GPIO_IDR_ID6_Pos                    (6U)
6408 #define GPIO_IDR_ID6_Msk                    (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
6409 #define GPIO_IDR_ID6                        GPIO_IDR_ID6_Msk
6410 #define GPIO_IDR_ID7_Pos                    (7U)
6411 #define GPIO_IDR_ID7_Msk                    (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
6412 #define GPIO_IDR_ID7                        GPIO_IDR_ID7_Msk
6413 #define GPIO_IDR_ID8_Pos                    (8U)
6414 #define GPIO_IDR_ID8_Msk                    (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
6415 #define GPIO_IDR_ID8                        GPIO_IDR_ID8_Msk
6416 #define GPIO_IDR_ID9_Pos                    (9U)
6417 #define GPIO_IDR_ID9_Msk                    (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
6418 #define GPIO_IDR_ID9                        GPIO_IDR_ID9_Msk
6419 #define GPIO_IDR_ID10_Pos                   (10U)
6420 #define GPIO_IDR_ID10_Msk                   (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
6421 #define GPIO_IDR_ID10                       GPIO_IDR_ID10_Msk
6422 #define GPIO_IDR_ID11_Pos                   (11U)
6423 #define GPIO_IDR_ID11_Msk                   (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
6424 #define GPIO_IDR_ID11                       GPIO_IDR_ID11_Msk
6425 #define GPIO_IDR_ID12_Pos                   (12U)
6426 #define GPIO_IDR_ID12_Msk                   (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
6427 #define GPIO_IDR_ID12                       GPIO_IDR_ID12_Msk
6428 #define GPIO_IDR_ID13_Pos                   (13U)
6429 #define GPIO_IDR_ID13_Msk                   (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
6430 #define GPIO_IDR_ID13                       GPIO_IDR_ID13_Msk
6431 #define GPIO_IDR_ID14_Pos                   (14U)
6432 #define GPIO_IDR_ID14_Msk                   (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
6433 #define GPIO_IDR_ID14                       GPIO_IDR_ID14_Msk
6434 #define GPIO_IDR_ID15_Pos                   (15U)
6435 #define GPIO_IDR_ID15_Msk                   (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
6436 #define GPIO_IDR_ID15                       GPIO_IDR_ID15_Msk
6437 
6438 /******************  Bits definition for GPIO_ODR register  *******************/
6439 #define GPIO_ODR_OD0_Pos                    (0U)
6440 #define GPIO_ODR_OD0_Msk                    (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
6441 #define GPIO_ODR_OD0                        GPIO_ODR_OD0_Msk
6442 #define GPIO_ODR_OD1_Pos                    (1U)
6443 #define GPIO_ODR_OD1_Msk                    (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
6444 #define GPIO_ODR_OD1                        GPIO_ODR_OD1_Msk
6445 #define GPIO_ODR_OD2_Pos                    (2U)
6446 #define GPIO_ODR_OD2_Msk                    (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
6447 #define GPIO_ODR_OD2                        GPIO_ODR_OD2_Msk
6448 #define GPIO_ODR_OD3_Pos                    (3U)
6449 #define GPIO_ODR_OD3_Msk                    (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
6450 #define GPIO_ODR_OD3                        GPIO_ODR_OD3_Msk
6451 #define GPIO_ODR_OD4_Pos                    (4U)
6452 #define GPIO_ODR_OD4_Msk                    (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
6453 #define GPIO_ODR_OD4                        GPIO_ODR_OD4_Msk
6454 #define GPIO_ODR_OD5_Pos                    (5U)
6455 #define GPIO_ODR_OD5_Msk                    (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
6456 #define GPIO_ODR_OD5                        GPIO_ODR_OD5_Msk
6457 #define GPIO_ODR_OD6_Pos                    (6U)
6458 #define GPIO_ODR_OD6_Msk                    (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
6459 #define GPIO_ODR_OD6                        GPIO_ODR_OD6_Msk
6460 #define GPIO_ODR_OD7_Pos                    (7U)
6461 #define GPIO_ODR_OD7_Msk                    (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
6462 #define GPIO_ODR_OD7                        GPIO_ODR_OD7_Msk
6463 #define GPIO_ODR_OD8_Pos                    (8U)
6464 #define GPIO_ODR_OD8_Msk                    (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
6465 #define GPIO_ODR_OD8                        GPIO_ODR_OD8_Msk
6466 #define GPIO_ODR_OD9_Pos                    (9U)
6467 #define GPIO_ODR_OD9_Msk                    (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
6468 #define GPIO_ODR_OD9                        GPIO_ODR_OD9_Msk
6469 #define GPIO_ODR_OD10_Pos                   (10U)
6470 #define GPIO_ODR_OD10_Msk                   (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
6471 #define GPIO_ODR_OD10                       GPIO_ODR_OD10_Msk
6472 #define GPIO_ODR_OD11_Pos                   (11U)
6473 #define GPIO_ODR_OD11_Msk                   (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
6474 #define GPIO_ODR_OD11                       GPIO_ODR_OD11_Msk
6475 #define GPIO_ODR_OD12_Pos                   (12U)
6476 #define GPIO_ODR_OD12_Msk                   (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
6477 #define GPIO_ODR_OD12                       GPIO_ODR_OD12_Msk
6478 #define GPIO_ODR_OD13_Pos                   (13U)
6479 #define GPIO_ODR_OD13_Msk                   (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
6480 #define GPIO_ODR_OD13                       GPIO_ODR_OD13_Msk
6481 #define GPIO_ODR_OD14_Pos                   (14U)
6482 #define GPIO_ODR_OD14_Msk                   (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
6483 #define GPIO_ODR_OD14                       GPIO_ODR_OD14_Msk
6484 #define GPIO_ODR_OD15_Pos                   (15U)
6485 #define GPIO_ODR_OD15_Msk                   (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
6486 #define GPIO_ODR_OD15                       GPIO_ODR_OD15_Msk
6487 
6488 /******************  Bits definition for GPIO_BSRR register  ******************/
6489 #define GPIO_BSRR_BS0_Pos                   (0U)
6490 #define GPIO_BSRR_BS0_Msk                   (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
6491 #define GPIO_BSRR_BS0                       GPIO_BSRR_BS0_Msk
6492 #define GPIO_BSRR_BS1_Pos                   (1U)
6493 #define GPIO_BSRR_BS1_Msk                   (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
6494 #define GPIO_BSRR_BS1                       GPIO_BSRR_BS1_Msk
6495 #define GPIO_BSRR_BS2_Pos                   (2U)
6496 #define GPIO_BSRR_BS2_Msk                   (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
6497 #define GPIO_BSRR_BS2                       GPIO_BSRR_BS2_Msk
6498 #define GPIO_BSRR_BS3_Pos                   (3U)
6499 #define GPIO_BSRR_BS3_Msk                   (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
6500 #define GPIO_BSRR_BS3                       GPIO_BSRR_BS3_Msk
6501 #define GPIO_BSRR_BS4_Pos                   (4U)
6502 #define GPIO_BSRR_BS4_Msk                   (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
6503 #define GPIO_BSRR_BS4                       GPIO_BSRR_BS4_Msk
6504 #define GPIO_BSRR_BS5_Pos                   (5U)
6505 #define GPIO_BSRR_BS5_Msk                   (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
6506 #define GPIO_BSRR_BS5                       GPIO_BSRR_BS5_Msk
6507 #define GPIO_BSRR_BS6_Pos                   (6U)
6508 #define GPIO_BSRR_BS6_Msk                   (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
6509 #define GPIO_BSRR_BS6                       GPIO_BSRR_BS6_Msk
6510 #define GPIO_BSRR_BS7_Pos                   (7U)
6511 #define GPIO_BSRR_BS7_Msk                   (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
6512 #define GPIO_BSRR_BS7                       GPIO_BSRR_BS7_Msk
6513 #define GPIO_BSRR_BS8_Pos                   (8U)
6514 #define GPIO_BSRR_BS8_Msk                   (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
6515 #define GPIO_BSRR_BS8                       GPIO_BSRR_BS8_Msk
6516 #define GPIO_BSRR_BS9_Pos                   (9U)
6517 #define GPIO_BSRR_BS9_Msk                   (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
6518 #define GPIO_BSRR_BS9                       GPIO_BSRR_BS9_Msk
6519 #define GPIO_BSRR_BS10_Pos                  (10U)
6520 #define GPIO_BSRR_BS10_Msk                  (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
6521 #define GPIO_BSRR_BS10                      GPIO_BSRR_BS10_Msk
6522 #define GPIO_BSRR_BS11_Pos                  (11U)
6523 #define GPIO_BSRR_BS11_Msk                  (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
6524 #define GPIO_BSRR_BS11                      GPIO_BSRR_BS11_Msk
6525 #define GPIO_BSRR_BS12_Pos                  (12U)
6526 #define GPIO_BSRR_BS12_Msk                  (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
6527 #define GPIO_BSRR_BS12                      GPIO_BSRR_BS12_Msk
6528 #define GPIO_BSRR_BS13_Pos                  (13U)
6529 #define GPIO_BSRR_BS13_Msk                  (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
6530 #define GPIO_BSRR_BS13                      GPIO_BSRR_BS13_Msk
6531 #define GPIO_BSRR_BS14_Pos                  (14U)
6532 #define GPIO_BSRR_BS14_Msk                  (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
6533 #define GPIO_BSRR_BS14                      GPIO_BSRR_BS14_Msk
6534 #define GPIO_BSRR_BS15_Pos                  (15U)
6535 #define GPIO_BSRR_BS15_Msk                  (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
6536 #define GPIO_BSRR_BS15                      GPIO_BSRR_BS15_Msk
6537 #define GPIO_BSRR_BR0_Pos                   (16U)
6538 #define GPIO_BSRR_BR0_Msk                   (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
6539 #define GPIO_BSRR_BR0                       GPIO_BSRR_BR0_Msk
6540 #define GPIO_BSRR_BR1_Pos                   (17U)
6541 #define GPIO_BSRR_BR1_Msk                   (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
6542 #define GPIO_BSRR_BR1                       GPIO_BSRR_BR1_Msk
6543 #define GPIO_BSRR_BR2_Pos                   (18U)
6544 #define GPIO_BSRR_BR2_Msk                   (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
6545 #define GPIO_BSRR_BR2                       GPIO_BSRR_BR2_Msk
6546 #define GPIO_BSRR_BR3_Pos                   (19U)
6547 #define GPIO_BSRR_BR3_Msk                   (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
6548 #define GPIO_BSRR_BR3                       GPIO_BSRR_BR3_Msk
6549 #define GPIO_BSRR_BR4_Pos                   (20U)
6550 #define GPIO_BSRR_BR4_Msk                   (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
6551 #define GPIO_BSRR_BR4                       GPIO_BSRR_BR4_Msk
6552 #define GPIO_BSRR_BR5_Pos                   (21U)
6553 #define GPIO_BSRR_BR5_Msk                   (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
6554 #define GPIO_BSRR_BR5                       GPIO_BSRR_BR5_Msk
6555 #define GPIO_BSRR_BR6_Pos                   (22U)
6556 #define GPIO_BSRR_BR6_Msk                   (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
6557 #define GPIO_BSRR_BR6                       GPIO_BSRR_BR6_Msk
6558 #define GPIO_BSRR_BR7_Pos                   (23U)
6559 #define GPIO_BSRR_BR7_Msk                   (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
6560 #define GPIO_BSRR_BR7                       GPIO_BSRR_BR7_Msk
6561 #define GPIO_BSRR_BR8_Pos                   (24U)
6562 #define GPIO_BSRR_BR8_Msk                   (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
6563 #define GPIO_BSRR_BR8                       GPIO_BSRR_BR8_Msk
6564 #define GPIO_BSRR_BR9_Pos                   (25U)
6565 #define GPIO_BSRR_BR9_Msk                   (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
6566 #define GPIO_BSRR_BR9                       GPIO_BSRR_BR9_Msk
6567 #define GPIO_BSRR_BR10_Pos                  (26U)
6568 #define GPIO_BSRR_BR10_Msk                  (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
6569 #define GPIO_BSRR_BR10                      GPIO_BSRR_BR10_Msk
6570 #define GPIO_BSRR_BR11_Pos                  (27U)
6571 #define GPIO_BSRR_BR11_Msk                  (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
6572 #define GPIO_BSRR_BR11                      GPIO_BSRR_BR11_Msk
6573 #define GPIO_BSRR_BR12_Pos                  (28U)
6574 #define GPIO_BSRR_BR12_Msk                  (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
6575 #define GPIO_BSRR_BR12                      GPIO_BSRR_BR12_Msk
6576 #define GPIO_BSRR_BR13_Pos                  (29U)
6577 #define GPIO_BSRR_BR13_Msk                  (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
6578 #define GPIO_BSRR_BR13                      GPIO_BSRR_BR13_Msk
6579 #define GPIO_BSRR_BR14_Pos                  (30U)
6580 #define GPIO_BSRR_BR14_Msk                  (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
6581 #define GPIO_BSRR_BR14                      GPIO_BSRR_BR14_Msk
6582 #define GPIO_BSRR_BR15_Pos                  (31U)
6583 #define GPIO_BSRR_BR15_Msk                  (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
6584 #define GPIO_BSRR_BR15                      GPIO_BSRR_BR15_Msk
6585 
6586 /****************** Bit definition for GPIO_LCKR register *********************/
6587 #define GPIO_LCKR_LCK0_Pos                  (0U)
6588 #define GPIO_LCKR_LCK0_Msk                  (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
6589 #define GPIO_LCKR_LCK0                      GPIO_LCKR_LCK0_Msk
6590 #define GPIO_LCKR_LCK1_Pos                  (1U)
6591 #define GPIO_LCKR_LCK1_Msk                  (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
6592 #define GPIO_LCKR_LCK1                      GPIO_LCKR_LCK1_Msk
6593 #define GPIO_LCKR_LCK2_Pos                  (2U)
6594 #define GPIO_LCKR_LCK2_Msk                  (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
6595 #define GPIO_LCKR_LCK2                      GPIO_LCKR_LCK2_Msk
6596 #define GPIO_LCKR_LCK3_Pos                  (3U)
6597 #define GPIO_LCKR_LCK3_Msk                  (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
6598 #define GPIO_LCKR_LCK3                      GPIO_LCKR_LCK3_Msk
6599 #define GPIO_LCKR_LCK4_Pos                  (4U)
6600 #define GPIO_LCKR_LCK4_Msk                  (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
6601 #define GPIO_LCKR_LCK4                      GPIO_LCKR_LCK4_Msk
6602 #define GPIO_LCKR_LCK5_Pos                  (5U)
6603 #define GPIO_LCKR_LCK5_Msk                  (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
6604 #define GPIO_LCKR_LCK5                      GPIO_LCKR_LCK5_Msk
6605 #define GPIO_LCKR_LCK6_Pos                  (6U)
6606 #define GPIO_LCKR_LCK6_Msk                  (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
6607 #define GPIO_LCKR_LCK6                      GPIO_LCKR_LCK6_Msk
6608 #define GPIO_LCKR_LCK7_Pos                  (7U)
6609 #define GPIO_LCKR_LCK7_Msk                  (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
6610 #define GPIO_LCKR_LCK7                      GPIO_LCKR_LCK7_Msk
6611 #define GPIO_LCKR_LCK8_Pos                  (8U)
6612 #define GPIO_LCKR_LCK8_Msk                  (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
6613 #define GPIO_LCKR_LCK8                      GPIO_LCKR_LCK8_Msk
6614 #define GPIO_LCKR_LCK9_Pos                  (9U)
6615 #define GPIO_LCKR_LCK9_Msk                  (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
6616 #define GPIO_LCKR_LCK9                      GPIO_LCKR_LCK9_Msk
6617 #define GPIO_LCKR_LCK10_Pos                 (10U)
6618 #define GPIO_LCKR_LCK10_Msk                 (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
6619 #define GPIO_LCKR_LCK10                     GPIO_LCKR_LCK10_Msk
6620 #define GPIO_LCKR_LCK11_Pos                 (11U)
6621 #define GPIO_LCKR_LCK11_Msk                 (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
6622 #define GPIO_LCKR_LCK11                     GPIO_LCKR_LCK11_Msk
6623 #define GPIO_LCKR_LCK12_Pos                 (12U)
6624 #define GPIO_LCKR_LCK12_Msk                 (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
6625 #define GPIO_LCKR_LCK12                     GPIO_LCKR_LCK12_Msk
6626 #define GPIO_LCKR_LCK13_Pos                 (13U)
6627 #define GPIO_LCKR_LCK13_Msk                 (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
6628 #define GPIO_LCKR_LCK13                     GPIO_LCKR_LCK13_Msk
6629 #define GPIO_LCKR_LCK14_Pos                 (14U)
6630 #define GPIO_LCKR_LCK14_Msk                 (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
6631 #define GPIO_LCKR_LCK14                     GPIO_LCKR_LCK14_Msk
6632 #define GPIO_LCKR_LCK15_Pos                 (15U)
6633 #define GPIO_LCKR_LCK15_Msk                 (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
6634 #define GPIO_LCKR_LCK15                     GPIO_LCKR_LCK15_Msk
6635 #define GPIO_LCKR_LCKK_Pos                  (16U)
6636 #define GPIO_LCKR_LCKK_Msk                  (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
6637 #define GPIO_LCKR_LCKK                      GPIO_LCKR_LCKK_Msk
6638 
6639 /****************** Bit definition for GPIO_AFRL register *********************/
6640 #define GPIO_AFRL_AFSEL0_Pos                (0U)
6641 #define GPIO_AFRL_AFSEL0_Msk                (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
6642 #define GPIO_AFRL_AFSEL0                    GPIO_AFRL_AFSEL0_Msk
6643 #define GPIO_AFRL_AFSEL0_0                  (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
6644 #define GPIO_AFRL_AFSEL0_1                  (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
6645 #define GPIO_AFRL_AFSEL0_2                  (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
6646 #define GPIO_AFRL_AFSEL0_3                  (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
6647 #define GPIO_AFRL_AFSEL1_Pos                (4U)
6648 #define GPIO_AFRL_AFSEL1_Msk                (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
6649 #define GPIO_AFRL_AFSEL1                    GPIO_AFRL_AFSEL1_Msk
6650 #define GPIO_AFRL_AFSEL1_0                  (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
6651 #define GPIO_AFRL_AFSEL1_1                  (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
6652 #define GPIO_AFRL_AFSEL1_2                  (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
6653 #define GPIO_AFRL_AFSEL1_3                  (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
6654 #define GPIO_AFRL_AFSEL2_Pos                (8U)
6655 #define GPIO_AFRL_AFSEL2_Msk                (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
6656 #define GPIO_AFRL_AFSEL2                    GPIO_AFRL_AFSEL2_Msk
6657 #define GPIO_AFRL_AFSEL2_0                  (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
6658 #define GPIO_AFRL_AFSEL2_1                  (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
6659 #define GPIO_AFRL_AFSEL2_2                  (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
6660 #define GPIO_AFRL_AFSEL2_3                  (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
6661 #define GPIO_AFRL_AFSEL3_Pos                (12U)
6662 #define GPIO_AFRL_AFSEL3_Msk                (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
6663 #define GPIO_AFRL_AFSEL3                    GPIO_AFRL_AFSEL3_Msk
6664 #define GPIO_AFRL_AFSEL3_0                  (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
6665 #define GPIO_AFRL_AFSEL3_1                  (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
6666 #define GPIO_AFRL_AFSEL3_2                  (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
6667 #define GPIO_AFRL_AFSEL3_3                  (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
6668 #define GPIO_AFRL_AFSEL4_Pos                (16U)
6669 #define GPIO_AFRL_AFSEL4_Msk                (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
6670 #define GPIO_AFRL_AFSEL4                    GPIO_AFRL_AFSEL4_Msk
6671 #define GPIO_AFRL_AFSEL4_0                  (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
6672 #define GPIO_AFRL_AFSEL4_1                  (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
6673 #define GPIO_AFRL_AFSEL4_2                  (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
6674 #define GPIO_AFRL_AFSEL4_3                  (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
6675 #define GPIO_AFRL_AFSEL5_Pos                (20U)
6676 #define GPIO_AFRL_AFSEL5_Msk                (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
6677 #define GPIO_AFRL_AFSEL5                    GPIO_AFRL_AFSEL5_Msk
6678 #define GPIO_AFRL_AFSEL5_0                  (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
6679 #define GPIO_AFRL_AFSEL5_1                  (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
6680 #define GPIO_AFRL_AFSEL5_2                  (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
6681 #define GPIO_AFRL_AFSEL5_3                  (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
6682 #define GPIO_AFRL_AFSEL6_Pos                (24U)
6683 #define GPIO_AFRL_AFSEL6_Msk                (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
6684 #define GPIO_AFRL_AFSEL6                    GPIO_AFRL_AFSEL6_Msk
6685 #define GPIO_AFRL_AFSEL6_0                  (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
6686 #define GPIO_AFRL_AFSEL6_1                  (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
6687 #define GPIO_AFRL_AFSEL6_2                  (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
6688 #define GPIO_AFRL_AFSEL6_3                  (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
6689 #define GPIO_AFRL_AFSEL7_Pos                (28U)
6690 #define GPIO_AFRL_AFSEL7_Msk                (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
6691 #define GPIO_AFRL_AFSEL7                    GPIO_AFRL_AFSEL7_Msk
6692 #define GPIO_AFRL_AFSEL7_0                  (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
6693 #define GPIO_AFRL_AFSEL7_1                  (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
6694 #define GPIO_AFRL_AFSEL7_2                  (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
6695 #define GPIO_AFRL_AFSEL7_3                  (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
6696 
6697 /****************** Bit definition for GPIO_AFRH register *********************/
6698 #define GPIO_AFRH_AFSEL8_Pos                (0U)
6699 #define GPIO_AFRH_AFSEL8_Msk                (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
6700 #define GPIO_AFRH_AFSEL8                    GPIO_AFRH_AFSEL8_Msk
6701 #define GPIO_AFRH_AFSEL8_0                  (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
6702 #define GPIO_AFRH_AFSEL8_1                  (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
6703 #define GPIO_AFRH_AFSEL8_2                  (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
6704 #define GPIO_AFRH_AFSEL8_3                  (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
6705 #define GPIO_AFRH_AFSEL9_Pos                (4U)
6706 #define GPIO_AFRH_AFSEL9_Msk                (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
6707 #define GPIO_AFRH_AFSEL9                    GPIO_AFRH_AFSEL9_Msk
6708 #define GPIO_AFRH_AFSEL9_0                  (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
6709 #define GPIO_AFRH_AFSEL9_1                  (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
6710 #define GPIO_AFRH_AFSEL9_2                  (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
6711 #define GPIO_AFRH_AFSEL9_3                  (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
6712 #define GPIO_AFRH_AFSEL10_Pos               (8U)
6713 #define GPIO_AFRH_AFSEL10_Msk               (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
6714 #define GPIO_AFRH_AFSEL10                   GPIO_AFRH_AFSEL10_Msk
6715 #define GPIO_AFRH_AFSEL10_0                 (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
6716 #define GPIO_AFRH_AFSEL10_1                 (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
6717 #define GPIO_AFRH_AFSEL10_2                 (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
6718 #define GPIO_AFRH_AFSEL10_3                 (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
6719 #define GPIO_AFRH_AFSEL11_Pos               (12U)
6720 #define GPIO_AFRH_AFSEL11_Msk               (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
6721 #define GPIO_AFRH_AFSEL11                   GPIO_AFRH_AFSEL11_Msk
6722 #define GPIO_AFRH_AFSEL11_0                 (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
6723 #define GPIO_AFRH_AFSEL11_1                 (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
6724 #define GPIO_AFRH_AFSEL11_2                 (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
6725 #define GPIO_AFRH_AFSEL11_3                 (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
6726 #define GPIO_AFRH_AFSEL12_Pos               (16U)
6727 #define GPIO_AFRH_AFSEL12_Msk               (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
6728 #define GPIO_AFRH_AFSEL12                   GPIO_AFRH_AFSEL12_Msk
6729 #define GPIO_AFRH_AFSEL12_0                 (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
6730 #define GPIO_AFRH_AFSEL12_1                 (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
6731 #define GPIO_AFRH_AFSEL12_2                 (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
6732 #define GPIO_AFRH_AFSEL12_3                 (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
6733 #define GPIO_AFRH_AFSEL13_Pos               (20U)
6734 #define GPIO_AFRH_AFSEL13_Msk               (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
6735 #define GPIO_AFRH_AFSEL13                   GPIO_AFRH_AFSEL13_Msk
6736 #define GPIO_AFRH_AFSEL13_0                 (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
6737 #define GPIO_AFRH_AFSEL13_1                 (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
6738 #define GPIO_AFRH_AFSEL13_2                 (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
6739 #define GPIO_AFRH_AFSEL13_3                 (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
6740 #define GPIO_AFRH_AFSEL14_Pos               (24U)
6741 #define GPIO_AFRH_AFSEL14_Msk               (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
6742 #define GPIO_AFRH_AFSEL14                   GPIO_AFRH_AFSEL14_Msk
6743 #define GPIO_AFRH_AFSEL14_0                 (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
6744 #define GPIO_AFRH_AFSEL14_1                 (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
6745 #define GPIO_AFRH_AFSEL14_2                 (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
6746 #define GPIO_AFRH_AFSEL14_3                 (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
6747 #define GPIO_AFRH_AFSEL15_Pos               (28U)
6748 #define GPIO_AFRH_AFSEL15_Msk               (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
6749 #define GPIO_AFRH_AFSEL15                   GPIO_AFRH_AFSEL15_Msk
6750 #define GPIO_AFRH_AFSEL15_0                 (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
6751 #define GPIO_AFRH_AFSEL15_1                 (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
6752 #define GPIO_AFRH_AFSEL15_2                 (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
6753 #define GPIO_AFRH_AFSEL15_3                 (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
6754 
6755 /******************  Bits definition for GPIO_BRR register  ******************/
6756 #define GPIO_BRR_BR0_Pos                    (0U)
6757 #define GPIO_BRR_BR0_Msk                    (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
6758 #define GPIO_BRR_BR0                        GPIO_BRR_BR0_Msk
6759 #define GPIO_BRR_BR1_Pos                    (1U)
6760 #define GPIO_BRR_BR1_Msk                    (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
6761 #define GPIO_BRR_BR1                        GPIO_BRR_BR1_Msk
6762 #define GPIO_BRR_BR2_Pos                    (2U)
6763 #define GPIO_BRR_BR2_Msk                    (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
6764 #define GPIO_BRR_BR2                        GPIO_BRR_BR2_Msk
6765 #define GPIO_BRR_BR3_Pos                    (3U)
6766 #define GPIO_BRR_BR3_Msk                    (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
6767 #define GPIO_BRR_BR3                        GPIO_BRR_BR3_Msk
6768 #define GPIO_BRR_BR4_Pos                    (4U)
6769 #define GPIO_BRR_BR4_Msk                    (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
6770 #define GPIO_BRR_BR4                        GPIO_BRR_BR4_Msk
6771 #define GPIO_BRR_BR5_Pos                    (5U)
6772 #define GPIO_BRR_BR5_Msk                    (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
6773 #define GPIO_BRR_BR5                        GPIO_BRR_BR5_Msk
6774 #define GPIO_BRR_BR6_Pos                    (6U)
6775 #define GPIO_BRR_BR6_Msk                    (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
6776 #define GPIO_BRR_BR6                        GPIO_BRR_BR6_Msk
6777 #define GPIO_BRR_BR7_Pos                    (7U)
6778 #define GPIO_BRR_BR7_Msk                    (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
6779 #define GPIO_BRR_BR7                        GPIO_BRR_BR7_Msk
6780 #define GPIO_BRR_BR8_Pos                    (8U)
6781 #define GPIO_BRR_BR8_Msk                    (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
6782 #define GPIO_BRR_BR8                        GPIO_BRR_BR8_Msk
6783 #define GPIO_BRR_BR9_Pos                    (9U)
6784 #define GPIO_BRR_BR9_Msk                    (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
6785 #define GPIO_BRR_BR9                        GPIO_BRR_BR9_Msk
6786 #define GPIO_BRR_BR10_Pos                   (10U)
6787 #define GPIO_BRR_BR10_Msk                   (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
6788 #define GPIO_BRR_BR10                       GPIO_BRR_BR10_Msk
6789 #define GPIO_BRR_BR11_Pos                   (11U)
6790 #define GPIO_BRR_BR11_Msk                   (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
6791 #define GPIO_BRR_BR11                       GPIO_BRR_BR11_Msk
6792 #define GPIO_BRR_BR12_Pos                   (12U)
6793 #define GPIO_BRR_BR12_Msk                   (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
6794 #define GPIO_BRR_BR12                       GPIO_BRR_BR12_Msk
6795 #define GPIO_BRR_BR13_Pos                   (13U)
6796 #define GPIO_BRR_BR13_Msk                   (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
6797 #define GPIO_BRR_BR13                       GPIO_BRR_BR13_Msk
6798 #define GPIO_BRR_BR14_Pos                   (14U)
6799 #define GPIO_BRR_BR14_Msk                   (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
6800 #define GPIO_BRR_BR14                       GPIO_BRR_BR14_Msk
6801 #define GPIO_BRR_BR15_Pos                   (15U)
6802 #define GPIO_BRR_BR15_Msk                   (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
6803 #define GPIO_BRR_BR15                       GPIO_BRR_BR15_Msk
6804 
6805 /******************  Bits definition for GPIO_HSLVR register  ******************/
6806 #define GPIO_HSLVR_HSLV0_Pos                (0U)
6807 #define GPIO_HSLVR_HSLV0_Msk                (0x1UL << GPIO_HSLVR_HSLV0_Pos)         /*!< 0x00000001 */
6808 #define GPIO_HSLVR_HSLV0                    GPIO_HSLVR_HSLV0_Msk
6809 #define GPIO_HSLVR_HSLV1_Pos                (1U)
6810 #define GPIO_HSLVR_HSLV1_Msk                (0x1UL << GPIO_HSLVR_HSLV1_Pos)         /*!< 0x00000002 */
6811 #define GPIO_HSLVR_HSLV1                    GPIO_HSLVR_HSLV1_Msk
6812 #define GPIO_HSLVR_HSLV2_Pos                (2U)
6813 #define GPIO_HSLVR_HSLV2_Msk                (0x1UL << GPIO_HSLVR_HSLV2_Pos)         /*!< 0x00000004 */
6814 #define GPIO_HSLVR_HSLV2                    GPIO_HSLVR_HSLV2_Msk
6815 #define GPIO_HSLVR_HSLV3_Pos                (3U)
6816 #define GPIO_HSLVR_HSLV3_Msk                (0x1UL << GPIO_HSLVR_HSLV3_Pos)         /*!< 0x00000008 */
6817 #define GPIO_HSLVR_HSLV3                    GPIO_HSLVR_HSLV3_Msk
6818 #define GPIO_HSLVR_HSLV4_Pos                (4U)
6819 #define GPIO_HSLVR_HSLV4_Msk                (0x1UL << GPIO_HSLVR_HSLV4_Pos)         /*!< 0x00000010 */
6820 #define GPIO_HSLVR_HSLV4                    GPIO_HSLVR_HSLV4_Msk
6821 #define GPIO_HSLVR_HSLV5_Pos                (5U)
6822 #define GPIO_HSLVR_HSLV5_Msk                (0x1UL << GPIO_HSLVR_HSLV5_Pos)         /*!< 0x00000020 */
6823 #define GPIO_HSLVR_HSLV5                    GPIO_HSLVR_HSLV5_Msk
6824 #define GPIO_HSLVR_HSLV6_Pos                (6U)
6825 #define GPIO_HSLVR_HSLV6_Msk                (0x1UL << GPIO_HSLVR_HSLV6_Pos)         /*!< 0x00000040 */
6826 #define GPIO_HSLVR_HSLV6                    GPIO_HSLVR_HSLV6_Msk
6827 #define GPIO_HSLVR_HSLV7_Pos                (7U)
6828 #define GPIO_HSLVR_HSLV7_Msk                (0x1UL << GPIO_HSLVR_HSLV7_Pos)         /*!< 0x00000080 */
6829 #define GPIO_HSLVR_HSLV7                    GPIO_HSLVR_HSLV7_Msk
6830 #define GPIO_HSLVR_HSLV8_Pos                (8U)
6831 #define GPIO_HSLVR_HSLV8_Msk                (0x1UL << GPIO_HSLVR_HSLV8_Pos)         /*!< 0x00000100 */
6832 #define GPIO_HSLVR_HSLV8                    GPIO_HSLVR_HSLV8_Msk
6833 #define GPIO_HSLVR_HSLV9_Pos                (9U)
6834 #define GPIO_HSLVR_HSLV9_Msk                (0x1UL << GPIO_HSLVR_HSLV9_Pos)         /*!< 0x00000200 */
6835 #define GPIO_HSLVR_HSLV9                    GPIO_HSLVR_HSLV9_Msk
6836 #define GPIO_HSLVR_HSLV10_Pos               (10U)
6837 #define GPIO_HSLVR_HSLV10_Msk               (0x1UL << GPIO_HSLVR_HSLV10_Pos)        /*!< 0x00000400 */
6838 #define GPIO_HSLVR_HSLV10                   GPIO_HSLVR_HSLV10_Msk
6839 #define GPIO_HSLVR_HSLV11_Pos               (11U)
6840 #define GPIO_HSLVR_HSLV11_Msk               (x1UL << GPIO_HSLVR_HSLV11_Pos)         /*!< 0x00000800 */
6841 #define GPIO_HSLVR_HSLV11                   GPIO_HSLVR_HSLV11_Msk
6842 #define GPIO_HSLVR_HSLV12_Pos               (12U)
6843 #define GPIO_HSLVR_HSLV12_Msk               (0x1UL << GPIO_HSLVR_HSLV12_Pos)        /*!< 0x00001000 */
6844 #define GPIO_HSLVR_HSLV12                   GPIO_HSLVR_HSLV12_Msk
6845 #define GPIO_HSLVR_HSLV13_Pos               (13U)
6846 #define GPIO_HSLVR_HSLV13_Msk               (0x1UL << GPIO_HSLVR_HSLV13_Pos)        /*!< 0x00002000 */
6847 #define GPIO_HSLVR_HSLV13                   GPIO_HSLVR_HSLV13_Msk
6848 #define GPIO_HSLVR_HSLV14_Pos               (14U)
6849 #define GPIO_HSLVR_HSLV14_Msk               (0x1UL << GPIO_HSLVR_HSLV14_Pos)        /*!< 0x00004000 */
6850 #define GPIO_HSLVR_HSLV14                   GPIO_HSLVR_HSLV14_Msk
6851 #define GPIO_HSLVR_HSLV15_Pos               (15U)
6852 #define GPIO_HSLVR_HSLV15_Msk               (0x1UL << GPIO_HSLVR_HSLV15_Pos)        /*!< 0x00008000 */
6853 #define GPIO_HSLVR_HSLV15                   GPIO_HSLVR_HSLV15_Msk
6854 
6855 /******************  Bits definition for GPIO_SECCFGR register  ******************/
6856 #define GPIO_SECCFGR_SEC0_Pos               (0U)
6857 #define GPIO_SECCFGR_SEC0_Msk               (0x1UL << GPIO_SECCFGR_SEC0_Pos)        /*!< 0x00000001 */
6858 #define GPIO_SECCFGR_SEC0                   GPIO_SECCFGR_SEC0_Msk
6859 #define GPIO_SECCFGR_SEC1_Pos               (1U)
6860 #define GPIO_SECCFGR_SEC1_Msk               (0x1UL << GPIO_SECCFGR_SEC1_Pos)        /*!< 0x00000002 */
6861 #define GPIO_SECCFGR_SEC1                   GPIO_SECCFGR_SEC1_Msk
6862 #define GPIO_SECCFGR_SEC2_Pos               (2U)
6863 #define GPIO_SECCFGR_SEC2_Msk               (0x1UL << GPIO_SECCFGR_SEC2_Pos)        /*!< 0x00000004 */
6864 #define GPIO_SECCFGR_SEC2                   GPIO_SECCFGR_SEC2_Msk
6865 #define GPIO_SECCFGR_SEC3_Pos               (3U)
6866 #define GPIO_SECCFGR_SEC3_Msk               (0x1UL << GPIO_SECCFGR_SEC3_Pos)        /*!< 0x00000008 */
6867 #define GPIO_SECCFGR_SEC3                   GPIO_SECCFGR_SEC3_Msk
6868 #define GPIO_SECCFGR_SEC4_Pos               (4U)
6869 #define GPIO_SECCFGR_SEC4_Msk               (0x1UL << GPIO_SECCFGR_SEC4_Pos)        /*!< 0x00000010 */
6870 #define GPIO_SECCFGR_SEC4                   GPIO_SECCFGR_SEC4_Msk
6871 #define GPIO_SECCFGR_SEC5_Pos               (5U)
6872 #define GPIO_SECCFGR_SEC5_Msk               (0x1UL << GPIO_SECCFGR_SEC5_Pos)        /*!< 0x00000020 */
6873 #define GPIO_SECCFGR_SEC5                   GPIO_SECCFGR_SEC5_Msk
6874 #define GPIO_SECCFGR_SEC6_Pos               (6U)
6875 #define GPIO_SECCFGR_SEC6_Msk               (0x1UL << GPIO_SECCFGR_SEC6_Pos)        /*!< 0x00000040 */
6876 #define GPIO_SECCFGR_SEC6                   GPIO_SECCFGR_SEC6_Msk
6877 #define GPIO_SECCFGR_SEC7_Pos               (7U)
6878 #define GPIO_SECCFGR_SEC7_Msk               (0x1UL << GPIO_SECCFGR_SEC7_Pos)        /*!< 0x00000080 */
6879 #define GPIO_SECCFGR_SEC7                   GPIO_SECCFGR_SEC7_Msk
6880 #define GPIO_SECCFGR_SEC8_Pos               (8U)
6881 #define GPIO_SECCFGR_SEC8_Msk               (0x1UL << GPIO_SECCFGR_SEC8_Pos)        /*!< 0x00000100 */
6882 #define GPIO_SECCFGR_SEC8                   GPIO_SECCFGR_SEC8_Msk
6883 #define GPIO_SECCFGR_SEC9_Pos               (9U)
6884 #define GPIO_SECCFGR_SEC9_Msk               (0x1UL << GPIO_SECCFGR_SEC9_Pos)        /*!< 0x00000200 */
6885 #define GPIO_SECCFGR_SEC9                   GPIO_SECCFGR_SEC9_Msk
6886 #define GPIO_SECCFGR_SEC10_Pos              (10U)
6887 #define GPIO_SECCFGR_SEC10_Msk              (0x1UL << GPIO_SECCFGR_SEC10_Pos)       /*!< 0x00000400 */
6888 #define GPIO_SECCFGR_SEC10                  GPIO_SECCFGR_SEC10_Msk
6889 #define GPIO_SECCFGR_SEC11_Pos              (11U)
6890 #define GPIO_SECCFGR_SEC11_Msk              (x1UL << GPIO_SECCFGR_SEC11_Pos)        /*!< 0x00000800 */
6891 #define GPIO_SECCFGR_SEC11                  GPIO_SECCFGR_SEC11_Msk
6892 #define GPIO_SECCFGR_SEC12_Pos              (12U)
6893 #define GPIO_SECCFGR_SEC12_Msk              (0x1UL << GPIO_SECCFGR_SEC12_Pos)       /*!< 0x00001000 */
6894 #define GPIO_SECCFGR_SEC12                  GPIO_SECCFGR_SEC12_Msk
6895 #define GPIO_SECCFGR_SEC13_Pos              (13U)
6896 #define GPIO_SECCFGR_SEC13_Msk              (0x1UL << GPIO_SECCFGR_SEC13_Pos)       /*!< 0x00002000 */
6897 #define GPIO_SECCFGR_SEC13                  GPIO_SECCFGR_SEC13_Msk
6898 #define GPIO_SECCFGR_SEC14_Pos              (14U)
6899 #define GPIO_SECCFGR_SEC14_Msk              (0x1UL << GPIO_SECCFGR_SEC14_Pos)       /*!< 0x00004000 */
6900 #define GPIO_SECCFGR_SEC14                  GPIO_SECCFGR_SEC14_Msk
6901 #define GPIO_SECCFGR_SEC15_Pos              (15U)
6902 #define GPIO_SECCFGR_SEC15_Msk              (0x1UL << GPIO_SECCFGR_SEC15_Pos)       /*!< 0x00008000 */
6903 #define GPIO_SECCFGR_SEC15                  GPIO_SECCFGR_SEC15_Msk
6904 
6905 /******************************************************************************/
6906 /*                                                                            */
6907 /*                                 ICACHE                                     */
6908 /*                                                                            */
6909 /******************************************************************************/
6910 /******************  Bit definition for ICACHE_CR register  *******************/
6911 #define ICACHE_CR_EN_Pos                    (0U)
6912 #define ICACHE_CR_EN_Msk                    (0x1UL << ICACHE_CR_EN_Pos)             /*!< 0x00000001 */
6913 #define ICACHE_CR_EN                        ICACHE_CR_EN_Msk                        /*!< Enable */
6914 #define ICACHE_CR_CACHEINV_Pos              (1U)
6915 #define ICACHE_CR_CACHEINV_Msk              (0x1UL << ICACHE_CR_CACHEINV_Pos)       /*!< 0x00000002 */
6916 #define ICACHE_CR_CACHEINV                  ICACHE_CR_CACHEINV_Msk                  /*!< Cache invalidation */
6917 #define ICACHE_CR_WAYSEL_Pos                (2U)
6918 #define ICACHE_CR_WAYSEL_Msk                (0x1UL << ICACHE_CR_WAYSEL_Pos)         /*!< 0x00000004 */
6919 #define ICACHE_CR_WAYSEL                    ICACHE_CR_WAYSEL_Msk                    /*!< Ways selection */
6920 #define ICACHE_CR_HITMEN_Pos                (16U)
6921 #define ICACHE_CR_HITMEN_Msk                (0x1UL << ICACHE_CR_HITMEN_Pos)         /*!< 0x00010000 */
6922 #define ICACHE_CR_HITMEN                    ICACHE_CR_HITMEN_Msk                    /*!< Hit monitor enable */
6923 #define ICACHE_CR_MISSMEN_Pos               (17U)
6924 #define ICACHE_CR_MISSMEN_Msk               (0x1UL << ICACHE_CR_MISSMEN_Pos)        /*!< 0x00020000 */
6925 #define ICACHE_CR_MISSMEN                   ICACHE_CR_MISSMEN_Msk                   /*!< Miss monitor enable */
6926 #define ICACHE_CR_HITMRST_Pos               (18U)
6927 #define ICACHE_CR_HITMRST_Msk               (0x1UL << ICACHE_CR_HITMRST_Pos)        /*!< 0x00040000 */
6928 #define ICACHE_CR_HITMRST                   ICACHE_CR_HITMRST_Msk                   /*!< Hit monitor reset */
6929 #define ICACHE_CR_MISSMRST_Pos              (19U)
6930 #define ICACHE_CR_MISSMRST_Msk              (0x1UL << ICACHE_CR_MISSMRST_Pos)       /*!< 0x00080000 */
6931 #define ICACHE_CR_MISSMRST                  ICACHE_CR_MISSMRST_Msk                  /*!< Miss monitor reset */
6932 
6933 /******************  Bit definition for ICACHE_SR register  *******************/
6934 #define ICACHE_SR_BUSYF_Pos                 (0U)
6935 #define ICACHE_SR_BUSYF_Msk                 (0x1UL << ICACHE_SR_BUSYF_Pos)          /*!< 0x00000001 */
6936 #define ICACHE_SR_BUSYF                     ICACHE_SR_BUSYF_Msk                     /*!< Busy flag */
6937 #define ICACHE_SR_BSYENDF_Pos               (1U)
6938 #define ICACHE_SR_BSYENDF_Msk               (0x1UL << ICACHE_SR_BSYENDF_Pos)        /*!< 0x00000002 */
6939 #define ICACHE_SR_BSYENDF                   ICACHE_SR_BSYENDF_Msk                   /*!< Busy end flag */
6940 #define ICACHE_SR_ERRF_Pos                  (2U)
6941 #define ICACHE_SR_ERRF_Msk                  (0x1UL << ICACHE_SR_ERRF_Pos)           /*!< 0x00000004 */
6942 #define ICACHE_SR_ERRF                      ICACHE_SR_ERRF_Msk                      /*!< Cache error flag */
6943 
6944 /******************  Bit definition for ICACHE_IER register  ******************/
6945 #define ICACHE_IER_BSYENDIE_Pos             (1U)
6946 #define ICACHE_IER_BSYENDIE_Msk             (0x1UL << ICACHE_IER_BSYENDIE_Pos)      /*!< 0x00000002 */
6947 #define ICACHE_IER_BSYENDIE                 ICACHE_IER_BSYENDIE_Msk                 /*!< Busy end interrupt enable */
6948 #define ICACHE_IER_ERRIE_Pos                (2U)
6949 #define ICACHE_IER_ERRIE_Msk                (0x1UL << ICACHE_IER_ERRIE_Pos)         /*!< 0x00000004 */
6950 #define ICACHE_IER_ERRIE                    ICACHE_IER_ERRIE_Msk                    /*!< Cache error interrupt enable */
6951 
6952 /******************  Bit definition for ICACHE_FCR register  ******************/
6953 #define ICACHE_FCR_CBSYENDF_Pos             (1U)
6954 #define ICACHE_FCR_CBSYENDF_Msk             (0x1UL << ICACHE_FCR_CBSYENDF_Pos)      /*!< 0x00000002 */
6955 #define ICACHE_FCR_CBSYENDF                 ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
6956 #define ICACHE_FCR_CERRF_Pos                (2U)
6957 #define ICACHE_FCR_CERRF_Msk                (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
6958 #define ICACHE_FCR_CERRF                    ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
6959 
6960 /******************  Bit definition for ICACHE_HMONR register  ****************/
6961 #define ICACHE_HMONR_HITMON_Pos             (0U)
6962 #define ICACHE_HMONR_HITMON_Msk             (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */
6963 #define ICACHE_HMONR_HITMON                 ICACHE_HMONR_HITMON_Msk                 /*!< Cache hit monitor register */
6964 
6965 /******************  Bit definition for ICACHE_MMONR register  ****************/
6966 #define ICACHE_MMONR_MISSMON_Pos            (0U)
6967 #define ICACHE_MMONR_MISSMON_Msk            (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos)  /*!< 0x0000FFFF */
6968 #define ICACHE_MMONR_MISSMON                ICACHE_MMONR_MISSMON_Msk                /*!< Cache miss monitor register */
6969 
6970 
6971 /******************************************************************************/
6972 /*                                                                            */
6973 /*                    Digital Temperature Sensor (DTS)                        */
6974 /*                                                                            */
6975 /******************************************************************************/
6976 
6977 /******************  Bit definition for DTS_CFGR1 register  ******************/
6978 #define DTS_CFGR1_TS1_EN_Pos               (0U)
6979 #define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */
6980 #define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */
6981 #define DTS_CFGR1_TS1_START_Pos            (4U)
6982 #define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */
6983 #define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */
6984 #define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)
6985 #define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */
6986 #define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */
6987 #define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */
6988 #define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */
6989 #define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */
6990 #define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */
6991 #define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)
6992 #define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */
6993 #define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */
6994 #define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */
6995 #define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */
6996 #define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */
6997 #define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */
6998 #define DTS_CFGR1_REFCLK_SEL_Pos           (20U)
6999 #define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */
7000 #define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */
7001 #define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)
7002 #define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */
7003 #define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */
7004 #define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)
7005 #define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */
7006 #define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/
7007 
7008 /******************  Bit definition for DTS_T0VALR1 register  ******************/
7009 #define DTS_T0VALR1_TS1_FMT0_Pos           (0U)
7010 #define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */
7011 #define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */
7012 #define DTS_T0VALR1_TS1_T0_Pos             (16U)
7013 #define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */
7014 #define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */
7015 
7016 /******************  Bit definition for DTS_RAMPVALR register  ******************/
7017 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)
7018 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */
7019 #define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */
7020 
7021 /******************  Bit definition for DTS_ITR1 register      ******************/
7022 #define DTS_ITR1_TS1_LITTHD_Pos            (0U)
7023 #define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */
7024 #define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */
7025 #define DTS_ITR1_TS1_HITTHD_Pos            (16U)
7026 #define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */
7027 #define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */
7028 
7029 /******************  Bit definition for DTS_DR register        ******************/
7030 #define DTS_DR_TS1_MFREQ_Pos               (0U)
7031 #define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */
7032 #define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */
7033 
7034 /******************  Bit definition for DTS_SR register        ******************/
7035 #define DTS_SR_TS1_ITEF_Pos                (0U)
7036 #define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */
7037 #define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */
7038 #define DTS_SR_TS1_ITLF_Pos                (1U)
7039 #define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */
7040 #define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */
7041 #define DTS_SR_TS1_ITHF_Pos                (2U)
7042 #define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */
7043 #define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */
7044 #define DTS_SR_TS1_AITEF_Pos               (4U)
7045 #define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */
7046 #define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */
7047 #define DTS_SR_TS1_AITLF_Pos               (5U)
7048 #define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */
7049 #define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */
7050 #define DTS_SR_TS1_AITHF_Pos               (6U)
7051 #define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */
7052 #define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */
7053 #define DTS_SR_TS1_RDY_Pos                 (15U)
7054 #define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */
7055 #define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */
7056 
7057 /******************  Bit definition for DTS_ITENR register      ******************/
7058 #define DTS_ITENR_TS1_ITEEN_Pos            (0U)
7059 #define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */
7060 #define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */
7061 #define DTS_ITENR_TS1_ITLEN_Pos            (1U)
7062 #define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */
7063 #define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */
7064 #define DTS_ITENR_TS1_ITHEN_Pos            (2U)
7065 #define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */
7066 #define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */
7067 #define DTS_ITENR_TS1_AITEEN_Pos           (4U)
7068 #define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */
7069 #define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */
7070 #define DTS_ITENR_TS1_AITLEN_Pos           (5U)
7071 #define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */
7072 #define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */
7073 #define DTS_ITENR_TS1_AITHEN_Pos           (6U)
7074 #define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */
7075 #define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */
7076 
7077 /******************  Bit definition for DTS_ICIFR register      ******************/
7078 #define DTS_ICIFR_TS1_CITEF_Pos            (0U)
7079 #define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */
7080 #define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */
7081 #define DTS_ICIFR_TS1_CITLF_Pos            (1U)
7082 #define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */
7083 #define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */
7084 #define DTS_ICIFR_TS1_CITHF_Pos            (2U)
7085 #define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */
7086 #define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */
7087 #define DTS_ICIFR_TS1_CAITEF_Pos           (4U)
7088 #define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */
7089 #define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */
7090 #define DTS_ICIFR_TS1_CAITLF_Pos           (5U)
7091 #define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */
7092 #define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */
7093 #define DTS_ICIFR_TS1_CAITHF_Pos           (6U)
7094 #define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */
7095 #define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */
7096 
7097 /******************************************************************************/
7098 /*                                                                            */
7099 /*                                    TIM                                     */
7100 /*                                                                            */
7101 /******************************************************************************/
7102 /*******************  Bit definition for TIM_CR1 register  ********************/
7103 #define TIM_CR1_CEN_Pos                     (0U)
7104 #define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)              /*!< 0x00000001 */
7105 #define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                         /*!<Counter enable */
7106 #define TIM_CR1_UDIS_Pos                    (1U)
7107 #define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)             /*!< 0x00000002 */
7108 #define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                        /*!<Update disable */
7109 #define TIM_CR1_URS_Pos                     (2U)
7110 #define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)              /*!< 0x00000004 */
7111 #define TIM_CR1_URS                         TIM_CR1_URS_Msk                         /*!<Update request source */
7112 #define TIM_CR1_OPM_Pos                     (3U)
7113 #define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)              /*!< 0x00000008 */
7114 #define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                         /*!<One pulse mode */
7115 #define TIM_CR1_DIR_Pos                     (4U)
7116 #define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)              /*!< 0x00000010 */
7117 #define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                         /*!<Direction */
7118 #define TIM_CR1_CMS_Pos                     (5U)
7119 #define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)              /*!< 0x00000060 */
7120 #define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                         /*!<CMS[1:0] bits (Center-aligned mode selection) */
7121 #define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)              /*!< 0x00000020 */
7122 #define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)              /*!< 0x00000040 */
7123 #define TIM_CR1_ARPE_Pos                    (7U)
7124 #define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)             /*!< 0x00000080 */
7125 #define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                        /*!<Auto-reload preload enable */
7126 #define TIM_CR1_CKD_Pos                     (8U)
7127 #define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)              /*!< 0x00000300 */
7128 #define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                         /*!<CKD[1:0] bits (clock division) */
7129 #define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)              /*!< 0x00000100 */
7130 #define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)              /*!< 0x00000200 */
7131 #define TIM_CR1_UIFREMAP_Pos                (11U)
7132 #define TIM_CR1_UIFREMAP_Msk                (0x1UL << TIM_CR1_UIFREMAP_Pos)         /*!< 0x00000800 */
7133 #define TIM_CR1_UIFREMAP                    TIM_CR1_UIFREMAP_Msk                    /*!<Update interrupt flag remap */
7134 #define TIM_CR1_DITHEN_Pos                  (12U)
7135 #define TIM_CR1_DITHEN_Msk                  (0x1UL << TIM_CR1_DITHEN_Pos)           /*!< 0x00001000 */
7136 #define TIM_CR1_DITHEN                      TIM_CR1_DITHEN_Msk                      /*!<Dithering enable */
7137 
7138 /*******************  Bit definition for TIM_CR2 register  ********************/
7139 #define TIM_CR2_CCPC_Pos                    (0U)
7140 #define TIM_CR2_CCPC_Msk                    (0x1UL << TIM_CR2_CCPC_Pos)             /*!< 0x00000001 */
7141 #define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                        /*!<Capture/Compare Preloaded Control */
7142 #define TIM_CR2_CCUS_Pos                    (2U)
7143 #define TIM_CR2_CCUS_Msk                    (0x1UL << TIM_CR2_CCUS_Pos)             /*!< 0x00000004 */
7144 #define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                        /*!<Capture/Compare Control Update Selection */
7145 #define TIM_CR2_CCDS_Pos                    (3U)
7146 #define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)             /*!< 0x00000008 */
7147 #define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                        /*!<Capture/Compare DMA Selection */
7148 #define TIM_CR2_MMS_Pos                     (4U)
7149 #define TIM_CR2_MMS_Msk                     (0x200007UL << TIM_CR2_MMS_Pos)         /*!< 0x02000070 */
7150 #define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                         /*!<MMS[3:0] bits (Master Mode Selection) */
7151 #define TIM_CR2_MMS_0                       (0x000001UL << TIM_CR2_MMS_Pos)         /*!< 0x00000010 */
7152 #define TIM_CR2_MMS_1                       (0x000002UL << TIM_CR2_MMS_Pos)         /*!< 0x00000020 */
7153 #define TIM_CR2_MMS_2                       (0x000004UL << TIM_CR2_MMS_Pos)         /*!< 0x00000040 */
7154 #define TIM_CR2_MMS_3                       (0x200000UL << TIM_CR2_MMS_Pos)         /*!< 0x02000000 */
7155 #define TIM_CR2_TI1S_Pos                    (7U)
7156 #define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)             /*!< 0x00000080 */
7157 #define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                        /*!<TI1 Selection */
7158 #define TIM_CR2_OIS1_Pos                    (8U)
7159 #define TIM_CR2_OIS1_Msk                    (0x1UL << TIM_CR2_OIS1_Pos)             /*!< 0x00000100 */
7160 #define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                        /*!<Output Idle state 1 (OC1 output) */
7161 #define TIM_CR2_OIS1N_Pos                   (9U)
7162 #define TIM_CR2_OIS1N_Msk                   (0x1UL << TIM_CR2_OIS1N_Pos)            /*!< 0x00000200 */
7163 #define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                       /*!<Output Idle state 1 (OC1N output) */
7164 #define TIM_CR2_OIS2_Pos                    (10U)
7165 #define TIM_CR2_OIS2_Msk                    (0x1UL << TIM_CR2_OIS2_Pos)             /*!< 0x00000400 */
7166 #define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                        /*!<Output Idle state 2 (OC2 output) */
7167 #define TIM_CR2_OIS2N_Pos                   (11U)
7168 #define TIM_CR2_OIS2N_Msk                   (0x1UL << TIM_CR2_OIS2N_Pos)            /*!< 0x00000800 */
7169 #define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                       /*!<Output Idle state 2 (OC2N output) */
7170 #define TIM_CR2_OIS3_Pos                    (12U)
7171 #define TIM_CR2_OIS3_Msk                    (0x1UL << TIM_CR2_OIS3_Pos)             /*!< 0x00001000 */
7172 #define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                        /*!<Output Idle state 3 (OC3 output) */
7173 #define TIM_CR2_OIS3N_Pos                   (13U)
7174 #define TIM_CR2_OIS3N_Msk                   (0x1UL << TIM_CR2_OIS3N_Pos)            /*!< 0x00002000 */
7175 #define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                       /*!<Output Idle state 3 (OC3N output) */
7176 #define TIM_CR2_OIS4_Pos                    (14U)
7177 #define TIM_CR2_OIS4_Msk                    (0x1UL << TIM_CR2_OIS4_Pos)             /*!< 0x00004000 */
7178 #define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                        /*!<Output Idle state 4 (OC4 output) */
7179 #define TIM_CR2_OIS4N_Pos                   (15U)
7180 #define TIM_CR2_OIS4N_Msk                   (0x1UL << TIM_CR2_OIS4N_Pos)            /*!< 0x00008000 */
7181 #define TIM_CR2_OIS4N                       TIM_CR2_OIS4N_Msk                       /*!<Output Idle state 4 (OC4N output) */
7182 #define TIM_CR2_OIS5_Pos                    (16U)
7183 #define TIM_CR2_OIS5_Msk                    (0x1UL << TIM_CR2_OIS5_Pos)             /*!< 0x00010000 */
7184 #define TIM_CR2_OIS5                        TIM_CR2_OIS5_Msk                        /*!<Output Idle state 5 (OC5 output) */
7185 #define TIM_CR2_OIS6_Pos                    (18U)
7186 #define TIM_CR2_OIS6_Msk                    (0x1UL << TIM_CR2_OIS6_Pos)             /*!< 0x00040000 */
7187 #define TIM_CR2_OIS6                        TIM_CR2_OIS6_Msk                        /*!<Output Idle state 6 (OC6 output) */
7188 #define TIM_CR2_MMS2_Pos                    (20U)
7189 #define TIM_CR2_MMS2_Msk                    (0xFUL << TIM_CR2_MMS2_Pos)             /*!< 0x00F00000 */
7190 #define TIM_CR2_MMS2                        TIM_CR2_MMS2_Msk                        /*!<MMS[2:0] bits (Master Mode Selection) */
7191 #define TIM_CR2_MMS2_0                      (0x1UL << TIM_CR2_MMS2_Pos)             /*!< 0x00100000 */
7192 #define TIM_CR2_MMS2_1                      (0x2UL << TIM_CR2_MMS2_Pos)             /*!< 0x00200000 */
7193 #define TIM_CR2_MMS2_2                      (0x4UL << TIM_CR2_MMS2_Pos)             /*!< 0x00400000 */
7194 #define TIM_CR2_MMS2_3                      (0x8UL << TIM_CR2_MMS2_Pos)             /*!< 0x00800000 */
7195 
7196 /*******************  Bit definition for TIM_SMCR register  *******************/
7197 #define TIM_SMCR_SMS_Pos                    (0U)
7198 #define TIM_SMCR_SMS_Msk                    (0x10007UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010007 */
7199 #define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                        /*!<SMS[2:0] bits (Slave mode selection) */
7200 #define TIM_SMCR_SMS_0                      (0x00001UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
7201 #define TIM_SMCR_SMS_1                      (0x00002UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
7202 #define TIM_SMCR_SMS_2                      (0x00004UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
7203 #define TIM_SMCR_SMS_3                      (0x10000UL << TIM_SMCR_SMS_Pos)         /*!< 0x00010000 */
7204 #define TIM_SMCR_OCCS_Pos                   (3U)
7205 #define TIM_SMCR_OCCS_Msk                   (0x1UL << TIM_SMCR_OCCS_Pos)            /*!< 0x00000008 */
7206 #define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                       /*!< OCREF clear selection */
7207 #define TIM_SMCR_TS_Pos                     (4U)
7208 #define TIM_SMCR_TS_Msk                     (0x30007UL << TIM_SMCR_TS_Pos)          /*!< 0x00300070 */
7209 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                         /*!<TS[2:0] bits (Trigger selection) */
7210 #define TIM_SMCR_TS_0                       (0x00001UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
7211 #define TIM_SMCR_TS_1                       (0x00002UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
7212 #define TIM_SMCR_TS_2                       (0x00004UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
7213 #define TIM_SMCR_TS_3                       (0x10000UL << TIM_SMCR_TS_Pos)          /*!< 0x00100000 */
7214 #define TIM_SMCR_TS_4                       (0x20000UL << TIM_SMCR_TS_Pos)          /*!< 0x00200000 */
7215 #define TIM_SMCR_MSM_Pos                    (7U)
7216 #define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)             /*!< 0x00000080 */
7217 #define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                        /*!<Master/slave mode */
7218 #define TIM_SMCR_ETF_Pos                    (8U)
7219 #define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)             /*!< 0x00000F00 */
7220 #define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                        /*!<ETF[3:0] bits (External trigger filter) */
7221 #define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000100 */
7222 #define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000200 */
7223 #define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000400 */
7224 #define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)             /*!< 0x00000800 */
7225 #define TIM_SMCR_ETPS_Pos                   (12U)
7226 #define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00003000 */
7227 #define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                       /*!<ETPS[1:0] bits (External trigger prescaler) */
7228 #define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00001000 */
7229 #define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)            /*!< 0x00002000 */
7230 #define TIM_SMCR_ECE_Pos                    (14U)
7231 #define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)             /*!< 0x00004000 */
7232 #define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                        /*!<External clock enable */
7233 #define TIM_SMCR_ETP_Pos                    (15U)
7234 #define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)             /*!< 0x00008000 */
7235 #define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                        /*!<External trigger polarity */
7236 #define TIM_SMCR_SMSPE_Pos                  (24U)
7237 #define TIM_SMCR_SMSPE_Msk                  (0x1UL << TIM_SMCR_SMSPE_Pos)           /*!< 0x02000000 */
7238 #define TIM_SMCR_SMSPE                      TIM_SMCR_SMSPE_Msk                      /*!<SMS preload enable */
7239 #define TIM_SMCR_SMSPS_Pos                  (25U)
7240 #define TIM_SMCR_SMSPS_Msk                  (0x1UL << TIM_SMCR_SMSPS_Pos)           /*!< 0x04000000 */
7241 #define TIM_SMCR_SMSPS                      TIM_SMCR_SMSPS_Msk                      /*!<SMS preload source */
7242 
7243 /*******************  Bit definition for TIM_DIER register  *******************/
7244 #define TIM_DIER_UIE_Pos                    (0U)
7245 #define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)             /*!< 0x00000001 */
7246 #define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                        /*!<Update interrupt enable */
7247 #define TIM_DIER_CC1IE_Pos                  (1U)
7248 #define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)           /*!< 0x00000002 */
7249 #define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                      /*!<Capture/Compare 1 interrupt enable */
7250 #define TIM_DIER_CC2IE_Pos                  (2U)
7251 #define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)           /*!< 0x00000004 */
7252 #define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                      /*!<Capture/Compare 2 interrupt enable */
7253 #define TIM_DIER_CC3IE_Pos                  (3U)
7254 #define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)           /*!< 0x00000008 */
7255 #define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                      /*!<Capture/Compare 3 interrupt enable */
7256 #define TIM_DIER_CC4IE_Pos                  (4U)
7257 #define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)           /*!< 0x00000010 */
7258 #define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                      /*!<Capture/Compare 4 interrupt enable */
7259 #define TIM_DIER_COMIE_Pos                  (5U)
7260 #define TIM_DIER_COMIE_Msk                  (0x1UL << TIM_DIER_COMIE_Pos)           /*!< 0x00000020 */
7261 #define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                      /*!<COM interrupt enable */
7262 #define TIM_DIER_TIE_Pos                    (6U)
7263 #define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)             /*!< 0x00000040 */
7264 #define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                        /*!<Trigger interrupt enable */
7265 #define TIM_DIER_BIE_Pos                    (7U)
7266 #define TIM_DIER_BIE_Msk                    (0x1UL << TIM_DIER_BIE_Pos)             /*!< 0x00000080 */
7267 #define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                        /*!<Break interrupt enable */
7268 #define TIM_DIER_UDE_Pos                    (8U)
7269 #define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)             /*!< 0x00000100 */
7270 #define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                        /*!<Update DMA request enable */
7271 #define TIM_DIER_CC1DE_Pos                  (9U)
7272 #define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)           /*!< 0x00000200 */
7273 #define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                      /*!<Capture/Compare 1 DMA request enable */
7274 #define TIM_DIER_CC2DE_Pos                  (10U)
7275 #define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)           /*!< 0x00000400 */
7276 #define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                      /*!<Capture/Compare 2 DMA request enable */
7277 #define TIM_DIER_CC3DE_Pos                  (11U)
7278 #define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)           /*!< 0x00000800 */
7279 #define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                      /*!<Capture/Compare 3 DMA request enable */
7280 #define TIM_DIER_CC4DE_Pos                  (12U)
7281 #define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)           /*!< 0x00001000 */
7282 #define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                      /*!<Capture/Compare 4 DMA request enable */
7283 #define TIM_DIER_COMDE_Pos                  (13U)
7284 #define TIM_DIER_COMDE_Msk                  (0x1UL << TIM_DIER_COMDE_Pos)           /*!< 0x00002000 */
7285 #define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                      /*!<COM DMA request enable */
7286 #define TIM_DIER_TDE_Pos                    (14U)
7287 #define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)             /*!< 0x00004000 */
7288 #define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                        /*!<Trigger DMA request enable */
7289 #define TIM_DIER_IDXIE_Pos                  (20U)
7290 #define TIM_DIER_IDXIE_Msk                  (0x1UL << TIM_DIER_IDXIE_Pos)           /*!< 0x00100000 */
7291 #define TIM_DIER_IDXIE                      TIM_DIER_IDXIE_Msk                      /*!<Encoder index interrupt enable */
7292 #define TIM_DIER_DIRIE_Pos                  (21U)
7293 #define TIM_DIER_DIRIE_Msk                  (0x1UL << TIM_DIER_DIRIE_Pos)           /*!< 0x00200000 */
7294 #define TIM_DIER_DIRIE                      TIM_DIER_DIRIE_Msk                      /*!<Encoder direction change interrupt enable */
7295 #define TIM_DIER_IERRIE_Pos                 (22U)
7296 #define TIM_DIER_IERRIE_Msk                 (0x1UL << TIM_DIER_IERRIE_Pos)          /*!< 0x00400000 */
7297 #define TIM_DIER_IERRIE                     TIM_DIER_IERRIE_Msk                     /*!<Encoder index error enable */
7298 #define TIM_DIER_TERRIE_Pos                 (23U)
7299 #define TIM_DIER_TERRIE_Msk                 (0x1UL << TIM_DIER_TERRIE_Pos)          /*!< 0x00800000 */
7300 #define TIM_DIER_TERRIE                     TIM_DIER_TERRIE_Msk                     /*!<Encoder transition error enable */
7301 
7302 /********************  Bit definition for TIM_SR register  ********************/
7303 #define TIM_SR_UIF_Pos                      (0U)
7304 #define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)               /*!< 0x00000001 */
7305 #define TIM_SR_UIF                          TIM_SR_UIF_Msk                          /*!<Update interrupt Flag */
7306 #define TIM_SR_CC1IF_Pos                    (1U)
7307 #define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)             /*!< 0x00000002 */
7308 #define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                        /*!<Capture/Compare 1 interrupt Flag */
7309 #define TIM_SR_CC2IF_Pos                    (2U)
7310 #define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)             /*!< 0x00000004 */
7311 #define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                        /*!<Capture/Compare 2 interrupt Flag */
7312 #define TIM_SR_CC3IF_Pos                    (3U)
7313 #define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)             /*!< 0x00000008 */
7314 #define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                        /*!<Capture/Compare 3 interrupt Flag */
7315 #define TIM_SR_CC4IF_Pos                    (4U)
7316 #define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)             /*!< 0x00000010 */
7317 #define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                        /*!<Capture/Compare 4 interrupt Flag */
7318 #define TIM_SR_COMIF_Pos                    (5U)
7319 #define TIM_SR_COMIF_Msk                    (0x1UL << TIM_SR_COMIF_Pos)             /*!< 0x00000020 */
7320 #define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                        /*!<COM interrupt Flag */
7321 #define TIM_SR_TIF_Pos                      (6U)
7322 #define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)               /*!< 0x00000040 */
7323 #define TIM_SR_TIF                          TIM_SR_TIF_Msk                          /*!<Trigger interrupt Flag */
7324 #define TIM_SR_BIF_Pos                      (7U)
7325 #define TIM_SR_BIF_Msk                      (0x1UL << TIM_SR_BIF_Pos)               /*!< 0x00000080 */
7326 #define TIM_SR_BIF                          TIM_SR_BIF_Msk                          /*!<Break interrupt Flag */
7327 #define TIM_SR_B2IF_Pos                     (8U)
7328 #define TIM_SR_B2IF_Msk                     (0x1UL << TIM_SR_B2IF_Pos)              /*!< 0x00000100 */
7329 #define TIM_SR_B2IF                         TIM_SR_B2IF_Msk                         /*!<Break 2 interrupt Flag */
7330 #define TIM_SR_CC1OF_Pos                    (9U)
7331 #define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)             /*!< 0x00000200 */
7332 #define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                        /*!<Capture/Compare 1 Overcapture Flag */
7333 #define TIM_SR_CC2OF_Pos                    (10U)
7334 #define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)             /*!< 0x00000400 */
7335 #define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                        /*!<Capture/Compare 2 Overcapture Flag */
7336 #define TIM_SR_CC3OF_Pos                    (11U)
7337 #define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)             /*!< 0x00000800 */
7338 #define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                        /*!<Capture/Compare 3 Overcapture Flag */
7339 #define TIM_SR_CC4OF_Pos                    (12U)
7340 #define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)             /*!< 0x00001000 */
7341 #define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                        /*!<Capture/Compare 4 Overcapture Flag */
7342 #define TIM_SR_SBIF_Pos                     (13U)
7343 #define TIM_SR_SBIF_Msk                     (0x1UL << TIM_SR_SBIF_Pos)              /*!< 0x00002000 */
7344 #define TIM_SR_SBIF                         TIM_SR_SBIF_Msk                         /*!<System Break interrupt Flag */
7345 #define TIM_SR_CC5IF_Pos                    (16U)
7346 #define TIM_SR_CC5IF_Msk                    (0x1UL << TIM_SR_CC5IF_Pos)             /*!< 0x00010000 */
7347 #define TIM_SR_CC5IF                        TIM_SR_CC5IF_Msk                        /*!<Capture/Compare 5 interrupt Flag */
7348 #define TIM_SR_CC6IF_Pos                    (17U)
7349 #define TIM_SR_CC6IF_Msk                    (0x1UL << TIM_SR_CC6IF_Pos)             /*!< 0x00020000 */
7350 #define TIM_SR_CC6IF                        TIM_SR_CC6IF_Msk                        /*!<Capture/Compare 6 interrupt Flag */
7351 #define TIM_SR_IDXF_Pos                     (20U)
7352 #define TIM_SR_IDXF_Msk                     (0x1UL << TIM_SR_IDXF_Pos)              /*!< 0x00100000 */
7353 #define TIM_SR_IDXF                         TIM_SR_IDXF_Msk                         /*!<Encoder index interrupt flag */
7354 #define TIM_SR_DIRF_Pos                     (21U)
7355 #define TIM_SR_DIRF_Msk                     (0x1UL << TIM_SR_DIRF_Pos)              /*!< 0x00200000 */
7356 #define TIM_SR_DIRF                         TIM_SR_DIRF_Msk                         /*!<Encoder direction change interrupt flag */
7357 #define TIM_SR_IERRF_Pos                    (22U)
7358 #define TIM_SR_IERRF_Msk                    (0x1UL << TIM_SR_IERRF_Pos)             /*!< 0x00400000 */
7359 #define TIM_SR_IERRF                        TIM_SR_IERRF_Msk                        /*!<Encoder index error flag */
7360 #define TIM_SR_TERRF_Pos                    (23U)
7361 #define TIM_SR_TERRF_Msk                    (0x1UL << TIM_SR_TERRF_Pos)             /*!< 0x00800000 */
7362 #define TIM_SR_TERRF                        TIM_SR_TERRF_Msk                        /*!<Encoder transition error flag */
7363 
7364 /*******************  Bit definition for TIM_EGR register  ********************/
7365 #define TIM_EGR_UG_Pos                      (0U)
7366 #define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)               /*!< 0x00000001 */
7367 #define TIM_EGR_UG                          TIM_EGR_UG_Msk                          /*!<Update Generation */
7368 #define TIM_EGR_CC1G_Pos                    (1U)
7369 #define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)             /*!< 0x00000002 */
7370 #define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                        /*!<Capture/Compare 1 Generation */
7371 #define TIM_EGR_CC2G_Pos                    (2U)
7372 #define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)             /*!< 0x00000004 */
7373 #define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                        /*!<Capture/Compare 2 Generation */
7374 #define TIM_EGR_CC3G_Pos                    (3U)
7375 #define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)             /*!< 0x00000008 */
7376 #define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                        /*!<Capture/Compare 3 Generation */
7377 #define TIM_EGR_CC4G_Pos                    (4U)
7378 #define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)             /*!< 0x00000010 */
7379 #define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                        /*!<Capture/Compare 4 Generation */
7380 #define TIM_EGR_COMG_Pos                    (5U)
7381 #define TIM_EGR_COMG_Msk                    (0x1UL << TIM_EGR_COMG_Pos)             /*!< 0x00000020 */
7382 #define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                        /*!<Capture/Compare Control Update Generation */
7383 #define TIM_EGR_TG_Pos                      (6U)
7384 #define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)               /*!< 0x00000040 */
7385 #define TIM_EGR_TG                          TIM_EGR_TG_Msk                          /*!<Trigger Generation */
7386 #define TIM_EGR_BG_Pos                      (7U)
7387 #define TIM_EGR_BG_Msk                      (0x1UL << TIM_EGR_BG_Pos)               /*!< 0x00000080 */
7388 #define TIM_EGR_BG                          TIM_EGR_BG_Msk                          /*!<Break Generation */
7389 #define TIM_EGR_B2G_Pos                     (8U)
7390 #define TIM_EGR_B2G_Msk                     (0x1UL << TIM_EGR_B2G_Pos)              /*!< 0x00000100 */
7391 #define TIM_EGR_B2G                         TIM_EGR_B2G_Msk                         /*!<Break 2 Generation */
7392 
7393 
7394 /******************  Bit definition for TIM_CCMR1 register  *******************/
7395 #define TIM_CCMR1_CC1S_Pos                  (0U)
7396 #define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000003 */
7397 #define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                      /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7398 #define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000001 */
7399 #define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)           /*!< 0x00000002 */
7400 #define TIM_CCMR1_OC1FE_Pos                 (2U)
7401 #define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)          /*!< 0x00000004 */
7402 #define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                     /*!<Output Compare 1 Fast enable */
7403 #define TIM_CCMR1_OC1PE_Pos                 (3U)
7404 #define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)          /*!< 0x00000008 */
7405 #define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                     /*!<Output Compare 1 Preload enable */
7406 #define TIM_CCMR1_OC1M_Pos                  (4U)
7407 #define TIM_CCMR1_OC1M_Msk                  (0x1007UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010070 */
7408 #define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                      /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7409 #define TIM_CCMR1_OC1M_0                    (0x0001UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000010 */
7410 #define TIM_CCMR1_OC1M_1                    (0x0002UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000020 */
7411 #define TIM_CCMR1_OC1M_2                    (0x0004UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00000040 */
7412 #define TIM_CCMR1_OC1M_3                    (0x1000UL << TIM_CCMR1_OC1M_Pos)        /*!< 0x00010000 */
7413 #define TIM_CCMR1_OC1CE_Pos                 (7U)
7414 #define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)          /*!< 0x00000080 */
7415 #define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                     /*!<Output Compare 1 Clear Enable */
7416 #define TIM_CCMR1_CC2S_Pos                  (8U)
7417 #define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000300 */
7418 #define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                      /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7419 #define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000100 */
7420 #define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)           /*!< 0x00000200 */
7421 #define TIM_CCMR1_OC2FE_Pos                 (10U)
7422 #define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)          /*!< 0x00000400 */
7423 #define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                     /*!<Output Compare 2 Fast enable */
7424 #define TIM_CCMR1_OC2PE_Pos                 (11U)
7425 #define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)          /*!< 0x00000800 */
7426 #define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                     /*!<Output Compare 2 Preload enable */
7427 #define TIM_CCMR1_OC2M_Pos                  (12U)
7428 #define TIM_CCMR1_OC2M_Msk                  (0x1007UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01007000 */
7429 #define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                      /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7430 #define TIM_CCMR1_OC2M_0                    (0x0001UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00001000 */
7431 #define TIM_CCMR1_OC2M_1                    (0x0002UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00002000 */
7432 #define TIM_CCMR1_OC2M_2                    (0x0004UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x00004000 */
7433 #define TIM_CCMR1_OC2M_3                    (0x1000UL << TIM_CCMR1_OC2M_Pos)        /*!< 0x01000000 */
7434 #define TIM_CCMR1_OC2CE_Pos                 (15U)
7435 #define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)          /*!< 0x00008000 */
7436 #define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                     /*!<Output Compare 2 Clear Enable */
7437 
7438 /*----------------------------------------------------------------------------*/
7439 #define TIM_CCMR1_IC1PSC_Pos                (2U)
7440 #define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x0000000C */
7441 #define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk                    /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7442 #define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000004 */
7443 #define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)         /*!< 0x00000008 */
7444 #define TIM_CCMR1_IC1F_Pos                  (4U)
7445 #define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)           /*!< 0x000000F0 */
7446 #define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                      /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7447 #define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000010 */
7448 #define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000020 */
7449 #define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000040 */
7450 #define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)           /*!< 0x00000080 */
7451 #define TIM_CCMR1_IC2PSC_Pos                (10U)
7452 #define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000C00 */
7453 #define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk                    /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7454 #define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000400 */
7455 #define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)         /*!< 0x00000800 */
7456 #define TIM_CCMR1_IC2F_Pos                  (12U)
7457 #define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)           /*!< 0x0000F000 */
7458 #define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                      /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7459 #define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00001000 */
7460 #define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00002000 */
7461 #define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00004000 */
7462 #define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)           /*!< 0x00008000 */
7463 
7464 /******************  Bit definition for TIM_CCMR2 register  *******************/
7465 #define TIM_CCMR2_CC3S_Pos                  (0U)
7466 #define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000003 */
7467 #define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                      /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7468 #define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000001 */
7469 #define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)           /*!< 0x00000002 */
7470 #define TIM_CCMR2_OC3FE_Pos                 (2U)
7471 #define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)          /*!< 0x00000004 */
7472 #define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                     /*!<Output Compare 3 Fast enable */
7473 #define TIM_CCMR2_OC3PE_Pos                 (3U)
7474 #define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)          /*!< 0x00000008 */
7475 #define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                     /*!<Output Compare 3 Preload enable */
7476 #define TIM_CCMR2_OC3M_Pos                  (4U)
7477 #define TIM_CCMR2_OC3M_Msk                  (0x1007UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010070 */
7478 #define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                      /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7479 #define TIM_CCMR2_OC3M_0                    (0x0001UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000010 */
7480 #define TIM_CCMR2_OC3M_1                    (0x0002UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000020 */
7481 #define TIM_CCMR2_OC3M_2                    (0x0004UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00000040 */
7482 #define TIM_CCMR2_OC3M_3                    (0x1000UL << TIM_CCMR2_OC3M_Pos)        /*!< 0x00010000 */
7483 #define TIM_CCMR2_OC3CE_Pos                 (7U)
7484 #define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)          /*!< 0x00000080 */
7485 #define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                     /*!<Output Compare 3 Clear Enable */
7486 #define TIM_CCMR2_CC4S_Pos                  (8U)
7487 #define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000300 */
7488 #define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                      /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7489 #define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000100 */
7490 #define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)           /*!< 0x00000200 */
7491 #define TIM_CCMR2_OC4FE_Pos                 (10U)
7492 #define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)          /*!< 0x00000400 */
7493 #define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                     /*!<Output Compare 4 Fast enable */
7494 #define TIM_CCMR2_OC4PE_Pos                 (11U)
7495 #define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)          /*!< 0x00000800 */
7496 #define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                     /*!<Output Compare 4 Preload enable */
7497 #define TIM_CCMR2_OC4M_Pos                  (12U)
7498 #define TIM_CCMR2_OC4M_Msk                  (0x1007UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01007000 */
7499 #define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                      /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7500 #define TIM_CCMR2_OC4M_0                    (0x0001UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00001000 */
7501 #define TIM_CCMR2_OC4M_1                    (0x0002UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00002000 */
7502 #define TIM_CCMR2_OC4M_2                    (0x0004UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x00004000 */
7503 #define TIM_CCMR2_OC4M_3                    (0x1000UL << TIM_CCMR2_OC4M_Pos)        /*!< 0x01000000 */
7504 #define TIM_CCMR2_OC4CE_Pos                 (15U)
7505 #define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)          /*!< 0x00008000 */
7506 #define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                     /*!<Output Compare 4 Clear Enable */
7507 
7508 /*----------------------------------------------------------------------------*/
7509 #define TIM_CCMR2_IC3PSC_Pos                (2U)
7510 #define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x0000000C */
7511 #define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk                    /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7512 #define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000004 */
7513 #define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)         /*!< 0x00000008 */
7514 #define TIM_CCMR2_IC3F_Pos                  (4U)
7515 #define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)           /*!< 0x000000F0 */
7516 #define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                      /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7517 #define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000010 */
7518 #define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000020 */
7519 #define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000040 */
7520 #define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)           /*!< 0x00000080 */
7521 #define TIM_CCMR2_IC4PSC_Pos                (10U)
7522 #define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000C00 */
7523 #define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk                    /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7524 #define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000400 */
7525 #define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)         /*!< 0x00000800 */
7526 #define TIM_CCMR2_IC4F_Pos                  (12U)
7527 #define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)           /*!< 0x0000F000 */
7528 #define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                      /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7529 #define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00001000 */
7530 #define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00002000 */
7531 #define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00004000 */
7532 #define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)           /*!< 0x00008000 */
7533 
7534 /******************  Bit definition for TIM_CCMR3 register  *******************/
7535 #define TIM_CCMR3_OC5FE_Pos                 (2U)
7536 #define TIM_CCMR3_OC5FE_Msk                 (0x1UL << TIM_CCMR3_OC5FE_Pos)          /*!< 0x00000004 */
7537 #define TIM_CCMR3_OC5FE                     TIM_CCMR3_OC5FE_Msk                     /*!<Output Compare 5 Fast enable */
7538 #define TIM_CCMR3_OC5PE_Pos                 (3U)
7539 #define TIM_CCMR3_OC5PE_Msk                 (0x1UL << TIM_CCMR3_OC5PE_Pos)          /*!< 0x00000008 */
7540 #define TIM_CCMR3_OC5PE                     TIM_CCMR3_OC5PE_Msk                     /*!<Output Compare 5 Preload enable */
7541 #define TIM_CCMR3_OC5M_Pos                  (4U)
7542 #define TIM_CCMR3_OC5M_Msk                  (0x1007UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010070 */
7543 #define TIM_CCMR3_OC5M                      TIM_CCMR3_OC5M_Msk                      /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
7544 #define TIM_CCMR3_OC5M_0                    (0x0001UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000010 */
7545 #define TIM_CCMR3_OC5M_1                    (0x0002UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000020 */
7546 #define TIM_CCMR3_OC5M_2                    (0x0004UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00000040 */
7547 #define TIM_CCMR3_OC5M_3                    (0x1000UL << TIM_CCMR3_OC5M_Pos)        /*!< 0x00010000 */
7548 #define TIM_CCMR3_OC5CE_Pos                 (7U)
7549 #define TIM_CCMR3_OC5CE_Msk                 (0x1UL << TIM_CCMR3_OC5CE_Pos)          /*!< 0x00000080 */
7550 #define TIM_CCMR3_OC5CE                     TIM_CCMR3_OC5CE_Msk                     /*!<Output Compare 5 Clear Enable */
7551 #define TIM_CCMR3_OC6FE_Pos                 (10U)
7552 #define TIM_CCMR3_OC6FE_Msk                 (0x1UL << TIM_CCMR3_OC6FE_Pos)          /*!< 0x00000400 */
7553 #define TIM_CCMR3_OC6FE                     TIM_CCMR3_OC6FE_Msk                     /*!<Output Compare 6 Fast enable */
7554 #define TIM_CCMR3_OC6PE_Pos                 (11U)
7555 #define TIM_CCMR3_OC6PE_Msk                 (0x1UL << TIM_CCMR3_OC6PE_Pos)          /*!< 0x00000800 */
7556 #define TIM_CCMR3_OC6PE                     TIM_CCMR3_OC6PE_Msk                     /*!<Output Compare 6 Preload enable */
7557 #define TIM_CCMR3_OC6M_Pos                  (12U)
7558 #define TIM_CCMR3_OC6M_Msk                  (0x1007UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01007000 */
7559 #define TIM_CCMR3_OC6M                      TIM_CCMR3_OC6M_Msk                      /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
7560 #define TIM_CCMR3_OC6M_0                    (0x0001UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00001000 */
7561 #define TIM_CCMR3_OC6M_1                    (0x0002UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00002000 */
7562 #define TIM_CCMR3_OC6M_2                    (0x0004UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x00004000 */
7563 #define TIM_CCMR3_OC6M_3                    (0x1000UL << TIM_CCMR3_OC6M_Pos)        /*!< 0x01000000 */
7564 #define TIM_CCMR3_OC6CE_Pos                 (15U)
7565 #define TIM_CCMR3_OC6CE_Msk                 (0x1UL << TIM_CCMR3_OC6CE_Pos)          /*!< 0x00008000 */
7566 #define TIM_CCMR3_OC6CE                     TIM_CCMR3_OC6CE_Msk                     /*!<Output Compare 6 Clear Enable */
7567 
7568 /*******************  Bit definition for TIM_CCER register  *******************/
7569 #define TIM_CCER_CC1E_Pos                   (0U)
7570 #define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)            /*!< 0x00000001 */
7571 #define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                       /*!<Capture/Compare 1 output enable */
7572 #define TIM_CCER_CC1P_Pos                   (1U)
7573 #define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)            /*!< 0x00000002 */
7574 #define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                       /*!<Capture/Compare 1 output Polarity */
7575 #define TIM_CCER_CC1NE_Pos                  (2U)
7576 #define TIM_CCER_CC1NE_Msk                  (0x1UL << TIM_CCER_CC1NE_Pos)           /*!< 0x00000004 */
7577 #define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                      /*!<Capture/Compare 1 Complementary output enable */
7578 #define TIM_CCER_CC1NP_Pos                  (3U)
7579 #define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)           /*!< 0x00000008 */
7580 #define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                      /*!<Capture/Compare 1 Complementary output Polarity */
7581 #define TIM_CCER_CC2E_Pos                   (4U)
7582 #define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)            /*!< 0x00000010 */
7583 #define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                       /*!<Capture/Compare 2 output enable */
7584 #define TIM_CCER_CC2P_Pos                   (5U)
7585 #define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)            /*!< 0x00000020 */
7586 #define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                       /*!<Capture/Compare 2 output Polarity */
7587 #define TIM_CCER_CC2NE_Pos                  (6U)
7588 #define TIM_CCER_CC2NE_Msk                  (0x1UL << TIM_CCER_CC2NE_Pos)           /*!< 0x00000040 */
7589 #define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                      /*!<Capture/Compare 2 Complementary output enable */
7590 #define TIM_CCER_CC2NP_Pos                  (7U)
7591 #define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)           /*!< 0x00000080 */
7592 #define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                      /*!<Capture/Compare 2 Complementary output Polarity */
7593 #define TIM_CCER_CC3E_Pos                   (8U)
7594 #define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)            /*!< 0x00000100 */
7595 #define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                       /*!<Capture/Compare 3 output enable */
7596 #define TIM_CCER_CC3P_Pos                   (9U)
7597 #define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)            /*!< 0x00000200 */
7598 #define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                       /*!<Capture/Compare 3 output Polarity */
7599 #define TIM_CCER_CC3NE_Pos                  (10U)
7600 #define TIM_CCER_CC3NE_Msk                  (0x1UL << TIM_CCER_CC3NE_Pos)           /*!< 0x00000400 */
7601 #define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                      /*!<Capture/Compare 3 Complementary output enable */
7602 #define TIM_CCER_CC3NP_Pos                  (11U)
7603 #define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)           /*!< 0x00000800 */
7604 #define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                      /*!<Capture/Compare 3 Complementary output Polarity */
7605 #define TIM_CCER_CC4E_Pos                   (12U)
7606 #define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)            /*!< 0x00001000 */
7607 #define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                       /*!<Capture/Compare 4 output enable */
7608 #define TIM_CCER_CC4P_Pos                   (13U)
7609 #define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)            /*!< 0x00002000 */
7610 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                       /*!<Capture/Compare 4 output Polarity */
7611 #define TIM_CCER_CC4NE_Pos                  (14U)
7612 #define TIM_CCER_CC4NE_Msk                  (0x1UL << TIM_CCER_CC4NE_Pos)           /*!< 0x00004000 */
7613 #define TIM_CCER_CC4NE                      TIM_CCER_CC4NE_Msk                      /*!<Capture/Compare 4 Complementary output enable */
7614 #define TIM_CCER_CC4NP_Pos                  (15U)
7615 #define TIM_CCER_CC4NP_Msk                  (0x1UL << TIM_CCER_CC4NP_Pos)           /*!< 0x00008000 */
7616 #define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                      /*!<Capture/Compare 4 Complementary output Polarity */
7617 #define TIM_CCER_CC5E_Pos                   (16U)
7618 #define TIM_CCER_CC5E_Msk                   (0x1UL << TIM_CCER_CC5E_Pos)            /*!< 0x00010000 */
7619 #define TIM_CCER_CC5E                       TIM_CCER_CC5E_Msk                       /*!<Capture/Compare 5 output enable */
7620 #define TIM_CCER_CC5P_Pos                   (17U)
7621 #define TIM_CCER_CC5P_Msk                   (0x1UL << TIM_CCER_CC5P_Pos)            /*!< 0x00020000 */
7622 #define TIM_CCER_CC5P                       TIM_CCER_CC5P_Msk                       /*!<Capture/Compare 5 output Polarity */
7623 #define TIM_CCER_CC6E_Pos                   (20U)
7624 #define TIM_CCER_CC6E_Msk                   (0x1UL << TIM_CCER_CC6E_Pos)            /*!< 0x00100000 */
7625 #define TIM_CCER_CC6E                       TIM_CCER_CC6E_Msk                       /*!<Capture/Compare 6 output enable */
7626 #define TIM_CCER_CC6P_Pos                   (21U)
7627 #define TIM_CCER_CC6P_Msk                   (0x1UL << TIM_CCER_CC6P_Pos)            /*!< 0x00200000 */
7628 #define TIM_CCER_CC6P                       TIM_CCER_CC6P_Msk                       /*!<Capture/Compare 6 output Polarity */
7629 
7630 /*******************  Bit definition for TIM_CNT register  ********************/
7631 #define TIM_CNT_CNT_Pos                     (0U)
7632 #define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)       /*!< 0xFFFFFFFF */
7633 #define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                         /*!<Counter Value */
7634 #define TIM_CNT_UIFCPY_Pos                  (31U)
7635 #define TIM_CNT_UIFCPY_Msk                  (0x1UL << TIM_CNT_UIFCPY_Pos)           /*!< 0x80000000 */
7636 #define TIM_CNT_UIFCPY                      TIM_CNT_UIFCPY_Msk                      /*!<Update interrupt flag copy (if UIFREMAP=1) */
7637 
7638 /*******************  Bit definition for TIM_PSC register  ********************/
7639 #define TIM_PSC_PSC_Pos                     (0U)
7640 #define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)           /*!< 0x0000FFFF */
7641 #define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                         /*!<Prescaler Value */
7642 
7643 /*******************  Bit definition for TIM_ARR register  ********************/
7644 #define TIM_ARR_ARR_Pos                     (0U)
7645 #define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)       /*!< 0xFFFFFFFF */
7646 #define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                         /*!<Actual auto-reload Value */
7647 
7648 /*******************  Bit definition for TIM_RCR register  ********************/
7649 #define TIM_RCR_REP_Pos                     (0U)
7650 #define TIM_RCR_REP_Msk                     (0xFFFFUL << TIM_RCR_REP_Pos)           /*!< 0x0000FFFF */
7651 #define TIM_RCR_REP                         TIM_RCR_REP_Msk                         /*!<Repetition Counter Value */
7652 
7653 /*******************  Bit definition for TIM_CCR1 register  *******************/
7654 #define TIM_CCR1_CCR1_Pos                   (0U)
7655 #define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)         /*!< 0x0000FFFF */
7656 #define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                       /*!<Capture/Compare 1 Value */
7657 
7658 /*******************  Bit definition for TIM_CCR2 register  *******************/
7659 #define TIM_CCR2_CCR2_Pos                   (0U)
7660 #define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)         /*!< 0x0000FFFF */
7661 #define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                       /*!<Capture/Compare 2 Value */
7662 
7663 /*******************  Bit definition for TIM_CCR3 register  *******************/
7664 #define TIM_CCR3_CCR3_Pos                   (0U)
7665 #define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)         /*!< 0x0000FFFF */
7666 #define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                       /*!<Capture/Compare 3 Value */
7667 
7668 /*******************  Bit definition for TIM_CCR4 register  *******************/
7669 #define TIM_CCR4_CCR4_Pos                   (0U)
7670 #define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)         /*!< 0x0000FFFF */
7671 #define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                       /*!<Capture/Compare 4 Value */
7672 
7673 /*******************  Bit definition for TIM_CCR5 register  *******************/
7674 #define TIM_CCR5_CCR5_Pos                   (0U)
7675 #define TIM_CCR5_CCR5_Msk                   (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)     /*!< 0xFFFFFFFF */
7676 #define TIM_CCR5_CCR5                       TIM_CCR5_CCR5_Msk                       /*!<Capture/Compare 5 Value */
7677 #define TIM_CCR5_GC5C1_Pos                  (29U)
7678 #define TIM_CCR5_GC5C1_Msk                  (0x1UL << TIM_CCR5_GC5C1_Pos)           /*!< 0x20000000 */
7679 #define TIM_CCR5_GC5C1                      TIM_CCR5_GC5C1_Msk                      /*!<Group Channel 5 and Channel 1 */
7680 #define TIM_CCR5_GC5C2_Pos                  (30U)
7681 #define TIM_CCR5_GC5C2_Msk                  (0x1UL << TIM_CCR5_GC5C2_Pos)           /*!< 0x40000000 */
7682 #define TIM_CCR5_GC5C2                      TIM_CCR5_GC5C2_Msk                      /*!<Group Channel 5 and Channel 2 */
7683 #define TIM_CCR5_GC5C3_Pos                  (31U)
7684 #define TIM_CCR5_GC5C3_Msk                  (0x1UL << TIM_CCR5_GC5C3_Pos)           /*!< 0x80000000 */
7685 #define TIM_CCR5_GC5C3                      TIM_CCR5_GC5C3_Msk                      /*!<Group Channel 5 and Channel 3 */
7686 
7687 /*******************  Bit definition for TIM_CCR6 register  *******************/
7688 #define TIM_CCR6_CCR6_Pos                   (0U)
7689 #define TIM_CCR6_CCR6_Msk                   (0xFFFFUL << TIM_CCR6_CCR6_Pos)         /*!< 0x0000FFFF */
7690 #define TIM_CCR6_CCR6                       TIM_CCR6_CCR6_Msk                       /*!<Capture/Compare 6 Value */
7691 
7692 /*******************  Bit definition for TIM_BDTR register  *******************/
7693 #define TIM_BDTR_DTG_Pos                    (0U)
7694 #define TIM_BDTR_DTG_Msk                    (0xFFUL << TIM_BDTR_DTG_Pos)            /*!< 0x000000FF */
7695 #define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                        /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7696 #define TIM_BDTR_DTG_0                      (0x01UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000001 */
7697 #define TIM_BDTR_DTG_1                      (0x02UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000002 */
7698 #define TIM_BDTR_DTG_2                      (0x04UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000004 */
7699 #define TIM_BDTR_DTG_3                      (0x08UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000008 */
7700 #define TIM_BDTR_DTG_4                      (0x10UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000010 */
7701 #define TIM_BDTR_DTG_5                      (0x20UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000020 */
7702 #define TIM_BDTR_DTG_6                      (0x40UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000040 */
7703 #define TIM_BDTR_DTG_7                      (0x80UL << TIM_BDTR_DTG_Pos)            /*!< 0x00000080 */
7704 #define TIM_BDTR_LOCK_Pos                   (8U)
7705 #define TIM_BDTR_LOCK_Msk                   (0x3UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000300 */
7706 #define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                       /*!<LOCK[1:0] bits (Lock Configuration) */
7707 #define TIM_BDTR_LOCK_0                     (0x1UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000100 */
7708 #define TIM_BDTR_LOCK_1                     (0x2UL << TIM_BDTR_LOCK_Pos)            /*!< 0x00000200 */
7709 #define TIM_BDTR_OSSI_Pos                   (10U)
7710 #define TIM_BDTR_OSSI_Msk                   (0x1UL << TIM_BDTR_OSSI_Pos)            /*!< 0x00000400 */
7711 #define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                       /*!<Off-State Selection for Idle mode */
7712 #define TIM_BDTR_OSSR_Pos                   (11U)
7713 #define TIM_BDTR_OSSR_Msk                   (0x1UL << TIM_BDTR_OSSR_Pos)            /*!< 0x00000800 */
7714 #define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                       /*!<Off-State Selection for Run mode */
7715 #define TIM_BDTR_BKE_Pos                    (12U)
7716 #define TIM_BDTR_BKE_Msk                    (0x1UL << TIM_BDTR_BKE_Pos)             /*!< 0x00001000 */
7717 #define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                        /*!<Break enable for Break 1 */
7718 #define TIM_BDTR_BKP_Pos                    (13U)
7719 #define TIM_BDTR_BKP_Msk                    (0x1UL << TIM_BDTR_BKP_Pos)             /*!< 0x00002000 */
7720 #define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                        /*!<Break Polarity for Break 1 */
7721 #define TIM_BDTR_AOE_Pos                    (14U)
7722 #define TIM_BDTR_AOE_Msk                    (0x1UL << TIM_BDTR_AOE_Pos)             /*!< 0x00004000 */
7723 #define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                        /*!<Automatic Output enable */
7724 #define TIM_BDTR_MOE_Pos                    (15U)
7725 #define TIM_BDTR_MOE_Msk                    (0x1UL << TIM_BDTR_MOE_Pos)             /*!< 0x00008000 */
7726 #define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                        /*!<Main Output enable */
7727 #define TIM_BDTR_BKF_Pos                    (16U)
7728 #define TIM_BDTR_BKF_Msk                    (0xFUL << TIM_BDTR_BKF_Pos)             /*!< 0x000F0000 */
7729 #define TIM_BDTR_BKF                        TIM_BDTR_BKF_Msk                        /*!<Break Filter for Break 1 */
7730 #define TIM_BDTR_BK2F_Pos                   (20U)
7731 #define TIM_BDTR_BK2F_Msk                   (0xFUL << TIM_BDTR_BK2F_Pos)            /*!< 0x00F00000 */
7732 #define TIM_BDTR_BK2F                       TIM_BDTR_BK2F_Msk                       /*!<Break Filter for Break 2 */
7733 #define TIM_BDTR_BK2E_Pos                   (24U)
7734 #define TIM_BDTR_BK2E_Msk                   (0x1UL << TIM_BDTR_BK2E_Pos)            /*!< 0x01000000 */
7735 #define TIM_BDTR_BK2E                       TIM_BDTR_BK2E_Msk                       /*!<Break enable for Break 2 */
7736 #define TIM_BDTR_BK2P_Pos                   (25U)
7737 #define TIM_BDTR_BK2P_Msk                   (0x1UL << TIM_BDTR_BK2P_Pos)            /*!< 0x02000000 */
7738 #define TIM_BDTR_BK2P                       TIM_BDTR_BK2P_Msk                       /*!<Break Polarity for Break 2 */
7739 #define TIM_BDTR_BKDSRM_Pos                 (26U)
7740 #define TIM_BDTR_BKDSRM_Msk                 (0x1UL << TIM_BDTR_BKDSRM_Pos)          /*!< 0x04000000 */
7741 #define TIM_BDTR_BKDSRM                     TIM_BDTR_BKDSRM_Msk                     /*!<Break disarming/re-arming */
7742 #define TIM_BDTR_BK2DSRM_Pos                (27U)
7743 #define TIM_BDTR_BK2DSRM_Msk                (0x1UL << TIM_BDTR_BK2DSRM_Pos)         /*!< 0x08000000 */
7744 #define TIM_BDTR_BK2DSRM                    TIM_BDTR_BK2DSRM_Msk                    /*!<Break2 disarming/re-arming */
7745 #define TIM_BDTR_BKBID_Pos                  (28U)
7746 #define TIM_BDTR_BKBID_Msk                  (0x1UL << TIM_BDTR_BKBID_Pos)           /*!< 0x10000000 */
7747 #define TIM_BDTR_BKBID                      TIM_BDTR_BKBID_Msk                      /*!<Break BIDirectional */
7748 #define TIM_BDTR_BK2BID_Pos                 (29U)
7749 #define TIM_BDTR_BK2BID_Msk                 (0x1UL << TIM_BDTR_BK2BID_Pos)          /*!< 0x20000000 */
7750 #define TIM_BDTR_BK2BID                     TIM_BDTR_BK2BID_Msk                     /*!<Break2 BIDirectional */
7751 
7752 /*******************  Bit definition for TIM_DCR register  ********************/
7753 #define TIM_DCR_DBA_Pos                     (0U)
7754 #define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)             /*!< 0x0000001F */
7755 #define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                         /*!<DBA[4:0] bits (DMA Base Address) */
7756 #define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)             /*!< 0x00000001 */
7757 #define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)             /*!< 0x00000002 */
7758 #define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)             /*!< 0x00000004 */
7759 #define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)             /*!< 0x00000008 */
7760 #define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)             /*!< 0x00000010 */
7761 #define TIM_DCR_DBL_Pos                     (8U)
7762 #define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)             /*!< 0x00001F00 */
7763 #define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                         /*!<DBL[4:0] bits (DMA Burst Length) */
7764 #define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)             /*!< 0x00000100 */
7765 #define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)             /*!< 0x00000200 */
7766 #define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)             /*!< 0x00000400 */
7767 #define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)             /*!< 0x00000800 */
7768 #define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)             /*!< 0x00001000 */
7769 #define TIM_DCR_DBSS_Pos                    (16U)
7770 #define TIM_DCR_DBSS_Msk                    (0xFUL << TIM_DCR_DBSS_Pos)             /*!< 0x00000F00 */
7771 #define TIM_DCR_DBSS                        TIM_DCR_DBSS_Msk                        /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
7772 #define TIM_DCR_DBSS_0                      (0x01UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000100 */
7773 #define TIM_DCR_DBSS_1                      (0x02UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000200 */
7774 #define TIM_DCR_DBSS_2                      (0x04UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000400 */
7775 #define TIM_DCR_DBSS_3                      (0x08UL << TIM_DCR_DBSS_Pos)            /*!< 0x00000800 */
7776 
7777 /*******************  Bit definition for TIM1_AF1 register  *******************/
7778 #define TIM1_AF1_BKINE_Pos                  (0U)
7779 #define TIM1_AF1_BKINE_Msk                  (0x1UL << TIM1_AF1_BKINE_Pos)           /*!< 0x00000001 */
7780 #define TIM1_AF1_BKINE                      TIM1_AF1_BKINE_Msk                      /*!<BRK BKIN input enable */
7781 #define TIM1_AF1_BKCMP1E_Pos                (1U)
7782 #define TIM1_AF1_BKCMP1E_Msk                (0x1UL << TIM1_AF1_BKCMP1E_Pos)         /*!< 0x00000002 */
7783 #define TIM1_AF1_BKCMP1E                    TIM1_AF1_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
7784 #define TIM1_AF1_BKCMP2E_Pos                (2U)
7785 #define TIM1_AF1_BKCMP2E_Msk                (0x1UL << TIM1_AF1_BKCMP2E_Pos)         /*!< 0x00000004 */
7786 #define TIM1_AF1_BKCMP2E                    TIM1_AF1_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
7787 #define TIM1_AF1_BKDF1BK0E_Pos              (8U)
7788 #define TIM1_AF1_BKDF1BK0E_Msk              (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)       /*!< 0x00000100 */
7789 #define TIM1_AF1_BKDF1BK0E                  TIM1_AF1_BKDF1BK0E_Msk                  /*!<BRK mdf1_break[0](TIM1) or mdf1_break[2](TIM2) enable */
7790 #define TIM1_AF1_BKINP_Pos                  (9U)
7791 #define TIM1_AF1_BKINP_Msk                  (0x1UL << TIM1_AF1_BKINP_Pos)           /*!< 0x00000200 */
7792 #define TIM1_AF1_BKINP                      TIM1_AF1_BKINP_Msk                      /*!<BRK BKIN input polarity */
7793 #define TIM1_AF1_BKCMP1P_Pos                (10U)
7794 #define TIM1_AF1_BKCMP1P_Msk                (0x1UL << TIM1_AF1_BKCMP1P_Pos)         /*!< 0x00000400 */
7795 #define TIM1_AF1_BKCMP1P                    TIM1_AF1_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
7796 #define TIM1_AF1_BKCMP2P_Pos                (11U)
7797 #define TIM1_AF1_BKCMP2P_Msk                (0x1UL << TIM1_AF1_BKCMP2P_Pos)         /*!< 0x00000800 */
7798 #define TIM1_AF1_BKCMP2P                    TIM1_AF1_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
7799 #define TIM1_AF1_ETRSEL_Pos                 (14U)
7800 #define TIM1_AF1_ETRSEL_Msk                 (0xFUL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x0003C000 */
7801 #define TIM1_AF1_ETRSEL                     TIM1_AF1_ETRSEL_Msk                     /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
7802 #define TIM1_AF1_ETRSEL_0                   (0x1UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00004000 */
7803 #define TIM1_AF1_ETRSEL_1                   (0x2UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00008000 */
7804 #define TIM1_AF1_ETRSEL_2                   (0x4UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00010000 */
7805 #define TIM1_AF1_ETRSEL_3                   (0x8UL << TIM1_AF1_ETRSEL_Pos)          /*!< 0x00020000 */
7806 
7807 /*******************  Bit definition for TIM1_AF2 register  *********************/
7808 #define TIM1_AF2_BK2INE_Pos                 (0U)
7809 #define TIM1_AF2_BK2INE_Msk                 (0x1UL << TIM1_AF2_BK2INE_Pos)          /*!< 0x00000001 */
7810 #define TIM1_AF2_BK2INE                     TIM1_AF2_BK2INE_Msk                     /*!<BRK2 BKIN input enable */
7811 #define TIM1_AF2_BK2CMP1E_Pos               (1U)
7812 #define TIM1_AF2_BK2CMP1E_Msk               (0x1UL << TIM1_AF2_BK2CMP1E_Pos)        /*!< 0x00000002 */
7813 #define TIM1_AF2_BK2CMP1E                   TIM1_AF2_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
7814 #define TIM1_AF2_BK2CMP2E_Pos               (2U)
7815 #define TIM1_AF2_BK2CMP2E_Msk               (0x1UL << TIM1_AF2_BK2CMP2E_Pos)        /*!< 0x00000004 */
7816 #define TIM1_AF2_BK2CMP2E                   TIM1_AF2_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
7817 #define TIM1_AF2_BK2DF1BK1E_Pos             (8U)
7818 #define TIM1_AF2_BK2DF1BK1E_Msk             (0x1UL << TIM1_AF2_BK2DF1BK1E_Pos)      /*!< 0x00000100 */
7819 #define TIM1_AF2_BK2DF1BK1E                 TIM1_AF2_BK2DF1BK1E_Msk                 /*!<BRK2 mdf1_break[1](TIM1) or mdf1_break[3](TIM8) enable */
7820 #define TIM1_AF2_BK2INP_Pos                 (9U)
7821 #define TIM1_AF2_BK2INP_Msk                 (0x1UL << TIM1_AF2_BK2INP_Pos)          /*!< 0x00000200 */
7822 #define TIM1_AF2_BK2INP                     TIM1_AF2_BK2INP_Msk                     /*!<BRK2 BKIN input polarity */
7823 #define TIM1_AF2_BK2CMP1P_Pos               (10U)
7824 #define TIM1_AF2_BK2CMP1P_Msk               (0x1UL << TIM1_AF2_BK2CMP1P_Pos)        /*!< 0x00000400 */
7825 #define TIM1_AF2_BK2CMP1P                   TIM1_AF2_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
7826 #define TIM1_AF2_BK2CMP2P_Pos               (11U)
7827 #define TIM1_AF2_BK2CMP2P_Msk               (0x1UL << TIM1_AF2_BK2CMP2P_Pos)        /*!< 0x00000800 */
7828 #define TIM1_AF2_BK2CMP2P                   TIM1_AF2_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
7829 #define TIM1_AF2_OCRSEL_Pos                 (16U)
7830 #define TIM1_AF2_OCRSEL_Msk                 (0x1UL << TIM1_AF2_OCRSEL_Pos)          /*!< 0x00010000 */
7831 #define TIM1_AF2_OCRSEL                     TIM1_AF2_OCRSEL_Msk                     /*!<OCREF_CLR source selection */
7832 #define TIM1_AF2_OCRSEL_0                   (0x1UL << TIM1_AF2_OCRSEL_Pos)          /*!< 0x00010000 */
7833 
7834 /*******************  Bit definition for TIM_TISEL register  *********************/
7835 #define TIM_TISEL_TI1SEL_Pos                (0U)
7836 #define TIM_TISEL_TI1SEL_Msk                (0xFUL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x0000000F */
7837 #define TIM_TISEL_TI1SEL                    TIM_TISEL_TI1SEL_Msk                    /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
7838 #define TIM_TISEL_TI1SEL_0                  (0x1UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000001 */
7839 #define TIM_TISEL_TI1SEL_1                  (0x2UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000002 */
7840 #define TIM_TISEL_TI1SEL_2                  (0x4UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000004 */
7841 #define TIM_TISEL_TI1SEL_3                  (0x8UL << TIM_TISEL_TI1SEL_Pos)         /*!< 0x00000008 */
7842 #define TIM_TISEL_TI2SEL_Pos                (8U)
7843 #define TIM_TISEL_TI2SEL_Msk                (0xFUL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000F00 */
7844 #define TIM_TISEL_TI2SEL                    TIM_TISEL_TI2SEL_Msk                    /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
7845 #define TIM_TISEL_TI2SEL_0                  (0x1UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000100 */
7846 #define TIM_TISEL_TI2SEL_1                  (0x2UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000200 */
7847 #define TIM_TISEL_TI2SEL_2                  (0x4UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000400 */
7848 #define TIM_TISEL_TI2SEL_3                  (0x8UL << TIM_TISEL_TI2SEL_Pos)         /*!< 0x00000800 */
7849 #define TIM_TISEL_TI3SEL_Pos                (16U)
7850 #define TIM_TISEL_TI3SEL_Msk                (0xFUL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x000F0000 */
7851 #define TIM_TISEL_TI3SEL                    TIM_TISEL_TI3SEL_Msk                    /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
7852 #define TIM_TISEL_TI3SEL_0                  (0x1UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00010000 */
7853 #define TIM_TISEL_TI3SEL_1                  (0x2UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00020000 */
7854 #define TIM_TISEL_TI3SEL_2                  (0x4UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00040000 */
7855 #define TIM_TISEL_TI3SEL_3                  (0x8UL << TIM_TISEL_TI3SEL_Pos)         /*!< 0x00080000 */
7856 #define TIM_TISEL_TI4SEL_Pos                (24U)
7857 #define TIM_TISEL_TI4SEL_Msk                (0xFUL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x0F000000 */
7858 #define TIM_TISEL_TI4SEL                    TIM_TISEL_TI4SEL_Msk                    /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
7859 #define TIM_TISEL_TI4SEL_0                  (0x1UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x01000000 */
7860 #define TIM_TISEL_TI4SEL_1                  (0x2UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x02000000 */
7861 #define TIM_TISEL_TI4SEL_2                  (0x4UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x04000000 */
7862 #define TIM_TISEL_TI4SEL_3                  (0x8UL << TIM_TISEL_TI4SEL_Pos)         /*!< 0x08000000 */
7863 
7864 /*******************  Bit definition for TIM_DTR2 register  *********************/
7865 #define TIM_DTR2_DTGF_Pos                   (0U)
7866 #define TIM_DTR2_DTGF_Msk                   (0xFFUL << TIM_DTR2_DTGF_Pos)           /*!< 0x0000000F */
7867 #define TIM_DTR2_DTGF                       TIM_DTR2_DTGF_Msk                       /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
7868 #define TIM_DTR2_DTGF_0                     (0x01UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000001 */
7869 #define TIM_DTR2_DTGF_1                     (0x02UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000002 */
7870 #define TIM_DTR2_DTGF_2                     (0x04UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000004 */
7871 #define TIM_DTR2_DTGF_3                     (0x08UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000008 */
7872 #define TIM_DTR2_DTGF_4                     (0x10UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000010 */
7873 #define TIM_DTR2_DTGF_5                     (0x20UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000020 */
7874 #define TIM_DTR2_DTGF_6                     (0x40UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000040 */
7875 #define TIM_DTR2_DTGF_7                     (0x80UL << TIM_DTR2_DTGF_Pos)           /*!< 0x00000080 */
7876 #define TIM_DTR2_DTAE_Pos                   (16U)
7877 #define TIM_DTR2_DTAE_Msk                   (0x1UL << TIM_DTR2_DTAE_Pos)            /*!< 0x00004000 */
7878 #define TIM_DTR2_DTAE                       TIM_DTR2_DTAE_Msk                       /*!<Deadtime asymmetric enable */
7879 #define TIM_DTR2_DTPE_Pos                   (17U)
7880 #define TIM_DTR2_DTPE_Msk                   (0x1UL << TIM_DTR2_DTPE_Pos)            /*!< 0x00008000 */
7881 #define TIM_DTR2_DTPE                       TIM_DTR2_DTPE_Msk                       /*!<Deadtime prelaod enable */
7882 
7883 /*******************  Bit definition for TIM_ECR register  *********************/
7884 #define TIM_ECR_IE_Pos                      (0U)
7885 #define TIM_ECR_IE_Msk                      (0x1UL << TIM_ECR_IE_Pos)               /*!< 0x00000001 */
7886 #define TIM_ECR_IE                          TIM_ECR_IE_Msk                          /*!<Index enable */
7887 #define TIM_ECR_IDIR_Pos                    (1U)
7888 #define TIM_ECR_IDIR_Msk                    (0x3UL << TIM_ECR_IDIR_Pos)             /*!< 0x00000006 */
7889 #define TIM_ECR_IDIR                        TIM_ECR_IDIR_Msk                        /*!<IDIR[1:0] bits (Index direction)*/
7890 #define TIM_ECR_IDIR_0                      (0x01UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000001 */
7891 #define TIM_ECR_IDIR_1                      (0x02UL << TIM_ECR_IDIR_Pos)            /*!< 0x00000002 */
7892 #define TIM_ECR_IBLK_Pos                    (3U)
7893 #define TIM_ECR_IBLK_Msk                    (0x5UL << TIM_ECR_IBLK_Pos)             /*!< 0x00000018 */
7894 #define TIM_ECR_IBLK                        TIM_ECR_IBLK_Msk                        /*!<IBLK[1:0] bits (Index blanking)*/
7895 #define TIM_ECR_IBLK_0                      (0x01UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000008 */
7896 #define TIM_ECR_IBLK_1                      (0x02UL << TIM_ECR_IBLK_Pos)            /*!< 0x00000010 */
7897 #define TIM_ECR_FIDX_Pos                    (5U)
7898 #define TIM_ECR_FIDX_Msk                    (0x1UL << TIM_ECR_FIDX_Pos)             /*!< 0x00000020 */
7899 #define TIM_ECR_FIDX                        TIM_ECR_FIDX_Msk                        /*!<First index enable */
7900 #define TIM_ECR_IPOS_Pos                    (6U)
7901 #define TIM_ECR_IPOS_Msk                    (0x3UL << TIM_ECR_IPOS_Pos)             /*!< 0x0000000C0 */
7902 #define TIM_ECR_IPOS                        TIM_ECR_IPOS_Msk                        /*!<IPOS[1:0] bits (Index positioning)*/
7903 #define TIM_ECR_IPOS_0                      (0x01UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000001 */
7904 #define TIM_ECR_IPOS_1                      (0x02UL << TIM_ECR_IPOS_Pos)            /*!< 0x00000002 */
7905 #define TIM_ECR_PW_Pos                      (16U)
7906 #define TIM_ECR_PW_Msk                      (0xFFUL << TIM_ECR_PW_Pos)              /*!< 0x00FF0000 */
7907 #define TIM_ECR_PW                          TIM_ECR_PW_Msk                          /*!<PW[7:0] bits (Pulse width)*/
7908 #define TIM_ECR_PW_0                        (0x01UL << TIM_ECR_PW_Pos)              /*!< 0x00010000 */
7909 #define TIM_ECR_PW_1                        (0x02UL << TIM_ECR_PW_Pos)              /*!< 0x00020000 */
7910 #define TIM_ECR_PW_2                        (0x04UL << TIM_ECR_PW_Pos)              /*!< 0x00040000 */
7911 #define TIM_ECR_PW_3                        (0x08UL << TIM_ECR_PW_Pos)              /*!< 0x00080000 */
7912 #define TIM_ECR_PW_4                        (0x10UL << TIM_ECR_PW_Pos)              /*!< 0x00100000 */
7913 #define TIM_ECR_PW_5                        (0x20UL << TIM_ECR_PW_Pos)              /*!< 0x00200000 */
7914 #define TIM_ECR_PW_6                        (0x40UL << TIM_ECR_PW_Pos)              /*!< 0x00400000 */
7915 #define TIM_ECR_PW_7                        (0x80UL << TIM_ECR_PW_Pos)              /*!< 0x00800000 */
7916 #define TIM_ECR_PWPRSC_Pos                  (24U)
7917 #define TIM_ECR_PWPRSC_Msk                  (0x7UL << TIM_ECR_PWPRSC_Pos)           /*!< 0x07000000 */
7918 #define TIM_ECR_PWPRSC                      TIM_ECR_PWPRSC_Msk                      /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
7919 #define TIM_ECR_PWPRSC_0                    (0x01UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x01000000 */
7920 #define TIM_ECR_PWPRSC_1                    (0x02UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x02000000 */
7921 #define TIM_ECR_PWPRSC_2                    (0x04UL << TIM_ECR_PWPRSC_Pos)          /*!< 0x04000000 */
7922 
7923 /*******************  Bit definition for TIM_DMAR register  *******************/
7924 #define TIM_DMAR_DMAB_Pos                   (0U)
7925 #define TIM_DMAR_DMAB_Msk                   (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0xFFFFFFFF */
7926 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                       /*!<DMA register for burst accesses */
7927 
7928 
7929 /******************************************************************************/
7930 /*                                                                            */
7931 /*                         Low Power Timer (LPTIM)                            */
7932 /*                                                                            */
7933 /******************************************************************************/
7934 /******************  Bit definition for LPTIM_ISR register  *******************/
7935 #define LPTIM_ISR_CC1IF_Pos                 (0U)
7936 #define LPTIM_ISR_CC1IF_Msk                 (0x1UL << LPTIM_ISR_CC1IF_Pos)          /*!< 0x00000001 */
7937 #define LPTIM_ISR_CC1IF                     LPTIM_ISR_CC1IF_Msk                     /*!< Capture/Compare 1 interrupt flag */
7938 #define LPTIM_ISR_ARRM_Pos                  (1U)
7939 #define LPTIM_ISR_ARRM_Msk                  (0x1UL << LPTIM_ISR_ARRM_Pos)           /*!< 0x00000002 */
7940 #define LPTIM_ISR_ARRM                      LPTIM_ISR_ARRM_Msk                      /*!< Autoreload match */
7941 #define LPTIM_ISR_EXTTRIG_Pos               (2U)
7942 #define LPTIM_ISR_EXTTRIG_Msk               (0x1UL << LPTIM_ISR_EXTTRIG_Pos)        /*!< 0x00000004 */
7943 #define LPTIM_ISR_EXTTRIG                   LPTIM_ISR_EXTTRIG_Msk                   /*!< External trigger edge event */
7944 #define LPTIM_ISR_CMP1OK_Pos                (3U)
7945 #define LPTIM_ISR_CMP1OK_Msk                (0x1UL << LPTIM_ISR_CMP1OK_Pos)         /*!< 0x00000008 */
7946 #define LPTIM_ISR_CMP1OK                    LPTIM_ISR_CMP1OK_Msk                    /*!< Compare register 1 update OK */
7947 #define LPTIM_ISR_ARROK_Pos                 (4U)
7948 #define LPTIM_ISR_ARROK_Msk                 (0x1UL << LPTIM_ISR_ARROK_Pos)          /*!< 0x00000010 */
7949 #define LPTIM_ISR_ARROK                     LPTIM_ISR_ARROK_Msk                     /*!< Autoreload register update OK */
7950 #define LPTIM_ISR_UP_Pos                    (5U)
7951 #define LPTIM_ISR_UP_Msk                    (0x1UL << LPTIM_ISR_UP_Pos)             /*!< 0x00000020 */
7952 #define LPTIM_ISR_UP                        LPTIM_ISR_UP_Msk                        /*!< Counter direction change down to up */
7953 #define LPTIM_ISR_DOWN_Pos                  (6U)
7954 #define LPTIM_ISR_DOWN_Msk                  (0x1UL << LPTIM_ISR_DOWN_Pos)           /*!< 0x00000040 */
7955 #define LPTIM_ISR_DOWN                      LPTIM_ISR_DOWN_Msk                      /*!< Counter direction change up to down */
7956 #define LPTIM_ISR_UE_Pos                    (7U)
7957 #define LPTIM_ISR_UE_Msk                    (0x1UL << LPTIM_ISR_UE_Pos)             /*!< 0x00000080 */
7958 #define LPTIM_ISR_UE                        LPTIM_ISR_UE_Msk                        /*!< Update event */
7959 #define LPTIM_ISR_REPOK_Pos                 (8U)
7960 #define LPTIM_ISR_REPOK_Msk                 (0x1UL << LPTIM_ISR_REPOK_Pos)          /*!< 0x00000100 */
7961 #define LPTIM_ISR_REPOK                     LPTIM_ISR_REPOK_Msk                     /*!< Repetition register update OK */
7962 #define LPTIM_ISR_CC2IF_Pos                 (9U)
7963 #define LPTIM_ISR_CC2IF_Msk                 (0x1UL << LPTIM_ISR_CC2IF_Pos)          /*!< 0x00000200 */
7964 #define LPTIM_ISR_CC2IF                     LPTIM_ISR_CC2IF_Msk                     /*!< Capture/Compare 2 interrupt flag */
7965 #define LPTIM_ISR_CC1OF_Pos                 (12U)
7966 #define LPTIM_ISR_CC1OF_Msk                 (0x1UL << LPTIM_ISR_CC1OF_Pos)          /*!< 0x00001000 */
7967 #define LPTIM_ISR_CC1OF                     LPTIM_ISR_CC1OF_Msk                     /*!< Capture/Compare 1 over-capture flag */
7968 #define LPTIM_ISR_CC2OF_Pos                 (13U)
7969 #define LPTIM_ISR_CC2OF_Msk                 (0x1UL << LPTIM_ISR_CC2OF_Pos)          /*!< 0x00002000 */
7970 #define LPTIM_ISR_CC2OF                     LPTIM_ISR_CC2OF_Msk                     /*!< Capture/Compare 2 over-capture flag */
7971 #define LPTIM_ISR_CMP2OK_Pos                (19U)
7972 #define LPTIM_ISR_CMP2OK_Msk                (0x1UL << LPTIM_ISR_CMP2OK_Pos)         /*!< 0x00080000 */
7973 #define LPTIM_ISR_CMP2OK                    LPTIM_ISR_CMP2OK_Msk                    /*!< Compare register 2 update OK */
7974 #define LPTIM_ISR_DIEROK_Pos                (24U)
7975 #define LPTIM_ISR_DIEROK_Msk                (0x1UL << LPTIM_ISR_DIEROK_Pos)         /*!< 0x01000000 */
7976 #define LPTIM_ISR_DIEROK                    LPTIM_ISR_DIEROK_Msk                    /*!< DMA & interrupt enable update OK */
7977 
7978 /******************  Bit definition for LPTIM_ICR register  *******************/
7979 #define LPTIM_ICR_CC1CF_Pos                 (0U)
7980 #define LPTIM_ICR_CC1CF_Msk                 (0x1UL << LPTIM_ICR_CC1CF_Pos)          /*!< 0x00000001 */
7981 #define LPTIM_ICR_CC1CF                     LPTIM_ICR_CC1CF_Msk                     /*!< Capture/Compare 1 clear flag  */
7982 #define LPTIM_ICR_ARRMCF_Pos                (1U)
7983 #define LPTIM_ICR_ARRMCF_Msk                (0x1UL << LPTIM_ICR_ARRMCF_Pos)         /*!< 0x00000002 */
7984 #define LPTIM_ICR_ARRMCF                    LPTIM_ICR_ARRMCF_Msk                    /*!< Autoreload match clear flag */
7985 #define LPTIM_ICR_EXTTRIGCF_Pos             (2U)
7986 #define LPTIM_ICR_EXTTRIGCF_Msk             (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)      /*!< 0x00000004 */
7987 #define LPTIM_ICR_EXTTRIGCF                 LPTIM_ICR_EXTTRIGCF_Msk                 /*!< External trigger edge event clear flag */
7988 #define LPTIM_ICR_CMP1OKCF_Pos              (3U)
7989 #define LPTIM_ICR_CMP1OKCF_Msk              (0x1UL << LPTIM_ICR_CMP1OKCF_Pos)       /*!< 0x00000008 */
7990 #define LPTIM_ICR_CMP1OKCF                  LPTIM_ICR_CMP1OKCF_Msk                  /*!< Compare register 1 update OK clear flag */
7991 #define LPTIM_ICR_ARROKCF_Pos               (4U)
7992 #define LPTIM_ICR_ARROKCF_Msk               (0x1UL << LPTIM_ICR_ARROKCF_Pos)        /*!< 0x00000010 */
7993 #define LPTIM_ICR_ARROKCF                   LPTIM_ICR_ARROKCF_Msk                   /*!< Autoreload register update OK clear flag */
7994 #define LPTIM_ICR_UPCF_Pos                  (5U)
7995 #define LPTIM_ICR_UPCF_Msk                  (0x1UL << LPTIM_ICR_UPCF_Pos)           /*!< 0x00000020 */
7996 #define LPTIM_ICR_UPCF                      LPTIM_ICR_UPCF_Msk                      /*!< Counter direction change down to up clear flag */
7997 #define LPTIM_ICR_DOWNCF_Pos                (6U)
7998 #define LPTIM_ICR_DOWNCF_Msk                (0x1UL << LPTIM_ICR_DOWNCF_Pos)         /*!< 0x00000040 */
7999 #define LPTIM_ICR_DOWNCF                    LPTIM_ICR_DOWNCF_Msk                    /*!< Counter direction change up to down clear flag */
8000 #define LPTIM_ICR_UECF_Pos                  (7U)
8001 #define LPTIM_ICR_UECF_Msk                  (0x1UL << LPTIM_ICR_UECF_Pos)           /*!< 0x00000080 */
8002 #define LPTIM_ICR_UECF                      LPTIM_ICR_UECF_Msk                      /*!< Update event clear flag */
8003 #define LPTIM_ICR_REPOKCF_Pos               (8U)
8004 #define LPTIM_ICR_REPOKCF_Msk               (0x1UL << LPTIM_ICR_REPOKCF_Pos)        /*!< 0x00000100 */
8005 #define LPTIM_ICR_REPOKCF                   LPTIM_ICR_REPOKCF_Msk                   /*!< Repetition register update OK clear flag */
8006 #define LPTIM_ICR_CC2CF_Pos                 (9U)
8007 #define LPTIM_ICR_CC2CF_Msk                 (0x1UL << LPTIM_ICR_CC2CF_Pos)          /*!< 0x00000200 */
8008 #define LPTIM_ICR_CC2CF                     LPTIM_ICR_CC2CF_Msk                     /*!< Capture/Compare 2 clear flag  */
8009 #define LPTIM_ICR_CC1OCF_Pos                (12U)
8010 #define LPTIM_ICR_CC1OCF_Msk                (0x1UL << LPTIM_ICR_CC1OCF_Pos)         /*!< 0x00001000 */
8011 #define LPTIM_ICR_CC1OCF                    LPTIM_ICR_CC1OCF_Msk                    /*!< Capture/Compare 1 over-capture clear flag */
8012 #define LPTIM_ICR_CC2OCF_Pos                (13U)
8013 #define LPTIM_ICR_CC2OCF_Msk                (0x1UL << LPTIM_ICR_CC2OCF_Pos)         /*!< 0x00002000 */
8014 #define LPTIM_ICR_CC2OCF                    LPTIM_ICR_CC2OCF_Msk                    /*!< Capture/Compare 2 over-capture clear flag */
8015 #define LPTIM_ICR_CMP2OKCF_Pos              (19U)
8016 #define LPTIM_ICR_CMP2OKCF_Msk              (0x1UL << LPTIM_ICR_CMP2OKCF_Pos)       /*!< 0x00080000 */
8017 #define LPTIM_ICR_CMP2OKCF                  LPTIM_ICR_CMP2OKCF_Msk                  /*!< Compare register 2 update OK clear flag */
8018 #define LPTIM_ICR_DIEROKCF_Pos              (24U)
8019 #define LPTIM_ICR_DIEROKCF_Msk              (0x1UL << LPTIM_ICR_DIEROKCF_Pos)       /*!< 0x01000000 */
8020 #define LPTIM_ICR_DIEROKCF                  LPTIM_ICR_DIEROKCF_Msk                  /*!< Interrupt enable register update OK clear flag */
8021 
8022 /******************  Bit definition for LPTIM_DIER register *******************/
8023 #define LPTIM_DIER_CC1IE_Pos                (0U)
8024 #define LPTIM_DIER_CC1IE_Msk                (0x1UL << LPTIM_DIER_CC1IE_Pos)         /*!< 0x00000001 */
8025 #define LPTIM_DIER_CC1IE                    LPTIM_DIER_CC1IE_Msk                    /*!< Compare/Compare interrupt enable */
8026 #define LPTIM_DIER_ARRMIE_Pos               (1U)
8027 #define LPTIM_DIER_ARRMIE_Msk               (0x1UL << LPTIM_DIER_ARRMIE_Pos)        /*!< 0x00000002 */
8028 #define LPTIM_DIER_ARRMIE                   LPTIM_DIER_ARRMIE_Msk                   /*!< Autoreload match interrupt enable */
8029 #define LPTIM_DIER_EXTTRIGIE_Pos            (2U)
8030 #define LPTIM_DIER_EXTTRIGIE_Msk            (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos)     /*!< 0x00000004 */
8031 #define LPTIM_DIER_EXTTRIGIE                LPTIM_DIER_EXTTRIGIE_Msk                /*!< External trigger edge event interrupt enable */
8032 #define LPTIM_DIER_CMP1OKIE_Pos             (3U)
8033 #define LPTIM_DIER_CMP1OKIE_Msk             (0x1UL << LPTIM_DIER_CMP1OKIE_Pos)      /*!< 0x00000008 */
8034 #define LPTIM_DIER_CMP1OKIE                 LPTIM_DIER_CMP1OKIE_Msk                 /*!< Compare register 1 update OK interrupt enable */
8035 #define LPTIM_DIER_ARROKIE_Pos              (4U)
8036 #define LPTIM_DIER_ARROKIE_Msk              (0x1UL << LPTIM_DIER_ARROKIE_Pos)       /*!< 0x00000010 */
8037 #define LPTIM_DIER_ARROKIE                  LPTIM_DIER_ARROKIE_Msk                  /*!< Autoreload register update OK interrupt enable */
8038 #define LPTIM_DIER_UPIE_Pos                 (5U)
8039 #define LPTIM_DIER_UPIE_Msk                 (0x1UL << LPTIM_DIER_UPIE_Pos)          /*!< 0x00000020 */
8040 #define LPTIM_DIER_UPIE                     LPTIM_DIER_UPIE_Msk                     /*!< Counter direction change down to up interrupt enable */
8041 #define LPTIM_DIER_DOWNIE_Pos               (6U)
8042 #define LPTIM_DIER_DOWNIE_Msk               (0x1UL << LPTIM_DIER_DOWNIE_Pos)        /*!< 0x00000040 */
8043 #define LPTIM_DIER_DOWNIE                   LPTIM_DIER_DOWNIE_Msk                   /*!< Counter direction change up to down interrupt enable */
8044 #define LPTIM_DIER_UEIE_Pos                 (7U)
8045 #define LPTIM_DIER_UEIE_Msk                 (0x1UL << LPTIM_DIER_UEIE_Pos)          /*!< 0x00000080 */
8046 #define LPTIM_DIER_UEIE                     LPTIM_DIER_UEIE_Msk                     /*!< Update event interrupt enable */
8047 #define LPTIM_DIER_REPOKIE_Pos              (8U)
8048 #define LPTIM_DIER_REPOKIE_Msk              (0x1UL << LPTIM_DIER_REPOKIE_Pos)       /*!< 0x00000100 */
8049 #define LPTIM_DIER_REPOKIE                  LPTIM_DIER_REPOKIE_Msk                  /*!< Repetition register update OK interrupt enable */
8050 #define LPTIM_DIER_CC2IE_Pos                (9U)
8051 #define LPTIM_DIER_CC2IE_Msk                (0x1UL << LPTIM_DIER_CC2IE_Pos)         /*!< 0x00000200 */
8052 #define LPTIM_DIER_CC2IE                    LPTIM_DIER_CC2IE_Msk                    /*!< Capture/Compare 2 interrupt interrupt enable */
8053 #define LPTIM_DIER_CC1OIE_Pos               (12U)
8054 #define LPTIM_DIER_CC1OIE_Msk               (0x1UL << LPTIM_DIER_CC1OIE_Pos)        /*!< 0x00001000 */
8055 #define LPTIM_DIER_CC1OIE                   LPTIM_DIER_CC1OIE_Msk                   /*!< Capture/Compare 1 over-capture interrupt enable */
8056 #define LPTIM_DIER_CC2OIE_Pos               (13U)
8057 #define LPTIM_DIER_CC2OIE_Msk               (0x1UL << LPTIM_DIER_CC2OIE_Pos)        /*!< 0x00002000 */
8058 #define LPTIM_DIER_CC2OIE                   LPTIM_DIER_CC2OIE_Msk                   /*!< Capture/Compare 2 over-capture interrupt enable */
8059 #define LPTIM_DIER_CC1DE_Pos                (16U)
8060 #define LPTIM_DIER_CC1DE_Msk                (0x1UL << LPTIM_DIER_CC1DE_Pos)         /*!< 0x00010000 */
8061 #define LPTIM_DIER_CC1DE                    LPTIM_DIER_CC1DE_Msk                    /*!< Capture/Compare 1 DMA request enable */
8062 #define LPTIM_DIER_CMP2OKIE_Pos             (19U)
8063 #define LPTIM_DIER_CMP2OKIE_Msk             (0x1UL << LPTIM_DIER_CMP2OKIE_Pos)      /*!< 0x00080000 */
8064 #define LPTIM_DIER_CMP2OKIE                 LPTIM_DIER_CMP2OKIE_Msk                 /*!< Compare register 2 update OK interrupt enable */
8065 #define LPTIM_DIER_UEDE_Pos                 (23U)
8066 #define LPTIM_DIER_UEDE_Msk                 (0x1UL << LPTIM_DIER_UEDE_Pos)          /*!< 0x00800000 */
8067 #define LPTIM_DIER_UEDE                     LPTIM_DIER_UEDE_Msk                     /*!< Update event DMA request enable */
8068 #define LPTIM_DIER_CC2DE_Pos                (25U)
8069 #define LPTIM_DIER_CC2DE_Msk                (0x1UL << LPTIM_DIER_CC2DE_Pos)         /*!< 0x02000000 */
8070 #define LPTIM_DIER_CC2DE                    LPTIM_DIER_CC2DE_Msk                    /*!< Capture/Compare 2 DMA request enable */
8071 
8072 /******************  Bit definition for LPTIM_CFGR register *******************/
8073 #define LPTIM_CFGR_CKSEL_Pos                (0U)
8074 #define LPTIM_CFGR_CKSEL_Msk                (0x1UL << LPTIM_CFGR_CKSEL_Pos)         /*!< 0x00000001 */
8075 #define LPTIM_CFGR_CKSEL                    LPTIM_CFGR_CKSEL_Msk                    /*!< Clock selector */
8076 #define LPTIM_CFGR_CKPOL_Pos                (1U)
8077 #define LPTIM_CFGR_CKPOL_Msk                (0x3UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000006 */
8078 #define LPTIM_CFGR_CKPOL                    LPTIM_CFGR_CKPOL_Msk                    /*!< CKPOL[1:0] bits (Clock polarity) */
8079 #define LPTIM_CFGR_CKPOL_0                  (0x1UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000002 */
8080 #define LPTIM_CFGR_CKPOL_1                  (0x2UL << LPTIM_CFGR_CKPOL_Pos)         /*!< 0x00000004 */
8081 #define LPTIM_CFGR_CKFLT_Pos                (3U)
8082 #define LPTIM_CFGR_CKFLT_Msk                (0x3UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000018 */
8083 #define LPTIM_CFGR_CKFLT                    LPTIM_CFGR_CKFLT_Msk                    /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
8084 #define LPTIM_CFGR_CKFLT_0                  (0x1UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000008 */
8085 #define LPTIM_CFGR_CKFLT_1                  (0x2UL << LPTIM_CFGR_CKFLT_Pos)         /*!< 0x00000010 */
8086 #define LPTIM_CFGR_TRGFLT_Pos               (6U)
8087 #define LPTIM_CFGR_TRGFLT_Msk               (0x3UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x000000C0 */
8088 #define LPTIM_CFGR_TRGFLT                   LPTIM_CFGR_TRGFLT_Msk                   /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
8089 #define LPTIM_CFGR_TRGFLT_0                 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000040 */
8090 #define LPTIM_CFGR_TRGFLT_1                 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)        /*!< 0x00000080 */
8091 #define LPTIM_CFGR_PRESC_Pos                (9U)
8092 #define LPTIM_CFGR_PRESC_Msk                (0x7UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000E00 */
8093 #define LPTIM_CFGR_PRESC                    LPTIM_CFGR_PRESC_Msk                    /*!< PRESC[2:0] bits (Clock prescaler) */
8094 #define LPTIM_CFGR_PRESC_0                  (0x1UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000200 */
8095 #define LPTIM_CFGR_PRESC_1                  (0x2UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000400 */
8096 #define LPTIM_CFGR_PRESC_2                  (0x4UL << LPTIM_CFGR_PRESC_Pos)         /*!< 0x00000800 */
8097 #define LPTIM_CFGR_TRIGSEL_Pos              (13U)
8098 #define LPTIM_CFGR_TRIGSEL_Msk              (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x0000E000 */
8099 #define LPTIM_CFGR_TRIGSEL                  LPTIM_CFGR_TRIGSEL_Msk                  /*!< TRIGSEL[2:0]] bits (Trigger selector) */
8100 #define LPTIM_CFGR_TRIGSEL_0                (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00002000 */
8101 #define LPTIM_CFGR_TRIGSEL_1                (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00004000 */
8102 #define LPTIM_CFGR_TRIGSEL_2                (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)       /*!< 0x00008000 */
8103 #define LPTIM_CFGR_TRIGEN_Pos               (17U)
8104 #define LPTIM_CFGR_TRIGEN_Msk               (0x3UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00060000 */
8105 #define LPTIM_CFGR_TRIGEN                   LPTIM_CFGR_TRIGEN_Msk                   /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
8106 #define LPTIM_CFGR_TRIGEN_0                 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00020000 */
8107 #define LPTIM_CFGR_TRIGEN_1                 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)        /*!< 0x00040000 */
8108 #define LPTIM_CFGR_TIMOUT_Pos               (19U)
8109 #define LPTIM_CFGR_TIMOUT_Msk               (0x1UL << LPTIM_CFGR_TIMOUT_Pos)        /*!< 0x00080000 */
8110 #define LPTIM_CFGR_TIMOUT                   LPTIM_CFGR_TIMOUT_Msk                   /*!< Timout enable */
8111 #define LPTIM_CFGR_WAVE_Pos                 (20U)
8112 #define LPTIM_CFGR_WAVE_Msk                 (0x1UL << LPTIM_CFGR_WAVE_Pos)          /*!< 0x00100000 */
8113 #define LPTIM_CFGR_WAVE                     LPTIM_CFGR_WAVE_Msk                     /*!< Waveform shape */
8114 #define LPTIM_CFGR_WAVPOL_Pos               (21U)
8115 #define LPTIM_CFGR_WAVPOL_Msk               (0x1UL << LPTIM_CFGR_WAVPOL_Pos)        /*!< 0x00200000 */
8116 #define LPTIM_CFGR_WAVPOL                   LPTIM_CFGR_WAVPOL_Msk                   /*!< Waveform shape */
8117 #define LPTIM_CFGR_PRELOAD_Pos              (22U)
8118 #define LPTIM_CFGR_PRELOAD_Msk              (0x1UL << LPTIM_CFGR_PRELOAD_Pos)       /*!< 0x00400000 */
8119 #define LPTIM_CFGR_PRELOAD                  LPTIM_CFGR_PRELOAD_Msk                  /*!< Reg update mode */
8120 #define LPTIM_CFGR_COUNTMODE_Pos            (23U)
8121 #define LPTIM_CFGR_COUNTMODE_Msk            (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)     /*!< 0x00800000 */
8122 #define LPTIM_CFGR_COUNTMODE                LPTIM_CFGR_COUNTMODE_Msk                /*!< Counter mode enable */
8123 #define LPTIM_CFGR_ENC_Pos                  (24U)
8124 #define LPTIM_CFGR_ENC_Msk                  (0x1UL << LPTIM_CFGR_ENC_Pos)           /*!< 0x01000000 */
8125 #define LPTIM_CFGR_ENC                      LPTIM_CFGR_ENC_Msk                      /*!< Encoder mode enable */
8126 
8127 /******************  Bit definition for LPTIM_CR register  ********************/
8128 #define LPTIM_CR_ENABLE_Pos                 (0U)
8129 #define LPTIM_CR_ENABLE_Msk                 (0x1UL << LPTIM_CR_ENABLE_Pos)          /*!< 0x00000001 */
8130 #define LPTIM_CR_ENABLE                     LPTIM_CR_ENABLE_Msk                     /*!< LPTIMer enable */
8131 #define LPTIM_CR_SNGSTRT_Pos                (1U)
8132 #define LPTIM_CR_SNGSTRT_Msk                (0x1UL << LPTIM_CR_SNGSTRT_Pos)         /*!< 0x00000002 */
8133 #define LPTIM_CR_SNGSTRT                    LPTIM_CR_SNGSTRT_Msk                    /*!< Timer start in single mode */
8134 #define LPTIM_CR_CNTSTRT_Pos                (2U)
8135 #define LPTIM_CR_CNTSTRT_Msk                (0x1UL << LPTIM_CR_CNTSTRT_Pos)         /*!< 0x00000004 */
8136 #define LPTIM_CR_CNTSTRT                    LPTIM_CR_CNTSTRT_Msk                    /*!< Timer start in continuous mode */
8137 #define LPTIM_CR_COUNTRST_Pos               (3U)
8138 #define LPTIM_CR_COUNTRST_Msk               (0x1UL << LPTIM_CR_COUNTRST_Pos)        /*!< 0x00000008 */
8139 #define LPTIM_CR_COUNTRST                   LPTIM_CR_COUNTRST_Msk                   /*!< Timer Counter reset in synchronous mode*/
8140 #define LPTIM_CR_RSTARE_Pos                 (4U)
8141 #define LPTIM_CR_RSTARE_Msk                 (0x1UL << LPTIM_CR_RSTARE_Pos)          /*!< 0x00000010 */
8142 #define LPTIM_CR_RSTARE                     LPTIM_CR_RSTARE_Msk                     /*!< Timer Counter reset after read enable (asynchronously)*/
8143 
8144 
8145 /******************  Bit definition for LPTIM_CCR1 register  ******************/
8146 #define LPTIM_CCR1_CCR1_Pos                 (0U)
8147 #define LPTIM_CCR1_CCR1_Msk                 (0xFFFFUL << LPTIM_CCR1_CCR1_Pos)       /*!< 0x0000FFFF */
8148 #define LPTIM_CCR1_CCR1                     LPTIM_CCR1_CCR1_Msk                     /*!< Compare register 1 */
8149 
8150 /******************  Bit definition for LPTIM_ARR register  *******************/
8151 #define LPTIM_ARR_ARR_Pos                   (0U)
8152 #define LPTIM_ARR_ARR_Msk                   (0xFFFFUL << LPTIM_ARR_ARR_Pos)         /*!< 0x0000FFFF */
8153 #define LPTIM_ARR_ARR                       LPTIM_ARR_ARR_Msk                       /*!< Auto reload register */
8154 
8155 /******************  Bit definition for LPTIM_CNT register  *******************/
8156 #define LPTIM_CNT_CNT_Pos                   (0U)
8157 #define LPTIM_CNT_CNT_Msk                   (0xFFFFUL << LPTIM_CNT_CNT_Pos)         /*!< 0x0000FFFF */
8158 #define LPTIM_CNT_CNT                       LPTIM_CNT_CNT_Msk                       /*!< Counter register */
8159 
8160 /******************  Bit definition for LPTIM_CFGR2 register  *****************/
8161 #define LPTIM_CFGR2_IN1SEL_Pos              (0U)
8162 #define LPTIM_CFGR2_IN1SEL_Msk              (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000003 */
8163 #define LPTIM_CFGR2_IN1SEL                  LPTIM_CFGR2_IN1SEL_Msk                  /*!< IN1SEL[1:0] bits (Remap selection) */
8164 #define LPTIM_CFGR2_IN1SEL_0                (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000001 */
8165 #define LPTIM_CFGR2_IN1SEL_1                (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)       /*!< 0x00000002 */
8166 #define LPTIM_CFGR2_IN2SEL_Pos              (4U)
8167 #define LPTIM_CFGR2_IN2SEL_Msk              (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000030 */
8168 #define LPTIM_CFGR2_IN2SEL                  LPTIM_CFGR2_IN2SEL_Msk                  /*!< IN2SEL[5:4] bits (Remap selection) */
8169 #define LPTIM_CFGR2_IN2SEL_0                (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000010 */
8170 #define LPTIM_CFGR2_IN2SEL_1                (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)       /*!< 0x00000020 */
8171 #define LPTIM_CFGR2_IC1SEL_Pos              (16U)
8172 #define LPTIM_CFGR2_IC1SEL_Msk              (0x3UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00000003 */
8173 #define LPTIM_CFGR2_IC1SEL                  LPTIM_CFGR2_IC1SEL_Msk                  /*!< IC1SEL[17:16] bits */
8174 #define LPTIM_CFGR2_IC1SEL_0                (0x1UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00010000 */
8175 #define LPTIM_CFGR2_IC1SEL_1                (0x2UL << LPTIM_CFGR2_IC1SEL_Pos)       /*!< 0x00020000 */
8176 #define LPTIM_CFGR2_IC2SEL_Pos              (20U)
8177 #define LPTIM_CFGR2_IC2SEL_Msk              (0x3UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00000030 */
8178 #define LPTIM_CFGR2_IC2SEL                  LPTIM_CFGR2_IC2SEL_Msk                  /*!< IC2SEL[21:20] bits */
8179 #define LPTIM_CFGR2_IC2SEL_0                (0x1UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00100000 */
8180 #define LPTIM_CFGR2_IC2SEL_1                (0x2UL << LPTIM_CFGR2_IC2SEL_Pos)       /*!< 0x00200000 */
8181 
8182 /******************  Bit definition for LPTIM_RCR register  *******************/
8183 #define LPTIM_RCR_REP_Pos                   (0U)
8184 #define LPTIM_RCR_REP_Msk                   (0xFFUL << LPTIM_RCR_REP_Pos)           /*!< 0x000000FF */
8185 #define LPTIM_RCR_REP                       LPTIM_RCR_REP_Msk                       /*!< Repetition register value */
8186 
8187 /*****************  Bit definition for LPTIM_CCMR1 register  ******************/
8188 #define LPTIM_CCMR1_CC1SEL_Pos              (0U)
8189 #define LPTIM_CCMR1_CC1SEL_Msk              (0x1UL << LPTIM_CCMR1_CC1SEL_Pos)       /*!< 0x00000001 */
8190 #define LPTIM_CCMR1_CC1SEL                  LPTIM_CCMR1_CC1SEL_Msk                  /*!< Capture/Compare 1 selection */
8191 #define LPTIM_CCMR1_CC1E_Pos                (1U)
8192 #define LPTIM_CCMR1_CC1E_Msk                (0x1UL << LPTIM_CCMR1_CC1E_Pos)         /*!< 0x00000002 */
8193 #define LPTIM_CCMR1_CC1E                    LPTIM_CCMR1_CC1E_Msk                    /*!< Capture/Compare 1 output enable */
8194 #define LPTIM_CCMR1_CC1P_Pos                (2U)
8195 #define LPTIM_CCMR1_CC1P_Msk                (0x3UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x0000000C */
8196 #define LPTIM_CCMR1_CC1P                    LPTIM_CCMR1_CC1P_Msk                    /*!< Capture/Compare 1 output polarity */
8197 #define LPTIM_CCMR1_CC1P_0                  (0x1UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000004 */
8198 #define LPTIM_CCMR1_CC1P_1                  (0x2UL << LPTIM_CCMR1_CC1P_Pos)         /*!< 0x00000008 */
8199 #define LPTIM_CCMR1_IC1PSC_Pos              (8U)
8200 #define LPTIM_CCMR1_IC1PSC_Msk              (0x3UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000300 */
8201 #define LPTIM_CCMR1_IC1PSC                  LPTIM_CCMR1_IC1PSC_Msk                  /*!< Input capture 1 prescaler */
8202 #define LPTIM_CCMR1_IC1PSC_0                (0x1UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000100 */
8203 #define LPTIM_CCMR1_IC1PSC_1                (0x2UL << LPTIM_CCMR1_IC1PSC_Pos)       /*!< 0x00000200 */
8204 #define LPTIM_CCMR1_IC1F_Pos                (12U)
8205 #define LPTIM_CCMR1_IC1F_Msk                (0x3UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00003000 */
8206 #define LPTIM_CCMR1_IC1F                    LPTIM_CCMR1_IC1F_Msk                    /*!< Input capture 1 filter */
8207 #define LPTIM_CCMR1_IC1F_0                  (0x1UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00001000 */
8208 #define LPTIM_CCMR1_IC1F_1                  (0x2UL << LPTIM_CCMR1_IC1F_Pos)         /*!< 0x00002000 */
8209 #define LPTIM_CCMR1_CC2SEL_Pos              (16U)
8210 #define LPTIM_CCMR1_CC2SEL_Msk              (0x1UL << LPTIM_CCMR1_CC2SEL_Pos)       /*!< 0x00010000 */
8211 #define LPTIM_CCMR1_CC2SEL                  LPTIM_CCMR1_CC2SEL_Msk                  /*!< Capture/Compare 2 selection */
8212 #define LPTIM_CCMR1_CC2E_Pos                (17U)
8213 #define LPTIM_CCMR1_CC2E_Msk                (0x1UL << LPTIM_CCMR1_CC2E_Pos)         /*!< 0x00020000 */
8214 #define LPTIM_CCMR1_CC2E                    LPTIM_CCMR1_CC2E_Msk                    /*!< Capture/Compare 2 output enable */
8215 #define LPTIM_CCMR1_CC2P_Pos                (18U)
8216 #define LPTIM_CCMR1_CC2P_Msk                (0x3UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x000C0000 */
8217 #define LPTIM_CCMR1_CC2P                    LPTIM_CCMR1_CC2P_Msk                    /*!< Capture/Compare 2 output polarity */
8218 #define LPTIM_CCMR1_CC2P_0                  (0x1UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00040000 */
8219 #define LPTIM_CCMR1_CC2P_1                  (0x2UL << LPTIM_CCMR1_CC2P_Pos)         /*!< 0x00080000 */
8220 #define LPTIM_CCMR1_IC2PSC_Pos              (24U)
8221 #define LPTIM_CCMR1_IC2PSC_Msk              (0x3UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x03000000 */
8222 #define LPTIM_CCMR1_IC2PSC                  LPTIM_CCMR1_IC2PSC_Msk                  /*!< Input capture 2 prescaler */
8223 #define LPTIM_CCMR1_IC2PSC_0                (0x1UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x01000000 */
8224 #define LPTIM_CCMR1_IC2PSC_1                (0x2UL << LPTIM_CCMR1_IC2PSC_Pos)       /*!< 0x02000000 */
8225 #define LPTIM_CCMR1_IC2F_Pos                (28U)
8226 #define LPTIM_CCMR1_IC2F_Msk                (0x3UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x30000000 */
8227 #define LPTIM_CCMR1_IC2F                    LPTIM_CCMR1_IC2F_Msk                    /*!< Input capture 2 filter */
8228 #define LPTIM_CCMR1_IC2F_0                  (0x1UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x10000000 */
8229 #define LPTIM_CCMR1_IC2F_1                  (0x2UL << LPTIM_CCMR1_IC2F_Pos)         /*!< 0x20000000 */
8230 
8231 /******************  Bit definition for LPTIM_CCR2 register  ******************/
8232 #define LPTIM_CCR2_CCR2_Pos                 (0U)
8233 #define LPTIM_CCR2_CCR2_Msk                 (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)       /*!< 0x0000FFFF */
8234 #define LPTIM_CCR2_CCR2                     LPTIM_CCR2_CCR2_Msk                     /*!< Compare register 2 */
8235 
8236 /******************************************************************************/
8237 /*                                                                            */
8238 /*                             Power Control                                  */
8239 /*                                                                            */
8240 /******************************************************************************/
8241 /********************  Bit definition for PWR_PMCR register  ******************/
8242 #define PWR_PMCR_LPMS_Pos                    (0U)
8243 #define PWR_PMCR_LPMS_Msk                    (0x1UL << PWR_PMCR_LPMS_Pos)
8244 #define PWR_PMCR_LPMS                        PWR_PMCR_LPMS_Msk
8245 #define PWR_PMCR_SVOS_Pos                    (2U)
8246 #define PWR_PMCR_SVOS_Msk                    (0x3UL << PWR_PMCR_SVOS_Pos)
8247 #define PWR_PMCR_SVOS                        PWR_PMCR_SVOS_Msk
8248 #define PWR_PMCR_SVOS_0                      (0x1UL << PWR_PMCR_SVOS_Pos)
8249 #define PWR_PMCR_SVOS_1                      (0x2UL << PWR_PMCR_SVOS_Pos)
8250 #define PWR_PMCR_CSSF_Pos                    (7U)
8251 #define PWR_PMCR_CSSF_Msk                    (0x1UL << PWR_PMCR_CSSF_Pos)
8252 #define PWR_PMCR_CSSF                        PWR_PMCR_CSSF_Msk
8253 #define PWR_PMCR_FLPS_Pos                    (9U)
8254 #define PWR_PMCR_FLPS_Msk                    (0x1UL << PWR_PMCR_FLPS_Pos)
8255 #define PWR_PMCR_FLPS                        PWR_PMCR_FLPS_Msk
8256 #define PWR_PMCR_BOOSTE_Pos                  (12U)
8257 #define PWR_PMCR_BOOSTE_Msk                  (0x1UL << PWR_PMCR_BOOSTE_Pos)
8258 #define PWR_PMCR_BOOSTE                      PWR_PMCR_BOOSTE_Msk
8259 #define PWR_PMCR_AVD_READY_Pos               (13U)
8260 #define PWR_PMCR_AVD_READY_Msk               (0x1UL << PWR_PMCR_AVD_READY_Pos)
8261 #define PWR_PMCR_AVD_READY                   PWR_PMCR_AVD_READY_Msk
8262 #define PWR_PMCR_SRAM2SO_Pos                 (25U)
8263 #define PWR_PMCR_SRAM2SO_Msk                 (0x1UL << PWR_PMCR_SRAM2SO_Pos)
8264 #define PWR_PMCR_SRAM2SO                     PWR_PMCR_SRAM2SO_Msk
8265 #define PWR_PMCR_SRAM1SO_Pos                 (26U)
8266 #define PWR_PMCR_SRAM1SO_Msk                 (0x1UL << PWR_PMCR_SRAM1SO_Pos)
8267 #define PWR_PMCR_SRAM1SO                     PWR_PMCR_SRAM1SO_Msk
8268 
8269 /********************  Bit definition for PWR_PMSR register  *******************/
8270 #define PWR_PMSR_STOPF_Pos                   (5U)
8271 #define PWR_PMSR_STOPF_Msk                   (0x1UL << PWR_PMSR_STOPF_Pos)
8272 #define PWR_PMSR_STOPF                       PWR_PMSR_STOPF_Msk
8273 #define PWR_PMSR_SBF_Pos                     (6U)
8274 #define PWR_PMSR_SBF_Msk                     (0x1UL << PWR_PMSR_SBF_Pos)
8275 #define PWR_PMSR_SBF                         PWR_PMSR_SBF_Msk
8276 
8277 /********************  Bit definition for PWR_VOSCR register  ******************/
8278 #define PWR_VOSCR_VOS_Pos                    (4U)
8279 #define PWR_VOSCR_VOS_Msk                    (0x3UL << PWR_VOSCR_VOS_Pos)
8280 #define PWR_VOSCR_VOS                        PWR_VOSCR_VOS_Msk
8281 #define PWR_VOSCR_VOS_0                      (0x1UL << PWR_VOSCR_VOS_Pos)
8282 #define PWR_VOSCR_VOS_1                      (0x2UL << PWR_VOSCR_VOS_Pos)
8283 
8284 /********************  Bit definition for PWR_VOSSR register  *****************/
8285 #define PWR_VOSSR_VOSRDY_Pos                 (3U)
8286 #define PWR_VOSSR_VOSRDY_Msk                 (0x1UL << PWR_VOSSR_VOSRDY_Pos)
8287 #define PWR_VOSSR_VOSRDY                     PWR_VOSSR_VOSRDY_Msk
8288 #define PWR_VOSSR_ACTVOSRDY_Pos              (13U)
8289 #define PWR_VOSSR_ACTVOSRDY_Msk              (0x1UL << PWR_VOSSR_ACTVOSRDY_Pos)
8290 #define PWR_VOSSR_ACTVOSRDY                  PWR_VOSSR_ACTVOSRDY_Msk
8291 #define PWR_VOSSR_ACTVOS_Pos                 (14U)
8292 #define PWR_VOSSR_ACTVOS_Msk                 (0x3UL << PWR_VOSSR_ACTVOS_Pos)
8293 #define PWR_VOSSR_ACTVOS                     PWR_VOSSR_ACTVOS_Msk
8294 #define PWR_VOSSR_ACTVOS_0                   (0x1UL << PWR_VOSSR_ACTVOS_Pos)
8295 #define PWR_VOSSR_ACTVOS_1                   (0x2UL << PWR_VOSSR_ACTVOS_Pos)
8296 
8297 /********************  Bit definition for PWR_BDCR register  ******************/
8298 #define PWR_BDCR_BREN_Pos                    (0U)
8299 #define PWR_BDCR_BREN_Msk                    (0x1UL << PWR_BDCR_BREN_Pos)
8300 #define PWR_BDCR_BREN                        PWR_BDCR_BREN_Msk
8301 #define PWR_BDCR_MONEN_Pos                   (1U)
8302 #define PWR_BDCR_MONEN_Msk                   (0x1UL << PWR_BDCR_MONEN_Pos)
8303 #define PWR_BDCR_MONEN                       PWR_BDCR_MONEN_Msk
8304 #define PWR_BDCR_VBE_Pos                     (8U)
8305 #define PWR_BDCR_VBE_Msk                     (0x1UL << PWR_BDCR_VBE_Pos)
8306 #define PWR_BDCR_VBE                         PWR_BDCR_VBE_Msk
8307 #define PWR_BDCR_VBRS_Pos                    (9U)
8308 #define PWR_BDCR_VBRS_Msk                    (0x1UL << PWR_BDCR_VBRS_Pos)
8309 #define PWR_BDCR_VBRS                        PWR_BDCR_VBRS_Msk
8310 
8311 /********************  Bit definition for PWR_DBPCR register  *****************/
8312 #define PWR_DBPCR_DBP_Pos                    (0U)
8313 #define PWR_DBPCR_DBP_Msk                    (0x1UL << PWR_DBPCR_DBP_Pos)
8314 #define PWR_DBPCR_DBP                        PWR_DBPCR_DBP_Msk
8315 
8316 /********************  Bit definition for PWR_BDSR register  ******************/
8317 #define PWR_BDSR_BRRDY_Pos                   (16U)
8318 #define PWR_BDSR_BRRDY_Msk                   (0x1UL << PWR_BDSR_BRRDY_Pos)
8319 #define PWR_BDSR_BRRDY                       PWR_BDSR_BRRDY_Msk
8320 #define PWR_BDSR_VBATL_Pos                   (20U)
8321 #define PWR_BDSR_VBATL_Msk                   (0x1UL << PWR_BDSR_VBATL_Pos)
8322 #define PWR_BDSR_VBATL                       PWR_BDSR_VBATL_Msk
8323 #define PWR_BDSR_VBATH_Pos                   (21U)
8324 #define PWR_BDSR_VBATH_Msk                   (0x1UL << PWR_BDSR_VBATH_Pos)
8325 #define PWR_BDSR_VBATH                       PWR_BDSR_VBATH_Msk
8326 #define PWR_BDSR_TEMPL_Pos                   (22U)
8327 #define PWR_BDSR_TEMPL_Msk                   (0x1UL << PWR_BDSR_TEMPL_Pos)
8328 #define PWR_BDSR_TEMPL                       PWR_BDSR_TEMPL_Msk
8329 #define PWR_BDSR_TEMPH_Pos                   (23U)
8330 #define PWR_BDSR_TEMPH_Msk                   (0x1UL << PWR_BDSR_TEMPH_Pos)
8331 #define PWR_BDSR_TEMPH                       PWR_BDSR_TEMPH_Msk
8332 
8333 
8334 /********************  Bit definition for PWR_SCCR register  ******************/
8335 #define PWR_SCCR_BYPASS_Pos                  (0U)
8336 #define PWR_SCCR_BYPASS_Msk                  (0x1UL << PWR_SCCR_BYPASS_Pos)
8337 #define PWR_SCCR_BYPASS                      PWR_SCCR_BYPASS_Msk
8338 #define PWR_SCCR_LDOEN_Pos                   (8U)
8339 #define PWR_SCCR_LDOEN_Msk                   (0x1UL << PWR_SCCR_LDOEN_Pos)
8340 #define PWR_SCCR_LDOEN                       PWR_SCCR_LDOEN_Msk
8341 
8342 /********************  Bit definition for PWR_VMCR register  ******************/
8343 #define PWR_VMCR_PVDEN_Pos                    (0U)
8344 #define PWR_VMCR_PVDEN_Msk                    (0x1UL << PWR_VMCR_PVDEN_Pos)
8345 #define PWR_VMCR_PVDEN                        PWR_VMCR_PVDEN_Msk
8346 #define PWR_VMCR_PLS_Pos                     (1U)
8347 #define PWR_VMCR_PLS_Msk                     (0x7UL << PWR_VMCR_PLS_Pos)
8348 #define PWR_VMCR_PLS                         PWR_VMCR_PLS_Msk
8349 #define PWR_VMCR_PLS_0                       (0x1UL << PWR_VMCR_PLS_Pos)
8350 #define PWR_VMCR_PLS_1                       (0x2UL << PWR_VMCR_PLS_Pos)
8351 #define PWR_VMCR_PLS_2                       (0x4UL << PWR_VMCR_PLS_Pos)
8352 #define PWR_VMCR_AVDEN_Pos                   (8U)
8353 #define PWR_VMCR_AVDEN_Msk                   (0x1UL << PWR_VMCR_AVDEN_Pos)
8354 #define PWR_VMCR_AVDEN                       PWR_VMCR_AVDEN_Msk
8355 #define PWR_VMCR_ALS_Pos                     (9U)
8356 #define PWR_VMCR_ALS_Msk                     (0x3UL << PWR_VMCR_ALS_Pos)
8357 #define PWR_VMCR_ALS                         PWR_VMCR_ALS_Msk
8358 #define PWR_VMCR_ALS_0                       (0x1UL << PWR_VMCR_ALS_Pos)
8359 #define PWR_VMCR_ALS_1                       (0x2UL << PWR_VMCR_ALS_Pos)
8360 
8361 
8362 /********************  Bit definition for PWR_VMSR register  ******************/
8363 #define PWR_VMSR_AVDO_Pos                    (19U)
8364 #define PWR_VMSR_AVDO_Msk                    (0x1UL << PWR_VMSR_AVDO_Pos)
8365 #define PWR_VMSR_AVDO                        PWR_VMSR_AVDO_Msk
8366 #define PWR_VMSR_VDDIO2RDY_Pos               (20U)
8367 #define PWR_VMSR_VDDIO2RDY_Msk               (0x1UL << PWR_VMSR_VDDIO2RDY_Pos)
8368 #define PWR_VMSR_VDDIO2RDY                   PWR_VMSR_VDDIO2RDY_Msk
8369 #define PWR_VMSR_PVDO_Pos                    (22U)
8370 #define PWR_VMSR_PVDO_Msk                    (0x1UL << PWR_VMSR_PVDO_Pos)
8371 #define PWR_VMSR_PVDO                        PWR_VMSR_PVDO_Msk
8372 
8373 /********************  Bit definition for PWR_WUSCR register  ****************/
8374 #define PWR_WUSCR_CWUF1_Pos                (0U)
8375 #define PWR_WUSCR_CWUF1_Msk                (0x1UL << PWR_WUSCR_CWUF1_Pos)
8376 #define PWR_WUSCR_CWUF1                    PWR_WUSCR_CWUF1_Msk
8377 #define PWR_WUSCR_CWUF2_Pos                (1U)
8378 #define PWR_WUSCR_CWUF2_Msk                (0x1UL << PWR_WUSCR_CWUF2_Pos)
8379 #define PWR_WUSCR_CWUF2                    PWR_WUSCR_CWUF2_Msk
8380 #define PWR_WUSCR_CWUF3_Pos                (2U)
8381 #define PWR_WUSCR_CWUF3_Msk                (0x1UL << PWR_WUSCR_CWUF3_Pos)
8382 #define PWR_WUSCR_CWUF3                    PWR_WUSCR_CWUF3_Msk
8383 #define PWR_WUSCR_CWUF4_Pos                (3U)
8384 #define PWR_WUSCR_CWUF4_Msk                (0x1UL << PWR_WUSCR_CWUF4_Pos)
8385 #define PWR_WUSCR_CWUF4                    PWR_WUSCR_CWUF4_Msk
8386 #define PWR_WUSCR_CWUF5_Pos                (4U)
8387 #define PWR_WUSCR_CWUF5_Msk                (0x1UL << PWR_WUSCR_CWUF5_Pos)
8388 #define PWR_WUSCR_CWUF5                    PWR_WUSCR_CWUF5_Msk
8389 #define PWR_WUSCR_CWUF_Pos                 (0U)
8390 #define PWR_WUSCR_CWUF_Msk                 (0x1FUL << PWR_WUSCR_CWUF_Pos)
8391 #define PWR_WUSCR_CWUF                     PWR_WUSCR_CWUF_Msk
8392 
8393 /********************  Bit definition for PWR_WUSR register  ****************/
8394 #define PWR_WUSR_WUF1_Pos                (0U)
8395 #define PWR_WUSR_WUF1_Msk                (0x1UL << PWR_WUSR_WUF1_Pos)
8396 #define PWR_WUSR_WUF1                    PWR_WUSR_WUF1_Msk
8397 #define PWR_WUSR_WUF2_Pos                (1U)
8398 #define PWR_WUSR_WUF2_Msk                (0x1UL << PWR_WUSR_WUF2_Pos)
8399 #define PWR_WUSR_WUF2                    PWR_WUSR_WUF2_Msk
8400 #define PWR_WUSR_WUF3_Pos                (2U)
8401 #define PWR_WUSR_WUF3_Msk                (0x1UL << PWR_WUSR_WUF3_Pos)
8402 #define PWR_WUSR_WUF3                    PWR_WUSR_WUF3_Msk
8403 #define PWR_WUSR_WUF4_Pos                (3U)
8404 #define PWR_WUSR_WUF4_Msk                (0x1UL << PWR_WUSR_WUF4_Pos)
8405 #define PWR_WUSR_WUF4                    PWR_WUSR_WUF4_Msk
8406 #define PWR_WUSR_WUF5_Pos                (4U)
8407 #define PWR_WUSR_WUF5_Msk                (0x1UL << PWR_WUSR_WUF5_Pos)
8408 #define PWR_WUSR_WUF5                    PWR_WUSR_WUF5_Msk
8409 
8410 /********************  Bit definition for PWR_WUCR register  ***************/
8411 #define PWR_WUCR_WUPEN1_Pos              (0U)
8412 #define PWR_WUCR_WUPEN1_Msk              (0x1UL << PWR_WUCR_WUPEN1_Pos)
8413 #define PWR_WUCR_WUPEN1                  PWR_WUCR_WUPEN1_Msk
8414 #define PWR_WUCR_WUPEN2_Pos              (1U)
8415 #define PWR_WUCR_WUPEN2_Msk              (0x1UL << PWR_WUCR_WUPEN2_Pos)
8416 #define PWR_WUCR_WUPEN2                  PWR_WUCR_WUPEN2_Msk
8417 #define PWR_WUCR_WUPEN3_Pos              (2U)
8418 #define PWR_WUCR_WUPEN3_Msk              (0x1UL << PWR_WUCR_WUPEN3_Pos)
8419 #define PWR_WUCR_WUPEN3                  PWR_WUCR_WUPEN3_Msk
8420 #define PWR_WUCR_WUPEN4_Pos              (3U)
8421 #define PWR_WUCR_WUPEN4_Msk              (0x1UL << PWR_WUCR_WUPEN4_Pos)
8422 #define PWR_WUCR_WUPEN4                  PWR_WUCR_WUPEN4_Msk
8423 #define PWR_WUCR_WUPEN5_Pos              (4U)
8424 #define PWR_WUCR_WUPEN5_Msk              (0x1UL << PWR_WUCR_WUPEN5_Pos)
8425 #define PWR_WUCR_WUPEN5                  PWR_WUCR_WUPEN5_Msk
8426 #define PWR_WUCR_WUPEN_Pos               (0U)
8427 #define PWR_WUCR_WUPEN_Msk               (0x1FUL << PWR_WUCR_WUPEN_Pos)
8428 #define PWR_WUCR_WUPEN                   PWR_WUCR_WUPEN_Msk
8429 #define PWR_WUCR_WUPP1_Pos               (8U)
8430 #define PWR_WUCR_WUPP1_Msk               (0x1UL << PWR_WUCR_WUPP1_Pos)
8431 #define PWR_WUCR_WUPP1                   PWR_WUCR_WUPP1_Msk
8432 #define PWR_WUCR_WUPP2_Pos               (9U)
8433 #define PWR_WUCR_WUPP2_Msk               (0x1UL << PWR_WUCR_WUPP2_Pos)
8434 #define PWR_WUCR_WUPP2                   PWR_WUCR_WUPP2_Msk
8435 #define PWR_WUCR_WUPP3_Pos               (10U)
8436 #define PWR_WUCR_WUPP3_Msk               (0x1UL << PWR_WUCR_WUPP3_Pos)
8437 #define PWR_WUCR_WUPP3                   PWR_WUCR_WUPP3_Msk
8438 #define PWR_WUCR_WUPP4_Pos               (11U)
8439 #define PWR_WUCR_WUPP4_Msk               (0x1UL << PWR_WUCR_WUPP4_Pos)
8440 #define PWR_WUCR_WUPP4                   PWR_WUCR_WUPP4_Msk
8441 #define PWR_WUCR_WUPP5_Pos               (12U)
8442 #define PWR_WUCR_WUPP5_Msk               (0x1UL << PWR_WUCR_WUPP5_Pos)
8443 #define PWR_WUCR_WUPP5                   PWR_WUCR_WUPP5_Msk
8444 #define PWR_WUCR_WUPPUPD1_Pos            (16U)
8445 #define PWR_WUCR_WUPPUPD1_Msk            (0x3UL << PWR_WUCR_WUPPUPD1_Pos)
8446 #define PWR_WUCR_WUPPUPD1                PWR_WUCR_WUPPUPD1_Msk
8447 #define PWR_WUCR_WUPPUPD1_0              (0x1UL << PWR_WUCR_WUPPUPD1_Pos)
8448 #define PWR_WUCR_WUPPUPD1_1              (0x2UL << PWR_WUCR_WUPPUPD1_Pos)
8449 #define PWR_WUCR_WUPPUPD2_Pos            (18U)
8450 #define PWR_WUCR_WUPPUPD2_Msk            (0x3UL << PWR_WUCR_WUPPUPD2_Pos)
8451 #define PWR_WUCR_WUPPUPD2                PWR_WUCR_WUPPUPD2_Msk
8452 #define PWR_WUCR_WUPPUPD2_0              (0x1UL << PWR_WUCR_WUPPUPD2_Pos)
8453 #define PWR_WUCR_WUPPUPD2_1              (0x2UL << PWR_WUCR_WUPPUPD2_Pos)
8454 #define PWR_WUCR_WUPPUPD3_Pos            (20U)
8455 #define PWR_WUCR_WUPPUPD3_Msk            (0x3UL << PWR_WUCR_WUPPUPD3_Pos)
8456 #define PWR_WUCR_WUPPUPD3                PWR_WUCR_WUPPUPD3_Msk
8457 #define PWR_WUCR_WUPPUPD3_0              (0x1UL << PWR_WUCR_WUPPUPD3_Pos)
8458 #define PWR_WUCR_WUPPUPD3_1              (0x2UL << PWR_WUCR_WUPPUPD3_Pos)
8459 #define PWR_WUCR_WUPPUPD4_Pos            (22U)
8460 #define PWR_WUCR_WUPPUPD4_Msk            (0x3UL << PWR_WUCR_WUPPUPD4_Pos)
8461 #define PWR_WUCR_WUPPUPD4                PWR_WUCR_WUPPUPD4_Msk
8462 #define PWR_WUCR_WUPPUPD4_0              (0x1UL << PWR_WUCR_WUPPUPD4_Pos)
8463 #define PWR_WUCR_WUPPUPD4_1              (0x2UL << PWR_WUCR_WUPPUPD4_Pos)
8464 #define PWR_WUCR_WUPPUPD5_Pos            (24U)
8465 #define PWR_WUCR_WUPPUPD5_Msk            (0x3UL << PWR_WUCR_WUPPUPD5_Pos)
8466 #define PWR_WUCR_WUPPUPD5                PWR_WUCR_WUPPUPD5_Msk
8467 #define PWR_WUCR_WUPPUPD5_0              (0x1UL << PWR_WUCR_WUPPUPD5_Pos)
8468 #define PWR_WUCR_WUPPUPD5_1              (0x2UL << PWR_WUCR_WUPPUPD5_Pos)
8469 
8470 /********************  Bit definition for PWR_IORETR register  ****************/
8471 #define PWR_IORETR_IORETEN_Pos           (0U)
8472 #define PWR_IORETR_IORETEN_Msk           (0x1UL << PWR_IORETR_IORETEN_Pos)
8473 #define PWR_IORETR_IORETEN               PWR_IORETR_IORETEN_Msk
8474 #define PWR_IORETR_JTAGIORETEN_Pos       (16U)
8475 #define PWR_IORETR_JTAGIORETEN_Msk       (0x1UL << PWR_IORETR_JTAGIORETEN_Pos)
8476 #define PWR_IORETR_JTAGIORETEN           PWR_IORETR_JTAGIORETEN_Msk
8477 
8478 /********************  Bit definition for PWR_PRIVCFGR register  **************/
8479 #define PWR_PRIVCFGR_PRIV_Pos            (1U)
8480 #define PWR_PRIVCFGR_PRIV_Msk            (0x1UL << PWR_PRIVCFGR_PRIV_Pos)
8481 #define PWR_PRIVCFGR_PRIV                PWR_PRIVCFGR_PRIV_Msk
8482 
8483 /******************************************************************************/
8484 /*                                                                            */
8485 /*                      SRAMs configuration controller                        */
8486 /*                                                                            */
8487 /******************************************************************************/
8488 /*******************  Bit definition for RAMCFG_CR register  ******************/
8489 #define RAMCFG_CR_ECCE_Pos                  (0U)
8490 #define RAMCFG_CR_ECCE_Msk                  (0x1UL << RAMCFG_CR_ECCE_Pos)           /*!< 0x00000001 */
8491 #define RAMCFG_CR_ECCE                      RAMCFG_CR_ECCE_Msk                      /*!< ECC Enable */
8492 #define RAMCFG_CR_ALE_Pos                   (4U)
8493 #define RAMCFG_CR_ALE_Msk                   (0x1UL << RAMCFG_CR_ALE_Pos)            /*!< 0x00000010 */
8494 #define RAMCFG_CR_ALE                       RAMCFG_CR_ALE_Msk                       /*!< Address Latching Enable */
8495 #define RAMCFG_CR_SRAMER_Pos                (8U)
8496 #define RAMCFG_CR_SRAMER_Msk                (0x1UL << RAMCFG_CR_SRAMER_Pos)         /*!< 0x00000100 */
8497 #define RAMCFG_CR_SRAMER                    RAMCFG_CR_SRAMER_Msk                    /*!< Start Erase */
8498 
8499 /*******************  Bit definition for RAMCFG_IER register  *****************/
8500 #define RAMCFG_IER_SEIE_Pos                 (0U)
8501 #define RAMCFG_IER_SEIE_Msk                 (0x1UL << RAMCFG_IER_SEIE_Pos)          /*!< 0x00000001 */
8502 #define RAMCFG_IER_SEIE                     RAMCFG_IER_SEIE_Msk                     /*!< Single Error Interrupt Enable */
8503 #define RAMCFG_IER_DEIE_Pos                 (1U)
8504 #define RAMCFG_IER_DEIE_Msk                 (0x1UL << RAMCFG_IER_DEIE_Pos)          /*!< 0x00000002 */
8505 #define RAMCFG_IER_DEIE                     RAMCFG_IER_DEIE_Msk                     /*!< Double Error Interrupt Enable */
8506 #define RAMCFG_IER_ECCNMI_Pos               (3U)
8507 #define RAMCFG_IER_ECCNMI_Msk               (0x1UL << RAMCFG_IER_ECCNMI_Pos)        /*!< 0x00000008 */
8508 #define RAMCFG_IER_ECCNMI                   RAMCFG_IER_ECCNMI_Msk                   /*!< NMI redirection interrupt */
8509 
8510 /*******************  Bit definition for RAMCFG_ISR register  *****************/
8511 #define RAMCFG_ISR_SEDC_Pos                 (0U)
8512 #define RAMCFG_ISR_SEDC_Msk                 (0x1UL << RAMCFG_ISR_SEDC_Pos)          /*!< 0x00000001 */
8513 #define RAMCFG_ISR_SEDC                     RAMCFG_ISR_SEDC_Msk                     /*!< Single Error Detected and Corrected flag */
8514 #define RAMCFG_ISR_DED_Pos                  (1U)
8515 #define RAMCFG_ISR_DED_Msk                  (0x1UL << RAMCFG_ISR_DED_Pos)           /*!< 0x00000002 */
8516 #define RAMCFG_ISR_DED                      RAMCFG_ISR_DED_Msk                      /*!< Double Error Detected flag */
8517 #define RAMCFG_ISR_SRAMBUSY_Pos             (8U)
8518 #define RAMCFG_ISR_SRAMBUSY_Msk             (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos)      /*!< 0x00000100 */
8519 #define RAMCFG_ISR_SRAMBUSY                 RAMCFG_ISR_SRAMBUSY_Msk                 /*!< SRAM busy flag */
8520 
8521 /*******************  Bit definition for RAMCFG_SEAR register  ****************/
8522 #define RAMCFG_SEAR_ESEA_Pos                (0U)
8523 #define RAMCFG_SEAR_ESEA_Msk                (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos)  /*!< 0xFFFFFFFF */
8524 #define RAMCFG_SEAR_ESEA                    RAMCFG_SEAR_ESEA_Msk                    /*!< ECC Single Error Address */
8525 
8526 /*******************  Bit definition for RAMCFG_DEAR register  ****************/
8527 #define RAMCFG_DEAR_EDEA_Pos                (0U)
8528 #define RAMCFG_DEAR_EDEA_Msk                (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos)  /*!< 0xFFFFFFFF */
8529 #define RAMCFG_DEAR_EDEA                    RAMCFG_DEAR_EDEA_Msk                    /*!< ECC Double Error Address */
8530 
8531 /*******************  Bit definition for RAMCFG_ICR register  *****************/
8532 #define RAMCFG_ICR_CSEDC_Pos                (0U)
8533 #define RAMCFG_ICR_CSEDC_Msk                (0x1UL << RAMCFG_ICR_CSEDC_Pos)         /*!< 0x00000001 */
8534 #define RAMCFG_ICR_CSEDC                    RAMCFG_ICR_CSEDC_Msk                    /*!< Clear ECC Single Error Detected and Corrected Flag */
8535 #define RAMCFG_ICR_CDED_Pos                 (1U)
8536 #define RAMCFG_ICR_CDED_Msk                 (0x1UL << RAMCFG_ICR_CDED_Pos)          /*!< 0x00000002 */
8537 #define RAMCFG_ICR_CDED                     RAMCFG_ICR_CDED_Msk                     /*!< Clear ECC Double Error Detected Flag*/
8538 
8539 /******************  Bit definition for RAMCFG_WPR1 register  *****************/
8540 #define RAMCFG_WPR1_P0WP_Pos                (0U)
8541 #define RAMCFG_WPR1_P0WP_Msk                (0x1UL << RAMCFG_WPR1_P0WP_Pos)         /*!< 0x00000001 */
8542 #define RAMCFG_WPR1_P0WP                    RAMCFG_WPR1_P0WP_Msk                    /*!< Write Protection Page 00 */
8543 #define RAMCFG_WPR1_P1WP_Pos                (1U)
8544 #define RAMCFG_WPR1_P1WP_Msk                (0x1UL << RAMCFG_WPR1_P1WP_Pos)         /*!< 0x00000002 */
8545 #define RAMCFG_WPR1_P1WP                    RAMCFG_WPR1_P1WP_Msk                    /*!< Write Protection Page 01 */
8546 #define RAMCFG_WPR1_P2WP_Pos                (2U)
8547 #define RAMCFG_WPR1_P2WP_Msk                (0x1UL << RAMCFG_WPR1_P2WP_Pos)         /*!< 0x00000004 */
8548 #define RAMCFG_WPR1_P2WP                    RAMCFG_WPR1_P2WP_Msk                    /*!< Write Protection Page 02 */
8549 #define RAMCFG_WPR1_P3WP_Pos                (3U)
8550 #define RAMCFG_WPR1_P3WP_Msk                (0x1UL << RAMCFG_WPR1_P3WP_Pos)         /*!< 0x00000008 */
8551 #define RAMCFG_WPR1_P3WP                    RAMCFG_WPR1_P3WP_Msk                    /*!< Write Protection Page 03 */
8552 #define RAMCFG_WPR1_P4WP_Pos                (4U)
8553 #define RAMCFG_WPR1_P4WP_Msk                (0x1UL << RAMCFG_WPR1_P4WP_Pos)         /*!< 0x00000010 */
8554 #define RAMCFG_WPR1_P4WP                    RAMCFG_WPR1_P4WP_Msk                    /*!< Write Protection Page 04 */
8555 #define RAMCFG_WPR1_P5WP_Pos                (5U)
8556 #define RAMCFG_WPR1_P5WP_Msk                (0x1UL << RAMCFG_WPR1_P5WP_Pos)         /*!< 0x00000020 */
8557 #define RAMCFG_WPR1_P5WP                    RAMCFG_WPR1_P5WP_Msk                    /*!< Write Protection Page 05 */
8558 #define RAMCFG_WPR1_P6WP_Pos                (6U)
8559 #define RAMCFG_WPR1_P6WP_Msk                (0x1UL << RAMCFG_WPR1_P6WP_Pos)         /*!< 0x00000040 */
8560 #define RAMCFG_WPR1_P6WP                    RAMCFG_WPR1_P6WP_Msk                    /*!< Write Protection Page 06 */
8561 #define RAMCFG_WPR1_P7WP_Pos                (7U)
8562 #define RAMCFG_WPR1_P7WP_Msk                (0x1UL << RAMCFG_WPR1_P7WP_Pos)         /*!< 0x00000080 */
8563 #define RAMCFG_WPR1_P7WP                    RAMCFG_WPR1_P7WP_Msk                    /*!< Write Protection Page 07 */
8564 #define RAMCFG_WPR1_P8WP_Pos                (8U)
8565 #define RAMCFG_WPR1_P8WP_Msk                (0x1UL << RAMCFG_WPR1_P8WP_Pos)         /*!< 0x00000100 */
8566 #define RAMCFG_WPR1_P8WP                    RAMCFG_WPR1_P8WP_Msk                    /*!< Write Protection Page 08 */
8567 #define RAMCFG_WPR1_P9WP_Pos                (9U)
8568 #define RAMCFG_WPR1_P9WP_Msk                (0x1UL << RAMCFG_WPR1_P9WP_Pos)         /*!< 0x00000200 */
8569 #define RAMCFG_WPR1_P9WP                    RAMCFG_WPR1_P9WP_Msk                    /*!< Write Protection Page 09 */
8570 #define RAMCFG_WPR1_P10WP_Pos               (10U)
8571 #define RAMCFG_WPR1_P10WP_Msk               (0x1UL << RAMCFG_WPR1_P10WP_Pos)        /*!< 0x00000400 */
8572 #define RAMCFG_WPR1_P10WP                   RAMCFG_WPR1_P10WP_Msk                   /*!< Write Protection Page 10 */
8573 #define RAMCFG_WPR1_P11WP_Pos               (11U)
8574 #define RAMCFG_WPR1_P11WP_Msk               (0x1UL << RAMCFG_WPR1_P11WP_Pos)        /*!< 0x00000800 */
8575 #define RAMCFG_WPR1_P11WP                   RAMCFG_WPR1_P11WP_Msk                   /*!< Write Protection Page 11 */
8576 #define RAMCFG_WPR1_P12WP_Pos               (12U)
8577 #define RAMCFG_WPR1_P12WP_Msk               (0x1UL << RAMCFG_WPR1_P12WP_Pos)        /*!< 0x00001000 */
8578 #define RAMCFG_WPR1_P12WP                   RAMCFG_WPR1_P12WP_Msk                   /*!< Write Protection Page 12 */
8579 #define RAMCFG_WPR1_P13WP_Pos               (13U)
8580 #define RAMCFG_WPR1_P13WP_Msk               (0x1UL << RAMCFG_WPR1_P13WP_Pos)        /*!< 0x00002000 */
8581 #define RAMCFG_WPR1_P13WP                   RAMCFG_WPR1_P13WP_Msk                   /*!< Write Protection Page 13 */
8582 #define RAMCFG_WPR1_P14WP_Pos               (14U)
8583 #define RAMCFG_WPR1_P14WP_Msk               (0x1UL << RAMCFG_WPR1_P14WP_Pos)        /*!< 0x00004000 */
8584 #define RAMCFG_WPR1_P14WP                   RAMCFG_WPR1_P14WP_Msk                   /*!< Write Protection Page 14 */
8585 #define RAMCFG_WPR1_P15WP_Pos               (15U)
8586 #define RAMCFG_WPR1_P15WP_Msk               (0x1UL << RAMCFG_WPR1_P15WP_Pos)        /*!< 0x00008000 */
8587 #define RAMCFG_WPR1_P15WP                   RAMCFG_WPR1_P15WP_Msk                   /*!< Write Protection Page 15 */
8588 #define RAMCFG_WPR1_P16WP_Pos               (16U)
8589 #define RAMCFG_WPR1_P16WP_Msk               (0x1UL << RAMCFG_WPR1_P16WP_Pos)        /*!< 0x00010000 */
8590 #define RAMCFG_WPR1_P16WP                   RAMCFG_WPR1_P16WP_Msk                   /*!< Write Protection Page 16 */
8591 
8592 /*****************  Bit definition for RAMCFG_ECCKEYR register  ***************/
8593 #define RAMCFG_ECCKEYR_ECCKEY_Pos           (0U)
8594 #define RAMCFG_ECCKEYR_ECCKEY_Msk           (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos)   /*!< 0x000000FF */
8595 #define RAMCFG_ECCKEYR_ECCKEY               RAMCFG_ECCKEYR_ECCKEY_Msk               /*!< ECC Write Protection Key */
8596 
8597 /*****************  Bit definition for RAMCFG_ERKEYR register  ****************/
8598 #define RAMCFG_ERKEYR_ERASEKEY_Pos          (0U)
8599 #define RAMCFG_ERKEYR_ERASEKEY_Msk          (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos)  /*!< 0x000000FF */
8600 #define RAMCFG_ERKEYR_ERASEKEY              RAMCFG_ERKEYR_ERASEKEY_Msk              /*!< Erase Write Protection Key */
8601 
8602 
8603 /******************************************************************************/
8604 /*                                                                            */
8605 /*                         Reset and Clock Control                            */
8606 /*                                                                            */
8607 /******************************************************************************/
8608 /********************  Bit definition for RCC_CR register  ********************/
8609 #define RCC_CR_HSION_Pos                    (0U)
8610 #define RCC_CR_HSION_Msk                    (0x1UL << RCC_CR_HSION_Pos)             /*!< 0x00000001 */
8611 #define RCC_CR_HSION                        RCC_CR_HSION_Msk                        /*!< Internal High Speed oscillator (HSI) clock enable */
8612 #define RCC_CR_HSIRDY_Pos                   (1U)
8613 #define RCC_CR_HSIRDY_Msk                   (0x1UL << RCC_CR_HSIRDY_Pos)            /*!< 0x00000002 */
8614 #define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                       /*!< Internal High Speed oscillator (HSI) clock ready flag */
8615 #define RCC_CR_HSIKERON_Pos                 (2U)
8616 #define RCC_CR_HSIKERON_Msk                 (0x1UL << RCC_CR_HSIKERON_Pos)          /*!< 0x00000004 */
8617 #define RCC_CR_HSIKERON                     RCC_CR_HSIKERON_Msk                     /*!< Internal High Speed oscillator (HSI) clock enable for some IPs Kernel */
8618 #define RCC_CR_HSIDIV_Pos                   (3U)
8619 #define RCC_CR_HSIDIV_Msk                   (0x3UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000018 */
8620 #define RCC_CR_HSIDIV                       RCC_CR_HSIDIV_Msk                       /*!< Internal High Speed clock divider selection */
8621 #define RCC_CR_HSIDIV_0                     (0x1UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000008 */
8622 #define RCC_CR_HSIDIV_1                     (0x2UL << RCC_CR_HSIDIV_Pos)            /*!< 0x00000010 */
8623 #define RCC_CR_HSIDIVF_Pos                  (5U)
8624 #define RCC_CR_HSIDIVF_Msk                  (0x1UL << RCC_CR_HSIDIVF_Pos)           /*!< 0x00000020 */
8625 #define RCC_CR_HSIDIVF                      RCC_CR_HSIDIVF_Msk                      /*!< HSI Divider flag */
8626 #define RCC_CR_CSION_Pos                    (8U)
8627 #define RCC_CR_CSION_Msk                    (0x1UL << RCC_CR_CSION_Pos)             /*!< 0x00000100 */
8628 #define RCC_CR_CSION                        RCC_CR_CSION_Msk                        /*!< The Internal RC 4MHz oscillator (CSI) clock enable */
8629 #define RCC_CR_CSIRDY_Pos                   (9U)
8630 #define RCC_CR_CSIRDY_Msk                   (0x1UL << RCC_CR_CSIRDY_Pos)            /*!< 0x00000200 */
8631 #define RCC_CR_CSIRDY                       RCC_CR_CSIRDY_Msk                       /*!< The Internal RC 4MHz oscillator (CSI) clock ready */
8632 #define RCC_CR_CSIKERON_Pos                 (10U)
8633 #define RCC_CR_CSIKERON_Msk                 (0x1UL << RCC_CR_CSIKERON_Pos)          /*!< 0x00000400 */
8634 #define RCC_CR_CSIKERON                     RCC_CR_CSIKERON_Msk                     /*!< The Internal RC 4MHz oscillator (CSI) clock enable for some IPs Kernel */
8635 #define RCC_CR_HSI48ON_Pos                  (12U)
8636 #define RCC_CR_HSI48ON_Msk                  (0x1UL << RCC_CR_HSI48ON_Pos)           /*!< 0x00001000 */
8637 #define RCC_CR_HSI48ON                      RCC_CR_HSI48ON_Msk                      /*!< HSI48 clock enable */
8638 #define RCC_CR_HSI48RDY_Pos                 (13U)
8639 #define RCC_CR_HSI48RDY_Msk                 (0x1UL << RCC_CR_HSI48RDY_Pos)          /*!< 0x00002000 */
8640 #define RCC_CR_HSI48RDY                     RCC_CR_HSI48RDY_Msk                     /*!< HSI48 clock ready */
8641 #define RCC_CR_HSEON_Pos                    (16U)
8642 #define RCC_CR_HSEON_Msk                    (0x1UL << RCC_CR_HSEON_Pos)             /*!< 0x00010000 */
8643 #define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                        /*!< External High Speed oscillator (HSE) clock enable */
8644 #define RCC_CR_HSERDY_Pos                   (17U)
8645 #define RCC_CR_HSERDY_Msk                   (0x1UL << RCC_CR_HSERDY_Pos)            /*!< 0x00020000 */
8646 #define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                       /*!< External High Speed oscillator (HSE) clock ready */
8647 #define RCC_CR_HSEBYP_Pos                   (18U)
8648 #define RCC_CR_HSEBYP_Msk                   (0x1UL << RCC_CR_HSEBYP_Pos)            /*!< 0x00040000 */
8649 #define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                       /*!< External High Speed oscillator (HSE) clock bypass */
8650 #define RCC_CR_HSECSSON_Pos                 (19U)
8651 #define RCC_CR_HSECSSON_Msk                 (0x1UL << RCC_CR_HSECSSON_Pos)          /*!< 0x00080000 */
8652 #define RCC_CR_HSECSSON                     RCC_CR_HSECSSON_Msk                     /*!< HSE Clock Security System enable */
8653 #define RCC_CR_HSEEXT_Pos                   (20U)
8654 #define RCC_CR_HSEEXT_Msk                   (0x1UL << RCC_CR_HSEEXT_Pos)            /*!< 0x00100000 */
8655 #define RCC_CR_HSEEXT                       RCC_CR_HSEEXT_Msk                       /*!< External High Speed clock type in Bypass mode */
8656 #define RCC_CR_PLL1ON_Pos                   (24U)
8657 #define RCC_CR_PLL1ON_Msk                   (0x1UL << RCC_CR_PLL1ON_Pos)            /*!< 0x01000000 */
8658 #define RCC_CR_PLL1ON                       RCC_CR_PLL1ON_Msk                       /*!< System PLL clock enable */
8659 #define RCC_CR_PLL1RDY_Pos                  (25U)
8660 #define RCC_CR_PLL1RDY_Msk                  (0x1UL << RCC_CR_PLL1RDY_Pos)           /*!< 0x02000000 */
8661 #define RCC_CR_PLL1RDY                      RCC_CR_PLL1RDY_Msk                      /*!< System PLL clock ready */
8662 #define RCC_CR_PLL2ON_Pos                   (26U)
8663 #define RCC_CR_PLL2ON_Msk                   (0x1UL << RCC_CR_PLL2ON_Pos)            /*!< 0x04000000 */
8664 #define RCC_CR_PLL2ON                       RCC_CR_PLL2ON_Msk                       /*!< PLL2 enable */
8665 #define RCC_CR_PLL2RDY_Pos                  (27U)
8666 #define RCC_CR_PLL2RDY_Msk                  (0x1UL << RCC_CR_PLL2RDY_Pos)           /*!< 0x08000000 */
8667 #define RCC_CR_PLL2RDY                      RCC_CR_PLL2RDY_Msk                      /*!< PLL2 ready */
8668 
8669 /********************  Bit definition for RCC_HSICFGR register  ***************/
8670 /*!< HSICAL configuration */
8671 #define RCC_HSICFGR_HSICAL_Pos               (0U)
8672 #define RCC_HSICFGR_HSICAL_Msk               (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000FFF */
8673 #define RCC_HSICFGR_HSICAL                   RCC_HSICFGR_HSICAL_Msk                   /*!< HSICAL[11:0] bits */
8674 #define RCC_HSICFGR_HSICAL_0                 (0x01UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000001 */
8675 #define RCC_HSICFGR_HSICAL_1                 (0x02UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000002 */
8676 #define RCC_HSICFGR_HSICAL_2                 (0x04UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000004 */
8677 #define RCC_HSICFGR_HSICAL_3                 (0x08UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000008 */
8678 #define RCC_HSICFGR_HSICAL_4                 (0x10UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000010 */
8679 #define RCC_HSICFGR_HSICAL_5                 (0x20UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000020 */
8680 #define RCC_HSICFGR_HSICAL_6                 (0x40UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000040 */
8681 #define RCC_HSICFGR_HSICAL_7                 (0x80UL << RCC_HSICFGR_HSICAL_Pos)       /*!< 0x00000080 */
8682 #define RCC_HSICFGR_HSICAL_8                 (0x100UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000100 */
8683 #define RCC_HSICFGR_HSICAL_9                 (0x200UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000200 */
8684 #define RCC_HSICFGR_HSICAL_10                (0x400UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000400 */
8685 #define RCC_HSICFGR_HSICAL_11                (0x800UL << RCC_HSICFGR_HSICAL_Pos)      /*!< 0x00000800 */
8686 
8687 /*!< HSITRIM configuration */
8688 #define RCC_HSICFGR_HSITRIM_Pos              (16U)
8689 #define RCC_HSICFGR_HSITRIM_Msk              (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x007F0000 */
8690 #define RCC_HSICFGR_HSITRIM                  RCC_HSICFGR_HSITRIM_Msk                  /*!< HSITRIM[6:0] bits */
8691 #define RCC_HSICFGR_HSITRIM_0                (0x01UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00010000 */
8692 #define RCC_HSICFGR_HSITRIM_1                (0x02UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00020000 */
8693 #define RCC_HSICFGR_HSITRIM_2                (0x04UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00040000 */
8694 #define RCC_HSICFGR_HSITRIM_3                (0x08UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00080000 */
8695 #define RCC_HSICFGR_HSITRIM_4                (0x10UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00100000 */
8696 #define RCC_HSICFGR_HSITRIM_5                (0x20UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00200000 */
8697 #define RCC_HSICFGR_HSITRIM_6                (0x40UL << RCC_HSICFGR_HSITRIM_Pos)      /*!< 0x00400000 */
8698 
8699 /********************  Bit definition for RCC_CRRCR register  *****************/
8700 /*!< HSI48CAL configuration */
8701 #define RCC_CRRCR_HSI48CAL_Pos              (0U)
8702 #define RCC_CRRCR_HSI48CAL_Msk              (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x000003FF */
8703 #define RCC_CRRCR_HSI48CAL                  RCC_CRRCR_HSI48CAL_Msk                  /*!< HSI48CAL[8:0] bits */
8704 #define RCC_CRRCR_HSI48CAL_0                (0x001UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000001 */
8705 #define RCC_CRRCR_HSI48CAL_1                (0x002UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000002 */
8706 #define RCC_CRRCR_HSI48CAL_2                (0x004UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000004 */
8707 #define RCC_CRRCR_HSI48CAL_3                (0x008UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000008 */
8708 #define RCC_CRRCR_HSI48CAL_4                (0x010UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000010 */
8709 #define RCC_CRRCR_HSI48CAL_5                (0x020UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000020 */
8710 #define RCC_CRRCR_HSI48CAL_6                (0x040UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000040 */
8711 #define RCC_CRRCR_HSI48CAL_7                (0x080UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000080 */
8712 #define RCC_CRRCR_HSI48CAL_8                (0x100UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000100 */
8713 #define RCC_CRRCR_HSI48CAL_9                (0x200UL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x00000200 */
8714 
8715 /********************  Bit definition for RCC_CSICFGR register  ***************/
8716 /*!< CSICAL configuration */
8717 #define RCC_CSICFGR_CSICAL_Pos               (0U)
8718 #define RCC_CSICFGR_CSICAL_Msk               (0xFFUL << RCC_CSICFGR_CSICAL_Pos)      /*!< 0x000000FF */
8719 #define RCC_CSICFGR_CSICAL                   RCC_CSICFGR_CSICAL_Msk                   /*!< CSICAL[7:0] bits */
8720 #define RCC_CSICFGR_CSICAL_0                 (0x01UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000001 */
8721 #define RCC_CSICFGR_CSICAL_1                 (0x02UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000002 */
8722 #define RCC_CSICFGR_CSICAL_2                 (0x04UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000004 */
8723 #define RCC_CSICFGR_CSICAL_3                 (0x08UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000008 */
8724 #define RCC_CSICFGR_CSICAL_4                 (0x10UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000010 */
8725 #define RCC_CSICFGR_CSICAL_5                 (0x20UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000020 */
8726 #define RCC_CSICFGR_CSICAL_6                 (0x40UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000040 */
8727 #define RCC_CSICFGR_CSICAL_7                 (0x80UL << RCC_CSICFGR_CSICAL_Pos)       /*!< 0x00000080 */
8728 
8729 /*!< CSITRIM configuration */
8730 #define RCC_CSICFGR_CSITRIM_Pos              (16U)
8731 #define RCC_CSICFGR_CSITRIM_Msk              (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x003F0000 */
8732 #define RCC_CSICFGR_CSITRIM                  RCC_CSICFGR_CSITRIM_Msk                  /*!< CSITRIM[5:0] bits */
8733 #define RCC_CSICFGR_CSITRIM_0                (0x01UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00010000 */
8734 #define RCC_CSICFGR_CSITRIM_1                (0x02UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00020000 */
8735 #define RCC_CSICFGR_CSITRIM_2                (0x04UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00040000 */
8736 #define RCC_CSICFGR_CSITRIM_3                (0x08UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00080000 */
8737 #define RCC_CSICFGR_CSITRIM_4                (0x10UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00100000 */
8738 #define RCC_CSICFGR_CSITRIM_5                (0x20UL << RCC_CSICFGR_CSITRIM_Pos)      /*!< 0x00200000 */
8739 
8740 /********************  Bit definition for RCC_CFGR1 register  ******************/
8741 /*!< SW configuration */
8742 #define RCC_CFGR1_SW_Pos                    (0U)
8743 #define RCC_CFGR1_SW_Msk                    (0x3UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000003 */
8744 #define RCC_CFGR1_SW                        RCC_CFGR1_SW_Msk                        /*!< SW[1:0] bits (System clock Switch) */
8745 #define RCC_CFGR1_SW_0                      (0x1UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000001 */
8746 #define RCC_CFGR1_SW_1                      (0x2UL << RCC_CFGR1_SW_Pos)             /*!< 0x00000002 */
8747 
8748 /*!< SWS configuration */
8749 #define RCC_CFGR1_SWS_Pos                   (3U)
8750 #define RCC_CFGR1_SWS_Msk                   (0x3UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000018 */
8751 #define RCC_CFGR1_SWS                       RCC_CFGR1_SWS_Msk                       /*!< SWS[1:0] bits (System Clock Switch Status) */
8752 #define RCC_CFGR1_SWS_0                     (0x1UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000008 */
8753 #define RCC_CFGR1_SWS_1                     (0x2UL << RCC_CFGR1_SWS_Pos)            /*!< 0x00000010 */
8754 
8755 #define RCC_CFGR1_STOPWUCK_Pos              (6U)
8756 #define RCC_CFGR1_STOPWUCK_Msk              (0x1UL << RCC_CFGR1_STOPWUCK_Pos)       /*!< 0x00000040 */
8757 #define RCC_CFGR1_STOPWUCK                  RCC_CFGR1_STOPWUCK_Msk                  /*!< Wake Up from stop and HSE CSS backup clock selection */
8758 #define RCC_CFGR1_STOPKERWUCK_Pos           (7U)
8759 #define RCC_CFGR1_STOPKERWUCK_Msk           (0x1UL << RCC_CFGR1_STOPKERWUCK_Pos)    /*!< 0x00000080 */
8760 #define RCC_CFGR1_STOPKERWUCK               RCC_CFGR1_STOPKERWUCK_Msk               /*!< Kernel Clock Selection after a Wake Up from STOP */
8761 
8762 /*!< RTCPRE configuration */
8763 #define RCC_CFGR1_RTCPRE_Pos                (8U)
8764 #define RCC_CFGR1_RTCPRE_Msk                (0x3FUL << RCC_CFGR1_RTCPRE_Pos)        /*!< 0x00003F00 */
8765 #define RCC_CFGR1_RTCPRE                    RCC_CFGR1_RTCPRE_Msk                    /*!< HSE division factor for RTC Clock */
8766 #define RCC_CFGR1_RTCPRE_0                  (0x1UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000100 */
8767 #define RCC_CFGR1_RTCPRE_1                  (0x2UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000200 */
8768 #define RCC_CFGR1_RTCPRE_2                  (0x4UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000400 */
8769 #define RCC_CFGR1_RTCPRE_3                  (0x8UL << RCC_CFGR1_RTCPRE_Pos)         /*!< 0x00000800 */
8770 #define RCC_CFGR1_RTCPRE_4                  (0x10UL << RCC_CFGR1_RTCPRE_Pos)        /*!< 0x00001000 */
8771 #define RCC_CFGR1_RTCPRE_5                  (0x20UL << RCC_CFGR1_RTCPRE_Pos)        /*!< 0x00002000 */
8772 
8773 /*!< TIMPRE configuration */
8774 #define RCC_CFGR1_TIMPRE_Pos                (15U)
8775 #define RCC_CFGR1_TIMPRE_Msk                (0x1UL << RCC_CFGR1_TIMPRE_Pos)
8776 #define RCC_CFGR1_TIMPRE                    RCC_CFGR1_TIMPRE_Msk                    /*!< 0x00008000 */
8777 
8778 /*!< MCO1 configuration */
8779 #define RCC_CFGR1_MCO1PRE_Pos               (18U)
8780 #define RCC_CFGR1_MCO1PRE_Msk               (0xFUL << RCC_CFGR1_MCO1PRE_Pos)
8781 #define RCC_CFGR1_MCO1PRE                   RCC_CFGR1_MCO1PRE_Msk                   /*!< 0x003C0000 */
8782 #define RCC_CFGR1_MCO1PRE_0                 (0x1UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00040000 */
8783 #define RCC_CFGR1_MCO1PRE_1                 (0x2UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00080000 */
8784 #define RCC_CFGR1_MCO1PRE_2                 (0x4UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00100000 */
8785 #define RCC_CFGR1_MCO1PRE_3                 (0x8UL << RCC_CFGR1_MCO1PRE_Pos)        /*!< 0x00200000 */
8786 
8787 #define RCC_CFGR1_MCO1SEL_Pos               (22U)
8788 #define RCC_CFGR1_MCO1SEL_Msk               (0x7UL << RCC_CFGR1_MCO1SEL_Pos)
8789 #define RCC_CFGR1_MCO1SEL                   RCC_CFGR1_MCO1SEL_Msk                   /*!< 0x01C00000 */
8790 #define RCC_CFGR1_MCO1SEL_0                 (0x1UL <<  RCC_CFGR1_MCO1SEL_Pos)       /*!< 0x00400000 */
8791 #define RCC_CFGR1_MCO1SEL_1                 (0x2UL <<  RCC_CFGR1_MCO1SEL_Pos)       /*!< 0x00800000 */
8792 #define RCC_CFGR1_MCO1SEL_2                 (0x4UL <<  RCC_CFGR1_MCO1SEL_Pos)       /*!< 0x01000000 */
8793 
8794 /*!< MCO2 configuration */
8795 #define RCC_CFGR1_MCO2PRE_Pos               (25U)
8796 #define RCC_CFGR1_MCO2PRE_Msk               (0xFUL << RCC_CFGR1_MCO2PRE_Pos)
8797 #define RCC_CFGR1_MCO2PRE                   RCC_CFGR1_MCO2PRE_Msk                   /*!< 0x1E000000 */
8798 #define RCC_CFGR1_MCO2PRE_0                 (0x1UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x02000000 */
8799 #define RCC_CFGR1_MCO2PRE_1                 (0x2UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x04000000 */
8800 #define RCC_CFGR1_MCO2PRE_2                 (0x4UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x08000000 */
8801 #define RCC_CFGR1_MCO2PRE_3                 (0x8UL << RCC_CFGR1_MCO2PRE_Pos)        /*!< 0x10000000 */
8802 
8803 #define RCC_CFGR1_MCO2SEL_Pos               (29U)
8804 #define RCC_CFGR1_MCO2SEL_Msk               (0x7UL << RCC_CFGR1_MCO2SEL_Pos)
8805 #define RCC_CFGR1_MCO2SEL                   RCC_CFGR1_MCO2SEL_Msk                   /*!< 0xE0000000 */
8806 #define RCC_CFGR1_MCO2SEL_0                 (0x1UL << RCC_CFGR1_MCO2SEL_Pos)        /*!< 0x20000000 */
8807 #define RCC_CFGR1_MCO2SEL_1                 (0x2UL << RCC_CFGR1_MCO2SEL_Pos)        /*!< 0x40000000 */
8808 #define RCC_CFGR1_MCO2SEL_2                 (0x4UL << RCC_CFGR1_MCO2SEL_Pos)        /*!< 0x80000000 */
8809 
8810 /********************  Bit definition for RCC_CFGR2 register  ******************/
8811 /*!< HPRE configuration */
8812 #define RCC_CFGR2_HPRE_Pos                  (0U)
8813 #define RCC_CFGR2_HPRE_Msk                  (0xFUL << RCC_CFGR2_HPRE_Pos)           /*!< 0x0000000F */
8814 #define RCC_CFGR2_HPRE                      RCC_CFGR2_HPRE_Msk                      /*!< HPRE[3:0] bits (AHB prescaler) */
8815 #define RCC_CFGR2_HPRE_0                    (0x1UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000001 */
8816 #define RCC_CFGR2_HPRE_1                    (0x2UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000002 */
8817 #define RCC_CFGR2_HPRE_2                    (0x4UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000004 */
8818 #define RCC_CFGR2_HPRE_3                    (0x8UL << RCC_CFGR2_HPRE_Pos)           /*!< 0x00000008 */
8819 
8820 /*!< PPRE1 configuration */
8821 #define RCC_CFGR2_PPRE1_Pos                 (4U)
8822 #define RCC_CFGR2_PPRE1_Msk                 (0x7UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000070 */
8823 #define RCC_CFGR2_PPRE1                     RCC_CFGR2_PPRE1_Msk                     /*!< PPRE1[2:0] bits (APB1 prescaler) */
8824 #define RCC_CFGR2_PPRE1_0                   (0x1UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000010 */
8825 #define RCC_CFGR2_PPRE1_1                   (0x2UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000020 */
8826 #define RCC_CFGR2_PPRE1_2                   (0x4UL << RCC_CFGR2_PPRE1_Pos)          /*!< 0x00000040 */
8827 
8828 /*!< PPRE2 configuration */
8829 #define RCC_CFGR2_PPRE2_Pos                 (8U)
8830 #define RCC_CFGR2_PPRE2_Msk                 (0x7UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000700 */
8831 #define RCC_CFGR2_PPRE2                     RCC_CFGR2_PPRE2_Msk                     /*!< PPRE2[2:0] bits (APB2 prescaler) */
8832 #define RCC_CFGR2_PPRE2_0                   (0x1UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000100 */
8833 #define RCC_CFGR2_PPRE2_1                   (0x2UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000200 */
8834 #define RCC_CFGR2_PPRE2_2                   (0x4UL << RCC_CFGR2_PPRE2_Pos)          /*!< 0x00000400 */
8835 
8836 /*!< PPRE3 configuration */
8837 #define RCC_CFGR2_PPRE3_Pos                 (12U)
8838 #define RCC_CFGR2_PPRE3_Msk                 (0x7UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00007000 */
8839 #define RCC_CFGR2_PPRE3                     RCC_CFGR2_PPRE3_Msk                     /*!< PPRE3[2:0] bits (APB3 prescaler) */
8840 #define RCC_CFGR2_PPRE3_0                   (0x1UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00001000 */
8841 #define RCC_CFGR2_PPRE3_1                   (0x2UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00002000 */
8842 #define RCC_CFGR2_PPRE3_2                   (0x4UL << RCC_CFGR2_PPRE3_Pos)          /*!< 0x00004000 */
8843 
8844 #define RCC_CFGR2_AHB1DIS_Pos               (16U)
8845 #define RCC_CFGR2_AHB1DIS_Msk               (0x1UL << RCC_CFGR2_AHB1DIS_Pos)        /*!< 0x00010000 */
8846 #define RCC_CFGR2_AHB1DIS                   RCC_CFGR2_AHB1DIS_Msk                   /*!< AHB1 clock disable */
8847 #define RCC_CFGR2_AHB2DIS_Pos               (17U)
8848 #define RCC_CFGR2_AHB2DIS_Msk               (0x1UL << RCC_CFGR2_AHB2DIS_Pos)        /*!< 0x00020000 */
8849 #define RCC_CFGR2_AHB2DIS                   RCC_CFGR2_AHB2DIS_Msk                   /*!< AHB2 clock disable */
8850 #define RCC_CFGR2_APB1DIS_Pos               (20U)
8851 #define RCC_CFGR2_APB1DIS_Msk               (0x1UL << RCC_CFGR2_APB1DIS_Pos)        /*!< 0x00100000 */
8852 #define RCC_CFGR2_APB1DIS                   RCC_CFGR2_APB1DIS_Msk                   /*!< APB1 clock disable */
8853 #define RCC_CFGR2_APB2DIS_Pos               (21U)
8854 #define RCC_CFGR2_APB2DIS_Msk               (0x1UL << RCC_CFGR2_APB2DIS_Pos)        /*!< 0x00200000 */
8855 #define RCC_CFGR2_APB2DIS                   RCC_CFGR2_APB2DIS_Msk                   /*!< APB2 clock disable */
8856 #define RCC_CFGR2_APB3DIS_Pos               (22U)
8857 #define RCC_CFGR2_APB3DIS_Msk               (0x1UL << RCC_CFGR2_APB3DIS_Pos)        /*!< 0x00400000 */
8858 #define RCC_CFGR2_APB3DIS                   RCC_CFGR2_APB3DIS_Msk                   /*!< APB3 clock disable */
8859 
8860 /********************  Bit definition for RCC_PLL1CFGR register  ***************/
8861 #define RCC_PLL1CFGR_PLL1SRC_Pos            (0U)
8862 #define RCC_PLL1CFGR_PLL1SRC_Msk            (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000003 */
8863 #define RCC_PLL1CFGR_PLL1SRC                RCC_PLL1CFGR_PLL1SRC_Msk
8864 #define RCC_PLL1CFGR_PLL1SRC_0              (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000001 */
8865 #define RCC_PLL1CFGR_PLL1SRC_1              (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos)     /*!< 0x00000002 */
8866 #define RCC_PLL1CFGR_PLL1RGE_Pos            (2U)
8867 #define RCC_PLL1CFGR_PLL1RGE_Msk            (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x0000000C */
8868 #define RCC_PLL1CFGR_PLL1RGE                RCC_PLL1CFGR_PLL1RGE_Msk
8869 #define RCC_PLL1CFGR_PLL1RGE_0              (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x00000004 */
8870 #define RCC_PLL1CFGR_PLL1RGE_1              (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos)     /*!< 0x00000008 */
8871 #define RCC_PLL1CFGR_PLL1FRACEN_Pos         (4U)
8872 #define RCC_PLL1CFGR_PLL1FRACEN_Msk         (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos)  /*!< 0x00000010 */
8873 #define RCC_PLL1CFGR_PLL1FRACEN             RCC_PLL1CFGR_PLL1FRACEN_Msk
8874 #define RCC_PLL1CFGR_PLL1VCOSEL_Pos         (5U)
8875 #define RCC_PLL1CFGR_PLL1VCOSEL_Msk         (0x1UL << RCC_PLL1CFGR_PLL1VCOSEL_Pos) /*!< 0x00000020 */
8876 #define RCC_PLL1CFGR_PLL1VCOSEL             RCC_PLL1CFGR_PLL1VCOSEL_Msk
8877 #define RCC_PLL1CFGR_PLL1M_Pos              (8U)
8878 #define RCC_PLL1CFGR_PLL1M_Msk              (0x3FUL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00003F00 */
8879 #define RCC_PLL1CFGR_PLL1M                  RCC_PLL1CFGR_PLL1M_Msk
8880 #define RCC_PLL1CFGR_PLL1M_0                (0x01UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000100 */
8881 #define RCC_PLL1CFGR_PLL1M_1                (0x02UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000200 */
8882 #define RCC_PLL1CFGR_PLL1M_2                (0x04UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000400 */
8883 #define RCC_PLL1CFGR_PLL1M_3                (0x08UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00000800 */
8884 #define RCC_PLL1CFGR_PLL1M_4                (0x10UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00001000 */
8885 #define RCC_PLL1CFGR_PLL1M_5                (0x20UL << RCC_PLL1CFGR_PLL1M_Pos)      /*!< 0x00002000 */
8886 #define RCC_PLL1CFGR_PLL1PEN_Pos            (16U)
8887 #define RCC_PLL1CFGR_PLL1PEN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos)     /*!< 0x00010000 */
8888 #define RCC_PLL1CFGR_PLL1PEN                RCC_PLL1CFGR_PLL1PEN_Msk
8889 #define RCC_PLL1CFGR_PLL1QEN_Pos            (17U)
8890 #define RCC_PLL1CFGR_PLL1QEN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos)     /*!< 0x00020000 */
8891 #define RCC_PLL1CFGR_PLL1QEN                RCC_PLL1CFGR_PLL1QEN_Msk
8892 #define RCC_PLL1CFGR_PLL1REN_Pos            (18U)
8893 #define RCC_PLL1CFGR_PLL1REN_Msk            (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos)     /*!< 0x00040000 */
8894 #define RCC_PLL1CFGR_PLL1REN                RCC_PLL1CFGR_PLL1REN_Msk
8895 
8896 /********************  Bit definition for RCC_PLL2CFGR register  ***************/
8897 #define RCC_PLL2CFGR_PLL2SRC_Pos            (0U)
8898 #define RCC_PLL2CFGR_PLL2SRC_Msk            (0x3UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000003 */
8899 #define RCC_PLL2CFGR_PLL2SRC                RCC_PLL2CFGR_PLL2SRC_Msk
8900 #define RCC_PLL2CFGR_PLL2SRC_0              (0x1UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000001 */
8901 #define RCC_PLL2CFGR_PLL2SRC_1              (0x2UL << RCC_PLL2CFGR_PLL2SRC_Pos)     /*!< 0x00000002 */
8902 #define RCC_PLL2CFGR_PLL2RGE_Pos            (2U)
8903 #define RCC_PLL2CFGR_PLL2RGE_Msk            (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x0000000C */
8904 #define RCC_PLL2CFGR_PLL2RGE                RCC_PLL2CFGR_PLL2RGE_Msk
8905 #define RCC_PLL2CFGR_PLL2RGE_0              (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x00000004 */
8906 #define RCC_PLL2CFGR_PLL2RGE_1              (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos)     /*!< 0x00000008 */
8907 #define RCC_PLL2CFGR_PLL2FRACEN_Pos         (4U)
8908 #define RCC_PLL2CFGR_PLL2FRACEN_Msk         (0x1UL << RCC_PLL2CFGR_PLL2FRACEN_Pos)  /*!< 0x00000010 */
8909 #define RCC_PLL2CFGR_PLL2FRACEN             RCC_PLL2CFGR_PLL2FRACEN_Msk
8910 #define RCC_PLL2CFGR_PLL2VCOSEL_Pos         (5U)
8911 #define RCC_PLL2CFGR_PLL2VCOSEL_Msk         (0x1UL << RCC_PLL2CFGR_PLL2VCOSEL_Pos)  /*!< 0x00000020 */
8912 #define RCC_PLL2CFGR_PLL2VCOSEL             RCC_PLL2CFGR_PLL2VCOSEL_Msk
8913 #define RCC_PLL2CFGR_PLL2M_Pos              (8U)
8914 #define RCC_PLL2CFGR_PLL2M_Msk              (0x3FUL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00003F00 */
8915 #define RCC_PLL2CFGR_PLL2M                  RCC_PLL2CFGR_PLL2M_Msk
8916 #define RCC_PLL2CFGR_PLL2M_0                (0x01UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000100 */
8917 #define RCC_PLL2CFGR_PLL2M_1                (0x02UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000200 */
8918 #define RCC_PLL2CFGR_PLL2M_2                (0x04UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000400 */
8919 #define RCC_PLL2CFGR_PLL2M_3                (0x08UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00000800 */
8920 #define RCC_PLL2CFGR_PLL2M_4                (0x10UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00001000 */
8921 #define RCC_PLL2CFGR_PLL2M_5                (0x20UL << RCC_PLL2CFGR_PLL2M_Pos)      /*!< 0x00002000 */
8922 #define RCC_PLL2CFGR_PLL2PEN_Pos            (16U)
8923 #define RCC_PLL2CFGR_PLL2PEN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2PEN_Pos)     /*!< 0x00010000 */
8924 #define RCC_PLL2CFGR_PLL2PEN                RCC_PLL2CFGR_PLL2PEN_Msk
8925 #define RCC_PLL2CFGR_PLL2QEN_Pos            (17U)
8926 #define RCC_PLL2CFGR_PLL2QEN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2QEN_Pos)     /*!< 0x00020000 */
8927 #define RCC_PLL2CFGR_PLL2QEN                RCC_PLL2CFGR_PLL2QEN_Msk
8928 #define RCC_PLL2CFGR_PLL2REN_Pos            (18U)
8929 #define RCC_PLL2CFGR_PLL2REN_Msk            (0x1UL << RCC_PLL2CFGR_PLL2REN_Pos)     /*!< 0x00040000 */
8930 #define RCC_PLL2CFGR_PLL2REN                RCC_PLL2CFGR_PLL2REN_Msk
8931 
8932 /********************  Bit definition for RCC_PLL1DIVR register  ***************/
8933 #define RCC_PLL1DIVR_PLL1N_Pos              (0U)
8934 #define RCC_PLL1DIVR_PLL1N_Msk              (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x000001FF */
8935 #define RCC_PLL1DIVR_PLL1N                  RCC_PLL1DIVR_PLL1N_Msk
8936 #define RCC_PLL1DIVR_PLL1N_0                (0x001UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000001 */
8937 #define RCC_PLL1DIVR_PLL1N_1                (0x002UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000002 */
8938 #define RCC_PLL1DIVR_PLL1N_2                (0x004UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000004 */
8939 #define RCC_PLL1DIVR_PLL1N_3                (0x008UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000008 */
8940 #define RCC_PLL1DIVR_PLL1N_4                (0x010UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000010 */
8941 #define RCC_PLL1DIVR_PLL1N_5                (0x020UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000020 */
8942 #define RCC_PLL1DIVR_PLL1N_6                (0x040UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000040 */
8943 #define RCC_PLL1DIVR_PLL1N_7                (0x080UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000080 */
8944 #define RCC_PLL1DIVR_PLL1N_8                (0x100UL << RCC_PLL1DIVR_PLL1N_Pos)     /*!< 0x00000100 */
8945 #define RCC_PLL1DIVR_PLL1P_Pos              (9U)
8946 #define RCC_PLL1DIVR_PLL1P_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos)      /*!< 0x0000FE00 */
8947 #define RCC_PLL1DIVR_PLL1P                  RCC_PLL1DIVR_PLL1P_Msk
8948 #define RCC_PLL1DIVR_PLL1P_0                (0x001UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000200 */
8949 #define RCC_PLL1DIVR_PLL1P_1                (0x002UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000400 */
8950 #define RCC_PLL1DIVR_PLL1P_2                (0x004UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00000800 */
8951 #define RCC_PLL1DIVR_PLL1P_3                (0x008UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00001000 */
8952 #define RCC_PLL1DIVR_PLL1P_4                (0x010UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00002000 */
8953 #define RCC_PLL1DIVR_PLL1P_5                (0x020UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00004000 */
8954 #define RCC_PLL1DIVR_PLL1P_6                (0x040UL << RCC_PLL1DIVR_PLL1P_Pos)     /*!< 0x00008000 */
8955 #define RCC_PLL1DIVR_PLL1Q_Pos              (16U)
8956 #define RCC_PLL1DIVR_PLL1Q_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos)      /*!< 0x007F0000 */
8957 #define RCC_PLL1DIVR_PLL1Q                  RCC_PLL1DIVR_PLL1Q_Msk
8958 #define RCC_PLL1DIVR_PLL1Q_0                (0x001UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00010000 */
8959 #define RCC_PLL1DIVR_PLL1Q_1                (0x002UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00020000 */
8960 #define RCC_PLL1DIVR_PLL1Q_2                (0x004UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00040000 */
8961 #define RCC_PLL1DIVR_PLL1Q_3                (0x008UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00080000 */
8962 #define RCC_PLL1DIVR_PLL1Q_4                (0x010UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00100000 */
8963 #define RCC_PLL1DIVR_PLL1Q_5                (0x020UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00200020 */
8964 #define RCC_PLL1DIVR_PLL1Q_6                (0x040UL << RCC_PLL1DIVR_PLL1Q_Pos)     /*!< 0x00400000 */
8965 #define RCC_PLL1DIVR_PLL1R_Pos              (24U)
8966 #define RCC_PLL1DIVR_PLL1R_Msk              (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos)      /*!< 0x7F000000 */
8967 #define RCC_PLL1DIVR_PLL1R                  RCC_PLL1DIVR_PLL1R_Msk
8968 #define RCC_PLL1DIVR_PLL1R_0                (0x001UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x01000000 */
8969 #define RCC_PLL1DIVR_PLL1R_1                (0x002UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x02000000 */
8970 #define RCC_PLL1DIVR_PLL1R_2                (0x004UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x04000000 */
8971 #define RCC_PLL1DIVR_PLL1R_3                (0x008UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x08000000 */
8972 #define RCC_PLL1DIVR_PLL1R_4                (0x010UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x10000000 */
8973 #define RCC_PLL1DIVR_PLL1R_5                (0x020UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x20000000 */
8974 #define RCC_PLL1DIVR_PLL1R_6                (0x040UL << RCC_PLL1DIVR_PLL1R_Pos)     /*!< 0x40000000 */
8975 
8976 /********************  Bit definition for RCC_PLL1FRACR register  ***************/
8977 #define RCC_PLL1FRACR_PLL1FRACN_Pos         (3U)
8978 #define RCC_PLL1FRACR_PLL1FRACN_Msk         (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x0000FFF8 */
8979 #define RCC_PLL1FRACR_PLL1FRACN             RCC_PLL1FRACR_PLL1FRACN_Msk
8980 #define RCC_PLL1FRACR_PLL1FRACN_0           (0x0001UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000008 */
8981 #define RCC_PLL1FRACR_PLL1FRACN_1           (0x0002UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000010 */
8982 #define RCC_PLL1FRACR_PLL1FRACN_2           (0x0004UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000020 */
8983 #define RCC_PLL1FRACR_PLL1FRACN_3           (0x0008UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000040 */
8984 #define RCC_PLL1FRACR_PLL1FRACN_4           (0x0010UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000080 */
8985 #define RCC_PLL1FRACR_PLL1FRACN_5           (0x0020UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000100 */
8986 #define RCC_PLL1FRACR_PLL1FRACN_6           (0x0040UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000200 */
8987 #define RCC_PLL1FRACR_PLL1FRACN_7           (0x0080UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000400 */
8988 #define RCC_PLL1FRACR_PLL1FRACN_8           (0x0100UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00000800 */
8989 #define RCC_PLL1FRACR_PLL1FRACN_9           (0x0200UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00001000 */
8990 #define RCC_PLL1FRACR_PLL1FRACN_10          (0x0400UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00002000 */
8991 #define RCC_PLL1FRACR_PLL1FRACN_11          (0x0800UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00004000 */
8992 #define RCC_PLL1FRACR_PLL1FRACN_12          (0x1000UL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x00008000 */
8993 
8994 /********************  Bit definition for RCC_PLL2DIVR register  ***************/
8995 #define RCC_PLL2DIVR_PLL2N_Pos              (0U)
8996 #define RCC_PLL2DIVR_PLL2N_Msk              (0x1FFUL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x000001FF */
8997 #define RCC_PLL2DIVR_PLL2N                  RCC_PLL2DIVR_PLL2N_Msk
8998 #define RCC_PLL2DIVR_PLL2N_0                (0x001UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000001 */
8999 #define RCC_PLL2DIVR_PLL2N_1                (0x002UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000002 */
9000 #define RCC_PLL2DIVR_PLL2N_2                (0x004UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000004 */
9001 #define RCC_PLL2DIVR_PLL2N_3                (0x008UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000008 */
9002 #define RCC_PLL2DIVR_PLL2N_4                (0x010UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000010 */
9003 #define RCC_PLL2DIVR_PLL2N_5                (0x020UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000020 */
9004 #define RCC_PLL2DIVR_PLL2N_6                (0x040UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000040 */
9005 #define RCC_PLL2DIVR_PLL2N_7                (0x080UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000080 */
9006 #define RCC_PLL2DIVR_PLL2N_8                (0x100UL << RCC_PLL2DIVR_PLL2N_Pos)     /*!< 0x00000100 */
9007 #define RCC_PLL2DIVR_PLL2P_Pos              (9U)
9008 #define RCC_PLL2DIVR_PLL2P_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2P_Pos)      /*!< 0x0000FE00 */
9009 #define RCC_PLL2DIVR_PLL2P                  RCC_PLL2DIVR_PLL2P_Msk
9010 #define RCC_PLL2DIVR_PLL2P_0                (0x001UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000200 */
9011 #define RCC_PLL2DIVR_PLL2P_1                (0x002UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000400 */
9012 #define RCC_PLL2DIVR_PLL2P_2                (0x004UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00000800 */
9013 #define RCC_PLL2DIVR_PLL2P_3                (0x008UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00001000 */
9014 #define RCC_PLL2DIVR_PLL2P_4                (0x010UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00002000 */
9015 #define RCC_PLL2DIVR_PLL2P_5                (0x020UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00004000 */
9016 #define RCC_PLL2DIVR_PLL2P_6                (0x040UL << RCC_PLL2DIVR_PLL2P_Pos)     /*!< 0x00008000 */
9017 #define RCC_PLL2DIVR_PLL2Q_Pos              (16U)
9018 #define RCC_PLL2DIVR_PLL2Q_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2Q_Pos)      /*!< 0x007F0000 */
9019 #define RCC_PLL2DIVR_PLL2Q                  RCC_PLL2DIVR_PLL2Q_Msk
9020 #define RCC_PLL2DIVR_PLL2Q_0                (0x001UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00010000 */
9021 #define RCC_PLL2DIVR_PLL2Q_1                (0x002UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00020000 */
9022 #define RCC_PLL2DIVR_PLL2Q_2                (0x004UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00040000 */
9023 #define RCC_PLL2DIVR_PLL2Q_3                (0x008UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00080000 */
9024 #define RCC_PLL2DIVR_PLL2Q_4                (0x010UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00100000 */
9025 #define RCC_PLL2DIVR_PLL2Q_5                (0x020UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00200020 */
9026 #define RCC_PLL2DIVR_PLL2Q_6                (0x040UL << RCC_PLL2DIVR_PLL2Q_Pos)     /*!< 0x00400000 */
9027 #define RCC_PLL2DIVR_PLL2R_Pos              (24U)
9028 #define RCC_PLL2DIVR_PLL2R_Msk              (0x7FUL << RCC_PLL2DIVR_PLL2R_Pos)      /*!< 0x7F000000 */
9029 #define RCC_PLL2DIVR_PLL2R                  RCC_PLL2DIVR_PLL2R_Msk
9030 #define RCC_PLL2DIVR_PLL2R_0                (0x001UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x01000000 */
9031 #define RCC_PLL2DIVR_PLL2R_1                (0x002UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x02000000 */
9032 #define RCC_PLL2DIVR_PLL2R_2                (0x004UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x04000000 */
9033 #define RCC_PLL2DIVR_PLL2R_3                (0x008UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x08000000 */
9034 #define RCC_PLL2DIVR_PLL2R_4                (0x010UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x10000000 */
9035 #define RCC_PLL2DIVR_PLL2R_5                (0x020UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x20000000 */
9036 #define RCC_PLL2DIVR_PLL2R_6                (0x040UL << RCC_PLL2DIVR_PLL2R_Pos)     /*!< 0x40000000 */
9037 
9038 /********************  Bit definition for RCC_PLL2FRACR register  ***************/
9039 #define RCC_PLL2FRACR_PLL2FRACN_Pos         (3U)
9040 #define RCC_PLL2FRACR_PLL2FRACN_Msk         (0x1FFFUL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x0000FFF8 */
9041 #define RCC_PLL2FRACR_PLL2FRACN             RCC_PLL2FRACR_PLL2FRACN_Msk
9042 #define RCC_PLL2FRACR_PLL2FRACN_0           (0x0001UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000008 */
9043 #define RCC_PLL2FRACR_PLL2FRACN_1           (0x0002UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000010 */
9044 #define RCC_PLL2FRACR_PLL2FRACN_2           (0x0004UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000020 */
9045 #define RCC_PLL2FRACR_PLL2FRACN_3           (0x0008UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000040 */
9046 #define RCC_PLL2FRACR_PLL2FRACN_4           (0x0010UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000080 */
9047 #define RCC_PLL2FRACR_PLL2FRACN_5           (0x0020UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000100 */
9048 #define RCC_PLL2FRACR_PLL2FRACN_6           (0x0040UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000200 */
9049 #define RCC_PLL2FRACR_PLL2FRACN_7           (0x0080UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000400 */
9050 #define RCC_PLL2FRACR_PLL2FRACN_8           (0x0100UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00000800 */
9051 #define RCC_PLL2FRACR_PLL2FRACN_9           (0x0200UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00001000 */
9052 #define RCC_PLL2FRACR_PLL2FRACN_10          (0x0400UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00002000 */
9053 #define RCC_PLL2FRACR_PLL2FRACN_11          (0x0800UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00004000 */
9054 #define RCC_PLL2FRACR_PLL2FRACN_12          (0x1000UL << RCC_PLL2FRACR_PLL2FRACN_Pos) /*!< 0x00008000 */
9055 
9056 /********************  Bit definition for RCC_CIER register  ******************/
9057 #define RCC_CIER_LSIRDYIE_Pos               (0U)
9058 #define RCC_CIER_LSIRDYIE_Msk               (0x1UL << RCC_CIER_LSIRDYIE_Pos)        /*!< 0x00000001 */
9059 #define RCC_CIER_LSIRDYIE                   RCC_CIER_LSIRDYIE_Msk
9060 #define RCC_CIER_LSERDYIE_Pos               (1U)
9061 #define RCC_CIER_LSERDYIE_Msk               (0x1UL << RCC_CIER_LSERDYIE_Pos)        /*!< 0x00000002 */
9062 #define RCC_CIER_LSERDYIE                   RCC_CIER_LSERDYIE_Msk
9063 #define RCC_CIER_CSIRDYIE_Pos               (2U)
9064 #define RCC_CIER_CSIRDYIE_Msk               (0x1UL << RCC_CIER_CSIRDYIE_Pos)        /*!< 0x00000004 */
9065 #define RCC_CIER_CSIRDYIE                   RCC_CIER_CSIRDYIE_Msk
9066 #define RCC_CIER_HSIRDYIE_Pos               (3U)
9067 #define RCC_CIER_HSIRDYIE_Msk               (0x1UL << RCC_CIER_HSIRDYIE_Pos)        /*!< 0x00000008 */
9068 #define RCC_CIER_HSIRDYIE                   RCC_CIER_HSIRDYIE_Msk
9069 #define RCC_CIER_HSERDYIE_Pos               (4U)
9070 #define RCC_CIER_HSERDYIE_Msk               (0x1UL << RCC_CIER_HSERDYIE_Pos)        /*!< 0x00000010 */
9071 #define RCC_CIER_HSERDYIE                   RCC_CIER_HSERDYIE_Msk
9072 #define RCC_CIER_HSI48RDYIE_Pos             (5U)
9073 #define RCC_CIER_HSI48RDYIE_Msk             (0x1UL << RCC_CIER_HSI48RDYIE_Pos)      /*!< 0x00000020 */
9074 #define RCC_CIER_HSI48RDYIE                 RCC_CIER_HSI48RDYIE_Msk
9075 #define RCC_CIER_PLL1RDYIE_Pos              (6U)
9076 #define RCC_CIER_PLL1RDYIE_Msk              (0x1UL << RCC_CIER_PLL1RDYIE_Pos)       /*!< 0x00000040 */
9077 #define RCC_CIER_PLL1RDYIE                  RCC_CIER_PLL1RDYIE_Msk
9078 #define RCC_CIER_PLL2RDYIE_Pos              (7U)
9079 #define RCC_CIER_PLL2RDYIE_Msk              (0x1UL << RCC_CIER_PLL2RDYIE_Pos)       /*!< 0x00000080 */
9080 #define RCC_CIER_PLL2RDYIE                  RCC_CIER_PLL2RDYIE_Msk
9081 
9082 /********************  Bit definition for RCC_CIFR register  ****************/
9083 #define RCC_CIFR_LSIRDYF_Pos                (0U)
9084 #define RCC_CIFR_LSIRDYF_Msk                (0x1UL << RCC_CIFR_LSIRDYF_Pos)         /*!< 0x00000001 */
9085 #define RCC_CIFR_LSIRDYF                    RCC_CIFR_LSIRDYF_Msk
9086 #define RCC_CIFR_LSERDYF_Pos                (1U)
9087 #define RCC_CIFR_LSERDYF_Msk                (0x1UL << RCC_CIFR_LSERDYF_Pos)         /*!< 0x00000002 */
9088 #define RCC_CIFR_LSERDYF                    RCC_CIFR_LSERDYF_Msk
9089 #define RCC_CIFR_CSIRDYF_Pos                (2U)
9090 #define RCC_CIFR_CSIRDYF_Msk                (0x1UL << RCC_CIFR_CSIRDYF_Pos)         /*!< 0x00000004 */
9091 #define RCC_CIFR_CSIRDYF                    RCC_CIFR_CSIRDYF_Msk
9092 #define RCC_CIFR_HSIRDYF_Pos                (3U)
9093 #define RCC_CIFR_HSIRDYF_Msk                (0x1UL << RCC_CIFR_HSIRDYF_Pos)         /*!< 0x00000008 */
9094 #define RCC_CIFR_HSIRDYF                    RCC_CIFR_HSIRDYF_Msk
9095 #define RCC_CIFR_HSERDYF_Pos                (4U)
9096 #define RCC_CIFR_HSERDYF_Msk                (0x1UL << RCC_CIFR_HSERDYF_Pos)         /*!< 0x00000010 */
9097 #define RCC_CIFR_HSERDYF                    RCC_CIFR_HSERDYF_Msk
9098 #define RCC_CIFR_HSI48RDYF_Pos              (5U)
9099 #define RCC_CIFR_HSI48RDYF_Msk              (0x1UL << RCC_CIFR_HSI48RDYF_Pos)       /*!< 0x00000020 */
9100 #define RCC_CIFR_HSI48RDYF                  RCC_CIFR_HSI48RDYF_Msk
9101 #define RCC_CIFR_PLL1RDYF_Pos               (6U)
9102 #define RCC_CIFR_PLL1RDYF_Msk               (0x1UL << RCC_CIFR_PLL1RDYF_Pos)        /*!< 0x00000040 */
9103 #define RCC_CIFR_PLL1RDYF                   RCC_CIFR_PLL1RDYF_Msk
9104 #define RCC_CIFR_PLL2RDYF_Pos               (7U)
9105 #define RCC_CIFR_PLL2RDYF_Msk               (0x1UL << RCC_CIFR_PLL2RDYF_Pos)        /*!< 0x00000080 */
9106 #define RCC_CIFR_PLL2RDYF                   RCC_CIFR_PLL2RDYF_Msk
9107 #define RCC_CIFR_HSECSSF_Pos                (10U)
9108 #define RCC_CIFR_HSECSSF_Msk                (0x1UL << RCC_CIFR_HSECSSF_Pos)         /*!< 0x00000400 */
9109 #define RCC_CIFR_HSECSSF                    RCC_CIFR_HSECSSF_Msk
9110 
9111 /********************  Bit definition for RCC_CICR register  ****************/
9112 #define RCC_CICR_LSIRDYC_Pos                (0U)
9113 #define RCC_CICR_LSIRDYC_Msk                (0x1UL << RCC_CICR_LSIRDYC_Pos)         /*!< 0x00000001 */
9114 #define RCC_CICR_LSIRDYC                    RCC_CICR_LSIRDYC_Msk
9115 #define RCC_CICR_LSERDYC_Pos                (1U)
9116 #define RCC_CICR_LSERDYC_Msk                (0x1UL << RCC_CICR_LSERDYC_Pos)         /*!< 0x00000002 */
9117 #define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk
9118 #define RCC_CICR_CSIRDYC_Pos                (2U)
9119 #define RCC_CICR_CSIRDYC_Msk                (0x1UL << RCC_CICR_CSIRDYC_Pos)         /*!< 0x00000004 */
9120 #define RCC_CICR_CSIRDYC                    RCC_CICR_CSIRDYC_Msk
9121 #define RCC_CICR_HSIRDYC_Pos                (3U)
9122 #define RCC_CICR_HSIRDYC_Msk                (0x1UL << RCC_CICR_HSIRDYC_Pos)         /*!< 0x00000008 */
9123 #define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk
9124 #define RCC_CICR_HSERDYC_Pos                (4U)
9125 #define RCC_CICR_HSERDYC_Msk                (0x1UL << RCC_CICR_HSERDYC_Pos)         /*!< 0x00000010 */
9126 #define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk
9127 #define RCC_CICR_HSI48RDYC_Pos              (5U)
9128 #define RCC_CICR_HSI48RDYC_Msk              (0x1UL << RCC_CICR_HSI48RDYC_Pos)       /*!< 0x00000020 */
9129 #define RCC_CICR_HSI48RDYC                  RCC_CICR_HSI48RDYC_Msk
9130 #define RCC_CICR_PLL1RDYC_Pos               (6U)
9131 #define RCC_CICR_PLL1RDYC_Msk               (0x1UL << RCC_CICR_PLL1RDYC_Pos)        /*!< 0x00000040 */
9132 #define RCC_CICR_PLL1RDYC                   RCC_CICR_PLL1RDYC_Msk
9133 #define RCC_CICR_PLL2RDYC_Pos               (7U)
9134 #define RCC_CICR_PLL2RDYC_Msk               (0x1UL << RCC_CICR_PLL2RDYC_Pos)        /*!< 0x00000080 */
9135 #define RCC_CICR_PLL2RDYC                   RCC_CICR_PLL2RDYC_Msk
9136 #define RCC_CICR_HSECSSC_Pos                (10U)
9137 #define RCC_CICR_HSECSSC_Msk                (0x1UL << RCC_CICR_HSECSSC_Pos)         /*!< 0x00000400 */
9138 #define RCC_CICR_HSECSSC                    RCC_CICR_HSECSSC_Msk
9139 
9140 /********************  Bit definition for RCC_AHB1RSTR register  **************/
9141 #define RCC_AHB1RSTR_GPDMA1RST_Pos          (0U)
9142 #define RCC_AHB1RSTR_GPDMA1RST_Msk          (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos)   /*!< 0x00000001 */
9143 #define RCC_AHB1RSTR_GPDMA1RST              RCC_AHB1RSTR_GPDMA1RST_Msk
9144 #define RCC_AHB1RSTR_GPDMA2RST_Pos          (1U)
9145 #define RCC_AHB1RSTR_GPDMA2RST_Msk          (0x1UL << RCC_AHB1RSTR_GPDMA2RST_Pos)   /*!< 0x00000002 */
9146 #define RCC_AHB1RSTR_GPDMA2RST              RCC_AHB1RSTR_GPDMA2RST_Msk
9147 #define RCC_AHB1RSTR_CRCRST_Pos             (12U)
9148 #define RCC_AHB1RSTR_CRCRST_Msk             (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)      /*!< 0x00001000 */
9149 #define RCC_AHB1RSTR_CRCRST                 RCC_AHB1RSTR_CRCRST_Msk
9150 #define RCC_AHB1RSTR_RAMCFGRST_Pos          (17U)
9151 #define RCC_AHB1RSTR_RAMCFGRST_Msk          (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos)   /*!< 0x00020000 */
9152 #define RCC_AHB1RSTR_RAMCFGRST              RCC_AHB1RSTR_RAMCFGRST_Msk
9153 #define RCC_AHB1RSTR_TZSC1RST_Pos           (24U)
9154 #define RCC_AHB1RSTR_TZSC1RST_Msk           (0x1UL << RCC_AHB1RSTR_TZSC1RST_Pos)    /*!< 0x01000000 */
9155 #define RCC_AHB1RSTR_TZSC1RST               RCC_AHB1RSTR_TZSC1RST_Msk
9156 
9157 /********************  Bit definition for RCC_AHB2RSTR register  **************/
9158 #define RCC_AHB2RSTR_GPIOARST_Pos           (0U)
9159 #define RCC_AHB2RSTR_GPIOARST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)    /*!< 0x00000001 */
9160 #define RCC_AHB2RSTR_GPIOARST               RCC_AHB2RSTR_GPIOARST_Msk
9161 #define RCC_AHB2RSTR_GPIOBRST_Pos           (1U)
9162 #define RCC_AHB2RSTR_GPIOBRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)    /*!< 0x00000002 */
9163 #define RCC_AHB2RSTR_GPIOBRST               RCC_AHB2RSTR_GPIOBRST_Msk
9164 #define RCC_AHB2RSTR_GPIOCRST_Pos           (2U)
9165 #define RCC_AHB2RSTR_GPIOCRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)    /*!< 0x00000004 */
9166 #define RCC_AHB2RSTR_GPIOCRST               RCC_AHB2RSTR_GPIOCRST_Msk
9167 #define RCC_AHB2RSTR_GPIODRST_Pos           (3U)
9168 #define RCC_AHB2RSTR_GPIODRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)    /*!< 0x00000008 */
9169 #define RCC_AHB2RSTR_GPIODRST               RCC_AHB2RSTR_GPIODRST_Msk
9170 #define RCC_AHB2RSTR_GPIOHRST_Pos           (7U)
9171 #define RCC_AHB2RSTR_GPIOHRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)    /*!< 0x00000080 */
9172 #define RCC_AHB2RSTR_GPIOHRST               RCC_AHB2RSTR_GPIOHRST_Msk
9173 #define RCC_AHB2RSTR_ADCRST_Pos             (10U)
9174 #define RCC_AHB2RSTR_ADCRST_Msk             (0x1UL << RCC_AHB2RSTR_ADCRST_Pos)      /*!< 0x00000400 */
9175 #define RCC_AHB2RSTR_ADCRST                 RCC_AHB2RSTR_ADCRST_Msk
9176 #define RCC_AHB2RSTR_DAC1RST_Pos            (11U)
9177 #define RCC_AHB2RSTR_DAC1RST_Msk            (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)     /*!< 0x00000800 */
9178 #define RCC_AHB2RSTR_DAC1RST                RCC_AHB2RSTR_DAC1RST_Msk
9179 #define RCC_AHB2RSTR_HASHRST_Pos            (17U)
9180 #define RCC_AHB2RSTR_HASHRST_Msk            (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)     /*!< 0x00020000 */
9181 #define RCC_AHB2RSTR_HASHRST                RCC_AHB2RSTR_HASHRST_Msk
9182 #define RCC_AHB2RSTR_RNGRST_Pos             (18U)
9183 #define RCC_AHB2RSTR_RNGRST_Msk             (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)      /*!< 0x00040000 */
9184 #define RCC_AHB2RSTR_RNGRST                 RCC_AHB2RSTR_RNGRST_Msk
9185 
9186 /********************  Bit definition for RCC_APB1LRSTR register  **************/
9187 #define RCC_APB1LRSTR_TIM2RST_Pos           (0U)
9188 #define RCC_APB1LRSTR_TIM2RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)    /*!< 0x00000001 */
9189 #define RCC_APB1LRSTR_TIM2RST               RCC_APB1LRSTR_TIM2RST_Msk
9190 #define RCC_APB1LRSTR_TIM3RST_Pos           (1U)
9191 #define RCC_APB1LRSTR_TIM3RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos)    /*!< 0x00000002 */
9192 #define RCC_APB1LRSTR_TIM3RST               RCC_APB1LRSTR_TIM3RST_Msk
9193 #define RCC_APB1LRSTR_TIM6RST_Pos           (4U)
9194 #define RCC_APB1LRSTR_TIM6RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)    /*!< 0x00000010 */
9195 #define RCC_APB1LRSTR_TIM6RST               RCC_APB1LRSTR_TIM6RST_Msk
9196 #define RCC_APB1LRSTR_TIM7RST_Pos           (5U)
9197 #define RCC_APB1LRSTR_TIM7RST_Msk           (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)    /*!< 0x00000020 */
9198 #define RCC_APB1LRSTR_TIM7RST               RCC_APB1LRSTR_TIM7RST_Msk
9199 #define RCC_APB1LRSTR_OPAMPRST_Pos          (13U)
9200 #define RCC_APB1LRSTR_OPAMPRST_Msk          (0x1UL << RCC_APB1LRSTR_OPAMPRST_Pos)  /*!< 0x00002000 */
9201 #define RCC_APB1LRSTR_OPAMPRST              RCC_APB1LRSTR_OPAMPRST_Msk
9202 #define RCC_APB1LRSTR_SPI2RST_Pos           (14U)
9203 #define RCC_APB1LRSTR_SPI2RST_Msk           (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)    /*!< 0x00004000 */
9204 #define RCC_APB1LRSTR_SPI2RST               RCC_APB1LRSTR_SPI2RST_Msk
9205 #define RCC_APB1LRSTR_SPI3RST_Pos           (15U)
9206 #define RCC_APB1LRSTR_SPI3RST_Msk           (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)    /*!< 0x00008000 */
9207 #define RCC_APB1LRSTR_SPI3RST               RCC_APB1LRSTR_SPI3RST_Msk
9208 #define RCC_APB1LRSTR_COMPRST_Pos           (16U)
9209 #define RCC_APB1LRSTR_COMPRST_Msk           (0x1UL << RCC_APB1LRSTR_COMPRST_Pos)    /*!< 0x00010000 */
9210 #define RCC_APB1LRSTR_COMPRST               RCC_APB1LRSTR_COMPRST_Msk
9211 #define RCC_APB1LRSTR_USART2RST_Pos         (17U)
9212 #define RCC_APB1LRSTR_USART2RST_Msk         (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)  /*!< 0x00020000 */
9213 #define RCC_APB1LRSTR_USART2RST             RCC_APB1LRSTR_USART2RST_Msk
9214 #define RCC_APB1LRSTR_USART3RST_Pos         (18U)
9215 #define RCC_APB1LRSTR_USART3RST_Msk         (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)  /*!< 0x00040000 */
9216 #define RCC_APB1LRSTR_USART3RST             RCC_APB1LRSTR_USART3RST_Msk
9217 #define RCC_APB1LRSTR_I2C1RST_Pos           (21U)
9218 #define RCC_APB1LRSTR_I2C1RST_Msk           (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)    /*!< 0x00200000 */
9219 #define RCC_APB1LRSTR_I2C1RST               RCC_APB1LRSTR_I2C1RST_Msk
9220 #define RCC_APB1LRSTR_I2C2RST_Pos           (22U)
9221 #define RCC_APB1LRSTR_I2C2RST_Msk           (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)    /*!< 0x00400000 */
9222 #define RCC_APB1LRSTR_I2C2RST               RCC_APB1LRSTR_I2C2RST_Msk
9223 #define RCC_APB1LRSTR_I3C1RST_Pos           (23U)
9224 #define RCC_APB1LRSTR_I3C1RST_Msk           (0x1UL << RCC_APB1LRSTR_I3C1RST_Pos)    /*!< 0x00800000 */
9225 #define RCC_APB1LRSTR_I3C1RST               RCC_APB1LRSTR_I3C1RST_Msk
9226 #define RCC_APB1LRSTR_CRSRST_Pos            (24U)
9227 #define RCC_APB1LRSTR_CRSRST_Msk            (0x1UL << RCC_APB1LRSTR_CRSRST_Pos)     /*!< 0x01000000 */
9228 #define RCC_APB1LRSTR_CRSRST                RCC_APB1LRSTR_CRSRST_Msk
9229 
9230 /********************  Bit definition for RCC_APB1HRSTR register  **************/
9231 #define RCC_APB1HRSTR_DTSRST_Pos            (3U)
9232 #define RCC_APB1HRSTR_DTSRST_Msk            (0x1UL << RCC_APB1HRSTR_DTSRST_Pos)     /*!< 0x00000008 */
9233 #define RCC_APB1HRSTR_DTSRST                RCC_APB1HRSTR_DTSRST_Msk
9234 #define RCC_APB1HRSTR_LPTIM2RST_Pos         (5U)
9235 #define RCC_APB1HRSTR_LPTIM2RST_Msk         (0x1UL << RCC_APB1HRSTR_LPTIM2RST_Pos)  /*!< 0x00000020 */
9236 #define RCC_APB1HRSTR_LPTIM2RST             RCC_APB1HRSTR_LPTIM2RST_Msk
9237 #define RCC_APB1HRSTR_FDCANRST_Pos          (9U)
9238 #define RCC_APB1HRSTR_FDCANRST_Msk          (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos)   /*!< 0x00000200 */
9239 #define RCC_APB1HRSTR_FDCANRST              RCC_APB1HRSTR_FDCANRST_Msk
9240 
9241 /********************  Bit definition for RCC_APB2RSTR register  **************/
9242 #define RCC_APB2RSTR_TIM1RST_Pos            (11U)
9243 #define RCC_APB2RSTR_TIM1RST_Msk            (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)     /*!< 0x00000800 */
9244 #define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk
9245 #define RCC_APB2RSTR_SPI1RST_Pos            (12U)
9246 #define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)     /*!< 0x00001000 */
9247 #define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk
9248 #define RCC_APB2RSTR_USART1RST_Pos          (14U)
9249 #define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos)   /*!< 0x00004000 */
9250 #define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk
9251 #define RCC_APB2RSTR_USBRST_Pos             (24U)
9252 #define RCC_APB2RSTR_USBRST_Msk             (0x1UL << RCC_APB2RSTR_USBRST_Pos)      /*!< 0x01000000 */
9253 #define RCC_APB2RSTR_USBRST                 RCC_APB2RSTR_USBRST_Msk
9254 
9255 /********************  Bit definition for RCC_APB3RSTR register  **************/
9256 #define RCC_APB3RSTR_LPUART1RST_Pos         (6U)
9257 #define RCC_APB3RSTR_LPUART1RST_Msk         (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos)  /*!< 0x00000040 */
9258 #define RCC_APB3RSTR_LPUART1RST             RCC_APB3RSTR_LPUART1RST_Msk
9259 #define RCC_APB3RSTR_I3C2RST_Pos            (9U)
9260 #define RCC_APB3RSTR_I3C2RST_Msk            (0x1UL << RCC_APB3RSTR_I3C2RST_Pos)     /*!< 0x00000200 */
9261 #define RCC_APB3RSTR_I3C2RST                RCC_APB3RSTR_I3C2RST_Msk
9262 #define RCC_APB3RSTR_LPTIM1RST_Pos          (11U)
9263 #define RCC_APB3RSTR_LPTIM1RST_Msk          (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos)   /*!< 0x00000800 */
9264 #define RCC_APB3RSTR_LPTIM1RST              RCC_APB3RSTR_LPTIM1RST_Msk
9265 
9266 /********************  Bit definition for RCC_AHB1ENR register  **************/
9267 #define RCC_AHB1ENR_GPDMA1EN_Pos            (0U)
9268 #define RCC_AHB1ENR_GPDMA1EN_Msk            (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos)     /*!< 0x00000001 */
9269 #define RCC_AHB1ENR_GPDMA1EN                RCC_AHB1ENR_GPDMA1EN_Msk
9270 #define RCC_AHB1ENR_GPDMA2EN_Pos            (1U)
9271 #define RCC_AHB1ENR_GPDMA2EN_Msk            (0x1UL << RCC_AHB1ENR_GPDMA2EN_Pos)     /*!< 0x00000002 */
9272 #define RCC_AHB1ENR_GPDMA2EN                RCC_AHB1ENR_GPDMA2EN_Msk
9273 #define RCC_AHB1ENR_FLITFEN_Pos             (8U)
9274 #define RCC_AHB1ENR_FLITFEN_Msk             (0x1UL << RCC_AHB1ENR_FLITFEN_Pos)      /*!< 0x00000100 */
9275 #define RCC_AHB1ENR_FLITFEN                 RCC_AHB1ENR_FLITFEN_Msk
9276 #define RCC_AHB1ENR_CRCEN_Pos               (12U)
9277 #define RCC_AHB1ENR_CRCEN_Msk               (0x1UL << RCC_AHB1ENR_CRCEN_Pos)        /*!< 0x00001000 */
9278 #define RCC_AHB1ENR_CRCEN                   RCC_AHB1ENR_CRCEN_Msk
9279 #define RCC_AHB1ENR_RAMCFGEN_Pos            (17U)
9280 #define RCC_AHB1ENR_RAMCFGEN_Msk            (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos)     /*!< 0x00020000 */
9281 #define RCC_AHB1ENR_RAMCFGEN                RCC_AHB1ENR_RAMCFGEN_Msk
9282 #define RCC_AHB1ENR_TZSC1EN_Pos             (24U)
9283 #define RCC_AHB1ENR_TZSC1EN_Msk             (0x1UL << RCC_AHB1ENR_TZSC1EN_Pos)      /*!< 0x01000000 */
9284 #define RCC_AHB1ENR_TZSC1EN                 RCC_AHB1ENR_TZSC1EN_Msk
9285 #define RCC_AHB1ENR_BKPRAMEN_Pos            (28U)
9286 #define RCC_AHB1ENR_BKPRAMEN_Msk            (0x1UL << RCC_AHB1ENR_BKPRAMEN_Pos)     /*!< 0x10000000 */
9287 #define RCC_AHB1ENR_BKPRAMEN                RCC_AHB1ENR_BKPRAMEN_Msk
9288 #define RCC_AHB1ENR_SRAM1EN_Pos             (31U)
9289 #define RCC_AHB1ENR_SRAM1EN_Msk             (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos)      /*!< 0x80000000 */
9290 #define RCC_AHB1ENR_SRAM1EN                 RCC_AHB1ENR_SRAM1EN_Msk
9291 
9292 /********************  Bit definition for RCC_AHB2ENR register  **************/
9293 #define RCC_AHB2ENR_GPIOAEN_Pos             (0U)
9294 #define RCC_AHB2ENR_GPIOAEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)      /*!< 0x00000001 */
9295 #define RCC_AHB2ENR_GPIOAEN                 RCC_AHB2ENR_GPIOAEN_Msk
9296 #define RCC_AHB2ENR_GPIOBEN_Pos             (1U)
9297 #define RCC_AHB2ENR_GPIOBEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)      /*!< 0x00000002 */
9298 #define RCC_AHB2ENR_GPIOBEN                 RCC_AHB2ENR_GPIOBEN_Msk
9299 #define RCC_AHB2ENR_GPIOCEN_Pos             (2U)
9300 #define RCC_AHB2ENR_GPIOCEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)      /*!< 0x00000004 */
9301 #define RCC_AHB2ENR_GPIOCEN                 RCC_AHB2ENR_GPIOCEN_Msk
9302 #define RCC_AHB2ENR_GPIODEN_Pos             (3U)
9303 #define RCC_AHB2ENR_GPIODEN_Msk             (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)      /*!< 0x00000008 */
9304 #define RCC_AHB2ENR_GPIODEN                 RCC_AHB2ENR_GPIODEN_Msk
9305 #define RCC_AHB2ENR_GPIOHEN_Pos             (7U)
9306 #define RCC_AHB2ENR_GPIOHEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos)      /*!< 0x00000080 */
9307 #define RCC_AHB2ENR_GPIOHEN                 RCC_AHB2ENR_GPIOHEN_Msk
9308 #define RCC_AHB2ENR_ADCEN_Pos               (10U)
9309 #define RCC_AHB2ENR_ADCEN_Msk               (0x1UL << RCC_AHB2ENR_ADCEN_Pos)        /*!< 0x00000400 */
9310 #define RCC_AHB2ENR_ADCEN                   RCC_AHB2ENR_ADCEN_Msk
9311 #define RCC_AHB2ENR_DAC1EN_Pos              (11U)
9312 #define RCC_AHB2ENR_DAC1EN_Msk              (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)       /*!< 0x00000800 */
9313 #define RCC_AHB2ENR_DAC1EN                  RCC_AHB2ENR_DAC1EN_Msk
9314 #define RCC_AHB2ENR_HASHEN_Pos              (17U)
9315 #define RCC_AHB2ENR_HASHEN_Msk              (0x1UL << RCC_AHB2ENR_HASHEN_Pos)       /*!< 0x00020000 */
9316 #define RCC_AHB2ENR_HASHEN                  RCC_AHB2ENR_HASHEN_Msk
9317 #define RCC_AHB2ENR_RNGEN_Pos               (18U)
9318 #define RCC_AHB2ENR_RNGEN_Msk               (0x1UL << RCC_AHB2ENR_RNGEN_Pos)        /*!< 0x00040000 */
9319 #define RCC_AHB2ENR_RNGEN                   RCC_AHB2ENR_RNGEN_Msk
9320 #define RCC_AHB2ENR_SRAM2EN_Pos             (30U)
9321 #define RCC_AHB2ENR_SRAM2EN_Msk             (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)      /*!< 0x40000000 */
9322 #define RCC_AHB2ENR_SRAM2EN                 RCC_AHB2ENR_SRAM2EN_Msk
9323 
9324 /********************  Bit definition for RCC_APB1LENR register  **************/
9325 #define RCC_APB1LENR_TIM2EN_Pos             (0U)
9326 #define RCC_APB1LENR_TIM2EN_Msk             (0x1UL << RCC_APB1LENR_TIM2EN_Pos)      /*!< 0x00000001 */
9327 #define RCC_APB1LENR_TIM2EN                 RCC_APB1LENR_TIM2EN_Msk
9328 #define RCC_APB1LENR_TIM3EN_Pos             (1U)
9329 #define RCC_APB1LENR_TIM3EN_Msk             (0x1UL << RCC_APB1LENR_TIM3EN_Pos)      /*!< 0x00000002 */
9330 #define RCC_APB1LENR_TIM3EN                 RCC_APB1LENR_TIM3EN_Msk
9331 #define RCC_APB1LENR_TIM6EN_Pos             (4U)
9332 #define RCC_APB1LENR_TIM6EN_Msk             (0x1UL << RCC_APB1LENR_TIM6EN_Pos)      /*!< 0x00000010 */
9333 #define RCC_APB1LENR_TIM6EN                 RCC_APB1LENR_TIM6EN_Msk
9334 #define RCC_APB1LENR_TIM7EN_Pos             (5U)
9335 #define RCC_APB1LENR_TIM7EN_Msk             (0x1UL << RCC_APB1LENR_TIM7EN_Pos)      /*!< 0x00000020 */
9336 #define RCC_APB1LENR_TIM7EN                 RCC_APB1LENR_TIM7EN_Msk
9337 #define RCC_APB1LENR_WWDGEN_Pos             (11U)
9338 #define RCC_APB1LENR_WWDGEN_Msk             (0x1UL << RCC_APB1LENR_WWDGEN_Pos)      /*!< 0x00000800 */
9339 #define RCC_APB1LENR_WWDGEN                 RCC_APB1LENR_WWDGEN_Msk
9340 #define RCC_APB1LENR_OPAMPEN_Pos            (13U)
9341 #define RCC_APB1LENR_OPAMPEN_Msk            (0x1UL << RCC_APB1LENR_OPAMPEN_Pos)     /*!< 0x00002000 */
9342 #define RCC_APB1LENR_OPAMPEN                 RCC_APB1LENR_OPAMPEN_Msk
9343 #define RCC_APB1LENR_SPI2EN_Pos             (14U)
9344 #define RCC_APB1LENR_SPI2EN_Msk             (0x1UL << RCC_APB1LENR_SPI2EN_Pos)      /*!< 0x00004000 */
9345 #define RCC_APB1LENR_SPI2EN                 RCC_APB1LENR_SPI2EN_Msk
9346 #define RCC_APB1LENR_SPI3EN_Pos             (15U)
9347 #define RCC_APB1LENR_SPI3EN_Msk             (0x1UL << RCC_APB1LENR_SPI3EN_Pos)      /*!< 0x00008000 */
9348 #define RCC_APB1LENR_SPI3EN                 RCC_APB1LENR_SPI3EN_Msk
9349 #define RCC_APB1LENR_COMPEN_Pos             (16U)
9350 #define RCC_APB1LENR_COMPEN_Msk             (0x1UL << RCC_APB1LENR_COMPEN_Pos)      /*!< 0x00010000 */
9351 #define RCC_APB1LENR_COMPEN                 RCC_APB1LENR_COMPEN_Msk
9352 #define RCC_APB1LENR_USART2EN_Pos           (17U)
9353 #define RCC_APB1LENR_USART2EN_Msk           (0x1UL << RCC_APB1LENR_USART2EN_Pos)    /*!< 0x00020000 */
9354 #define RCC_APB1LENR_USART2EN               RCC_APB1LENR_USART2EN_Msk
9355 #define RCC_APB1LENR_USART3EN_Pos           (18U)
9356 #define RCC_APB1LENR_USART3EN_Msk           (0x1UL << RCC_APB1LENR_USART3EN_Pos)    /*!< 0x00040000 */
9357 #define RCC_APB1LENR_USART3EN               RCC_APB1LENR_USART3EN_Msk
9358 #define RCC_APB1LENR_I2C1EN_Pos             (21U)
9359 #define RCC_APB1LENR_I2C1EN_Msk             (0x1UL << RCC_APB1LENR_I2C1EN_Pos)      /*!< 0x00200000 */
9360 #define RCC_APB1LENR_I2C1EN                 RCC_APB1LENR_I2C1EN_Msk
9361 #define RCC_APB1LENR_I2C2EN_Pos             (22U)
9362 #define RCC_APB1LENR_I2C2EN_Msk             (0x1UL << RCC_APB1LENR_I2C2EN_Pos)      /*!< 0x00400000 */
9363 #define RCC_APB1LENR_I2C2EN                 RCC_APB1LENR_I2C2EN_Msk
9364 #define RCC_APB1LENR_I3C1EN_Pos             (23U)
9365 #define RCC_APB1LENR_I3C1EN_Msk             (0x1UL << RCC_APB1LENR_I3C1EN_Pos)      /*!< 0x00800000 */
9366 #define RCC_APB1LENR_I3C1EN                 RCC_APB1LENR_I3C1EN_Msk
9367 #define RCC_APB1LENR_CRSEN_Pos              (24U)
9368 #define RCC_APB1LENR_CRSEN_Msk              (0x1UL << RCC_APB1LENR_CRSEN_Pos)       /*!< 0x01000000 */
9369 #define RCC_APB1LENR_CRSEN                   RCC_APB1LENR_CRSEN_Msk
9370 
9371 /********************  Bit definition for RCC_APB1HENR register  **************/
9372 #define RCC_APB1HENR_DTSEN_Pos              (3U)
9373 #define RCC_APB1HENR_DTSEN_Msk              (0x1UL << RCC_APB1HENR_DTSEN_Pos)       /*!< 0x00000008 */
9374 #define RCC_APB1HENR_DTSEN                  RCC_APB1HENR_DTSEN_Msk
9375 #define RCC_APB1HENR_LPTIM2EN_Pos           (5U)
9376 #define RCC_APB1HENR_LPTIM2EN_Msk           (0x1UL << RCC_APB1HENR_LPTIM2EN_Pos)    /*!< 0x00000020 */
9377 #define RCC_APB1HENR_LPTIM2EN               RCC_APB1HENR_LPTIM2EN_Msk
9378 #define RCC_APB1HENR_FDCANEN_Pos            (9U)
9379 #define RCC_APB1HENR_FDCANEN_Msk            (0x1UL << RCC_APB1HENR_FDCANEN_Pos)     /*!< 0x00000200 */
9380 #define RCC_APB1HENR_FDCANEN                 RCC_APB1HENR_FDCANEN_Msk
9381 
9382 /********************  Bit definition for RCC_APB2ENR register  **************/
9383 #define RCC_APB2ENR_TIM1EN_Pos              (11U)
9384 #define RCC_APB2ENR_TIM1EN_Msk              (0x1UL << RCC_APB2ENR_TIM1EN_Pos)       /*!< 0x00000800 */
9385 #define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk
9386 #define RCC_APB2ENR_SPI1EN_Pos              (12U)
9387 #define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)       /*!< 0x00001000 */
9388 #define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk
9389 #define RCC_APB2ENR_USART1EN_Pos            (14U)
9390 #define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos)     /*!< 0x00004000 */
9391 #define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk
9392 #define RCC_APB2ENR_USBEN_Pos               (24U)
9393 #define RCC_APB2ENR_USBEN_Msk               (0x1UL << RCC_APB2ENR_USBEN_Pos)        /*!< 0x01000000 */
9394 #define RCC_APB2ENR_USBEN                   RCC_APB2ENR_USBEN_Msk
9395 
9396 /********************  Bit definition for RCC_APB3ENR register  **************/
9397 #define RCC_APB3ENR_SBSEN_Pos               (1U)
9398 #define RCC_APB3ENR_SBSEN_Msk               (0x1UL << RCC_APB3ENR_SBSEN_Pos)        /*!< 0x00000002 */
9399 #define RCC_APB3ENR_SBSEN                   RCC_APB3ENR_SBSEN_Msk
9400 #define RCC_APB3ENR_LPUART1EN_Pos           (6U)
9401 #define RCC_APB3ENR_LPUART1EN_Msk           (0x1UL << RCC_APB3ENR_LPUART1EN_Pos)    /*!< 0x00000040 */
9402 #define RCC_APB3ENR_LPUART1EN               RCC_APB3ENR_LPUART1EN_Msk
9403 #define RCC_APB3ENR_I3C2EN_Pos              (9U)
9404 #define RCC_APB3ENR_I3C2EN_Msk              (0x1UL << RCC_APB3ENR_I3C2EN_Pos)       /*!< 0x00000200 */
9405 #define RCC_APB3ENR_I3C2EN                  RCC_APB3ENR_I3C2EN_Msk
9406 #define RCC_APB3ENR_LPTIM1EN_Pos            (11U)
9407 #define RCC_APB3ENR_LPTIM1EN_Msk            (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos)     /*!< 0x00000800 */
9408 #define RCC_APB3ENR_LPTIM1EN                RCC_APB3ENR_LPTIM1EN_Msk
9409 #define RCC_APB3ENR_RTCAPBEN_Pos            (21U)
9410 #define RCC_APB3ENR_RTCAPBEN_Msk            (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos)     /*!< 0x00200000 */
9411 #define RCC_APB3ENR_RTCAPBEN                RCC_APB3ENR_RTCAPBEN_Msk
9412 
9413 /********************  Bit definition for RCC_AHB1LPENR register  **************/
9414 #define RCC_AHB1LPENR_GPDMA1LPEN_Pos        (0U)
9415 #define RCC_AHB1LPENR_GPDMA1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000000*/
9416 #define RCC_AHB1LPENR_GPDMA1LPEN            RCC_AHB1LPENR_GPDMA1LPEN_Msk
9417 #define RCC_AHB1LPENR_GPDMA2LPEN_Pos        (1U)
9418 #define RCC_AHB1LPENR_GPDMA2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPDMA2LPEN_Pos) /*!< 0x00000000*/
9419 #define RCC_AHB1LPENR_GPDMA2LPEN            RCC_AHB1LPENR_GPDMA2LPEN_Msk
9420 #define RCC_AHB1LPENR_FLITFLPEN_Pos         (8U)
9421 #define RCC_AHB1LPENR_FLITFLPEN_Msk         (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)   /*!< 0x00000100*/
9422 #define RCC_AHB1LPENR_FLITFLPEN             RCC_AHB1LPENR_FLITFLPEN_Msk
9423 #define RCC_AHB1LPENR_CRCLPEN_Pos           (12U)
9424 #define RCC_AHB1LPENR_CRCLPEN_Msk           (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)    /*!< 0x00001000 */
9425 #define RCC_AHB1LPENR_CRCLPEN               RCC_AHB1LPENR_CRCLPEN_Msk
9426 #define RCC_AHB1LPENR_RAMCFGLPEN_Pos        (17U)
9427 #define RCC_AHB1LPENR_RAMCFGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_RAMCFGLPEN_Pos) /*!< 0x00020000 */
9428 #define RCC_AHB1LPENR_RAMCFGLPEN            RCC_AHB1LPENR_RAMCFGLPEN_Msk
9429 #define RCC_AHB1LPENR_TZSC1LPEN_Pos         (24U)
9430 #define RCC_AHB1LPENR_TZSC1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_TZSC1LPEN_Pos)  /*!< 0x01000000 */
9431 #define RCC_AHB1LPENR_TZSC1LPEN             RCC_AHB1LPENR_TZSC1LPEN_Msk
9432 #define RCC_AHB1LPENR_BKPRAMLPEN_Pos        (28U)
9433 #define RCC_AHB1LPENR_BKPRAMLPEN_Msk        (0x1UL << RCC_AHB1LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
9434 #define RCC_AHB1LPENR_BKPRAMLPEN            RCC_AHB1LPENR_BKPRAMLPEN_Msk
9435 #define RCC_AHB1LPENR_ICACHELPEN_Pos        (29U)
9436 #define RCC_AHB1LPENR_ICACHELPEN_Msk        (0x1UL << RCC_AHB1LPENR_ICACHELPEN_Pos) /*!< 0x20000000 */
9437 #define RCC_AHB1LPENR_ICACHELPEN            RCC_AHB1LPENR_ICACHELPEN_Msk
9438 #define RCC_AHB1LPENR_SRAM1LPEN_Pos         (31U)
9439 #define RCC_AHB1LPENR_SRAM1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)  /*!< 0x80000000 */
9440 #define RCC_AHB1LPENR_SRAM1LPEN             RCC_AHB1LPENR_SRAM1LPEN_Msk
9441 
9442 /********************  Bit definition for RCC_AHB2LPENR register  **************/
9443 #define RCC_AHB2LPENR_GPIOALPEN_Pos         (0U)
9444 #define RCC_AHB2LPENR_GPIOALPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOALPEN_Pos)  /*!< 0x00000001 */
9445 #define RCC_AHB2LPENR_GPIOALPEN             RCC_AHB2LPENR_GPIOALPEN_Msk
9446 #define RCC_AHB2LPENR_GPIOBLPEN_Pos         (1U)
9447 #define RCC_AHB2LPENR_GPIOBLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOBLPEN_Pos)  /*!< 0x00000002 */
9448 #define RCC_AHB2LPENR_GPIOBLPEN             RCC_AHB2LPENR_GPIOBLPEN_Msk
9449 #define RCC_AHB2LPENR_GPIOCLPEN_Pos         (2U)
9450 #define RCC_AHB2LPENR_GPIOCLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOCLPEN_Pos)  /*!< 0x00000004 */
9451 #define RCC_AHB2LPENR_GPIOCLPEN             RCC_AHB2LPENR_GPIOCLPEN_Msk
9452 #define RCC_AHB2LPENR_GPIODLPEN_Pos         (3U)
9453 #define RCC_AHB2LPENR_GPIODLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIODLPEN_Pos)  /*!< 0x00000008 */
9454 #define RCC_AHB2LPENR_GPIODLPEN             RCC_AHB2LPENR_GPIODLPEN_Msk
9455 #define RCC_AHB2LPENR_GPIOHLPEN_Pos         (7U)
9456 #define RCC_AHB2LPENR_GPIOHLPEN_Msk         (0x1UL << RCC_AHB2LPENR_GPIOHLPEN_Pos)  /*!< 0x00000080 */
9457 #define RCC_AHB2LPENR_GPIOHLPEN             RCC_AHB2LPENR_GPIOHLPEN_Msk
9458 #define RCC_AHB2LPENR_ADCLPEN_Pos           (10U)
9459 #define RCC_AHB2LPENR_ADCLPEN_Msk           (0x1UL << RCC_AHB2LPENR_ADCLPEN_Pos)    /*!< 0x00000400 */
9460 #define RCC_AHB2LPENR_ADCLPEN               RCC_AHB2LPENR_ADCLPEN_Msk
9461 #define RCC_AHB2LPENR_DAC1LPEN_Pos          (11U)
9462 #define RCC_AHB2LPENR_DAC1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_DAC1LPEN_Pos)   /*!< 0x00000800 */
9463 #define RCC_AHB2LPENR_DAC1LPEN              RCC_AHB2LPENR_DAC1LPEN_Msk
9464 #define RCC_AHB2LPENR_HASHLPEN_Pos          (17U)
9465 #define RCC_AHB2LPENR_HASHLPEN_Msk          (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)   /*!< 0x00020000 */
9466 #define RCC_AHB2LPENR_HASHLPEN              RCC_AHB2LPENR_HASHLPEN_Msk
9467 #define RCC_AHB2LPENR_RNGLPEN_Pos           (18U)
9468 #define RCC_AHB2LPENR_RNGLPEN_Msk           (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)    /*!< 0x00040000 */
9469 #define RCC_AHB2LPENR_RNGLPEN               RCC_AHB2LPENR_RNGLPEN_Msk
9470 #define RCC_AHB2LPENR_SRAM2LPEN_Pos         (30U)
9471 #define RCC_AHB2LPENR_SRAM2LPEN_Msk         (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos)  /*!< 0x40000000 */
9472 #define RCC_AHB2LPENR_SRAM2LPEN             RCC_AHB2LPENR_SRAM2LPEN_Msk
9473 
9474 /********************  Bit definition for RCC_APB1LLPENR register  **************/
9475 #define RCC_APB1LLPENR_TIM2LPEN_Pos         (0U)
9476 #define RCC_APB1LLPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)  /*!< 0x00000001 */
9477 #define RCC_APB1LLPENR_TIM2LPEN             RCC_APB1LLPENR_TIM2LPEN_Msk
9478 #define RCC_APB1LLPENR_TIM3LPEN_Pos         (1U)
9479 #define RCC_APB1LLPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos)  /*!< 0x00000002 */
9480 #define RCC_APB1LLPENR_TIM3LPEN             RCC_APB1LLPENR_TIM3LPEN_Msk
9481 #define RCC_APB1LLPENR_TIM6LPEN_Pos         (4U)
9482 #define RCC_APB1LLPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)  /*!< 0x00000010 */
9483 #define RCC_APB1LLPENR_TIM6LPEN             RCC_APB1LLPENR_TIM6LPEN_Msk
9484 #define RCC_APB1LLPENR_TIM7LPEN_Pos         (5U)
9485 #define RCC_APB1LLPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)  /*!< 0x00000020 */
9486 #define RCC_APB1LLPENR_TIM7LPEN             RCC_APB1LLPENR_TIM7LPEN_Msk
9487 #define RCC_APB1LLPENR_WWDGLPEN_Pos         (11U)
9488 #define RCC_APB1LLPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LLPENR_WWDGLPEN_Pos)  /*!< 0x00000800 */
9489 #define RCC_APB1LLPENR_WWDGLPEN             RCC_APB1LLPENR_WWDGLPEN_Msk
9490 #define RCC_APB1LLPENR_OPAMPLPEN_Pos        (13U)
9491 #define RCC_APB1LLPENR_OPAMPLPEN_Msk        (0x1UL << RCC_APB1LLPENR_OPAMPLPEN_Pos) /*!< 0x00002000 */
9492 #define RCC_APB1LLPENR_OPAMPLPEN            RCC_APB1LLPENR_OPAMPLPEN_Msk
9493 #define RCC_APB1LLPENR_SPI2LPEN_Pos         (14U)
9494 #define RCC_APB1LLPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)  /*!< 0x00004000 */
9495 #define RCC_APB1LLPENR_SPI2LPEN             RCC_APB1LLPENR_SPI2LPEN_Msk
9496 #define RCC_APB1LLPENR_SPI3LPEN_Pos         (15U)
9497 #define RCC_APB1LLPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)  /*!< 0x00008000 */
9498 #define RCC_APB1LLPENR_SPI3LPEN             RCC_APB1LLPENR_SPI3LPEN_Msk
9499 #define RCC_APB1LLPENR_COMPLPEN_Pos         (16U)
9500 #define RCC_APB1LLPENR_COMPLPEN_Msk         (0x1UL << RCC_APB1LLPENR_COMPLPEN_Pos)  /*!< 0x00010000 */
9501 #define RCC_APB1LLPENR_COMPLPEN             RCC_APB1LLPENR_COMPLPEN_Msk
9502 #define RCC_APB1LLPENR_USART2LPEN_Pos       (17U)
9503 #define RCC_APB1LLPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
9504 #define RCC_APB1LLPENR_USART2LPEN           RCC_APB1LLPENR_USART2LPEN_Msk
9505 #define RCC_APB1LLPENR_USART3LPEN_Pos       (18U)
9506 #define RCC_APB1LLPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
9507 #define RCC_APB1LLPENR_USART3LPEN           RCC_APB1LLPENR_USART3LPEN_Msk
9508 #define RCC_APB1LLPENR_I2C1LPEN_Pos         (21U)
9509 #define RCC_APB1LLPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)  /*!< 0x00200000 */
9510 #define RCC_APB1LLPENR_I2C1LPEN             RCC_APB1LLPENR_I2C1LPEN_Msk
9511 #define RCC_APB1LLPENR_I2C2LPEN_Pos         (22U)
9512 #define RCC_APB1LLPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)  /*!< 0x00400000 */
9513 #define RCC_APB1LLPENR_I2C2LPEN             RCC_APB1LLPENR_I2C2LPEN_Msk
9514 #define RCC_APB1LLPENR_I3C1LPEN_Pos         (23U)
9515 #define RCC_APB1LLPENR_I3C1LPEN_Msk         (0x1UL << RCC_APB1LLPENR_I3C1LPEN_Pos)  /*!< 0x00800000 */
9516 #define RCC_APB1LLPENR_I3C1LPEN             RCC_APB1LLPENR_I3C1LPEN_Msk
9517 #define RCC_APB1LLPENR_CRSLPEN_Pos          (24U)
9518 #define RCC_APB1LLPENR_CRSLPEN_Msk          (0x1UL << RCC_APB1LLPENR_CRSLPEN_Pos)   /*!< 0x01000000 */
9519 #define RCC_APB1LLPENR_CRSLPEN              RCC_APB1LLPENR_CRSLPEN_Msk
9520 
9521 /********************  Bit definition for RCC_APB1HLPENR register  **************/
9522 #define RCC_APB1HLPENR_DTSLPEN_Pos          (3U)
9523 #define RCC_APB1HLPENR_DTSLPEN_Msk          (0x1UL << RCC_APB1HLPENR_DTSLPEN_Pos)    /*!< 0x00000008 */
9524 #define RCC_APB1HLPENR_DTSLPEN              RCC_APB1HLPENR_DTSLPEN_Msk
9525 #define RCC_APB1HLPENR_LPTIM2LPEN_Pos       (5U)
9526 #define RCC_APB1HLPENR_LPTIM2LPEN_Msk       (0x1UL << RCC_APB1HLPENR_LPTIM2LPEN_Pos) /*!< 0x00000020 */
9527 #define RCC_APB1HLPENR_LPTIM2LPEN           RCC_APB1HLPENR_LPTIM2LPEN_Msk
9528 #define RCC_APB1HLPENR_FDCANLPEN_Pos        (9U)
9529 #define RCC_APB1HLPENR_FDCANLPEN_Msk        (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos)  /*!< 0x00000200 */
9530 #define RCC_APB1HLPENR_FDCANLPEN            RCC_APB1HLPENR_FDCANLPEN_Msk
9531 
9532 /********************  Bit definition for RCC_APB2LPENR register  **************/
9533 #define RCC_APB2LPENR_TIM1LPEN_Pos          (11U)
9534 #define RCC_APB2LPENR_TIM1LPEN_Msk          (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)   /*!< 0x00000800 */
9535 #define RCC_APB2LPENR_TIM1LPEN              RCC_APB2LPENR_TIM1LPEN_Msk
9536 #define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)
9537 #define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)   /*!< 0x00001000 */
9538 #define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk
9539 #define RCC_APB2LPENR_USART1LPEN_Pos        (14U)
9540 #define RCC_APB2LPENR_USART1LPEN_Msk        (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
9541 #define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk
9542 #define RCC_APB2LPENR_USBLPEN_Pos           (24U)
9543 #define RCC_APB2LPENR_USBLPEN_Msk           (0x1UL << RCC_APB2LPENR_USBLPEN_Pos)    /*!< 0x01000000 */
9544 #define RCC_APB2LPENR_USBLPEN               RCC_APB2LPENR_USBLPEN_Msk
9545 
9546 /********************  Bit definition for RCC_APB3LPENR register  **************/
9547 #define RCC_APB3LPENR_SBSLPEN_Pos           (1U)
9548 #define RCC_APB3LPENR_SBSLPEN_Msk           (0x1UL << RCC_APB3LPENR_SBSLPEN_Pos)    /*!< 0x00000001 */
9549 #define RCC_APB3LPENR_SBSLPEN               RCC_APB3LPENR_SBSLPEN_Msk
9550 #define RCC_APB3LPENR_LPUART1LPEN_Pos       (6U)
9551 #define RCC_APB3LPENR_LPUART1LPEN_Msk       (0x1UL << RCC_APB3LPENR_LPUART1LPEN_Pos) /*!< 0x00000040 */
9552 #define RCC_APB3LPENR_LPUART1LPEN           RCC_APB3LPENR_LPUART1LPEN_Msk
9553 #define RCC_APB3LPENR_I3C2LPEN_Pos          (9U)
9554 #define RCC_APB3LPENR_I3C2LPEN_Msk          (0x1UL << RCC_APB3LPENR_I3C2LPEN_Pos)   /*!< 0x00000100 */
9555 #define RCC_APB3LPENR_I3C2LPEN              RCC_APB3LPENR_I3C2LPEN_Msk
9556 #define RCC_APB3LPENR_LPTIM1LPEN_Pos        (11U)
9557 #define RCC_APB3LPENR_LPTIM1LPEN_Msk        (0x1UL << RCC_APB3LPENR_LPTIM1LPEN_Pos) /*!< 0x00000800 */
9558 #define RCC_APB3LPENR_LPTIM1LPEN            RCC_APB3LPENR_LPTIM1LPEN_Msk
9559 #define RCC_APB3LPENR_RTCAPBLPEN_Pos        (21U)
9560 #define RCC_APB3LPENR_RTCAPBLPEN_Msk        (0x1UL << RCC_APB3LPENR_RTCAPBLPEN_Pos) /*!< 0x00200000 */
9561 #define RCC_APB3LPENR_RTCAPBLPEN            RCC_APB3LPENR_RTCAPBLPEN_Msk
9562 
9563 /********************  Bit definition for RCC_CCIPR1 register  ******************/
9564 #define RCC_CCIPR1_USART1SEL_Pos            (0U)
9565 #define RCC_CCIPR1_USART1SEL_Msk            (0x7UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000007 */
9566 #define RCC_CCIPR1_USART1SEL                RCC_CCIPR1_USART1SEL_Msk
9567 #define RCC_CCIPR1_USART1SEL_0              (0x1UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000001 */
9568 #define RCC_CCIPR1_USART1SEL_1              (0x2UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000002 */
9569 #define RCC_CCIPR1_USART1SEL_2              (0x4UL << RCC_CCIPR1_USART1SEL_Pos)     /*!< 0x00000004 */
9570 
9571 #define RCC_CCIPR1_USART2SEL_Pos            (3U)
9572 #define RCC_CCIPR1_USART2SEL_Msk            (0x7UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000038 */
9573 #define RCC_CCIPR1_USART2SEL                RCC_CCIPR1_USART2SEL_Msk
9574 #define RCC_CCIPR1_USART2SEL_0              (0x1UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000008 */
9575 #define RCC_CCIPR1_USART2SEL_1              (0x2UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000010 */
9576 #define RCC_CCIPR1_USART2SEL_2              (0x4UL << RCC_CCIPR1_USART2SEL_Pos)     /*!< 0x00000020 */
9577 
9578 #define RCC_CCIPR1_USART3SEL_Pos            (6U)
9579 #define RCC_CCIPR1_USART3SEL_Msk            (0x7UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x000001C0 */
9580 #define RCC_CCIPR1_USART3SEL                RCC_CCIPR1_USART3SEL_Msk
9581 #define RCC_CCIPR1_USART3SEL_0              (0x1UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x00000040 */
9582 #define RCC_CCIPR1_USART3SEL_1              (0x2UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x00000080 */
9583 #define RCC_CCIPR1_USART3SEL_2              (0x4UL << RCC_CCIPR1_USART3SEL_Pos)     /*!< 0x00000100 */
9584 
9585 #define RCC_CCIPR1_TIMICSEL_Pos             (31U)
9586 #define RCC_CCIPR1_TIMICSEL_Msk             (0x1UL << RCC_CCIPR1_TIMICSEL_Pos)      /*!< 0x10000000 */
9587 #define RCC_CCIPR1_TIMICSEL                 RCC_CCIPR1_TIMICSEL_Msk
9588 
9589 /********************  Bit definition for RCC_CCIPR2 register  ******************/
9590 #define RCC_CCIPR2_LPTIM1SEL_Pos            (8U)
9591 #define RCC_CCIPR2_LPTIM1SEL_Msk            (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000700 */
9592 #define RCC_CCIPR2_LPTIM1SEL                RCC_CCIPR2_LPTIM1SEL_Msk
9593 #define RCC_CCIPR2_LPTIM1SEL_0              (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000100 */
9594 #define RCC_CCIPR2_LPTIM1SEL_1              (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000200 */
9595 #define RCC_CCIPR2_LPTIM1SEL_2              (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos)     /*!< 0x00000400 */
9596 
9597 #define RCC_CCIPR2_LPTIM2SEL_Pos            (12U)
9598 #define RCC_CCIPR2_LPTIM2SEL_Msk            (0x7UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00007000 */
9599 #define RCC_CCIPR2_LPTIM2SEL                RCC_CCIPR2_LPTIM2SEL_Msk
9600 #define RCC_CCIPR2_LPTIM2SEL_0              (0x1UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00001000 */
9601 #define RCC_CCIPR2_LPTIM2SEL_1              (0x2UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00002000 */
9602 #define RCC_CCIPR2_LPTIM2SEL_2              (0x4UL << RCC_CCIPR2_LPTIM2SEL_Pos)     /*!< 0x00004000 */
9603 
9604 /********************  Bit definition for RCC_CCIPR3 register  ***************/
9605 #define RCC_CCIPR3_SPI1SEL_Pos              (0U)
9606 #define RCC_CCIPR3_SPI1SEL_Msk              (0x7UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000007 */
9607 #define RCC_CCIPR3_SPI1SEL                  RCC_CCIPR3_SPI1SEL_Msk
9608 #define RCC_CCIPR3_SPI1SEL_0                (0x1UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000001 */
9609 #define RCC_CCIPR3_SPI1SEL_1                (0x2UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000002 */
9610 #define RCC_CCIPR3_SPI1SEL_2                (0x4UL << RCC_CCIPR3_SPI1SEL_Pos)       /*!< 0x00000004 */
9611 
9612 #define RCC_CCIPR3_SPI2SEL_Pos              (3U)
9613 #define RCC_CCIPR3_SPI2SEL_Msk              (0x7UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000038 */
9614 #define RCC_CCIPR3_SPI2SEL                  RCC_CCIPR3_SPI2SEL_Msk
9615 #define RCC_CCIPR3_SPI2SEL_0                (0x1UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000008 */
9616 #define RCC_CCIPR3_SPI2SEL_1                (0x2UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000010 */
9617 #define RCC_CCIPR3_SPI2SEL_2                (0x4UL << RCC_CCIPR3_SPI2SEL_Pos)       /*!< 0x00000020 */
9618 
9619 #define RCC_CCIPR3_SPI3SEL_Pos              (6U)
9620 #define RCC_CCIPR3_SPI3SEL_Msk              (0x7UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x000001C0 */
9621 #define RCC_CCIPR3_SPI3SEL                  RCC_CCIPR3_SPI3SEL_Msk
9622 #define RCC_CCIPR3_SPI3SEL_0                (0x1UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x00000040 */
9623 #define RCC_CCIPR3_SPI3SEL_1                (0x2UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x00000080 */
9624 #define RCC_CCIPR3_SPI3SEL_2                (0x4UL << RCC_CCIPR3_SPI3SEL_Pos)       /*!< 0x00000100 */
9625 
9626 #define RCC_CCIPR3_LPUART1SEL_Pos           (24U)
9627 #define RCC_CCIPR3_LPUART1SEL_Msk           (0x7UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x07000000 */
9628 #define RCC_CCIPR3_LPUART1SEL               RCC_CCIPR3_LPUART1SEL_Msk
9629 #define RCC_CCIPR3_LPUART1SEL_0             (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x01000000 */
9630 #define RCC_CCIPR3_LPUART1SEL_1             (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x02000000 */
9631 #define RCC_CCIPR3_LPUART1SEL_2             (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos)    /*!< 0x04000000 */
9632 
9633 /********************  Bit definition for RCC_CCIPR4 register  ***************/
9634 
9635 #define RCC_CCIPR4_SYSTICKSEL_Pos           (2U)
9636 #define RCC_CCIPR4_SYSTICKSEL_Msk           (0x3UL << RCC_CCIPR4_SYSTICKSEL_Pos)    /*!< 0x0000000C */
9637 #define RCC_CCIPR4_SYSTICKSEL               RCC_CCIPR4_SYSTICKSEL_Msk
9638 #define RCC_CCIPR4_SYSTICKSEL_0             (0x1UL << RCC_CCIPR4_SYSTICKSEL_Pos)    /*!< 0x00000004 */
9639 #define RCC_CCIPR4_SYSTICKSEL_1             (0x2UL << RCC_CCIPR4_SYSTICKSEL_Pos)    /*!< 0x00000008 */
9640 
9641 #define RCC_CCIPR4_USBSEL_Pos               (4U)
9642 #define RCC_CCIPR4_USBSEL_Msk               (0x3UL << RCC_CCIPR4_USBSEL_Pos)        /*!< 0x00000030 */
9643 #define RCC_CCIPR4_USBSEL                   RCC_CCIPR4_USBSEL_Msk
9644 #define RCC_CCIPR4_USBSEL_0                 (0x1UL << RCC_CCIPR4_USBSEL_Pos)        /*!< 0x00000010 */
9645 #define RCC_CCIPR4_USBSEL_1                 (0x2UL << RCC_CCIPR4_USBSEL_Pos)        /*!< 0x00000020 */
9646 
9647 #define RCC_CCIPR4_I2C1SEL_Pos             (16U)
9648 #define RCC_CCIPR4_I2C1SEL_Msk             (0x3UL << RCC_CCIPR4_I2C1SEL_Pos)      /*!< 0x00030000 */
9649 #define RCC_CCIPR4_I2C1SEL                 RCC_CCIPR4_I2C1SEL_Msk
9650 #define RCC_CCIPR4_I2C1SEL_0               (0x1UL << RCC_CCIPR4_I2C1SEL_Pos)      /*!< 0x00010000 */
9651 #define RCC_CCIPR4_I2C1SEL_1               (0x2UL << RCC_CCIPR4_I2C1SEL_Pos)      /*!< 0x00020000 */
9652 
9653 #define RCC_CCIPR4_I2C2SEL_Pos             (18U)
9654 #define RCC_CCIPR4_I2C2SEL_Msk             (0x3UL << RCC_CCIPR4_I2C2SEL_Pos)      /*!< 0x000C0000 */
9655 #define RCC_CCIPR4_I2C2SEL                 RCC_CCIPR4_I2C2SEL_Msk
9656 #define RCC_CCIPR4_I2C2SEL_0               (0x1UL << RCC_CCIPR4_I2C2SEL_Pos)      /*!< 0x00040000 */
9657 #define RCC_CCIPR4_I2C2SEL_1               (0x2UL << RCC_CCIPR4_I2C2SEL_Pos)      /*!< 0x00080000 */
9658 
9659 #define RCC_CCIPR4_I3C1SEL_Pos             (24U)
9660 #define RCC_CCIPR4_I3C1SEL_Msk             (0x3UL << RCC_CCIPR4_I3C1SEL_Pos)      /*!< 0x03000000 */
9661 #define RCC_CCIPR4_I3C1SEL                 RCC_CCIPR4_I3C1SEL_Msk
9662 #define RCC_CCIPR4_I3C1SEL_0               (0x1UL << RCC_CCIPR4_I3C1SEL_Pos)      /*!< 0x01000000 */
9663 #define RCC_CCIPR4_I3C1SEL_1               (0x2UL << RCC_CCIPR4_I3C1SEL_Pos)      /*!< 0x02000000 */
9664 
9665 #define RCC_CCIPR4_I3C2SEL_Pos             (26U)
9666 #define RCC_CCIPR4_I3C2SEL_Msk             (0x3UL << RCC_CCIPR4_I3C2SEL_Pos)      /*!< 0x0C000000 */
9667 #define RCC_CCIPR4_I3C2SEL                 RCC_CCIPR4_I3C2SEL_Msk
9668 #define RCC_CCIPR4_I3C2SEL_0               (0x1UL << RCC_CCIPR4_I3C2SEL_Pos)      /*!< 0x04000000 */
9669 #define RCC_CCIPR4_I3C2SEL_1               (0x2UL << RCC_CCIPR4_I3C2SEL_Pos)      /*!< 0x08000000 */
9670 
9671 /********************  Bit definition for RCC_CCIPR5 register  ***************/
9672 
9673 #define RCC_CCIPR5_ADCDACSEL_Pos           (0U)
9674 #define RCC_CCIPR5_ADCDACSEL_Msk           (0x7UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000007 */
9675 #define RCC_CCIPR5_ADCDACSEL               RCC_CCIPR5_ADCDACSEL_Msk
9676 #define RCC_CCIPR5_ADCDACSEL_0             (0x1UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000001 */
9677 #define RCC_CCIPR5_ADCDACSEL_1             (0x2UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000002 */
9678 #define RCC_CCIPR5_ADCDACSEL_2             (0x4UL << RCC_CCIPR5_ADCDACSEL_Pos)    /*!< 0x00000004 */
9679 
9680 #define RCC_CCIPR5_DACSEL_Pos              (3U)
9681 #define RCC_CCIPR5_DACSEL_Msk              (0x1UL << RCC_CCIPR5_DACSEL_Pos)       /*!< 0x00000008 */
9682 #define RCC_CCIPR5_DACSEL                  RCC_CCIPR5_DACSEL_Msk
9683 
9684 #define RCC_CCIPR5_RNGSEL_Pos              (4U)
9685 #define RCC_CCIPR5_RNGSEL_Msk              (0x3UL << RCC_CCIPR5_RNGSEL_Pos)       /*!< 0x00000030 */
9686 #define RCC_CCIPR5_RNGSEL                  RCC_CCIPR5_RNGSEL_Msk
9687 #define RCC_CCIPR5_RNGSEL_0                (0x1UL << RCC_CCIPR5_RNGSEL_Pos)       /*!< 0x00000010 */
9688 #define RCC_CCIPR5_RNGSEL_1                (0x2UL << RCC_CCIPR5_RNGSEL_Pos)       /*!< 0x00000020 */
9689 
9690 #define RCC_CCIPR5_FDCANSEL_Pos            (8U)
9691 #define RCC_CCIPR5_FDCANSEL_Msk            (0x3UL << RCC_CCIPR5_FDCANSEL_Pos)     /*!< 0x00000300 */
9692 #define RCC_CCIPR5_FDCANSEL                RCC_CCIPR5_FDCANSEL_Msk
9693 #define RCC_CCIPR5_FDCANSEL_0              (0x1UL << RCC_CCIPR5_FDCANSEL_Pos)     /*!< 0x00000100 */
9694 #define RCC_CCIPR5_FDCANSEL_1              (0x2UL << RCC_CCIPR5_FDCANSEL_Pos)     /*!< 0x00000200 */
9695 
9696 #define RCC_CCIPR5_CKERPSEL_Pos            (30U)
9697 #define RCC_CCIPR5_CKERPSEL_Msk            (0x3UL << RCC_CCIPR5_CKERPSEL_Pos)     /*!< 0xC0000000 */
9698 #define RCC_CCIPR5_CKERPSEL                RCC_CCIPR5_CKERPSEL_Msk
9699 #define RCC_CCIPR5_CKERPSEL_0              (0x1UL << RCC_CCIPR5_CKERPSEL_Pos)     /*!< 0x40000000 */
9700 #define RCC_CCIPR5_CKERPSEL_1              (0x2UL << RCC_CCIPR5_CKERPSEL_Pos)     /*!< 0x80000000 */
9701 
9702 /********************  Bit definition for RCC_BDCR register  ******************/
9703 #define RCC_BDCR_LSEON_Pos                  (0U)
9704 #define RCC_BDCR_LSEON_Msk                  (0x1UL << RCC_BDCR_LSEON_Pos)           /*!< 0x00000001 */
9705 #define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk
9706 #define RCC_BDCR_LSERDY_Pos                 (1U)
9707 #define RCC_BDCR_LSERDY_Msk                 (0x1UL << RCC_BDCR_LSERDY_Pos)          /*!< 0x00000002 */
9708 #define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk
9709 #define RCC_BDCR_LSEBYP_Pos                 (2U)
9710 #define RCC_BDCR_LSEBYP_Msk                 (0x1UL << RCC_BDCR_LSEBYP_Pos)          /*!< 0x00000004 */
9711 #define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk
9712 #define RCC_BDCR_LSEDRV_Pos                 (3U)
9713 #define RCC_BDCR_LSEDRV_Msk                 (0x3UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000018 */
9714 #define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk
9715 #define RCC_BDCR_LSEDRV_0                   (0x1UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000008 */
9716 #define RCC_BDCR_LSEDRV_1                   (0x2UL << RCC_BDCR_LSEDRV_Pos)          /*!< 0x00000010 */
9717 #define RCC_BDCR_LSECSSON_Pos               (5U)
9718 #define RCC_BDCR_LSECSSON_Msk               (0x1UL << RCC_BDCR_LSECSSON_Pos)        /*!< 0x00000020 */
9719 #define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk
9720 #define RCC_BDCR_LSECSSD_Pos                (6U)
9721 #define RCC_BDCR_LSECSSD_Msk                (0x1UL << RCC_BDCR_LSECSSD_Pos)         /*!< 0x00000040 */
9722 #define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk
9723 #define RCC_BDCR_LSEEXT_Pos                 (7U)
9724 #define RCC_BDCR_LSEEXT_Msk                 (0x1UL << RCC_BDCR_LSEEXT_Pos)          /*!< 0x00000080 */
9725 #define RCC_BDCR_LSEEXT                     RCC_BDCR_LSEEXT_Msk
9726 #define RCC_BDCR_RTCSEL_Pos                 (8U)
9727 #define RCC_BDCR_RTCSEL_Msk                 (0x3UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000300 */
9728 #define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk
9729 #define RCC_BDCR_RTCSEL_0                   (0x1UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000100 */
9730 #define RCC_BDCR_RTCSEL_1                   (0x2UL << RCC_BDCR_RTCSEL_Pos)          /*!< 0x00000200 */
9731 #define RCC_BDCR_RTCEN_Pos                  (15U)
9732 #define RCC_BDCR_RTCEN_Msk                  (0x1UL << RCC_BDCR_RTCEN_Pos)           /*!< 0x00008000 */
9733 #define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk
9734 #define RCC_BDCR_VSWRST_Pos                 (16U)
9735 #define RCC_BDCR_VSWRST_Msk                 (0x1UL << RCC_BDCR_VSWRST_Pos)          /*!< 0x00010000 */
9736 #define RCC_BDCR_VSWRST                     RCC_BDCR_VSWRST_Msk
9737 #define RCC_BDCR_LSCOEN_Pos                 (24U)
9738 #define RCC_BDCR_LSCOEN_Msk                 (0x1UL << RCC_BDCR_LSCOEN_Pos)          /*!< 0x01000000 */
9739 #define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk
9740 #define RCC_BDCR_LSCOSEL_Pos                (25U)
9741 #define RCC_BDCR_LSCOSEL_Msk                (0x1UL << RCC_BDCR_LSCOSEL_Pos)         /*!< 0x02000000 */
9742 #define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk
9743 #define RCC_BDCR_LSION_Pos                  (26U)
9744 #define RCC_BDCR_LSION_Msk                  (0x1UL << RCC_BDCR_LSION_Pos)           /*!< 0x04000000 */
9745 #define RCC_BDCR_LSION                      RCC_BDCR_LSION_Msk
9746 #define RCC_BDCR_LSIRDY_Pos                 (27U)
9747 #define RCC_BDCR_LSIRDY_Msk                 (0x1UL << RCC_BDCR_LSIRDY_Pos)          /*!< 0x08000000 */
9748 #define RCC_BDCR_LSIRDY                     RCC_BDCR_LSIRDY_Msk
9749 
9750 /********************  Bit definition for RCC_RSR register  *******************/
9751 #define RCC_RSR_RMVF_Pos                    (23U)
9752 #define RCC_RSR_RMVF_Msk                    (0x1UL << RCC_RSR_RMVF_Pos)             /*!< 0x00800000 */
9753 #define RCC_RSR_RMVF                        RCC_RSR_RMVF_Msk
9754 #define RCC_RSR_PINRSTF_Pos                 (26U)
9755 #define RCC_RSR_PINRSTF_Msk                 (0x1UL << RCC_RSR_PINRSTF_Pos)          /*!< 0x04000000 */
9756 #define RCC_RSR_PINRSTF                     RCC_RSR_PINRSTF_Msk
9757 #define RCC_RSR_BORRSTF_Pos                 (27U)
9758 #define RCC_RSR_BORRSTF_Msk                 (0x1UL << RCC_RSR_BORRSTF_Pos)          /*!< 0x08000000 */
9759 #define RCC_RSR_BORRSTF                     RCC_RSR_BORRSTF_Msk
9760 #define RCC_RSR_SFTRSTF_Pos                 (28U)
9761 #define RCC_RSR_SFTRSTF_Msk                 (0x1UL << RCC_RSR_SFTRSTF_Pos)          /*!< 0x10000000 */
9762 #define RCC_RSR_SFTRSTF                     RCC_RSR_SFTRSTF_Msk
9763 #define RCC_RSR_IWDGRSTF_Pos                (29U)
9764 #define RCC_RSR_IWDGRSTF_Msk                (0x1UL << RCC_RSR_IWDGRSTF_Pos)         /*!< 0x20000000 */
9765 #define RCC_RSR_IWDGRSTF                    RCC_RSR_IWDGRSTF_Msk
9766 #define RCC_RSR_WWDGRSTF_Pos                (30U)
9767 #define RCC_RSR_WWDGRSTF_Msk                (0x1UL << RCC_RSR_WWDGRSTF_Pos)         /*!< 0x40000000 */
9768 #define RCC_RSR_WWDGRSTF                    RCC_RSR_WWDGRSTF_Msk
9769 #define RCC_RSR_LPWRRSTF_Pos                (31U)
9770 #define RCC_RSR_LPWRRSTF_Msk                (0x1UL << RCC_RSR_LPWRRSTF_Pos)         /*!< 0x80000000 */
9771 #define RCC_RSR_LPWRRSTF                    RCC_RSR_LPWRRSTF_Msk
9772 
9773 /********************  Bit definition for RCC_PRIVCFGR register  **************/
9774 #define RCC_PRIVCFGR_PRIV_Pos               (1U)
9775 #define RCC_PRIVCFGR_PRIV_Msk               (0x1UL << RCC_PRIVCFGR_PRIV_Pos)        /*!< 0x00000002 */
9776 #define RCC_PRIVCFGR_PRIV                   RCC_PRIVCFGR_PRIV_Msk
9777 
9778 /******************************************************************************/
9779 /*                                                                            */
9780 /*                           Real-Time Clock (RTC)                            */
9781 /*                                                                            */
9782 /******************************************************************************/
9783 /********************  Bits definition for RTC_TR register  *******************/
9784 #define RTC_TR_SU_Pos                       (0U)
9785 #define RTC_TR_SU_Msk                       (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
9786 #define RTC_TR_SU                           RTC_TR_SU_Msk
9787 #define RTC_TR_SU_0                         (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
9788 #define RTC_TR_SU_1                         (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
9789 #define RTC_TR_SU_2                         (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
9790 #define RTC_TR_SU_3                         (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
9791 #define RTC_TR_ST_Pos                       (4U)
9792 #define RTC_TR_ST_Msk                       (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
9793 #define RTC_TR_ST                           RTC_TR_ST_Msk
9794 #define RTC_TR_ST_0                         (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
9795 #define RTC_TR_ST_1                         (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
9796 #define RTC_TR_ST_2                         (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
9797 #define RTC_TR_MNU_Pos                      (8U)
9798 #define RTC_TR_MNU_Msk                      (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
9799 #define RTC_TR_MNU                          RTC_TR_MNU_Msk
9800 #define RTC_TR_MNU_0                        (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
9801 #define RTC_TR_MNU_1                        (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
9802 #define RTC_TR_MNU_2                        (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
9803 #define RTC_TR_MNU_3                        (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
9804 #define RTC_TR_MNT_Pos                      (12U)
9805 #define RTC_TR_MNT_Msk                      (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
9806 #define RTC_TR_MNT                          RTC_TR_MNT_Msk
9807 #define RTC_TR_MNT_0                        (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
9808 #define RTC_TR_MNT_1                        (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
9809 #define RTC_TR_MNT_2                        (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
9810 #define RTC_TR_HU_Pos                       (16U)
9811 #define RTC_TR_HU_Msk                       (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
9812 #define RTC_TR_HU                           RTC_TR_HU_Msk
9813 #define RTC_TR_HU_0                         (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
9814 #define RTC_TR_HU_1                         (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
9815 #define RTC_TR_HU_2                         (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
9816 #define RTC_TR_HU_3                         (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
9817 #define RTC_TR_HT_Pos                       (20U)
9818 #define RTC_TR_HT_Msk                       (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
9819 #define RTC_TR_HT                           RTC_TR_HT_Msk
9820 #define RTC_TR_HT_0                         (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
9821 #define RTC_TR_HT_1                         (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
9822 #define RTC_TR_PM_Pos                       (22U)
9823 #define RTC_TR_PM_Msk                       (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
9824 #define RTC_TR_PM                           RTC_TR_PM_Msk
9825 
9826 /********************  Bits definition for RTC_DR register  *******************/
9827 #define RTC_DR_DU_Pos                       (0U)
9828 #define RTC_DR_DU_Msk                       (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
9829 #define RTC_DR_DU                           RTC_DR_DU_Msk
9830 #define RTC_DR_DU_0                         (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
9831 #define RTC_DR_DU_1                         (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
9832 #define RTC_DR_DU_2                         (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
9833 #define RTC_DR_DU_3                         (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
9834 #define RTC_DR_DT_Pos                       (4U)
9835 #define RTC_DR_DT_Msk                       (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
9836 #define RTC_DR_DT                           RTC_DR_DT_Msk
9837 #define RTC_DR_DT_0                         (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
9838 #define RTC_DR_DT_1                         (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
9839 #define RTC_DR_MU_Pos                       (8U)
9840 #define RTC_DR_MU_Msk                       (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
9841 #define RTC_DR_MU                           RTC_DR_MU_Msk
9842 #define RTC_DR_MU_0                         (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
9843 #define RTC_DR_MU_1                         (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
9844 #define RTC_DR_MU_2                         (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
9845 #define RTC_DR_MU_3                         (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
9846 #define RTC_DR_MT_Pos                       (12U)
9847 #define RTC_DR_MT_Msk                       (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
9848 #define RTC_DR_MT                           RTC_DR_MT_Msk
9849 #define RTC_DR_WDU_Pos                      (13U)
9850 #define RTC_DR_WDU_Msk                      (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
9851 #define RTC_DR_WDU                          RTC_DR_WDU_Msk
9852 #define RTC_DR_WDU_0                        (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
9853 #define RTC_DR_WDU_1                        (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
9854 #define RTC_DR_WDU_2                        (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
9855 #define RTC_DR_YU_Pos                       (16U)
9856 #define RTC_DR_YU_Msk                       (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
9857 #define RTC_DR_YU                           RTC_DR_YU_Msk
9858 #define RTC_DR_YU_0                         (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
9859 #define RTC_DR_YU_1                         (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
9860 #define RTC_DR_YU_2                         (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
9861 #define RTC_DR_YU_3                         (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
9862 #define RTC_DR_YT_Pos                       (20U)
9863 #define RTC_DR_YT_Msk                       (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
9864 #define RTC_DR_YT                           RTC_DR_YT_Msk
9865 #define RTC_DR_YT_0                         (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
9866 #define RTC_DR_YT_1                         (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
9867 #define RTC_DR_YT_2                         (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
9868 #define RTC_DR_YT_3                         (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
9869 
9870 /********************  Bits definition for RTC_SSR register  ******************/
9871 #define RTC_SSR_SS_Pos                      (0U)
9872 #define RTC_SSR_SS_Msk                      (0xFFFFFFFFUL << RTC_SSR_SS_Pos)        /*!< 0xFFFFFFFF */
9873 #define RTC_SSR_SS                          RTC_SSR_SS_Msk
9874 
9875 /********************  Bits definition for RTC_ICSR register  ******************/
9876 #define RTC_ICSR_ALRAWF_Pos                 (0U)
9877 #define RTC_ICSR_ALRAWF_Msk                 (0x1UL << RTC_ICSR_ALRAWF_Pos)          /*!< 0x00000001 */
9878 #define RTC_ICSR_ALRAWF                     RTC_ICSR_ALRAWF_Msk
9879 #define RTC_ICSR_ALRBWF_Pos                 (1U)
9880 #define RTC_ICSR_ALRBWF_Msk                 (0x1UL << RTC_ICSR_ALRBWF_Pos)          /*!< 0x00000002 */
9881 #define RTC_ICSR_ALRBWF                     RTC_ICSR_ALRBWF_Msk
9882 #define RTC_ICSR_WUTWF_Pos                  (2U)
9883 #define RTC_ICSR_WUTWF_Msk                  (0x1UL << RTC_ICSR_WUTWF_Pos)           /*!< 0x00000004 */
9884 #define RTC_ICSR_WUTWF                      RTC_ICSR_WUTWF_Msk
9885 #define RTC_ICSR_SHPF_Pos                   (3U)
9886 #define RTC_ICSR_SHPF_Msk                   (0x1UL << RTC_ICSR_SHPF_Pos)            /*!< 0x00000008 */
9887 #define RTC_ICSR_SHPF                       RTC_ICSR_SHPF_Msk
9888 #define RTC_ICSR_INITS_Pos                  (4U)
9889 #define RTC_ICSR_INITS_Msk                  (0x1UL << RTC_ICSR_INITS_Pos)           /*!< 0x00000010 */
9890 #define RTC_ICSR_INITS                      RTC_ICSR_INITS_Msk
9891 #define RTC_ICSR_RSF_Pos                    (5U)
9892 #define RTC_ICSR_RSF_Msk                    (0x1UL << RTC_ICSR_RSF_Pos)             /*!< 0x00000020 */
9893 #define RTC_ICSR_RSF                        RTC_ICSR_RSF_Msk
9894 #define RTC_ICSR_INITF_Pos                  (6U)
9895 #define RTC_ICSR_INITF_Msk                  (0x1UL << RTC_ICSR_INITF_Pos)           /*!< 0x00000040 */
9896 #define RTC_ICSR_INITF                      RTC_ICSR_INITF_Msk
9897 #define RTC_ICSR_INIT_Pos                   (7U)
9898 #define RTC_ICSR_INIT_Msk                   (0x1UL << RTC_ICSR_INIT_Pos)            /*!< 0x00000080 */
9899 #define RTC_ICSR_INIT                       RTC_ICSR_INIT_Msk
9900 #define RTC_ICSR_BIN_Pos                    (8U)
9901 #define RTC_ICSR_BIN_Msk                    (0x3UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000300 */
9902 #define RTC_ICSR_BIN                        RTC_ICSR_BIN_Msk
9903 #define RTC_ICSR_BIN_0                      (0x1UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000100 */
9904 #define RTC_ICSR_BIN_1                      (0x2UL << RTC_ICSR_BIN_Pos)             /*!< 0x00000200 */
9905 #define RTC_ICSR_BCDU_Pos                   (10U)
9906 #define RTC_ICSR_BCDU_Msk                   (0x7UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001C00 */
9907 #define RTC_ICSR_BCDU                       RTC_ICSR_BCDU_Msk
9908 #define RTC_ICSR_BCDU_0                     (0x1UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000400 */
9909 #define RTC_ICSR_BCDU_1                     (0x2UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00000800 */
9910 #define RTC_ICSR_BCDU_2                     (0x4UL << RTC_ICSR_BCDU_Pos)            /*!< 0x00001000 */
9911 #define RTC_ICSR_RECALPF_Pos                (16U)
9912 #define RTC_ICSR_RECALPF_Msk                (0x1UL << RTC_ICSR_RECALPF_Pos)         /*!< 0x00010000 */
9913 #define RTC_ICSR_RECALPF                    RTC_ICSR_RECALPF_Msk
9914 
9915 /********************  Bits definition for RTC_PRER register  *****************/
9916 #define RTC_PRER_PREDIV_S_Pos               (0U)
9917 #define RTC_PRER_PREDIV_S_Msk               (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
9918 #define RTC_PRER_PREDIV_S                   RTC_PRER_PREDIV_S_Msk
9919 #define RTC_PRER_PREDIV_A_Pos               (16U)
9920 #define RTC_PRER_PREDIV_A_Msk               (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
9921 #define RTC_PRER_PREDIV_A                   RTC_PRER_PREDIV_A_Msk
9922 
9923 /********************  Bits definition for RTC_WUTR register  *****************/
9924 #define RTC_WUTR_WUT_Pos                    (0U)
9925 #define RTC_WUTR_WUT_Msk                    (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
9926 #define RTC_WUTR_WUT                        RTC_WUTR_WUT_Msk
9927 #define RTC_WUTR_WUTOCLR_Pos                (16U)
9928 #define RTC_WUTR_WUTOCLR_Msk                (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)      /*!< 0x0000FFFF */
9929 #define RTC_WUTR_WUTOCLR                    RTC_WUTR_WUTOCLR_Msk
9930 
9931 /********************  Bits definition for RTC_CR register  *******************/
9932 #define RTC_CR_WUCKSEL_Pos                  (0U)
9933 #define RTC_CR_WUCKSEL_Msk                  (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
9934 #define RTC_CR_WUCKSEL                      RTC_CR_WUCKSEL_Msk
9935 #define RTC_CR_WUCKSEL_0                    (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
9936 #define RTC_CR_WUCKSEL_1                    (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
9937 #define RTC_CR_WUCKSEL_2                    (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
9938 #define RTC_CR_TSEDGE_Pos                   (3U)
9939 #define RTC_CR_TSEDGE_Msk                   (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
9940 #define RTC_CR_TSEDGE                       RTC_CR_TSEDGE_Msk
9941 #define RTC_CR_REFCKON_Pos                  (4U)
9942 #define RTC_CR_REFCKON_Msk                  (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
9943 #define RTC_CR_REFCKON                      RTC_CR_REFCKON_Msk
9944 #define RTC_CR_BYPSHAD_Pos                  (5U)
9945 #define RTC_CR_BYPSHAD_Msk                  (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
9946 #define RTC_CR_BYPSHAD                      RTC_CR_BYPSHAD_Msk
9947 #define RTC_CR_FMT_Pos                      (6U)
9948 #define RTC_CR_FMT_Msk                      (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
9949 #define RTC_CR_FMT                          RTC_CR_FMT_Msk
9950 #define RTC_CR_SSRUIE_Pos                   (7U)
9951 #define RTC_CR_SSRUIE_Msk                   (0x1UL << RTC_CR_SSRUIE_Pos)            /*!< 0x00000080 */
9952 #define RTC_CR_SSRUIE                       RTC_CR_SSRUIE_Msk
9953 #define RTC_CR_ALRAE_Pos                    (8U)
9954 #define RTC_CR_ALRAE_Msk                    (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
9955 #define RTC_CR_ALRAE                        RTC_CR_ALRAE_Msk
9956 #define RTC_CR_ALRBE_Pos                    (9U)
9957 #define RTC_CR_ALRBE_Msk                    (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
9958 #define RTC_CR_ALRBE                        RTC_CR_ALRBE_Msk
9959 #define RTC_CR_WUTE_Pos                     (10U)
9960 #define RTC_CR_WUTE_Msk                     (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
9961 #define RTC_CR_WUTE                         RTC_CR_WUTE_Msk
9962 #define RTC_CR_TSE_Pos                      (11U)
9963 #define RTC_CR_TSE_Msk                      (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
9964 #define RTC_CR_TSE                          RTC_CR_TSE_Msk
9965 #define RTC_CR_ALRAIE_Pos                   (12U)
9966 #define RTC_CR_ALRAIE_Msk                   (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
9967 #define RTC_CR_ALRAIE                       RTC_CR_ALRAIE_Msk
9968 #define RTC_CR_ALRBIE_Pos                   (13U)
9969 #define RTC_CR_ALRBIE_Msk                   (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
9970 #define RTC_CR_ALRBIE                       RTC_CR_ALRBIE_Msk
9971 #define RTC_CR_WUTIE_Pos                    (14U)
9972 #define RTC_CR_WUTIE_Msk                    (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
9973 #define RTC_CR_WUTIE                        RTC_CR_WUTIE_Msk
9974 #define RTC_CR_TSIE_Pos                     (15U)
9975 #define RTC_CR_TSIE_Msk                     (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
9976 #define RTC_CR_TSIE                         RTC_CR_TSIE_Msk
9977 #define RTC_CR_ADD1H_Pos                    (16U)
9978 #define RTC_CR_ADD1H_Msk                    (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
9979 #define RTC_CR_ADD1H                        RTC_CR_ADD1H_Msk
9980 #define RTC_CR_SUB1H_Pos                    (17U)
9981 #define RTC_CR_SUB1H_Msk                    (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
9982 #define RTC_CR_SUB1H                        RTC_CR_SUB1H_Msk
9983 #define RTC_CR_BKP_Pos                      (18U)
9984 #define RTC_CR_BKP_Msk                      (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
9985 #define RTC_CR_BKP                          RTC_CR_BKP_Msk
9986 #define RTC_CR_COSEL_Pos                    (19U)
9987 #define RTC_CR_COSEL_Msk                    (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
9988 #define RTC_CR_COSEL                        RTC_CR_COSEL_Msk
9989 #define RTC_CR_POL_Pos                      (20U)
9990 #define RTC_CR_POL_Msk                      (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
9991 #define RTC_CR_POL                          RTC_CR_POL_Msk
9992 #define RTC_CR_OSEL_Pos                     (21U)
9993 #define RTC_CR_OSEL_Msk                     (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
9994 #define RTC_CR_OSEL                         RTC_CR_OSEL_Msk
9995 #define RTC_CR_OSEL_0                       (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
9996 #define RTC_CR_OSEL_1                       (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
9997 #define RTC_CR_COE_Pos                      (23U)
9998 #define RTC_CR_COE_Msk                      (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
9999 #define RTC_CR_COE                          RTC_CR_COE_Msk
10000 #define RTC_CR_ITSE_Pos                     (24U)
10001 #define RTC_CR_ITSE_Msk                     (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
10002 #define RTC_CR_ITSE                         RTC_CR_ITSE_Msk                         /*!<Timestamp on internal event enable  */
10003 #define RTC_CR_TAMPTS_Pos                   (25U)
10004 #define RTC_CR_TAMPTS_Msk                   (0x1UL << RTC_CR_TAMPTS_Pos)            /*!< 0x02000000 */
10005 #define RTC_CR_TAMPTS                       RTC_CR_TAMPTS_Msk                       /*!<Activate timestamp on tamper detection event  */
10006 #define RTC_CR_TAMPOE_Pos                   (26U)
10007 #define RTC_CR_TAMPOE_Msk                   (0x1UL << RTC_CR_TAMPOE_Pos)            /*!< 0x04000000 */
10008 #define RTC_CR_TAMPOE                       RTC_CR_TAMPOE_Msk                       /*!<Tamper detection output enable on TAMPALARM  */
10009 #define RTC_CR_ALRAFCLR_Pos                 (27U)
10010 #define RTC_CR_ALRAFCLR_Msk                 (0x1UL << RTC_CR_ALRAFCLR_Pos)          /*!< 0x8000000 */
10011 #define RTC_CR_ALRAFCLR                     RTC_CR_ALRAFCLR_Msk                     /*!<Alarm A mask */
10012 #define RTC_CR_ALRBFCLR_Pos                 (28U)
10013 #define RTC_CR_ALRBFCLR_Msk                 (0x1UL << RTC_CR_ALRBFCLR_Pos)          /*!< 0x10000000 */
10014 #define RTC_CR_ALRBFCLR                     RTC_CR_ALRBFCLR_Msk                     /*!<Alarm B mask */
10015 #define RTC_CR_TAMPALRM_PU_Pos              (29U)
10016 #define RTC_CR_TAMPALRM_PU_Msk              (0x1UL << RTC_CR_TAMPALRM_PU_Pos)       /*!< 0x20000000 */
10017 #define RTC_CR_TAMPALRM_PU                  RTC_CR_TAMPALRM_PU_Msk                  /*!<TAMPALARM output pull-up config */
10018 #define RTC_CR_TAMPALRM_TYPE_Pos            (30U)
10019 #define RTC_CR_TAMPALRM_TYPE_Msk            (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)     /*!< 0x40000000 */
10020 #define RTC_CR_TAMPALRM_TYPE                RTC_CR_TAMPALRM_TYPE_Msk                /*!<TAMPALARM output type  */
10021 #define RTC_CR_OUT2EN_Pos                   (31U)
10022 #define RTC_CR_OUT2EN_Msk                   (0x1UL << RTC_CR_OUT2EN_Pos)            /*!< 0x80000000 */
10023 #define RTC_CR_OUT2EN                       RTC_CR_OUT2EN_Msk                       /*!<RTC_OUT2 output enable */
10024 
10025 /********************  Bits definition for RTC_PRIVCFGR register  *****************/
10026 #define RTC_PRIVCFGR_ALRAPRIV_Pos           (0U)
10027 #define RTC_PRIVCFGR_ALRAPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos)    /*!< 0x00000001 */
10028 #define RTC_PRIVCFGR_ALRAPRIV               RTC_PRIVCFGR_ALRAPRIV_Msk
10029 #define RTC_PRIVCFGR_ALRBPRIV_Pos           (1U)
10030 #define RTC_PRIVCFGR_ALRBPRIV_Msk           (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos)    /*!< 0x00000002 */
10031 #define RTC_PRIVCFGR_ALRBPRIV               RTC_PRIVCFGR_ALRBPRIV_Msk
10032 #define RTC_PRIVCFGR_WUTPRIV_Pos            (2U)
10033 #define RTC_PRIVCFGR_WUTPRIV_Msk            (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos)     /*!< 0x00000004 */
10034 #define RTC_PRIVCFGR_WUTPRIV                RTC_PRIVCFGR_WUTPRIV_Msk
10035 #define RTC_PRIVCFGR_TSPRIV_Pos             (3U)
10036 #define RTC_PRIVCFGR_TSPRIV_Msk             (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos)      /*!< 0x00000008 */
10037 #define RTC_PRIVCFGR_TSPRIV                 RTC_PRIVCFGR_TSPRIV_Msk
10038 #define RTC_PRIVCFGR_CALPRIV_Pos            (13U)
10039 #define RTC_PRIVCFGR_CALPRIV_Msk            (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos)     /*!< 0x00002000 */
10040 #define RTC_PRIVCFGR_CALPRIV                RTC_PRIVCFGR_CALPRIV_Msk
10041 #define RTC_PRIVCFGR_INITPRIV_Pos           (14U)
10042 #define RTC_PRIVCFGR_INITPRIV_Msk           (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos)    /*!< 0x00004000 */
10043 #define RTC_PRIVCFGR_INITPRIV               RTC_PRIVCFGR_INITPRIV_Msk
10044 #define RTC_PRIVCFGR_PRIV_Pos               (15U)
10045 #define RTC_PRIVCFGR_PRIV_Msk               (0x1UL << RTC_PRIVCFGR_PRIV_Pos)        /*!< 0x00008000 */
10046 #define RTC_PRIVCFGR_PRIV                   RTC_PRIVCFGR_PRIV_Msk
10047 
10048 
10049 /********************  Bits definition for RTC_WPR register  ******************/
10050 #define RTC_WPR_KEY_Pos                     (0U)
10051 #define RTC_WPR_KEY_Msk                     (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
10052 #define RTC_WPR_KEY                         RTC_WPR_KEY_Msk
10053 
10054 /********************  Bits definition for RTC_CALR register  *****************/
10055 #define RTC_CALR_CALM_Pos                   (0U)
10056 #define RTC_CALR_CALM_Msk                   (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
10057 #define RTC_CALR_CALM                       RTC_CALR_CALM_Msk
10058 #define RTC_CALR_CALM_0                     (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
10059 #define RTC_CALR_CALM_1                     (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
10060 #define RTC_CALR_CALM_2                     (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
10061 #define RTC_CALR_CALM_3                     (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
10062 #define RTC_CALR_CALM_4                     (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
10063 #define RTC_CALR_CALM_5                     (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
10064 #define RTC_CALR_CALM_6                     (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
10065 #define RTC_CALR_CALM_7                     (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
10066 #define RTC_CALR_CALM_8                     (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
10067 #define RTC_CALR_LPCAL_Pos                  (12U)
10068 #define RTC_CALR_LPCAL_Msk                  (0x1UL << RTC_CALR_LPCAL_Pos)           /*!< 0x00001000 */
10069 #define RTC_CALR_CALW16                     RTC_CALR_CALW16_Msk
10070 #define RTC_CALR_CALW16_Pos                 (13U)
10071 #define RTC_CALR_CALW16_Msk                 (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
10072 #define RTC_CALR_LPCAL                      RTC_CALR_LPCAL_Msk
10073 #define RTC_CALR_CALW8_Pos                  (14U)
10074 #define RTC_CALR_CALW8_Msk                  (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
10075 #define RTC_CALR_CALW8                      RTC_CALR_CALW8_Msk
10076 #define RTC_CALR_CALP_Pos                   (15U)
10077 #define RTC_CALR_CALP_Msk                   (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
10078 #define RTC_CALR_CALP                       RTC_CALR_CALP_Msk
10079 
10080 /********************  Bits definition for RTC_SHIFTR register  ***************/
10081 #define RTC_SHIFTR_SUBFS_Pos                (0U)
10082 #define RTC_SHIFTR_SUBFS_Msk                (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
10083 #define RTC_SHIFTR_SUBFS                    RTC_SHIFTR_SUBFS_Msk
10084 #define RTC_SHIFTR_ADD1S_Pos                (31U)
10085 #define RTC_SHIFTR_ADD1S_Msk                (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
10086 #define RTC_SHIFTR_ADD1S                    RTC_SHIFTR_ADD1S_Msk
10087 
10088 /********************  Bits definition for RTC_TSTR register  *****************/
10089 #define RTC_TSTR_SU_Pos                     (0U)
10090 #define RTC_TSTR_SU_Msk                     (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
10091 #define RTC_TSTR_SU                         RTC_TSTR_SU_Msk
10092 #define RTC_TSTR_SU_0                       (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
10093 #define RTC_TSTR_SU_1                       (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
10094 #define RTC_TSTR_SU_2                       (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
10095 #define RTC_TSTR_SU_3                       (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
10096 #define RTC_TSTR_ST_Pos                     (4U)
10097 #define RTC_TSTR_ST_Msk                     (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
10098 #define RTC_TSTR_ST                         RTC_TSTR_ST_Msk
10099 #define RTC_TSTR_ST_0                       (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
10100 #define RTC_TSTR_ST_1                       (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
10101 #define RTC_TSTR_ST_2                       (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
10102 #define RTC_TSTR_MNU_Pos                    (8U)
10103 #define RTC_TSTR_MNU_Msk                    (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
10104 #define RTC_TSTR_MNU                        RTC_TSTR_MNU_Msk
10105 #define RTC_TSTR_MNU_0                      (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
10106 #define RTC_TSTR_MNU_1                      (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
10107 #define RTC_TSTR_MNU_2                      (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
10108 #define RTC_TSTR_MNU_3                      (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
10109 #define RTC_TSTR_MNT_Pos                    (12U)
10110 #define RTC_TSTR_MNT_Msk                    (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
10111 #define RTC_TSTR_MNT                        RTC_TSTR_MNT_Msk
10112 #define RTC_TSTR_MNT_0                      (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
10113 #define RTC_TSTR_MNT_1                      (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
10114 #define RTC_TSTR_MNT_2                      (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
10115 #define RTC_TSTR_HU_Pos                     (16U)
10116 #define RTC_TSTR_HU_Msk                     (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
10117 #define RTC_TSTR_HU                         RTC_TSTR_HU_Msk
10118 #define RTC_TSTR_HU_0                       (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
10119 #define RTC_TSTR_HU_1                       (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
10120 #define RTC_TSTR_HU_2                       (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
10121 #define RTC_TSTR_HU_3                       (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
10122 #define RTC_TSTR_HT_Pos                     (20U)
10123 #define RTC_TSTR_HT_Msk                     (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
10124 #define RTC_TSTR_HT                         RTC_TSTR_HT_Msk
10125 #define RTC_TSTR_HT_0                       (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
10126 #define RTC_TSTR_HT_1                       (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
10127 #define RTC_TSTR_PM_Pos                     (22U)
10128 #define RTC_TSTR_PM_Msk                     (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
10129 #define RTC_TSTR_PM                         RTC_TSTR_PM_Msk
10130 
10131 /********************  Bits definition for RTC_TSDR register  *****************/
10132 #define RTC_TSDR_DU_Pos                     (0U)
10133 #define RTC_TSDR_DU_Msk                     (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
10134 #define RTC_TSDR_DU                         RTC_TSDR_DU_Msk
10135 #define RTC_TSDR_DU_0                       (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
10136 #define RTC_TSDR_DU_1                       (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
10137 #define RTC_TSDR_DU_2                       (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
10138 #define RTC_TSDR_DU_3                       (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
10139 #define RTC_TSDR_DT_Pos                     (4U)
10140 #define RTC_TSDR_DT_Msk                     (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
10141 #define RTC_TSDR_DT                         RTC_TSDR_DT_Msk
10142 #define RTC_TSDR_DT_0                       (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
10143 #define RTC_TSDR_DT_1                       (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
10144 #define RTC_TSDR_MU_Pos                     (8U)
10145 #define RTC_TSDR_MU_Msk                     (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
10146 #define RTC_TSDR_MU                         RTC_TSDR_MU_Msk
10147 #define RTC_TSDR_MU_0                       (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
10148 #define RTC_TSDR_MU_1                       (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
10149 #define RTC_TSDR_MU_2                       (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
10150 #define RTC_TSDR_MU_3                       (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
10151 #define RTC_TSDR_MT_Pos                     (12U)
10152 #define RTC_TSDR_MT_Msk                     (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
10153 #define RTC_TSDR_MT                         RTC_TSDR_MT_Msk
10154 #define RTC_TSDR_WDU_Pos                    (13U)
10155 #define RTC_TSDR_WDU_Msk                    (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
10156 #define RTC_TSDR_WDU                        RTC_TSDR_WDU_Msk
10157 #define RTC_TSDR_WDU_0                      (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
10158 #define RTC_TSDR_WDU_1                      (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
10159 #define RTC_TSDR_WDU_2                      (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
10160 
10161 /********************  Bits definition for RTC_TSSSR register  ****************/
10162 #define RTC_TSSSR_SS_Pos                    (0U)
10163 #define RTC_TSSSR_SS_Msk                    (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)      /*!< 0xFFFFFFFF */
10164 #define RTC_TSSSR_SS                        RTC_TSSSR_SS_Msk                        /*!< rtc timestamp sub second > */
10165 
10166 /********************  Bits definition for RTC_ALRMAR register  ***************/
10167 #define RTC_ALRMAR_SU_Pos                   (0U)
10168 #define RTC_ALRMAR_SU_Msk                   (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
10169 #define RTC_ALRMAR_SU                       RTC_ALRMAR_SU_Msk
10170 #define RTC_ALRMAR_SU_0                     (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
10171 #define RTC_ALRMAR_SU_1                     (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
10172 #define RTC_ALRMAR_SU_2                     (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
10173 #define RTC_ALRMAR_SU_3                     (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
10174 #define RTC_ALRMAR_ST_Pos                   (4U)
10175 #define RTC_ALRMAR_ST_Msk                   (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
10176 #define RTC_ALRMAR_ST                       RTC_ALRMAR_ST_Msk
10177 #define RTC_ALRMAR_ST_0                     (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
10178 #define RTC_ALRMAR_ST_1                     (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
10179 #define RTC_ALRMAR_ST_2                     (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
10180 #define RTC_ALRMAR_MSK1_Pos                 (7U)
10181 #define RTC_ALRMAR_MSK1_Msk                 (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
10182 #define RTC_ALRMAR_MSK1                     RTC_ALRMAR_MSK1_Msk
10183 #define RTC_ALRMAR_MNU_Pos                  (8U)
10184 #define RTC_ALRMAR_MNU_Msk                  (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
10185 #define RTC_ALRMAR_MNU                      RTC_ALRMAR_MNU_Msk
10186 #define RTC_ALRMAR_MNU_0                    (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
10187 #define RTC_ALRMAR_MNU_1                    (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
10188 #define RTC_ALRMAR_MNU_2                    (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
10189 #define RTC_ALRMAR_MNU_3                    (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
10190 #define RTC_ALRMAR_MNT_Pos                  (12U)
10191 #define RTC_ALRMAR_MNT_Msk                  (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
10192 #define RTC_ALRMAR_MNT                      RTC_ALRMAR_MNT_Msk
10193 #define RTC_ALRMAR_MNT_0                    (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
10194 #define RTC_ALRMAR_MNT_1                    (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
10195 #define RTC_ALRMAR_MNT_2                    (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
10196 #define RTC_ALRMAR_MSK2_Pos                 (15U)
10197 #define RTC_ALRMAR_MSK2_Msk                 (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
10198 #define RTC_ALRMAR_MSK2                     RTC_ALRMAR_MSK2_Msk
10199 #define RTC_ALRMAR_HU_Pos                   (16U)
10200 #define RTC_ALRMAR_HU_Msk                   (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
10201 #define RTC_ALRMAR_HU                       RTC_ALRMAR_HU_Msk
10202 #define RTC_ALRMAR_HU_0                     (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
10203 #define RTC_ALRMAR_HU_1                     (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
10204 #define RTC_ALRMAR_HU_2                     (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
10205 #define RTC_ALRMAR_HU_3                     (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
10206 #define RTC_ALRMAR_HT_Pos                   (20U)
10207 #define RTC_ALRMAR_HT_Msk                   (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
10208 #define RTC_ALRMAR_HT                       RTC_ALRMAR_HT_Msk
10209 #define RTC_ALRMAR_HT_0                     (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
10210 #define RTC_ALRMAR_HT_1                     (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
10211 #define RTC_ALRMAR_PM_Pos                   (22U)
10212 #define RTC_ALRMAR_PM_Msk                   (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
10213 #define RTC_ALRMAR_PM                       RTC_ALRMAR_PM_Msk
10214 #define RTC_ALRMAR_MSK3_Pos                 (23U)
10215 #define RTC_ALRMAR_MSK3_Msk                 (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
10216 #define RTC_ALRMAR_MSK3                     RTC_ALRMAR_MSK3_Msk
10217 #define RTC_ALRMAR_DU_Pos                   (24U)
10218 #define RTC_ALRMAR_DU_Msk                   (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
10219 #define RTC_ALRMAR_DU                       RTC_ALRMAR_DU_Msk
10220 #define RTC_ALRMAR_DU_0                     (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
10221 #define RTC_ALRMAR_DU_1                     (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
10222 #define RTC_ALRMAR_DU_2                     (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
10223 #define RTC_ALRMAR_DU_3                     (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
10224 #define RTC_ALRMAR_DT_Pos                   (28U)
10225 #define RTC_ALRMAR_DT_Msk                   (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
10226 #define RTC_ALRMAR_DT                       RTC_ALRMAR_DT_Msk
10227 #define RTC_ALRMAR_DT_0                     (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
10228 #define RTC_ALRMAR_DT_1                     (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
10229 #define RTC_ALRMAR_WDSEL_Pos                (30U)
10230 #define RTC_ALRMAR_WDSEL_Msk                (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
10231 #define RTC_ALRMAR_WDSEL                    RTC_ALRMAR_WDSEL_Msk
10232 #define RTC_ALRMAR_MSK4_Pos                 (31U)
10233 #define RTC_ALRMAR_MSK4_Msk                 (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
10234 #define RTC_ALRMAR_MSK4                     RTC_ALRMAR_MSK4_Msk
10235 
10236 /********************  Bits definition for RTC_ALRMASSR register  *************/
10237 #define RTC_ALRMASSR_SS_Pos                 (0U)
10238 #define RTC_ALRMASSR_SS_Msk                 (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
10239 #define RTC_ALRMASSR_SS                     RTC_ALRMASSR_SS_Msk
10240 #define RTC_ALRMASSR_MASKSS_Pos             (24U)
10241 #define RTC_ALRMASSR_MASKSS_Msk             (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x3F000000 */
10242 #define RTC_ALRMASSR_MASKSS                 RTC_ALRMASSR_MASKSS_Msk
10243 #define RTC_ALRMASSR_MASKSS_0               (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
10244 #define RTC_ALRMASSR_MASKSS_1               (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
10245 #define RTC_ALRMASSR_MASKSS_2               (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
10246 #define RTC_ALRMASSR_MASKSS_3               (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
10247 #define RTC_ALRMASSR_MASKSS_4               (0x10UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x10000000 */
10248 #define RTC_ALRMASSR_MASKSS_5               (0x20UL << RTC_ALRMASSR_MASKSS_Pos)     /*!< 0x20000000 */
10249 #define RTC_ALRMASSR_SSCLR_Pos              (31U)
10250 #define RTC_ALRMASSR_SSCLR_Msk              (0x1UL << RTC_ALRMASSR_SSCLR_Pos)       /*!< 0x80000000 */
10251 #define RTC_ALRMASSR_SSCLR                  RTC_ALRMASSR_SSCLR_Msk
10252 
10253 /********************  Bits definition for RTC_ALRMBR register  ***************/
10254 #define RTC_ALRMBR_SU_Pos                   (0U)
10255 #define RTC_ALRMBR_SU_Msk                   (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
10256 #define RTC_ALRMBR_SU                       RTC_ALRMBR_SU_Msk
10257 #define RTC_ALRMBR_SU_0                     (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
10258 #define RTC_ALRMBR_SU_1                     (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
10259 #define RTC_ALRMBR_SU_2                     (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
10260 #define RTC_ALRMBR_SU_3                     (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
10261 #define RTC_ALRMBR_ST_Pos                   (4U)
10262 #define RTC_ALRMBR_ST_Msk                   (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
10263 #define RTC_ALRMBR_ST                       RTC_ALRMBR_ST_Msk
10264 #define RTC_ALRMBR_ST_0                     (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
10265 #define RTC_ALRMBR_ST_1                     (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
10266 #define RTC_ALRMBR_ST_2                     (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
10267 #define RTC_ALRMBR_MSK1_Pos                 (7U)
10268 #define RTC_ALRMBR_MSK1_Msk                 (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
10269 #define RTC_ALRMBR_MSK1                     RTC_ALRMBR_MSK1_Msk
10270 #define RTC_ALRMBR_MNU_Pos                  (8U)
10271 #define RTC_ALRMBR_MNU_Msk                  (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
10272 #define RTC_ALRMBR_MNU                      RTC_ALRMBR_MNU_Msk
10273 #define RTC_ALRMBR_MNU_0                    (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
10274 #define RTC_ALRMBR_MNU_1                    (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
10275 #define RTC_ALRMBR_MNU_2                    (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
10276 #define RTC_ALRMBR_MNU_3                    (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
10277 #define RTC_ALRMBR_MNT_Pos                  (12U)
10278 #define RTC_ALRMBR_MNT_Msk                  (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
10279 #define RTC_ALRMBR_MNT                      RTC_ALRMBR_MNT_Msk
10280 #define RTC_ALRMBR_MNT_0                    (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
10281 #define RTC_ALRMBR_MNT_1                    (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
10282 #define RTC_ALRMBR_MNT_2                    (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
10283 #define RTC_ALRMBR_MSK2_Pos                 (15U)
10284 #define RTC_ALRMBR_MSK2_Msk                 (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
10285 #define RTC_ALRMBR_MSK2                     RTC_ALRMBR_MSK2_Msk
10286 #define RTC_ALRMBR_HU_Pos                   (16U)
10287 #define RTC_ALRMBR_HU_Msk                   (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
10288 #define RTC_ALRMBR_HU                       RTC_ALRMBR_HU_Msk
10289 #define RTC_ALRMBR_HU_0                     (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
10290 #define RTC_ALRMBR_HU_1                     (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
10291 #define RTC_ALRMBR_HU_2                     (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
10292 #define RTC_ALRMBR_HU_3                     (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
10293 #define RTC_ALRMBR_HT_Pos                   (20U)
10294 #define RTC_ALRMBR_HT_Msk                   (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
10295 #define RTC_ALRMBR_HT                       RTC_ALRMBR_HT_Msk
10296 #define RTC_ALRMBR_HT_0                     (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
10297 #define RTC_ALRMBR_HT_1                     (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
10298 #define RTC_ALRMBR_PM_Pos                   (22U)
10299 #define RTC_ALRMBR_PM_Msk                   (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
10300 #define RTC_ALRMBR_PM                       RTC_ALRMBR_PM_Msk
10301 #define RTC_ALRMBR_MSK3_Pos                 (23U)
10302 #define RTC_ALRMBR_MSK3_Msk                 (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
10303 #define RTC_ALRMBR_MSK3                     RTC_ALRMBR_MSK3_Msk
10304 #define RTC_ALRMBR_DU_Pos                   (24U)
10305 #define RTC_ALRMBR_DU_Msk                   (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
10306 #define RTC_ALRMBR_DU                       RTC_ALRMBR_DU_Msk
10307 #define RTC_ALRMBR_DU_0                     (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
10308 #define RTC_ALRMBR_DU_1                     (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
10309 #define RTC_ALRMBR_DU_2                     (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
10310 #define RTC_ALRMBR_DU_3                     (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
10311 #define RTC_ALRMBR_DT_Pos                   (28U)
10312 #define RTC_ALRMBR_DT_Msk                   (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
10313 #define RTC_ALRMBR_DT                       RTC_ALRMBR_DT_Msk
10314 #define RTC_ALRMBR_DT_0                     (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
10315 #define RTC_ALRMBR_DT_1                     (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
10316 #define RTC_ALRMBR_WDSEL_Pos                (30U)
10317 #define RTC_ALRMBR_WDSEL_Msk                (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
10318 #define RTC_ALRMBR_WDSEL                    RTC_ALRMBR_WDSEL_Msk
10319 #define RTC_ALRMBR_MSK4_Pos                 (31U)
10320 #define RTC_ALRMBR_MSK4_Msk                 (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
10321 #define RTC_ALRMBR_MSK4                     RTC_ALRMBR_MSK4_Msk
10322 
10323 /********************  Bits definition for RTC_ALRMBSSR register  *************/
10324 #define RTC_ALRMBSSR_SS_Pos                 (0U)
10325 #define RTC_ALRMBSSR_SS_Msk                 (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
10326 #define RTC_ALRMBSSR_SS                     RTC_ALRMBSSR_SS_Msk
10327 #define RTC_ALRMBSSR_MASKSS_Pos             (24U)
10328 #define RTC_ALRMBSSR_MASKSS_Msk             (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x3F000000 */
10329 #define RTC_ALRMBSSR_MASKSS                 RTC_ALRMBSSR_MASKSS_Msk
10330 #define RTC_ALRMBSSR_MASKSS_0               (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
10331 #define RTC_ALRMBSSR_MASKSS_1               (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
10332 #define RTC_ALRMBSSR_MASKSS_2               (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
10333 #define RTC_ALRMBSSR_MASKSS_3               (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
10334 #define RTC_ALRMBSSR_MASKSS_4               (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x10000000 */
10335 #define RTC_ALRMBSSR_MASKSS_5               (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)     /*!< 0x20000000 */
10336 #define RTC_ALRMBSSR_SSCLR_Pos              (31U)
10337 #define RTC_ALRMBSSR_SSCLR_Msk              (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)       /*!< 0x80000000 */
10338 #define RTC_ALRMBSSR_SSCLR                  RTC_ALRMBSSR_SSCLR_Msk
10339 
10340 /********************  Bits definition for RTC_SR register  *******************/
10341 #define RTC_SR_ALRAF_Pos                    (0U)
10342 #define RTC_SR_ALRAF_Msk                    (0x1UL << RTC_SR_ALRAF_Pos)             /*!< 0x00000001 */
10343 #define RTC_SR_ALRAF                        RTC_SR_ALRAF_Msk
10344 #define RTC_SR_ALRBF_Pos                    (1U)
10345 #define RTC_SR_ALRBF_Msk                    (0x1UL << RTC_SR_ALRBF_Pos)             /*!< 0x00000002 */
10346 #define RTC_SR_ALRBF                        RTC_SR_ALRBF_Msk
10347 #define RTC_SR_WUTF_Pos                     (2U)
10348 #define RTC_SR_WUTF_Msk                     (0x1UL << RTC_SR_WUTF_Pos)              /*!< 0x00000004 */
10349 #define RTC_SR_WUTF                         RTC_SR_WUTF_Msk
10350 #define RTC_SR_TSF_Pos                      (3U)
10351 #define RTC_SR_TSF_Msk                      (0x1UL << RTC_SR_TSF_Pos)               /*!< 0x00000008 */
10352 #define RTC_SR_TSF                          RTC_SR_TSF_Msk
10353 #define RTC_SR_TSOVF_Pos                    (4U)
10354 #define RTC_SR_TSOVF_Msk                    (0x1UL << RTC_SR_TSOVF_Pos)             /*!< 0x00000010 */
10355 #define RTC_SR_TSOVF                        RTC_SR_TSOVF_Msk
10356 #define RTC_SR_ITSF_Pos                     (5U)
10357 #define RTC_SR_ITSF_Msk                     (0x1UL << RTC_SR_ITSF_Pos)              /*!< 0x00000020 */
10358 #define RTC_SR_ITSF                         RTC_SR_ITSF_Msk
10359 #define RTC_SR_SSRUF_Pos                    (6U)
10360 #define RTC_SR_SSRUF_Msk                    (0x1UL << RTC_SR_SSRUF_Pos)             /*!< 0x00000040 */
10361 #define RTC_SR_SSRUF                        RTC_SR_SSRUF_Msk
10362 
10363 /********************  Bits definition for RTC_MISR register  *****************/
10364 #define RTC_MISR_ALRAMF_Pos                 (0U)
10365 #define RTC_MISR_ALRAMF_Msk                 (0x1UL << RTC_MISR_ALRAMF_Pos)          /*!< 0x00000001 */
10366 #define RTC_MISR_ALRAMF                     RTC_MISR_ALRAMF_Msk
10367 #define RTC_MISR_ALRBMF_Pos                 (1U)
10368 #define RTC_MISR_ALRBMF_Msk                 (0x1UL << RTC_MISR_ALRBMF_Pos)          /*!< 0x00000002 */
10369 #define RTC_MISR_ALRBMF                     RTC_MISR_ALRBMF_Msk
10370 #define RTC_MISR_WUTMF_Pos                  (2U)
10371 #define RTC_MISR_WUTMF_Msk                  (0x1UL << RTC_MISR_WUTMF_Pos)           /*!< 0x00000004 */
10372 #define RTC_MISR_WUTMF                      RTC_MISR_WUTMF_Msk
10373 #define RTC_MISR_TSMF_Pos                   (3U)
10374 #define RTC_MISR_TSMF_Msk                   (0x1UL << RTC_MISR_TSMF_Pos)            /*!< 0x00000008 */
10375 #define RTC_MISR_TSMF                       RTC_MISR_TSMF_Msk
10376 #define RTC_MISR_TSOVMF_Pos                 (4U)
10377 #define RTC_MISR_TSOVMF_Msk                 (0x1UL << RTC_MISR_TSOVMF_Pos)          /*!< 0x00000010 */
10378 #define RTC_MISR_TSOVMF                     RTC_MISR_TSOVMF_Msk
10379 #define RTC_MISR_ITSMF_Pos                  (5U)
10380 #define RTC_MISR_ITSMF_Msk                  (0x1UL << RTC_MISR_ITSMF_Pos)           /*!< 0x00000020 */
10381 #define RTC_MISR_ITSMF                      RTC_MISR_ITSMF_Msk
10382 #define RTC_MISR_SSRUMF_Pos                 (6U)
10383 #define RTC_MISR_SSRUMF_Msk                 (0x1UL << RTC_MISR_SSRUMF_Pos)          /*!< 0x00000040 */
10384 #define RTC_MISR_SSRUMF                     RTC_MISR_SSRUMF_Msk
10385 
10386 
10387 /********************  Bits definition for RTC_SCR register  ******************/
10388 #define RTC_SCR_CALRAF_Pos                  (0U)
10389 #define RTC_SCR_CALRAF_Msk                  (0x1UL << RTC_SCR_CALRAF_Pos)           /*!< 0x00000001 */
10390 #define RTC_SCR_CALRAF                      RTC_SCR_CALRAF_Msk
10391 #define RTC_SCR_CALRBF_Pos                  (1U)
10392 #define RTC_SCR_CALRBF_Msk                  (0x1UL << RTC_SCR_CALRBF_Pos)           /*!< 0x00000002 */
10393 #define RTC_SCR_CALRBF                      RTC_SCR_CALRBF_Msk
10394 #define RTC_SCR_CWUTF_Pos                   (2U)
10395 #define RTC_SCR_CWUTF_Msk                   (0x1UL << RTC_SCR_CWUTF_Pos)            /*!< 0x00000004 */
10396 #define RTC_SCR_CWUTF                       RTC_SCR_CWUTF_Msk
10397 #define RTC_SCR_CTSF_Pos                    (3U)
10398 #define RTC_SCR_CTSF_Msk                    (0x1UL << RTC_SCR_CTSF_Pos)             /*!< 0x00000008 */
10399 #define RTC_SCR_CTSF                        RTC_SCR_CTSF_Msk
10400 #define RTC_SCR_CTSOVF_Pos                  (4U)
10401 #define RTC_SCR_CTSOVF_Msk                  (0x1UL << RTC_SCR_CTSOVF_Pos)           /*!< 0x00000010 */
10402 #define RTC_SCR_CTSOVF                      RTC_SCR_CTSOVF_Msk
10403 #define RTC_SCR_CITSF_Pos                   (5U)
10404 #define RTC_SCR_CITSF_Msk                   (0x1UL << RTC_SCR_CITSF_Pos)            /*!< 0x00000020 */
10405 #define RTC_SCR_CITSF                       RTC_SCR_CITSF_Msk
10406 #define RTC_SCR_CSSRUF_Pos                  (6U)
10407 #define RTC_SCR_CSSRUF_Msk                  (0x1UL << RTC_SCR_CSSRUF_Pos)           /*!< 0x00000040 */
10408 #define RTC_SCR_CSSRUF                      RTC_SCR_CSSRUF_Msk
10409 
10410 
10411 /********************  Bits definition for RTC_ALRABINR register  ******************/
10412 #define RTC_ALRABINR_SS_Pos                 (0U)
10413 #define RTC_ALRABINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)   /*!< 0xFFFFFFFF */
10414 #define RTC_ALRABINR_SS                     RTC_ALRABINR_SS_Msk
10415 
10416 /********************  Bits definition for RTC_ALRBBINR register  ******************/
10417 #define RTC_ALRBBINR_SS_Pos                 (0U)
10418 #define RTC_ALRBBINR_SS_Msk                 (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)   /*!< 0xFFFFFFFF */
10419 #define RTC_ALRBBINR_SS                     RTC_ALRBBINR_SS_Msk
10420 
10421 /******************************************************************************/
10422 /*                                                                            */
10423 /*                     Tamper and backup register (TAMP)                      */
10424 /*                                                                            */
10425 /******************************************************************************/
10426 /********************  Bits definition for TAMP_CR1 register  *****************/
10427 #define TAMP_CR1_TAMP1E_Pos                 (0U)
10428 #define TAMP_CR1_TAMP1E_Msk                 (0x1UL << TAMP_CR1_TAMP1E_Pos)          /*!< 0x00000001 */
10429 #define TAMP_CR1_TAMP1E                     TAMP_CR1_TAMP1E_Msk
10430 #define TAMP_CR1_TAMP2E_Pos                 (1U)
10431 #define TAMP_CR1_TAMP2E_Msk                 (0x1UL << TAMP_CR1_TAMP2E_Pos)          /*!< 0x00000002 */
10432 #define TAMP_CR1_TAMP2E                     TAMP_CR1_TAMP2E_Msk
10433 #define TAMP_CR1_ITAMP1E_Pos                (16U)
10434 #define TAMP_CR1_ITAMP1E_Msk                (0x1UL << TAMP_CR1_ITAMP1E_Pos)         /*!< 0x00010000 */
10435 #define TAMP_CR1_ITAMP1E                    TAMP_CR1_ITAMP1E_Msk
10436 #define TAMP_CR1_ITAMP2E_Pos                (17U)
10437 #define TAMP_CR1_ITAMP2E_Msk                (0x1UL << TAMP_CR1_ITAMP2E_Pos)         /*!< 0x00020000 */
10438 #define TAMP_CR1_ITAMP2E                    TAMP_CR1_ITAMP2E_Msk
10439 #define TAMP_CR1_ITAMP3E_Pos                (18U)
10440 #define TAMP_CR1_ITAMP3E_Msk                (0x1UL << TAMP_CR1_ITAMP3E_Pos)         /*!< 0x00040000 */
10441 #define TAMP_CR1_ITAMP3E                    TAMP_CR1_ITAMP3E_Msk
10442 #define TAMP_CR1_ITAMP4E_Pos                (19U)
10443 #define TAMP_CR1_ITAMP4E_Msk                (0x1UL << TAMP_CR1_ITAMP4E_Pos)         /*!< 0x00080000 */
10444 #define TAMP_CR1_ITAMP4E                    TAMP_CR1_ITAMP4E_Msk
10445 #define TAMP_CR1_ITAMP5E_Pos                (20U)
10446 #define TAMP_CR1_ITAMP5E_Msk                (0x1UL << TAMP_CR1_ITAMP5E_Pos)         /*!< 0x00100000 */
10447 #define TAMP_CR1_ITAMP5E                    TAMP_CR1_ITAMP5E_Msk
10448 #define TAMP_CR1_ITAMP6E_Pos                (21U)
10449 #define TAMP_CR1_ITAMP6E_Msk                (0x1UL << TAMP_CR1_ITAMP6E_Pos)         /*!< 0x00200000 */
10450 #define TAMP_CR1_ITAMP6E                    TAMP_CR1_ITAMP6E_Msk
10451 #define TAMP_CR1_ITAMP7E_Pos                (22U)
10452 #define TAMP_CR1_ITAMP7E_Msk                (0x1UL << TAMP_CR1_ITAMP7E_Pos)         /*!< 0x00400000 */
10453 #define TAMP_CR1_ITAMP7E                    TAMP_CR1_ITAMP7E_Msk
10454 #define TAMP_CR1_ITAMP8E_Pos                (23U)
10455 #define TAMP_CR1_ITAMP8E_Msk                (0x1UL << TAMP_CR1_ITAMP8E_Pos)         /*!< 0x00800000 */
10456 #define TAMP_CR1_ITAMP8E                    TAMP_CR1_ITAMP8E_Msk
10457 #define TAMP_CR1_ITAMP9E_Pos                (24U)
10458 #define TAMP_CR1_ITAMP9E_Msk                (0x1UL << TAMP_CR1_ITAMP9E_Pos)         /*!< 0x01000000 */
10459 #define TAMP_CR1_ITAMP9E                    TAMP_CR1_ITAMP9E_Msk
10460 #define TAMP_CR1_ITAMP11E_Pos               (26U)
10461 #define TAMP_CR1_ITAMP11E_Msk               (0x1UL << TAMP_CR1_ITAMP11E_Pos)        /*!< 0x04000000 */
10462 #define TAMP_CR1_ITAMP11E                   TAMP_CR1_ITAMP11E_Msk
10463 #define TAMP_CR1_ITAMP12E_Pos               (27U)
10464 #define TAMP_CR1_ITAMP12E_Msk               (0x1UL << TAMP_CR1_ITAMP12E_Pos)        /*!< 0x08000000 */
10465 #define TAMP_CR1_ITAMP12E                   TAMP_CR1_ITAMP12E_Msk
10466 #define TAMP_CR1_ITAMP13E_Pos               (28U)
10467 #define TAMP_CR1_ITAMP13E_Msk               (0x1UL << TAMP_CR1_ITAMP13E_Pos)        /*!< 0x10000000 */
10468 #define TAMP_CR1_ITAMP13E                   TAMP_CR1_ITAMP13E_Msk
10469 #define TAMP_CR1_ITAMP15E_Pos               (30U)
10470 #define TAMP_CR1_ITAMP15E_Msk               (0x1UL << TAMP_CR1_ITAMP15E_Pos)        /*!< 0x40000000 */
10471 #define TAMP_CR1_ITAMP15E                   TAMP_CR1_ITAMP15E_Msk
10472 
10473 /********************  Bits definition for TAMP_CR2 register  *****************/
10474 #define TAMP_CR2_TAMP1NOERASE_Pos           (0U)
10475 #define TAMP_CR2_TAMP1NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)    /*!< 0x00000001 */
10476 #define TAMP_CR2_TAMP1NOERASE               TAMP_CR2_TAMP1NOERASE_Msk
10477 #define TAMP_CR2_TAMP2NOERASE_Pos           (1U)
10478 #define TAMP_CR2_TAMP2NOERASE_Msk           (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)    /*!< 0x00000002 */
10479 #define TAMP_CR2_TAMP2NOERASE               TAMP_CR2_TAMP2NOERASE_Msk
10480 #define TAMP_CR2_TAMP1MSK_Pos               (16U)
10481 #define TAMP_CR2_TAMP1MSK_Msk               (0x1UL << TAMP_CR2_TAMP1MSK_Pos)        /*!< 0x00010000 */
10482 #define TAMP_CR2_TAMP1MSK                   TAMP_CR2_TAMP1MSK_Msk
10483 #define TAMP_CR2_TAMP2MSK_Pos               (17U)
10484 #define TAMP_CR2_TAMP2MSK_Msk               (0x1UL << TAMP_CR2_TAMP2MSK_Pos)        /*!< 0x00020000 */
10485 #define TAMP_CR2_TAMP2MSK                   TAMP_CR2_TAMP2MSK_Msk
10486 #define TAMP_CR2_BKBLOCK_Pos                (22U)
10487 #define TAMP_CR2_BKBLOCK_Msk                (0x1UL << TAMP_CR2_BKBLOCK_Pos)         /*!< 0x00400000 */
10488 #define TAMP_CR2_BKBLOCK                    TAMP_CR2_BKBLOCK_Msk
10489 #define TAMP_CR2_BKERASE_Pos                (23U)
10490 #define TAMP_CR2_BKERASE_Msk                (0x1UL << TAMP_CR2_BKERASE_Pos)         /*!< 0x00800000 */
10491 #define TAMP_CR2_BKERASE                    TAMP_CR2_BKERASE_Msk
10492 #define TAMP_CR2_TAMP1TRG_Pos               (24U)
10493 #define TAMP_CR2_TAMP1TRG_Msk               (0x1UL << TAMP_CR2_TAMP1TRG_Pos)        /*!< 0x01000000 */
10494 #define TAMP_CR2_TAMP1TRG                   TAMP_CR2_TAMP1TRG_Msk
10495 #define TAMP_CR2_TAMP2TRG_Pos               (25U)
10496 #define TAMP_CR2_TAMP2TRG_Msk               (0x1UL << TAMP_CR2_TAMP2TRG_Pos)        /*!< 0x02000000 */
10497 #define TAMP_CR2_TAMP2TRG                   TAMP_CR2_TAMP2TRG_Msk
10498 
10499 /********************  Bits definition for TAMP_CR3 register  *****************/
10500 #define TAMP_CR3_ITAMP1NOER_Pos             (0U)
10501 #define TAMP_CR3_ITAMP1NOER_Msk             (0x1UL << TAMP_CR3_ITAMP1NOER_Pos)      /*!< 0x00000001 */
10502 #define TAMP_CR3_ITAMP1NOER                 TAMP_CR3_ITAMP1NOER_Msk
10503 #define TAMP_CR3_ITAMP2NOER_Pos             (1U)
10504 #define TAMP_CR3_ITAMP2NOER_Msk             (0x1UL << TAMP_CR3_ITAMP2NOER_Pos)      /*!< 0x00000002 */
10505 #define TAMP_CR3_ITAMP2NOER                 TAMP_CR3_ITAMP2NOER_Msk
10506 #define TAMP_CR3_ITAMP3NOER_Pos             (2U)
10507 #define TAMP_CR3_ITAMP3NOER_Msk             (0x1UL << TAMP_CR3_ITAMP3NOER_Pos)      /*!< 0x00000004 */
10508 #define TAMP_CR3_ITAMP3NOER                 TAMP_CR3_ITAMP3NOER_Msk
10509 #define TAMP_CR3_ITAMP4NOER_Pos             (3U)
10510 #define TAMP_CR3_ITAMP4NOER_Msk             (0x1UL << TAMP_CR3_ITAMP4NOER_Pos)      /*!< 0x00000008 */
10511 #define TAMP_CR3_ITAMP4NOER                 TAMP_CR3_ITAMP4NOER_Msk
10512 #define TAMP_CR3_ITAMP5NOER_Pos             (4U)
10513 #define TAMP_CR3_ITAMP5NOER_Msk             (0x1UL << TAMP_CR3_ITAMP5NOER_Pos)      /*!< 0x00000010 */
10514 #define TAMP_CR3_ITAMP5NOER                 TAMP_CR3_ITAMP5NOER_Msk
10515 #define TAMP_CR3_ITAMP6NOER_Pos             (5U)
10516 #define TAMP_CR3_ITAMP6NOER_Msk             (0x1UL << TAMP_CR3_ITAMP6NOER_Pos)      /*!< 0x00000020 */
10517 #define TAMP_CR3_ITAMP6NOER                 TAMP_CR3_ITAMP6NOER_Msk
10518 #define TAMP_CR3_ITAMP7NOER_Pos             (6U)
10519 #define TAMP_CR3_ITAMP7NOER_Msk             (0x1UL << TAMP_CR3_ITAMP7NOER_Pos)      /*!< 0x00000040 */
10520 #define TAMP_CR3_ITAMP7NOER                 TAMP_CR3_ITAMP7NOER_Msk
10521 #define TAMP_CR3_ITAMP8NOER_Pos             (7U)
10522 #define TAMP_CR3_ITAMP8NOER_Msk             (0x1UL << TAMP_CR3_ITAMP8NOER_Pos)      /*!< 0x00000080 */
10523 #define TAMP_CR3_ITAMP8NOER                 TAMP_CR3_ITAMP8NOER_Msk
10524 #define TAMP_CR3_ITAMP9NOER_Pos             (8U)
10525 #define TAMP_CR3_ITAMP9NOER_Msk             (0x1UL << TAMP_CR3_ITAMP9NOER_Pos)      /*!< 0x00000100 */
10526 #define TAMP_CR3_ITAMP9NOER                 TAMP_CR3_ITAMP9NOER_Msk
10527 #define TAMP_CR3_ITAMP11NOER_Pos            (10U)
10528 #define TAMP_CR3_ITAMP11NOER_Msk            (0x1UL << TAMP_CR3_ITAMP11NOER_Pos)     /*!< 0x00000400 */
10529 #define TAMP_CR3_ITAMP11NOER                TAMP_CR3_ITAMP11NOER_Msk
10530 #define TAMP_CR3_ITAMP12NOER_Pos            (11U)
10531 #define TAMP_CR3_ITAMP12NOER_Msk            (0x1UL << TAMP_CR3_ITAMP12NOER_Pos)     /*!< 0x00000800 */
10532 #define TAMP_CR3_ITAMP12NOER                TAMP_CR3_ITAMP12NOER_Msk
10533 #define TAMP_CR3_ITAMP13NOER_Pos            (12U)
10534 #define TAMP_CR3_ITAMP13NOER_Msk            (0x1UL << TAMP_CR3_ITAMP13NOER_Pos)     /*!< 0x00001000 */
10535 #define TAMP_CR3_ITAMP13NOER                TAMP_CR3_ITAMP13NOER_Msk
10536 #define TAMP_CR3_ITAMP15NOER_Pos            (14U)
10537 #define TAMP_CR3_ITAMP15NOER_Msk            (0x1UL << TAMP_CR3_ITAMP15NOER_Pos)     /*!< 0x00004000 */
10538 #define TAMP_CR3_ITAMP15NOER                TAMP_CR3_ITAMP15NOER_Msk
10539 
10540 /********************  Bits definition for TAMP_FLTCR register  ***************/
10541 #define TAMP_FLTCR_TAMPFREQ_Pos             (0U)
10542 #define TAMP_FLTCR_TAMPFREQ_Msk             (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000007 */
10543 #define TAMP_FLTCR_TAMPFREQ                 TAMP_FLTCR_TAMPFREQ_Msk
10544 #define TAMP_FLTCR_TAMPFREQ_0               (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000001 */
10545 #define TAMP_FLTCR_TAMPFREQ_1               (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000002 */
10546 #define TAMP_FLTCR_TAMPFREQ_2               (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)      /*!< 0x00000004 */
10547 #define TAMP_FLTCR_TAMPFLT_Pos              (3U)
10548 #define TAMP_FLTCR_TAMPFLT_Msk              (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000018 */
10549 #define TAMP_FLTCR_TAMPFLT                  TAMP_FLTCR_TAMPFLT_Msk
10550 #define TAMP_FLTCR_TAMPFLT_0                (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000008 */
10551 #define TAMP_FLTCR_TAMPFLT_1                (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)       /*!< 0x00000010 */
10552 #define TAMP_FLTCR_TAMPPRCH_Pos             (5U)
10553 #define TAMP_FLTCR_TAMPPRCH_Msk             (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000060 */
10554 #define TAMP_FLTCR_TAMPPRCH                 TAMP_FLTCR_TAMPPRCH_Msk
10555 #define TAMP_FLTCR_TAMPPRCH_0               (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000020 */
10556 #define TAMP_FLTCR_TAMPPRCH_1               (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)      /*!< 0x00000040 */
10557 #define TAMP_FLTCR_TAMPPUDIS_Pos            (7U)
10558 #define TAMP_FLTCR_TAMPPUDIS_Msk            (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)     /*!< 0x00000080 */
10559 #define TAMP_FLTCR_TAMPPUDIS                TAMP_FLTCR_TAMPPUDIS_Msk
10560 
10561 /********************  Bits definition for TAMP_ATCR1 register  ***************/
10562 #define TAMP_ATCR1_TAMP1AM_Pos              (0U)
10563 #define TAMP_ATCR1_TAMP1AM_Msk              (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)       /*!< 0x00000001 */
10564 #define TAMP_ATCR1_TAMP1AM                  TAMP_ATCR1_TAMP1AM_Msk
10565 #define TAMP_ATCR1_TAMP2AM_Pos              (1U)
10566 #define TAMP_ATCR1_TAMP2AM_Msk              (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)       /*!< 0x00000002 */
10567 #define TAMP_ATCR1_TAMP2AM                  TAMP_ATCR1_TAMP2AM_Msk
10568 #define TAMP_ATCR1_ATOSEL1_Pos              (8U)
10569 #define TAMP_ATCR1_ATOSEL1_Msk              (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000300 */
10570 #define TAMP_ATCR1_ATOSEL1                  TAMP_ATCR1_ATOSEL1_Msk
10571 #define TAMP_ATCR1_ATOSEL1_0                (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000100 */
10572 #define TAMP_ATCR1_ATOSEL1_1                (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)       /*!< 0x00000200 */
10573 #define TAMP_ATCR1_ATOSEL2_Pos              (10U)
10574 #define TAMP_ATCR1_ATOSEL2_Msk              (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000C00 */
10575 #define TAMP_ATCR1_ATOSEL2                  TAMP_ATCR1_ATOSEL2_Msk
10576 #define TAMP_ATCR1_ATOSEL2_0                (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000400 */
10577 #define TAMP_ATCR1_ATOSEL2_1                (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)       /*!< 0x00000800 */
10578 #define TAMP_ATCR1_ATCKSEL_Pos              (16U)
10579 #define TAMP_ATCR1_ATCKSEL_Msk              (0xFUL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x000F0000 */
10580 #define TAMP_ATCR1_ATCKSEL                  TAMP_ATCR1_ATCKSEL_Msk
10581 #define TAMP_ATCR1_ATCKSEL_0                (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00010000 */
10582 #define TAMP_ATCR1_ATCKSEL_1                (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00020000 */
10583 #define TAMP_ATCR1_ATCKSEL_2                (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00040000 */
10584 #define TAMP_ATCR1_ATCKSEL_3                (0x8UL << TAMP_ATCR1_ATCKSEL_Pos)       /*!< 0x00080000 */
10585 #define TAMP_ATCR1_ATPER_Pos                (24U)
10586 #define TAMP_ATCR1_ATPER_Msk                (0x7UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x07000000 */
10587 #define TAMP_ATCR1_ATPER                    TAMP_ATCR1_ATPER_Msk
10588 #define TAMP_ATCR1_ATPER_0                  (0x1UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x01000000 */
10589 #define TAMP_ATCR1_ATPER_1                  (0x2UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x02000000 */
10590 #define TAMP_ATCR1_ATPER_2                  (0x4UL << TAMP_ATCR1_ATPER_Pos)         /*!< 0x04000000 */
10591 #define TAMP_ATCR1_ATOSHARE_Pos             (30U)
10592 #define TAMP_ATCR1_ATOSHARE_Msk             (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)      /*!< 0x40000000 */
10593 #define TAMP_ATCR1_ATOSHARE                 TAMP_ATCR1_ATOSHARE_Msk
10594 #define TAMP_ATCR1_FLTEN_Pos                (31U)
10595 #define TAMP_ATCR1_FLTEN_Msk                (0x1UL << TAMP_ATCR1_FLTEN_Pos)         /*!< 0x80000000 */
10596 #define TAMP_ATCR1_FLTEN                    TAMP_ATCR1_FLTEN_Msk
10597 
10598 /********************  Bits definition for TAMP_ATSEEDR register  ******************/
10599 #define TAMP_ATSEEDR_SEED_Pos               (0U)
10600 #define TAMP_ATSEEDR_SEED_Msk               (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
10601 #define TAMP_ATSEEDR_SEED                   TAMP_ATSEEDR_SEED_Msk
10602 
10603 /********************  Bits definition for TAMP_ATOR register  ******************/
10604 #define TAMP_ATOR_PRNG_Pos                  (0U)
10605 #define TAMP_ATOR_PRNG_Msk                  (0xFFUL << TAMP_ATOR_PRNG_Pos)            /*!< 0x000000FF */
10606 #define TAMP_ATOR_PRNG                      TAMP_ATOR_PRNG_Msk
10607 #define TAMP_ATOR_PRNG_0                    (0x1UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000001 */
10608 #define TAMP_ATOR_PRNG_1                    (0x2UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000002 */
10609 #define TAMP_ATOR_PRNG_2                    (0x4UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000004 */
10610 #define TAMP_ATOR_PRNG_3                    (0x8UL << TAMP_ATOR_PRNG_Pos)           /*!< 0x00000008 */
10611 #define TAMP_ATOR_PRNG_4                    (0x10UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000010 */
10612 #define TAMP_ATOR_PRNG_5                    (0x20UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000020 */
10613 #define TAMP_ATOR_PRNG_6                    (0x40UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000040 */
10614 #define TAMP_ATOR_PRNG_7                    (0x80UL << TAMP_ATOR_PRNG_Pos)          /*!< 0x00000080 */
10615 #define TAMP_ATOR_SEEDF_Pos                 (14U)
10616 #define TAMP_ATOR_SEEDF_Msk                 (1UL << TAMP_ATOR_SEEDF_Pos)            /*!< 0x00004000 */
10617 #define TAMP_ATOR_SEEDF                     TAMP_ATOR_SEEDF_Msk
10618 #define TAMP_ATOR_INITS_Pos                 (15U)
10619 #define TAMP_ATOR_INITS_Msk                 (1UL << TAMP_ATOR_INITS_Pos)            /*!< 0x00008000 */
10620 #define TAMP_ATOR_INITS                     TAMP_ATOR_INITS_Msk
10621 
10622 /********************  Bits definition for TAMP_ATCR2 register  ***************/
10623 #define TAMP_ATCR2_ATOSEL1_Pos              (8U)
10624 #define TAMP_ATCR2_ATOSEL1_Msk              (0x7UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000700 */
10625 #define TAMP_ATCR2_ATOSEL1                  TAMP_ATCR2_ATOSEL1_Msk
10626 #define TAMP_ATCR2_ATOSEL1_0                (0x1UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000100 */
10627 #define TAMP_ATCR2_ATOSEL1_1                (0x2UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000200 */
10628 #define TAMP_ATCR2_ATOSEL1_2                (0x4UL << TAMP_ATCR2_ATOSEL1_Pos)       /*!< 0x00000400 */
10629 #define TAMP_ATCR2_ATOSEL2_Pos              (11U)
10630 #define TAMP_ATCR2_ATOSEL2_Msk              (0x7UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00003800 */
10631 #define TAMP_ATCR2_ATOSEL2                  TAMP_ATCR2_ATOSEL2_Msk
10632 #define TAMP_ATCR2_ATOSEL2_0                (0x1UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00000800 */
10633 #define TAMP_ATCR2_ATOSEL2_1                (0x2UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00001000 */
10634 #define TAMP_ATCR2_ATOSEL2_2                (0x4UL << TAMP_ATCR2_ATOSEL2_Pos)       /*!< 0x00002000 */
10635 
10636 /********************  Bits definition for TAMP_SECCFGR register  *************/
10637 /* Keep SEC acronym  name as following devices (STM32H562xx, STM32H563xx, STM32H573xx) with secure
10638    acronym to avoid duplicated bits definitions */
10639 #define TAMP_SECCFGR_BKPRWSEC_Pos           (0U)
10640 #define TAMP_SECCFGR_BKPRWSEC_Msk           (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x000000FF */
10641 #define TAMP_SECCFGR_BKPRWSEC               TAMP_SECCFGR_BKPRWSEC_Msk
10642 #define TAMP_SECCFGR_BKPRWSEC_0             (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000001 */
10643 #define TAMP_SECCFGR_BKPRWSEC_1             (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000002 */
10644 #define TAMP_SECCFGR_BKPRWSEC_2             (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000004 */
10645 #define TAMP_SECCFGR_BKPRWSEC_3             (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos)    /*!< 0x00000008 */
10646 #define TAMP_SECCFGR_BKPRWSEC_4             (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000010 */
10647 #define TAMP_SECCFGR_BKPRWSEC_5             (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000020 */
10648 #define TAMP_SECCFGR_BKPRWSEC_6             (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000040 */
10649 #define TAMP_SECCFGR_BKPRWSEC_7             (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos)   /*!< 0x00000080 */
10650 #define TAMP_SECCFGR_BKPWSEC_Pos            (16U)
10651 #define TAMP_SECCFGR_BKPWSEC_Msk            (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00FF0000 */
10652 #define TAMP_SECCFGR_BKPWSEC                TAMP_SECCFGR_BKPWSEC_Msk
10653 #define TAMP_SECCFGR_BKPWSEC_0              (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00010000 */
10654 #define TAMP_SECCFGR_BKPWSEC_1              (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00020000 */
10655 #define TAMP_SECCFGR_BKPWSEC_2              (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00040000 */
10656 #define TAMP_SECCFGR_BKPWSEC_3              (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos)     /*!< 0x00080000 */
10657 #define TAMP_SECCFGR_BKPWSEC_4              (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00100000 */
10658 #define TAMP_SECCFGR_BKPWSEC_5              (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00200000 */
10659 #define TAMP_SECCFGR_BKPWSEC_6              (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00400000 */
10660 #define TAMP_SECCFGR_BKPWSEC_7              (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos)    /*!< 0x00800000 */
10661 
10662 /********************  Bits definition for TAMP_PRIVCFGR register  ************/
10663 #define TAMP_PRIVCFGR_CNT1PRIV_Pos          (15U)
10664 #define TAMP_PRIVCFGR_CNT1PRIV_Msk          (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos)     /*!< 0x20000000 */
10665 #define TAMP_PRIVCFGR_CNT1PRIV              TAMP_PRIVCFGR_CNT1PRIV_Msk
10666 #define TAMP_PRIVCFGR_BKPRWPRIV_Pos         (29U)
10667 #define TAMP_PRIVCFGR_BKPRWPRIV_Msk         (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos)    /*!< 0x20000000 */
10668 #define TAMP_PRIVCFGR_BKPRWPRIV             TAMP_PRIVCFGR_BKPRWPRIV_Msk
10669 #define TAMP_PRIVCFGR_BKPWPRIV_Pos          (30U)
10670 #define TAMP_PRIVCFGR_BKPWPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos)     /*!< 0x40000000 */
10671 #define TAMP_PRIVCFGR_BKPWPRIV              TAMP_PRIVCFGR_BKPWPRIV_Msk
10672 #define TAMP_PRIVCFGR_TAMPPRIV_Pos          (31U)
10673 #define TAMP_PRIVCFGR_TAMPPRIV_Msk          (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos)   /*!< 0x80000000 */
10674 #define TAMP_PRIVCFGR_TAMPPRIV              TAMP_PRIVCFGR_TAMPPRIV_Msk
10675 
10676 /********************  Bits definition for TAMP_IER register  *****************/
10677 #define TAMP_IER_TAMP1IE_Pos                (0U)
10678 #define TAMP_IER_TAMP1IE_Msk                (0x1UL << TAMP_IER_TAMP1IE_Pos)         /*!< 0x00000001 */
10679 #define TAMP_IER_TAMP1IE                    TAMP_IER_TAMP1IE_Msk
10680 #define TAMP_IER_TAMP2IE_Pos                (1U)
10681 #define TAMP_IER_TAMP2IE_Msk                (0x1UL << TAMP_IER_TAMP2IE_Pos)         /*!< 0x00000002 */
10682 #define TAMP_IER_TAMP2IE                    TAMP_IER_TAMP2IE_Msk
10683 #define TAMP_IER_ITAMP1IE_Pos               (16U)
10684 #define TAMP_IER_ITAMP1IE_Msk               (0x1UL << TAMP_IER_ITAMP1IE_Pos)        /*!< 0x00010000 */
10685 #define TAMP_IER_ITAMP1IE                   TAMP_IER_ITAMP1IE_Msk
10686 #define TAMP_IER_ITAMP2IE_Pos               (17U)
10687 #define TAMP_IER_ITAMP2IE_Msk               (0x1UL << TAMP_IER_ITAMP2IE_Pos)        /*!< 0x00020000 */
10688 #define TAMP_IER_ITAMP2IE                   TAMP_IER_ITAMP2IE_Msk
10689 #define TAMP_IER_ITAMP3IE_Pos               (18U)
10690 #define TAMP_IER_ITAMP3IE_Msk               (0x1UL << TAMP_IER_ITAMP3IE_Pos)        /*!< 0x00040000 */
10691 #define TAMP_IER_ITAMP3IE                   TAMP_IER_ITAMP3IE_Msk
10692 #define TAMP_IER_ITAMP4IE_Pos               (19U)
10693 #define TAMP_IER_ITAMP4IE_Msk               (0x1UL << TAMP_IER_ITAMP4IE_Pos)        /*!< 0x00080000 */
10694 #define TAMP_IER_ITAMP4IE                   TAMP_IER_ITAMP4IE_Msk
10695 #define TAMP_IER_ITAMP5IE_Pos               (20U)
10696 #define TAMP_IER_ITAMP5IE_Msk               (0x1UL << TAMP_IER_ITAMP5IE_Pos)        /*!< 0x00100000 */
10697 #define TAMP_IER_ITAMP5IE                   TAMP_IER_ITAMP5IE_Msk
10698 #define TAMP_IER_ITAMP6IE_Pos               (21U)
10699 #define TAMP_IER_ITAMP6IE_Msk               (0x1UL << TAMP_IER_ITAMP6IE_Pos)        /*!< 0x00200000 */
10700 #define TAMP_IER_ITAMP6IE                   TAMP_IER_ITAMP6IE_Msk
10701 #define TAMP_IER_ITAMP7IE_Pos               (22U)
10702 #define TAMP_IER_ITAMP7IE_Msk               (0x1UL << TAMP_IER_ITAMP7IE_Pos)        /*!< 0x00400000 */
10703 #define TAMP_IER_ITAMP7IE                   TAMP_IER_ITAMP7IE_Msk
10704 #define TAMP_IER_ITAMP8IE_Pos               (23U)
10705 #define TAMP_IER_ITAMP8IE_Msk               (0x1UL << TAMP_IER_ITAMP8IE_Pos)        /*!< 0x00800000 */
10706 #define TAMP_IER_ITAMP8IE                   TAMP_IER_ITAMP8IE_Msk
10707 #define TAMP_IER_ITAMP9IE_Pos               (24U)
10708 #define TAMP_IER_ITAMP9IE_Msk               (0x1UL << TAMP_IER_ITAMP9IE_Pos)        /*!< 0x01000000 */
10709 #define TAMP_IER_ITAMP9IE                   TAMP_IER_ITAMP9IE_Msk
10710 #define TAMP_IER_ITAMP11IE_Pos              (26U)
10711 #define TAMP_IER_ITAMP11IE_Msk              (0x1UL << TAMP_IER_ITAMP11IE_Pos)       /*!< 0x04000000 */
10712 #define TAMP_IER_ITAMP11IE                  TAMP_IER_ITAMP11IE_Msk
10713 #define TAMP_IER_ITAMP12IE_Pos              (27U)
10714 #define TAMP_IER_ITAMP12IE_Msk              (0x1UL << TAMP_IER_ITAMP12IE_Pos)       /*!< 0x08000000 */
10715 #define TAMP_IER_ITAMP12IE                  TAMP_IER_ITAMP12IE_Msk
10716 #define TAMP_IER_ITAMP13IE_Pos              (28U)
10717 #define TAMP_IER_ITAMP13IE_Msk              (0x1UL << TAMP_IER_ITAMP13IE_Pos)       /*!< 0x10000000 */
10718 #define TAMP_IER_ITAMP13IE                  TAMP_IER_ITAMP13IE_Msk
10719 #define TAMP_IER_ITAMP15IE_Pos              (30U)
10720 #define TAMP_IER_ITAMP15IE_Msk              (0x1UL << TAMP_IER_ITAMP15IE_Pos)       /*!< 0x40000000 */
10721 #define TAMP_IER_ITAMP15IE                  TAMP_IER_ITAMP15IE_Msk
10722 
10723 /********************  Bits definition for TAMP_SR register  *****************/
10724 #define TAMP_SR_TAMP1F_Pos                  (0U)
10725 #define TAMP_SR_TAMP1F_Msk                  (0x1UL << TAMP_SR_TAMP1F_Pos)           /*!< 0x00000001 */
10726 #define TAMP_SR_TAMP1F                      TAMP_SR_TAMP1F_Msk
10727 #define TAMP_SR_TAMP2F_Pos                  (1U)
10728 #define TAMP_SR_TAMP2F_Msk                  (0x1UL << TAMP_SR_TAMP2F_Pos)           /*!< 0x00000002 */
10729 #define TAMP_SR_TAMP2F                      TAMP_SR_TAMP2F_Msk
10730 #define TAMP_SR_ITAMP1F_Pos                 (16U)
10731 #define TAMP_SR_ITAMP1F_Msk                 (0x1UL << TAMP_SR_ITAMP1F_Pos)          /*!< 0x00010000 */
10732 #define TAMP_SR_ITAMP1F                     TAMP_SR_ITAMP1F_Msk
10733 #define TAMP_SR_ITAMP2F_Pos                 (17U)
10734 #define TAMP_SR_ITAMP2F_Msk                 (0x1UL << TAMP_SR_ITAMP2F_Pos)          /*!< 0x00020000 */
10735 #define TAMP_SR_ITAMP2F                     TAMP_SR_ITAMP2F_Msk
10736 #define TAMP_SR_ITAMP3F_Pos                 (18U)
10737 #define TAMP_SR_ITAMP3F_Msk                 (0x1UL << TAMP_SR_ITAMP3F_Pos)          /*!< 0x00040000 */
10738 #define TAMP_SR_ITAMP3F                     TAMP_SR_ITAMP3F_Msk
10739 #define TAMP_SR_ITAMP4F_Pos                 (19U)
10740 #define TAMP_SR_ITAMP4F_Msk                 (0x1UL << TAMP_SR_ITAMP4F_Pos)          /*!< 0x00080000 */
10741 #define TAMP_SR_ITAMP4F                     TAMP_SR_ITAMP4F_Msk
10742 #define TAMP_SR_ITAMP5F_Pos                 (20U)
10743 #define TAMP_SR_ITAMP5F_Msk                 (0x1UL << TAMP_SR_ITAMP5F_Pos)          /*!< 0x00100000 */
10744 #define TAMP_SR_ITAMP5F                     TAMP_SR_ITAMP5F_Msk
10745 #define TAMP_SR_ITAMP6F_Pos                 (21U)
10746 #define TAMP_SR_ITAMP6F_Msk                 (0x1UL << TAMP_SR_ITAMP6F_Pos)          /*!< 0x00200000 */
10747 #define TAMP_SR_ITAMP6F                     TAMP_SR_ITAMP6F_Msk
10748 #define TAMP_SR_ITAMP7F_Pos                 (22U)
10749 #define TAMP_SR_ITAMP7F_Msk                 (0x1UL << TAMP_SR_ITAMP7F_Pos)          /*!< 0x00400000 */
10750 #define TAMP_SR_ITAMP7F                     TAMP_SR_ITAMP7F_Msk
10751 #define TAMP_SR_ITAMP8F_Pos                 (23U)
10752 #define TAMP_SR_ITAMP8F_Msk                 (0x1UL << TAMP_SR_ITAMP8F_Pos)          /*!< 0x00800000 */
10753 #define TAMP_SR_ITAMP8F                     TAMP_SR_ITAMP8F_Msk
10754 #define TAMP_SR_ITAMP9F_Pos                 (24U)
10755 #define TAMP_SR_ITAMP9F_Msk                 (0x1UL << TAMP_SR_ITAMP9F_Pos)          /*!< 0x01000000 */
10756 #define TAMP_SR_ITAMP9F                     TAMP_SR_ITAMP9F_Msk
10757 #define TAMP_SR_ITAMP11F_Pos                (26U)
10758 #define TAMP_SR_ITAMP11F_Msk                (0x1UL << TAMP_SR_ITAMP11F_Pos)         /*!< 0x04000000 */
10759 #define TAMP_SR_ITAMP11F                    TAMP_SR_ITAMP11F_Msk
10760 #define TAMP_SR_ITAMP12F_Pos                (27U)
10761 #define TAMP_SR_ITAMP12F_Msk                (0x1UL << TAMP_SR_ITAMP12F_Pos)         /*!< 0x08000000 */
10762 #define TAMP_SR_ITAMP12F                    TAMP_SR_ITAMP12F_Msk
10763 #define TAMP_SR_ITAMP13F_Pos                (28U)
10764 #define TAMP_SR_ITAMP13F_Msk                (0x1UL << TAMP_SR_ITAMP13F_Pos)         /*!< 0x10000000 */
10765 #define TAMP_SR_ITAMP13F                    TAMP_SR_ITAMP13F_Msk
10766 #define TAMP_SR_ITAMP15F_Pos                (30U)
10767 #define TAMP_SR_ITAMP15F_Msk                (0x1UL << TAMP_SR_ITAMP15F_Pos)         /*!< 0x40000000 */
10768 #define TAMP_SR_ITAMP15F                    TAMP_SR_ITAMP15F_Msk
10769 
10770 /********************  Bits definition for TAMP_MISR register  ****************/
10771 #define TAMP_MISR_TAMP1MF_Pos               (0U)
10772 #define TAMP_MISR_TAMP1MF_Msk               (0x1UL << TAMP_MISR_TAMP1MF_Pos)        /*!< 0x00000001 */
10773 #define TAMP_MISR_TAMP1MF                   TAMP_MISR_TAMP1MF_Msk
10774 #define TAMP_MISR_TAMP2MF_Pos               (1U)
10775 #define TAMP_MISR_TAMP2MF_Msk               (0x1UL << TAMP_MISR_TAMP2MF_Pos)        /*!< 0x00000002 */
10776 #define TAMP_MISR_TAMP2MF                   TAMP_MISR_TAMP2MF_Msk
10777 #define TAMP_MISR_ITAMP1MF_Pos              (16U)
10778 #define TAMP_MISR_ITAMP1MF_Msk              (0x1UL << TAMP_MISR_ITAMP1MF_Pos)       /*!< 0x00010000 */
10779 #define TAMP_MISR_ITAMP1MF                  TAMP_MISR_ITAMP1MF_Msk
10780 #define TAMP_MISR_ITAMP2MF_Pos              (17U)
10781 #define TAMP_MISR_ITAMP2MF_Msk              (0x1UL << TAMP_MISR_ITAMP2MF_Pos)       /*!< 0x00020000 */
10782 #define TAMP_MISR_ITAMP2MF                  TAMP_MISR_ITAMP2MF_Msk
10783 #define TAMP_MISR_ITAMP3MF_Pos              (18U)
10784 #define TAMP_MISR_ITAMP3MF_Msk              (0x1UL << TAMP_MISR_ITAMP3MF_Pos)       /*!< 0x00040000 */
10785 #define TAMP_MISR_ITAMP3MF                  TAMP_MISR_ITAMP3MF_Msk
10786 #define TAMP_MISR_ITAMP4MF_Pos              (19U)
10787 #define TAMP_MISR_ITAMP4MF_Msk              (0x1UL << TAMP_MISR_ITAMP4MF_Pos)       /*!< 0x00080000 */
10788 #define TAMP_MISR_ITAMP4MF                  TAMP_MISR_ITAMP4MF_Msk
10789 #define TAMP_MISR_ITAMP5MF_Pos              (20U)
10790 #define TAMP_MISR_ITAMP5MF_Msk              (0x1UL << TAMP_MISR_ITAMP5MF_Pos)       /*!< 0x00100000 */
10791 #define TAMP_MISR_ITAMP5MF                  TAMP_MISR_ITAMP5MF_Msk
10792 #define TAMP_MISR_ITAMP6MF_Pos              (21U)
10793 #define TAMP_MISR_ITAMP6MF_Msk              (0x1UL << TAMP_MISR_ITAMP6MF_Pos)       /*!< 0x00200000 */
10794 #define TAMP_MISR_ITAMP6MF                  TAMP_MISR_ITAMP6MF_Msk
10795 #define TAMP_MISR_ITAMP7MF_Pos              (22U)
10796 #define TAMP_MISR_ITAMP7MF_Msk              (0x1UL << TAMP_MISR_ITAMP7MF_Pos)       /*!< 0x00400000 */
10797 #define TAMP_MISR_ITAMP7MF                  TAMP_MISR_ITAMP7MF_Msk
10798 #define TAMP_MISR_ITAMP8MF_Pos              (23U)
10799 #define TAMP_MISR_ITAMP8MF_Msk              (0x1UL << TAMP_MISR_ITAMP8MF_Pos)       /*!< 0x00800000 */
10800 #define TAMP_MISR_ITAMP8MF                  TAMP_MISR_ITAMP8MF_Msk
10801 #define TAMP_MISR_ITAMP9MF_Pos              (24U)
10802 #define TAMP_MISR_ITAMP9MF_Msk              (0x1UL << TAMP_MISR_ITAMP9MF_Pos)       /*!< 0x01000000 */
10803 #define TAMP_MISR_ITAMP9MF                  TAMP_MISR_ITAMP9MF_Msk
10804 #define TAMP_MISR_ITAMP11MF_Pos             (26U)
10805 #define TAMP_MISR_ITAMP11MF_Msk             (0x1UL << TAMP_MISR_ITAMP11MF_Pos)      /*!< 0x04000000 */
10806 #define TAMP_MISR_ITAMP11MF                 TAMP_MISR_ITAMP11MF_Msk
10807 #define TAMP_MISR_ITAMP12MF_Pos             (27U)
10808 #define TAMP_MISR_ITAMP12MF_Msk             (0x1UL << TAMP_MISR_ITAMP12MF_Pos)       /*!< 0x08000000 */
10809 #define TAMP_MISR_ITAMP12MF                 TAMP_MISR_ITAMP12MF_Msk
10810 #define TAMP_MISR_ITAMP13MF_Pos             (28U)
10811 #define TAMP_MISR_ITAMP13MF_Msk             (0x1UL << TAMP_MISR_ITAMP13MF_Pos)       /*!< 0x10000000 */
10812 #define TAMP_MISR_ITAMP13MF                 TAMP_MISR_ITAMP13MF_Msk
10813 #define TAMP_MISR_ITAMP15MF_Pos             (30U)
10814 #define TAMP_MISR_ITAMP15MF_Msk             (0x1UL << TAMP_MISR_ITAMP15MF_Pos)      /*!< 0x40000000 */
10815 #define TAMP_MISR_ITAMP15MF                 TAMP_MISR_ITAMP15MF_Msk
10816 
10817 
10818 /********************  Bits definition for TAMP_SCR register  *****************/
10819 #define TAMP_SCR_CTAMP1F_Pos                (0U)
10820 #define TAMP_SCR_CTAMP1F_Msk                (0x1UL << TAMP_SCR_CTAMP1F_Pos)         /*!< 0x00000001 */
10821 #define TAMP_SCR_CTAMP1F                    TAMP_SCR_CTAMP1F_Msk
10822 #define TAMP_SCR_CTAMP2F_Pos                (1U)
10823 #define TAMP_SCR_CTAMP2F_Msk                (0x1UL << TAMP_SCR_CTAMP2F_Pos)         /*!< 0x00000002 */
10824 #define TAMP_SCR_CTAMP2F                    TAMP_SCR_CTAMP2F_Msk
10825 #define TAMP_SCR_CITAMP1F_Pos               (16U)
10826 #define TAMP_SCR_CITAMP1F_Msk               (0x1UL << TAMP_SCR_CITAMP1F_Pos)        /*!< 0x00010000 */
10827 #define TAMP_SCR_CITAMP1F                   TAMP_SCR_CITAMP1F_Msk
10828 #define TAMP_SCR_CITAMP2F_Pos               (17U)
10829 #define TAMP_SCR_CITAMP2F_Msk               (0x1UL << TAMP_SCR_CITAMP2F_Pos)        /*!< 0x00020000 */
10830 #define TAMP_SCR_CITAMP2F                   TAMP_SCR_CITAMP2F_Msk
10831 #define TAMP_SCR_CITAMP3F_Pos               (18U)
10832 #define TAMP_SCR_CITAMP3F_Msk               (0x1UL << TAMP_SCR_CITAMP3F_Pos)        /*!< 0x00040000 */
10833 #define TAMP_SCR_CITAMP3F                   TAMP_SCR_CITAMP3F_Msk
10834 #define TAMP_SCR_CITAMP4F_Pos               (19U)
10835 #define TAMP_SCR_CITAMP4F_Msk               (0x1UL << TAMP_SCR_CITAMP4F_Pos)        /*!< 0x00080000 */
10836 #define TAMP_SCR_CITAMP4F                   TAMP_SCR_CITAMP4F_Msk
10837 #define TAMP_SCR_CITAMP5F_Pos               (20U)
10838 #define TAMP_SCR_CITAMP5F_Msk               (0x1UL << TAMP_SCR_CITAMP5F_Pos)        /*!< 0x00100000 */
10839 #define TAMP_SCR_CITAMP5F                   TAMP_SCR_CITAMP5F_Msk
10840 #define TAMP_SCR_CITAMP6F_Pos               (21U)
10841 #define TAMP_SCR_CITAMP6F_Msk               (0x1UL << TAMP_SCR_CITAMP6F_Pos)        /*!< 0x00200000 */
10842 #define TAMP_SCR_CITAMP6F                   TAMP_SCR_CITAMP6F_Msk
10843 #define TAMP_SCR_CITAMP7F_Pos               (22U)
10844 #define TAMP_SCR_CITAMP7F_Msk               (0x1UL << TAMP_SCR_CITAMP7F_Pos)        /*!< 0x00400000 */
10845 #define TAMP_SCR_CITAMP7F                   TAMP_SCR_CITAMP7F_Msk
10846 #define TAMP_SCR_CITAMP8F_Pos               (23U)
10847 #define TAMP_SCR_CITAMP8F_Msk               (0x1UL << TAMP_SCR_CITAMP8F_Pos)        /*!< 0x00800000 */
10848 #define TAMP_SCR_CITAMP8F                   TAMP_SCR_CITAMP8F_Msk
10849 #define TAMP_SCR_CITAMP9F_Pos               (24U)
10850 #define TAMP_SCR_CITAMP9F_Msk               (0x1UL << TAMP_SCR_CITAMP9F_Pos)        /*!< 0x00100000 */
10851 #define TAMP_SCR_CITAMP9F                   TAMP_SCR_CITAMP9F_Msk
10852 #define TAMP_SCR_CITAMP11F_Pos              (26U)
10853 #define TAMP_SCR_CITAMP11F_Msk              (0x1UL << TAMP_SCR_CITAMP11F_Pos)       /*!< 0x00400000 */
10854 #define TAMP_SCR_CITAMP11F                  TAMP_SCR_CITAMP11F_Msk
10855 #define TAMP_SCR_CITAMP12F_Pos              (27U)
10856 #define TAMP_SCR_CITAMP12F_Msk              (0x1UL << TAMP_SCR_CITAMP12F_Pos)       /*!< 0x08000000 */
10857 #define TAMP_SCR_CITAMP12F                  TAMP_SCR_CITAMP12F_Msk
10858 #define TAMP_SCR_CITAMP13F_Pos              (28U)
10859 #define TAMP_SCR_CITAMP13F_Msk              (0x1UL << TAMP_SCR_CITAMP13F_Pos)       /*!< 0x10000000 */
10860 #define TAMP_SCR_CITAMP13F                  TAMP_SCR_CITAMP13F_Msk
10861 #define TAMP_SCR_CITAMP15F_Pos              (30U)
10862 #define TAMP_SCR_CITAMP15F_Msk              (0x1UL << TAMP_SCR_CITAMP15F_Pos)       /*!< 0x40000000 */
10863 #define TAMP_SCR_CITAMP15F                  TAMP_SCR_CITAMP15F_Msk
10864 /********************  Bits definition for TAMP_COUNT1R register  ***************/
10865 #define TAMP_COUNT1R_COUNT_Pos              (0U)
10866 #define TAMP_COUNT1R_COUNT_Msk              (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
10867 #define TAMP_COUNT1R_COUNT                  TAMP_COUNT1R_COUNT_Msk
10868 
10869 
10870 /********************  Bits definition for TAMP_ERCFG register  ***************/
10871 #define TAMP_ERCFGR_ERCFG0_Pos              (0U)
10872 #define TAMP_ERCFGR_ERCFG0_Msk              (0x1UL << TAMP_ERCFGR_ERCFG0_Pos)         /*!< 0x00000001 */
10873 #define TAMP_ERCFGR_ERCFG0                  TAMP_ERCFGR_ERCFG0_Msk
10874 
10875 /********************  Bits definition for TAMP_BKP0R register  ***************/
10876 #define TAMP_BKP0R_Pos                      (0U)
10877 #define TAMP_BKP0R_Msk                      (0xFFFFFFFFUL << TAMP_BKP0R_Pos)        /*!< 0xFFFFFFFF */
10878 #define TAMP_BKP0R                          TAMP_BKP0R_Msk
10879 
10880 /********************  Bits definition for TAMP_BKP1R register  ****************/
10881 #define TAMP_BKP1R_Pos                      (0U)
10882 #define TAMP_BKP1R_Msk                      (0xFFFFFFFFUL << TAMP_BKP1R_Pos)        /*!< 0xFFFFFFFF */
10883 #define TAMP_BKP1R                          TAMP_BKP1R_Msk
10884 
10885 /********************  Bits definition for TAMP_BKP2R register  ****************/
10886 #define TAMP_BKP2R_Pos                      (0U)
10887 #define TAMP_BKP2R_Msk                      (0xFFFFFFFFUL << TAMP_BKP2R_Pos)        /*!< 0xFFFFFFFF */
10888 #define TAMP_BKP2R                          TAMP_BKP2R_Msk
10889 
10890 /********************  Bits definition for TAMP_BKP3R register  ****************/
10891 #define TAMP_BKP3R_Pos                      (0U)
10892 #define TAMP_BKP3R_Msk                      (0xFFFFFFFFUL << TAMP_BKP3R_Pos)        /*!< 0xFFFFFFFF */
10893 #define TAMP_BKP3R                          TAMP_BKP3R_Msk
10894 
10895 /********************  Bits definition for TAMP_BKP4R register  ****************/
10896 #define TAMP_BKP4R_Pos                      (0U)
10897 #define TAMP_BKP4R_Msk                      (0xFFFFFFFFUL << TAMP_BKP4R_Pos)        /*!< 0xFFFFFFFF */
10898 #define TAMP_BKP4R                          TAMP_BKP4R_Msk
10899 
10900 /********************  Bits definition for TAMP_BKP5R register  ****************/
10901 #define TAMP_BKP5R_Pos                      (0U)
10902 #define TAMP_BKP5R_Msk                      (0xFFFFFFFFUL << TAMP_BKP5R_Pos)        /*!< 0xFFFFFFFF */
10903 #define TAMP_BKP5R                          TAMP_BKP5R_Msk
10904 
10905 /********************  Bits definition for TAMP_BKP6R register  ****************/
10906 #define TAMP_BKP6R_Pos                      (0U)
10907 #define TAMP_BKP6R_Msk                      (0xFFFFFFFFUL << TAMP_BKP6R_Pos)        /*!< 0xFFFFFFFF */
10908 #define TAMP_BKP6R                          TAMP_BKP6R_Msk
10909 
10910 /********************  Bits definition for TAMP_BKP7R register  ****************/
10911 #define TAMP_BKP7R_Pos                      (0U)
10912 #define TAMP_BKP7R_Msk                      (0xFFFFFFFFUL << TAMP_BKP7R_Pos)        /*!< 0xFFFFFFFF */
10913 #define TAMP_BKP7R                          TAMP_BKP7R_Msk
10914 
10915 /********************  Bits definition for TAMP_BKP8R register  ****************/
10916 #define TAMP_BKP8R_Pos                      (0U)
10917 #define TAMP_BKP8R_Msk                      (0xFFFFFFFFUL << TAMP_BKP8R_Pos)        /*!< 0xFFFFFFFF */
10918 #define TAMP_BKP8R                          TAMP_BKP8R_Msk
10919 
10920 /********************  Bits definition for TAMP_BKP9R register  ****************/
10921 #define TAMP_BKP9R_Pos                      (0U)
10922 #define TAMP_BKP9R_Msk                      (0xFFFFFFFFUL << TAMP_BKP9R_Pos)        /*!< 0xFFFFFFFF */
10923 #define TAMP_BKP9R                          TAMP_BKP9R_Msk
10924 
10925 /********************  Bits definition for TAMP_BKP10R register  ***************/
10926 #define TAMP_BKP10R_Pos                     (0U)
10927 #define TAMP_BKP10R_Msk                     (0xFFFFFFFFUL << TAMP_BKP10R_Pos)       /*!< 0xFFFFFFFF */
10928 #define TAMP_BKP10R                         TAMP_BKP10R_Msk
10929 
10930 /********************  Bits definition for TAMP_BKP11R register  ***************/
10931 #define TAMP_BKP11R_Pos                     (0U)
10932 #define TAMP_BKP11R_Msk                     (0xFFFFFFFFUL << TAMP_BKP11R_Pos)       /*!< 0xFFFFFFFF */
10933 #define TAMP_BKP11R                         TAMP_BKP11R_Msk
10934 
10935 /********************  Bits definition for TAMP_BKP12R register  ***************/
10936 #define TAMP_BKP12R_Pos                     (0U)
10937 #define TAMP_BKP12R_Msk                     (0xFFFFFFFFUL << TAMP_BKP12R_Pos)       /*!< 0xFFFFFFFF */
10938 #define TAMP_BKP12R                         TAMP_BKP12R_Msk
10939 
10940 /********************  Bits definition for TAMP_BKP13R register  ***************/
10941 #define TAMP_BKP13R_Pos                     (0U)
10942 #define TAMP_BKP13R_Msk                     (0xFFFFFFFFUL << TAMP_BKP13R_Pos)       /*!< 0xFFFFFFFF */
10943 #define TAMP_BKP13R                         TAMP_BKP13R_Msk
10944 
10945 /********************  Bits definition for TAMP_BKP14R register  ***************/
10946 #define TAMP_BKP14R_Pos                     (0U)
10947 #define TAMP_BKP14R_Msk                     (0xFFFFFFFFUL << TAMP_BKP14R_Pos)       /*!< 0xFFFFFFFF */
10948 #define TAMP_BKP14R                         TAMP_BKP14R_Msk
10949 
10950 /********************  Bits definition for TAMP_BKP15R register  ***************/
10951 #define TAMP_BKP15R_Pos                     (0U)
10952 #define TAMP_BKP15R_Msk                     (0xFFFFFFFFUL << TAMP_BKP15R_Pos)       /*!< 0xFFFFFFFF */
10953 #define TAMP_BKP15R                         TAMP_BKP15R_Msk
10954 
10955 /********************  Bits definition for TAMP_BKP16R register  ***************/
10956 #define TAMP_BKP16R_Pos                     (0U)
10957 #define TAMP_BKP16R_Msk                     (0xFFFFFFFFUL << TAMP_BKP16R_Pos)       /*!< 0xFFFFFFFF */
10958 #define TAMP_BKP16R                         TAMP_BKP16R_Msk
10959 
10960 /********************  Bits definition for TAMP_BKP17R register  ***************/
10961 #define TAMP_BKP17R_Pos                     (0U)
10962 #define TAMP_BKP17R_Msk                     (0xFFFFFFFFUL << TAMP_BKP17R_Pos)       /*!< 0xFFFFFFFF */
10963 #define TAMP_BKP17R                         TAMP_BKP17R_Msk
10964 
10965 /********************  Bits definition for TAMP_BKP18R register  ***************/
10966 #define TAMP_BKP18R_Pos                     (0U)
10967 #define TAMP_BKP18R_Msk                     (0xFFFFFFFFUL << TAMP_BKP18R_Pos)       /*!< 0xFFFFFFFF */
10968 #define TAMP_BKP18R                         TAMP_BKP18R_Msk
10969 
10970 /********************  Bits definition for TAMP_BKP19R register  ***************/
10971 #define TAMP_BKP19R_Pos                     (0U)
10972 #define TAMP_BKP19R_Msk                     (0xFFFFFFFFUL << TAMP_BKP19R_Pos)       /*!< 0xFFFFFFFF */
10973 #define TAMP_BKP19R                         TAMP_BKP19R_Msk
10974 
10975 /********************  Bits definition for TAMP_BKP20R register  ***************/
10976 #define TAMP_BKP20R_Pos                     (0U)
10977 #define TAMP_BKP20R_Msk                     (0xFFFFFFFFUL << TAMP_BKP20R_Pos)       /*!< 0xFFFFFFFF */
10978 #define TAMP_BKP20R                         TAMP_BKP20R_Msk
10979 
10980 /********************  Bits definition for TAMP_BKP21R register  ***************/
10981 #define TAMP_BKP21R_Pos                     (0U)
10982 #define TAMP_BKP21R_Msk                     (0xFFFFFFFFUL << TAMP_BKP21R_Pos)       /*!< 0xFFFFFFFF */
10983 #define TAMP_BKP21R                         TAMP_BKP21R_Msk
10984 
10985 /********************  Bits definition for TAMP_BKP22R register  ***************/
10986 #define TAMP_BKP22R_Pos                     (0U)
10987 #define TAMP_BKP22R_Msk                     (0xFFFFFFFFUL << TAMP_BKP22R_Pos)       /*!< 0xFFFFFFFF */
10988 #define TAMP_BKP22R                         TAMP_BKP22R_Msk
10989 
10990 /********************  Bits definition for TAMP_BKP23R register  ***************/
10991 #define TAMP_BKP23R_Pos                     (0U)
10992 #define TAMP_BKP23R_Msk                     (0xFFFFFFFFUL << TAMP_BKP23R_Pos)       /*!< 0xFFFFFFFF */
10993 #define TAMP_BKP23R                         TAMP_BKP23R_Msk
10994 
10995 /********************  Bits definition for TAMP_BKP24R register  ***************/
10996 #define TAMP_BKP24R_Pos                     (0U)
10997 #define TAMP_BKP24R_Msk                     (0xFFFFFFFFUL << TAMP_BKP24R_Pos)       /*!< 0xFFFFFFFF */
10998 #define TAMP_BKP24R                         TAMP_BKP24R_Msk
10999 
11000 /********************  Bits definition for TAMP_BKP25R register  ***************/
11001 #define TAMP_BKP25R_Pos                     (0U)
11002 #define TAMP_BKP25R_Msk                     (0xFFFFFFFFUL << TAMP_BKP25R_Pos)       /*!< 0xFFFFFFFF */
11003 #define TAMP_BKP25R                         TAMP_BKP25R_Msk
11004 
11005 /********************  Bits definition for TAMP_BKP26R register  ***************/
11006 #define TAMP_BKP26R_Pos                     (0U)
11007 #define TAMP_BKP26R_Msk                     (0xFFFFFFFFUL << TAMP_BKP26R_Pos)       /*!< 0xFFFFFFFF */
11008 #define TAMP_BKP26R                         TAMP_BKP26R_Msk
11009 
11010 /********************  Bits definition for TAMP_BKP27R register  ***************/
11011 #define TAMP_BKP27R_Pos                     (0U)
11012 #define TAMP_BKP27R_Msk                     (0xFFFFFFFFUL << TAMP_BKP27R_Pos)       /*!< 0xFFFFFFFF */
11013 #define TAMP_BKP27R                         TAMP_BKP27R_Msk
11014 
11015 /********************  Bits definition for TAMP_BKP28R register  ***************/
11016 #define TAMP_BKP28R_Pos                     (0U)
11017 #define TAMP_BKP28R_Msk                     (0xFFFFFFFFUL << TAMP_BKP28R_Pos)       /*!< 0xFFFFFFFF */
11018 #define TAMP_BKP28R                         TAMP_BKP28R_Msk
11019 
11020 /********************  Bits definition for TAMP_BKP29R register  ***************/
11021 #define TAMP_BKP29R_Pos                     (0U)
11022 #define TAMP_BKP29R_Msk                     (0xFFFFFFFFUL << TAMP_BKP29R_Pos)       /*!< 0xFFFFFFFF */
11023 #define TAMP_BKP29R                         TAMP_BKP29R_Msk
11024 
11025 /********************  Bits definition for TAMP_BKP30R register  ***************/
11026 #define TAMP_BKP30R_Pos                     (0U)
11027 #define TAMP_BKP30R_Msk                     (0xFFFFFFFFUL << TAMP_BKP30R_Pos)       /*!< 0xFFFFFFFF */
11028 #define TAMP_BKP30R                         TAMP_BKP30R_Msk
11029 
11030 /********************  Bits definition for TAMP_BKP31R register  ***************/
11031 #define TAMP_BKP31R_Pos                     (0U)
11032 #define TAMP_BKP31R_Msk                     (0xFFFFFFFFUL << TAMP_BKP31R_Pos)       /*!< 0xFFFFFFFF */
11033 #define TAMP_BKP31R                         TAMP_BKP31R_Msk
11034 
11035 /******************************************************************************/
11036 /*                                                                            */
11037 /*                                 SBS                                        */
11038 /*                                                                            */
11039 /******************************************************************************/
11040 /********************  Bit definition for SBS_HDPLCR register  *****************/
11041 #define SBS_HDPLCR_INCR_HDPL_Pos            (0U)
11042 #define SBS_HDPLCR_INCR_HDPL_Msk            (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos)     /*!< 0x000000FF */
11043 #define SBS_HDPLCR_INCR_HDPL                SBS_HDPLCR_INCR_HDPL_Msk                 /*!< Increment HDPL value. */
11044 
11045 /********************  Bit definition for SBS_HDPLSR register  *****************/
11046 #define SBS_HDPLSR_HDPL_Pos                 (0U)
11047 #define SBS_HDPLSR_HDPL_Msk                 (0xFFUL << SBS_HDPLSR_HDPL_Pos)          /*!< 0x000000FF */
11048 #define SBS_HDPLSR_HDPL                     SBS_HDPLSR_HDPL_Msk                      /*!< HDPL value. */
11049 
11050 /********************  Bit definition for SBS_DBGCR register  *****************/
11051 #define SBS_DBGCR_AP_UNLOCK_Pos           (0U)
11052 #define SBS_DBGCR_AP_UNLOCK_Msk           (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos)    /*!< 0x000000FF */
11053 #define SBS_DBGCR_AP_UNLOCK               SBS_DBGCR_AP_UNLOCK_Msk                /*!< Open the Access Port. */
11054 
11055 #define SBS_DBGCR_DBG_UNLOCK_Pos          (8U)
11056 #define SBS_DBGCR_DBG_UNLOCK_Msk          (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos)   /*!< 0x0000FF00 */
11057 #define SBS_DBGCR_DBG_UNLOCK              SBS_DBGCR_DBG_UNLOCK_Msk               /*!< Open the debug when DBG_AUTH_HDPL is reached. */
11058 
11059 #define SBS_DBGCR_DBG_AUTH_HDPL_Pos       (16U)
11060 #define SBS_DBGCR_DBG_AUTH_HDPL_Msk       (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */
11061 #define SBS_DBGCR_DBG_AUTH_HDPL           SBS_DBGCR_DBG_AUTH_HDPL_Msk             /*!< HDPL value when the debug should be effectively opened. */
11062 
11063 /********************  Bit definition for SBS_DBGLCKR register  *****************/
11064 #define SBS_DBGLOCKR_DBGCFG_LOCK_Pos      (0U)
11065 #define SBS_DBGLOCKR_DBGCFG_LOCK_Msk      (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */
11066 #define SBS_DBGLOCKR_DBGCFG_LOCK          SBS_DBGLOCKR_DBGCFG_LOCK_Msk             /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */
11067 
11068 /******************  Bit definition for SBS_PMCR register  ****************/
11069 #define SBS_PMCR_PB6_FMP_Pos              (16U)
11070 #define SBS_PMCR_PB6_FMP_Msk              (0x1UL << SBS_PMCR_PB6_FMP_Pos)            /*!< 0x00010000 */
11071 #define SBS_PMCR_PB6_FMP                  SBS_PMCR_PB6_FMP_Msk                       /*!< Fast-mode Plus command on PB(6) */
11072 #define SBS_PMCR_PB7_FMP_Pos              (17U)
11073 #define SBS_PMCR_PB7_FMP_Msk              (0x1UL << SBS_PMCR_PB7_FMP_Pos)            /*!< 0x00020000 */
11074 #define SBS_PMCR_PB7_FMP                  SBS_PMCR_PB7_FMP_Msk                       /*!< Fast-mode Plus command on PB(7) */
11075 #define SBS_PMCR_PB8_FMP_Pos              (18U)
11076 #define SBS_PMCR_PB8_FMP_Msk              (0x1UL << SBS_PMCR_PB8_FMP_Pos)            /*!< 0x00040000 */
11077 #define SBS_PMCR_PB8_FMP                  SBS_PMCR_PB8_FMP_Msk                       /*!< Fast-mode Plus command on PB(8) */
11078 
11079 /******************  Bit definition for SBS_FPUIMR register  ***************/
11080 #define SBS_FPUIMR_FPU_IE_Pos            (0U)
11081 #define SBS_FPUIMR_FPU_IE_Msk            (0x3FUL << SBS_FPUIMR_FPU_IE_Pos)           /*!< 0x0000003F - */
11082 #define SBS_FPUIMR_FPU_IE                SBS_FPUIMR_FPU_IE_Msk                       /*!<  All FPU interrupts enable */
11083 #define SBS_FPUIMR_FPU_IE_0              (0x1UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000001 - Invalid operation Interrupt enable */
11084 #define SBS_FPUIMR_FPU_IE_1              (0x2UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000002 - Divide-by-zero Interrupt enable */
11085 #define SBS_FPUIMR_FPU_IE_2              (0x4UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000004 - Underflow Interrupt enable */
11086 #define SBS_FPUIMR_FPU_IE_3              (0x8UL << SBS_FPUIMR_FPU_IE_Pos)            /*!< 0x00000008 - Overflow Interrupt enable */
11087 #define SBS_FPUIMR_FPU_IE_4              (0x10UL << SBS_FPUIMR_FPU_IE_Pos)           /*!< 0x00000010 - Input denormal Interrupt enable */
11088 #define SBS_FPUIMR_FPU_IE_5              (0x20UL << SBS_FPUIMR_FPU_IE_Pos)           /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */
11089 
11090 /******************  Bit definition for SBS_MESR register  ****************/
11091 #define SBS_MESR_MCLR_Pos                (0U)
11092 #define SBS_MESR_MCLR_Msk                (0x1UL << SBS_MESR_MCLR_Pos)         /*!< 0x00000001 */
11093 #define SBS_MESR_MCLR                    SBS_MESR_MCLR_Msk                    /*!< Status of Erase after Reset */
11094 #define SBS_MESR_IPMEE_Pos               (16U)
11095 #define SBS_MESR_IPMEE_Msk               (0x1UL << SBS_MESR_IPMEE_Pos)        /*!< 0x00010000 */
11096 #define SBS_MESR_IPMEE                   SBS_MESR_IPMEE_Msk                   /*!< Status of End of Erase for ICache and PKA RAMs */
11097 
11098 /******************  Bit definition for SBS_CCCSR register  ****************/
11099 #define SBS_CCCSR_EN1_Pos                (0U)
11100 #define SBS_CCCSR_EN1_Msk                (0x1UL << SBS_CCCSR_EN1_Pos)         /*!< 0x00000001 */
11101 #define SBS_CCCSR_EN1                    SBS_CCCSR_EN1_Msk                    /*!< Enable compensation cell for VDD power rail */
11102 #define SBS_CCCSR_CS1_Pos                (1U)
11103 #define SBS_CCCSR_CS1_Msk                (0x1UL << SBS_CCCSR_CS1_Pos)         /*!< 0x00000002 */
11104 #define SBS_CCCSR_CS1                    SBS_CCCSR_CS1_Msk                    /*!< Code selection for VDD power rail */
11105 #define SBS_CCCSR_EN2_Pos                (2U)
11106 #define SBS_CCCSR_EN2_Msk                (0x1UL << SBS_CCCSR_EN2_Pos)         /*!< 0x00000004 */
11107 #define SBS_CCCSR_EN2                    SBS_CCCSR_EN2_Msk                    /*!< Enable compensation cell for VDDIO power rail */
11108 #define SBS_CCCSR_CS2_Pos                (3U)
11109 #define SBS_CCCSR_CS2_Msk                (0x1UL << SBS_CCCSR_CS2_Pos)         /*!< 0x00000008 */
11110 #define SBS_CCCSR_CS2                    SBS_CCCSR_CS2_Msk                    /*!< Code selection for VDDIO power rail */
11111 #define SBS_CCCSR_RDY1_Pos               (8U)
11112 #define SBS_CCCSR_RDY1_Msk               (0x1UL << SBS_CCCSR_RDY1_Pos)        /*!< 0x00000100 */
11113 #define SBS_CCCSR_RDY1                   SBS_CCCSR_RDY1_Msk                   /*!< VDD compensation cell ready flag */
11114 #define SBS_CCCSR_RDY2_Pos               (9U)
11115 #define SBS_CCCSR_RDY2_Msk               (0x1UL << SBS_CCCSR_RDY2_Pos)        /*!< 0x00000200 */
11116 #define SBS_CCCSR_RDY2                   SBS_CCCSR_RDY2_Msk                   /*!< VDDIO compensation cell ready flag */
11117 
11118 /******************  Bit definition for SBS_CCVALR register  ****************/
11119 #define SBS_CCVALR_ANSRC1_Pos            (0U)
11120 #define SBS_CCVALR_ANSRC1_Msk            (0xFUL << SBS_CCVALR_ANSRC1_Pos)     /*!< 0x0000000F */
11121 #define SBS_CCVALR_ANSRC1                SBS_CCVALR_ANSRC1_Msk                /*!< NMOS compensation value */
11122 #define SBS_CCVALR_APSRC1_Pos            (4U)
11123 #define SBS_CCVALR_APSRC1_Msk            (0xFUL << SBS_CCVALR_APSRC1_Pos)     /*!< 0x000000F0 */
11124 #define SBS_CCVALR_APSRC1                SBS_CCVALR_APSRC1_Msk                /*!< PMOS compensation value */
11125 #define SBS_CCVALR_ANSRC2_Pos            (8U)
11126 #define SBS_CCVALR_ANSRC2_Msk            (0xFUL << SBS_CCVALR_ANSRC2_Pos)     /*!< 0x00000F00 */
11127 #define SBS_CCVALR_ANSRC2                SBS_CCVALR_ANSRC2_Msk                /*!< NMOS compensation value */
11128 #define SBS_CCVALR_APSRC2_Pos            (12U)
11129 #define SBS_CCVALR_APSRC2_Msk            (0xFUL << SBS_CCVALR_APSRC2_Pos)     /*!< 0x0000F000 */
11130 #define SBS_CCVALR_APSRC2                SBS_CCVALR_APSRC2_Msk                /*!< PMOS compensation value */
11131 
11132 /******************  Bit definition for SBS_CCSWCR register  ****************/
11133 #define SBS_CCSWCR_SW_ANSRC1_Pos         (0U)
11134 #define SBS_CCSWCR_SW_ANSRC1_Msk         (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos)  /*!< 0x0000000F */
11135 #define SBS_CCSWCR_SW_ANSRC1             SBS_CCSWCR_SW_ANSRC1_Msk             /*!< NMOS compensation code for VDD Power Rail */
11136 #define SBS_CCSWCR_SW_APSRC1_Pos         (4U)
11137 #define SBS_CCSWCR_SW_APSRC1_Msk         (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos)  /*!< 0x000000F0 */
11138 #define SBS_CCSWCR_SW_APSRC1             SBS_CCSWCR_SW_APSRC1_Msk             /*!< PMOS compensation code for VDD Power Rail */
11139 #define SBS_CCSWCR_SW_ANSRC2_Pos         (8U)
11140 #define SBS_CCSWCR_SW_ANSRC2_Msk         (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos)  /*!< 0x00000F00 */
11141 #define SBS_CCSWCR_SW_ANSRC2             SBS_CCSWCR_SW_ANSRC2_Msk             /*!< NMOS compensation code for VDDIO Power Rail */
11142 #define SBS_CCSWCR_SW_APSRC2_Pos         (12U)
11143 #define SBS_CCSWCR_SW_APSRC2_Msk         (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos)  /*!< 0x0000F000 */
11144 #define SBS_CCSWCR_SW_APSRC2             SBS_CCSWCR_SW_APSRC2_Msk             /*!< PMOS compensation code for VDDIO Power Rail */
11145 
11146 /******************  Bit definition for SBS_CFGR2 register  ****************/
11147 #define SBS_CFGR2_CLL_Pos                (0U)
11148 #define SBS_CFGR2_CLL_Msk                (0x1UL << SBS_CFGR2_CLL_Pos)   /*!< 0x00000001 */
11149 #define SBS_CFGR2_CLL                    SBS_CFGR2_CLL_Msk              /*!< Core Lockup Lock */
11150 #define SBS_CFGR2_SEL_Pos                (1U)
11151 #define SBS_CFGR2_SEL_Msk                (0x1UL << SBS_CFGR2_SEL_Pos)   /*!< 0x00000002 */
11152 #define SBS_CFGR2_SEL                    SBS_CFGR2_SEL_Msk              /*!< SRAM ECC Lock */
11153 #define SBS_CFGR2_PVDL_Pos               (2U)
11154 #define SBS_CFGR2_PVDL_Msk               (0x1UL << SBS_CFGR2_PVDL_Pos)  /*!< 0x00000004 */
11155 #define SBS_CFGR2_PVDL                   SBS_CFGR2_PVDL_Msk             /*!<  PVD Lock */
11156 #define SBS_CFGR2_ECCL_Pos               (3U)
11157 #define SBS_CFGR2_ECCL_Msk               (0x1UL << SBS_CFGR2_ECCL_Pos)  /*!< 0x00000008 */
11158 #define SBS_CFGR2_ECCL                   SBS_CFGR2_ECCL_Msk             /*!< Flash ECC Lock*/
11159 
11160 /******************  Bit definition for SBS_CNSLCKR register  **************/
11161 #define SBS_CNSLCKR_LOCKNSVTOR_Pos       (0U)
11162 #define SBS_CNSLCKR_LOCKNSVTOR_Msk       (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */
11163 #define SBS_CNSLCKR_LOCKNSVTOR           SBS_CNSLCKR_LOCKNSVTOR_Msk            /*!< Disable VTOR_NS register writes by SW or debug agent */
11164 #define SBS_CNSLCKR_LOCKNSMPU_Pos        (1U)
11165 #define SBS_CNSLCKR_LOCKNSMPU_Msk        (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos)  /*!< 0x00000002 */
11166 #define SBS_CNSLCKR_LOCKNSMPU            SBS_CNSLCKR_LOCKNSMPU_Msk             /*!< Disable Non-Secure MPU registers writes by SW or debug agent */
11167 
11168 /******************  Bit definition for SBS_ECCNMIR register  ***************/
11169 #define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos   (0U)
11170 #define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk   (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos)   /*!< 0x00000001 */
11171 #define SBS_ECCNMIR_ECCNMI_MASK_EN       SBS_ECCNMIR_ECCNMI_MASK_EN_Msk              /*!< Disable NMI in case of double ECC error in flash interface */
11172 
11173 /*****************************************************************************/
11174 /*                                                                           */
11175 /*                        Global TrustZone Control                           */
11176 /*                                                                           */
11177 /*****************************************************************************/
11178 
11179 /*******************  Bits definition for GTZC_TZSC_MPCWM_CFGR register  **********/
11180 #define GTZC_TZSC_MPCWM_CFGR_SREN_Pos       (0U)
11181 #define GTZC_TZSC_MPCWM_CFGR_SREN_Msk       (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos)
11182 #define GTZC_TZSC_MPCWM_CFGR_SREN           GTZC_TZSC_MPCWM_CFGR_SREN_Msk
11183 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos     (1U)
11184 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk     (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos)
11185 #define GTZC_TZSC_MPCWM_CFGR_SRLOCK         GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk
11186 #define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos       (9U)
11187 #define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk       (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos)
11188 #define GTZC_TZSC_MPCWM_CFGR_PRIV           GTZC_TZSC_MPCWM_CFGR_PRIV_Msk
11189 
11190 /*******************  Bits definition for GTZC_TZSC_MPCWMR register  **************/
11191 #define GTZC_TZSC_MPCWMR_SUBZ_START_Pos     (0U)
11192 #define GTZC_TZSC_MPCWMR_SUBZ_START_Msk     (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos)
11193 #define GTZC_TZSC_MPCWMR_SUBZ_START         GTZC_TZSC_MPCWMR_SUBZ_START_Msk
11194 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos    (16U)
11195 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk    (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos)
11196 #define GTZC_TZSC_MPCWMR_SUBZ_LENGTH        GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk
11197 
11198 /*******  Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers  *****/
11199 /*******  Bits definition for TZIC _IERx/_SRx/_IFCRx registers  ********/
11200 
11201 /***************  Bits definition for register x=1 (TZSC1) *************/
11202 #define GTZC_CFGR1_TIM2_Pos                 (0U)
11203 #define GTZC_CFGR1_TIM2_Msk                 (0x01UL << GTZC_CFGR1_TIM2_Pos)
11204 #define GTZC_CFGR1_TIM3_Pos                 (1U)
11205 #define GTZC_CFGR1_TIM3_Msk                 (0x01UL << GTZC_CFGR1_TIM3_Pos)
11206 #define GTZC_CFGR1_TIM6_Pos                 (4U)
11207 #define GTZC_CFGR1_TIM6_Msk                 (0x01UL << GTZC_CFGR1_TIM6_Pos)
11208 #define GTZC_CFGR1_TIM7_Pos                 (5U)
11209 #define GTZC_CFGR1_TIM7_Msk                 (0x01UL << GTZC_CFGR1_TIM7_Pos)
11210 #define GTZC_CFGR1_WWDG_Pos                 (9U)
11211 #define GTZC_CFGR1_WWDG_Msk                 (0x01UL << GTZC_CFGR1_WWDG_Pos)
11212 #define GTZC_CFGR1_IWDG_Pos                 (10U)
11213 #define GTZC_CFGR1_IWDG_Msk                 (0x01UL << GTZC_CFGR1_IWDG_Pos)
11214 #define GTZC_CFGR1_SPI2_Pos                 (11U)
11215 #define GTZC_CFGR1_SPI2_Msk                 (0x01UL << GTZC_CFGR1_SPI2_Pos)
11216 #define GTZC_CFGR1_SPI3_Pos                 (12U)
11217 #define GTZC_CFGR1_SPI3_Msk                 (0x01UL << GTZC_CFGR1_SPI3_Pos)
11218 #define GTZC_CFGR1_USART2_Pos               (13U)
11219 #define GTZC_CFGR1_USART2_Msk               (0x01UL << GTZC_CFGR1_USART2_Pos)
11220 #define GTZC_CFGR1_USART3_Pos               (14U)
11221 #define GTZC_CFGR1_USART3_Msk               (0x01UL << GTZC_CFGR1_USART3_Pos)
11222 #define GTZC_CFGR1_I2C1_Pos                 (17U)
11223 #define GTZC_CFGR1_I2C1_Msk                 (0x01UL << GTZC_CFGR1_I2C1_Pos)
11224 #define GTZC_CFGR1_I2C2_Pos                 (18U)
11225 #define GTZC_CFGR1_I2C2_Msk                 (0x01UL << GTZC_CFGR1_I2C2_Pos)
11226 #define GTZC_CFGR1_I3C1_Pos                 (19U)
11227 #define GTZC_CFGR1_I3C1_Msk                 (0x01UL << GTZC_CFGR1_I3C1_Pos)
11228 #define GTZC_CFGR1_CRS_Pos                  (20U)
11229 #define GTZC_CFGR1_CRS_Msk                  (0x01UL << GTZC_CFGR1_CRS_Pos)
11230 #define GTZC_CFGR1_DAC1_Pos                 (25U)
11231 #define GTZC_CFGR1_DAC1_Msk                 (0x01UL << GTZC_CFGR1_DAC1_Pos)
11232 #define GTZC_CFGR1_DTS_Pos                  (30U)
11233 #define GTZC_CFGR1_DTS_Msk                  (0x01UL << GTZC_CFGR1_DTS_Pos)
11234 #define GTZC_CFGR1_LPTIM2_Pos               (31U)
11235 #define GTZC_CFGR1_LPTIM2_Msk               (0x01UL << GTZC_CFGR1_LPTIM2_Pos)
11236 
11237 
11238 /***************  Bits definition for register x=2 (TZSC1) *************/
11239 #define GTZC_CFGR2_FDCAN1_Pos               (0U)
11240 #define GTZC_CFGR2_FDCAN1_Msk               (0x01UL << GTZC_CFGR2_FDCAN1_Pos)
11241 #define GTZC_CFGR2_OPAMP_Pos                (3U)
11242 #define GTZC_CFGR2_OPAMP_Msk                (0x01UL << GTZC_CFGR2_OPAMP_Pos)
11243 #define GTZC_CFGR2_COMP_Pos                 (4U)
11244 #define GTZC_CFGR2_COMP_Msk                 (0x01UL << GTZC_CFGR2_COMP_Pos)
11245 #define GTZC_CFGR2_TIM1_Pos                 (8U)
11246 #define GTZC_CFGR2_TIM1_Msk                 (0x01UL << GTZC_CFGR2_TIM1_Pos)
11247 #define GTZC_CFGR2_SPI1_Pos                 (9U)
11248 #define GTZC_CFGR2_SPI1_Msk                 (0x01UL << GTZC_CFGR2_SPI1_Pos)
11249 #define GTZC_CFGR2_USART1_Pos               (11U)
11250 #define GTZC_CFGR2_USART1_Msk               (0x01UL << GTZC_CFGR2_USART1_Pos)
11251 #define GTZC_CFGR2_USB_Pos                  (19U)
11252 #define GTZC_CFGR2_USB_Msk                  (0x01UL << GTZC_CFGR2_USB_Pos)
11253 #define GTZC_CFGR2_LPUART1_Pos              (25U)
11254 #define GTZC_CFGR2_LPUART1_Msk              (0x01UL << GTZC_CFGR2_LPUART1_Pos)
11255 #define GTZC_CFGR2_LPTIM1_Pos               (28U)
11256 #define GTZC_CFGR2_LPTIM1_Msk               (0x01UL << GTZC_CFGR2_LPTIM1_Pos)
11257 
11258 /***************  Bits definition for register x=3 (TZSC1) *************/
11259 #define GTZC_CFGR3_I3C2_Pos                 (2U)
11260 #define GTZC_CFGR3_I3C2_Msk                 (0x01UL << GTZC_CFGR3_I3C2_Pos)
11261 #define GTZC_CFGR3_CRC_Pos                  (8U)
11262 #define GTZC_CFGR3_CRC_Msk                  (0x01UL << GTZC_CFGR3_CRC_Pos)
11263 #define GTZC_CFGR3_ICACHE_REG_Pos           (12U)
11264 #define GTZC_CFGR3_ICACHE_REG_Msk           (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos)
11265 #define GTZC_CFGR3_ADC_Pos                  (14U)
11266 #define GTZC_CFGR3_ADC_Msk                  (0x01UL << GTZC_CFGR3_ADC_Pos)
11267 #define GTZC_CFGR3_HASH_Pos                 (17U)
11268 #define GTZC_CFGR3_HASH_Msk                 (0x01UL << GTZC_CFGR3_HASH_Pos)
11269 #define GTZC_CFGR3_RNG_Pos                  (18U)
11270 #define GTZC_CFGR3_RNG_Msk                  (0x01UL << GTZC_CFGR3_RNG_Pos)
11271 #define GTZC_CFGR3_RAMCFG_Pos               (26U)
11272 #define GTZC_CFGR3_RAMCFG_Msk               (0x01UL << GTZC_CFGR3_RAMCFG_Pos)
11273 
11274 /***************  Bits definition for register x=4 (TZSC1) *************/
11275 #define GTZC_CFGR4_GPDMA1_Pos               (0U)
11276 #define GTZC_CFGR4_GPDMA1_Msk               (0x01UL << GTZC_CFGR4_GPDMA1_Pos)
11277 #define GTZC_CFGR4_GPDMA2_Pos               (1U)
11278 #define GTZC_CFGR4_GPDMA2_Msk               (0x01UL << GTZC_CFGR4_GPDMA2_Pos)
11279 #define GTZC_CFGR4_FLASH_Pos                (2U)
11280 #define GTZC_CFGR4_FLASH_Msk                (0x01UL << GTZC_CFGR4_FLASH_Pos)
11281 #define GTZC_CFGR4_FLASH_REG_Pos            (3U)
11282 #define GTZC_CFGR4_FLASH_REG_Msk            (0x01UL << GTZC_CFGR4_FLASH_REG_Pos)
11283 #define GTZC_CFGR4_SBS_Pos                  (6U)
11284 #define GTZC_CFGR4_SBS_Msk                  (0x01UL << GTZC_CFGR4_SBS_Pos)
11285 #define GTZC_CFGR4_RTC_Pos                  (7U)
11286 #define GTZC_CFGR4_RTC_Msk                  (0x01UL << GTZC_CFGR4_RTC_Pos)
11287 #define GTZC_CFGR4_TAMP_Pos                 (8U)
11288 #define GTZC_CFGR4_TAMP_Msk                 (0x01UL << GTZC_CFGR4_TAMP_Pos)
11289 #define GTZC_CFGR4_PWR_Pos                  (9U)
11290 #define GTZC_CFGR4_PWR_Msk                  (0x01UL << GTZC_CFGR4_PWR_Pos)
11291 #define GTZC_CFGR4_RCC_Pos                  (10U)
11292 #define GTZC_CFGR4_RCC_Msk                  (0x01UL << GTZC_CFGR4_RCC_Pos)
11293 #define GTZC_CFGR4_EXTI_Pos                 (11U)
11294 #define GTZC_CFGR4_EXTI_Msk                 (0x01UL << GTZC_CFGR4_EXTI_Pos)
11295 #define GTZC_CFGR4_TZSC_Pos                 (16U)
11296 #define GTZC_CFGR4_TZSC_Msk                 (0x01UL << GTZC_CFGR4_TZSC_Pos)
11297 #define GTZC_CFGR4_BKPSRAM_Pos              (20U)
11298 #define GTZC_CFGR4_BKPSRAM_Msk              (0x01UL << GTZC_CFGR4_BKPSRAM_Pos)
11299 #define GTZC_CFGR4_SRAM1_Pos                (24U)
11300 #define GTZC_CFGR4_SRAM1_Msk                (0x01UL << GTZC_CFGR4_SRAM1_Pos)
11301 #define GTZC_CFGR4_MPCBB1_REG_Pos           (25U)
11302 #define GTZC_CFGR4_MPCBB1_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos)
11303 #define GTZC_CFGR4_SRAM2_Pos                (26U)
11304 #define GTZC_CFGR4_SRAM2_Msk                (0x01UL << GTZC_CFGR4_SRAM2_Pos)
11305 #define GTZC_CFGR4_MPCBB2_REG_Pos           (27U)
11306 #define GTZC_CFGR4_MPCBB2_REG_Msk           (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos)
11307 
11308 
11309 /*******************  Bits definition for GTZC_TZSC_PRIVCFGR1 register  ***************/
11310 #define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos           GTZC_CFGR1_TIM2_Pos
11311 #define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk           GTZC_CFGR1_TIM2_Msk
11312 #define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos           GTZC_CFGR1_TIM3_Pos
11313 #define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk           GTZC_CFGR1_TIM3_Msk
11314 #define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos           GTZC_CFGR1_TIM6_Pos
11315 #define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk           GTZC_CFGR1_TIM6_Msk
11316 #define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos           GTZC_CFGR1_TIM7_Pos
11317 #define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk           GTZC_CFGR1_TIM7_Msk
11318 #define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos           GTZC_CFGR1_WWDG_Pos
11319 #define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk           GTZC_CFGR1_WWDG_Msk
11320 #define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos           GTZC_CFGR1_IWDG_Pos
11321 #define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk           GTZC_CFGR1_IWDG_Msk
11322 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos           GTZC_CFGR1_SPI2_Pos
11323 #define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk           GTZC_CFGR1_SPI2_Msk
11324 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos           GTZC_CFGR1_SPI3_Pos
11325 #define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk           GTZC_CFGR1_SPI3_Msk
11326 #define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos           GTZC_CFGR1_I2C1_Pos
11327 #define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk           GTZC_CFGR1_I2C1_Msk
11328 #define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos           GTZC_CFGR1_I2C2_Pos
11329 #define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk           GTZC_CFGR1_I2C2_Msk
11330 #define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos           GTZC_CFGR1_I3C1_Pos
11331 #define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk           GTZC_CFGR1_I3C1_Msk
11332 #define GTZC_TZSC1_PRIVCFGR1_CRS_Pos            GTZC_CFGR1_CRS_Pos
11333 #define GTZC_TZSC1_PRIVCFGR1_CRS_Msk            GTZC_CFGR1_CRS_Msk
11334 #define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos           GTZC_CFGR1_DAC1_Pos
11335 #define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk           GTZC_CFGR1_DAC1_Msk
11336 #define GTZC_TZSC1_PRIVCFGR1_DTS_Pos            GTZC_CFGR1_DTS_Pos
11337 #define GTZC_TZSC1_PRIVCFGR1_DTS_Msk            GTZC_CFGR1_DTS_Msk
11338 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos         GTZC_CFGR1_LPTIM2_Pos
11339 #define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk         GTZC_CFGR1_LPTIM2_Msk
11340 
11341 /*******************  Bits definition for GTZC_TZSC_PRIVCFGR2 register  ***************/
11342 #define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos         GTZC_CFGR2_FDCAN1_Pos
11343 #define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk         GTZC_CFGR2_FDCAN1_Msk
11344 #define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos           GTZC_CFGR2_TIM1_Pos
11345 #define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk           GTZC_CFGR2_TIM1_Msk
11346 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos           GTZC_CFGR2_SPI1_Pos
11347 #define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk           GTZC_CFGR2_SPI1_Msk
11348 #define GTZC_TZSC1_PRIVCFGR2_USART1_Pos         GTZC_CFGR2_USART1_Pos
11349 #define GTZC_TZSC1_PRIVCFGR2_USART1_Msk         GTZC_CFGR2_USART1_Msk
11350 #define GTZC_TZSC1_PRIVCFGR2_USB_Pos            GTZC_CFGR2_USB_Pos
11351 #define GTZC_TZSC1_PRIVCFGR2_USB_Msk            GTZC_CFGR2_USB_Msk
11352 #define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos        GTZC_CFGR2_LPUART1_Pos
11353 #define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk        GTZC_CFGR2_LPUART1_Msk
11354 #define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos         GTZC_CFGR2_LPTIM1_Pos
11355 #define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk         GTZC_CFGR2_LPTIM1_Msk
11356 
11357 /*******************  Bits definition for GTZC_TZSC_PRIVCFGR3 register  ***************/
11358 #define GTZC_TZSC1_PRIVCFGR3_CRC_Pos            GTZC_CFGR3_CRC_Pos
11359 #define GTZC_TZSC1_PRIVCFGR3_CRC_Msk            GTZC_CFGR3_CRC_Msk
11360 #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos     GTZC_CFGR3_ICACHE_REG_Pos
11361 #define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk     GTZC_CFGR3_ICACHE_REG_Msk
11362 #define GTZC_TZSC1_PRIVCFGR3_ADC_Pos            GTZC_CFGR3_ADC_Pos
11363 #define GTZC_TZSC1_PRIVCFGR3_ADC_Msk            GTZC_CFGR3_ADC_Msk
11364 #define GTZC_TZSC1_PRIVCFGR3_HASH_Pos           GTZC_CFGR3_HASH_Pos
11365 #define GTZC_TZSC1_PRIVCFGR3_HASH_Msk           GTZC_CFGR3_HASH_Msk
11366 #define GTZC_TZSC1_PRIVCFGR3_RNG_Pos            GTZC_CFGR3_RNG_Pos
11367 #define GTZC_TZSC1_PRIVCFGR3_RNG_Msk            GTZC_CFGR3_RNG_Msk
11368 #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos         GTZC_CFGR3_RAMCFG_Pos
11369 #define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk         GTZC_CFGR3_RAMCFG_Msk
11370 
11371 
11372 /*******************  Bits definition for GTZC_MPCBB_CR register  *****************/
11373 #define GTZC_MPCBB_CR_GLOCK_Pos             (0U)
11374 #define GTZC_MPCBB_CR_GLOCK_Msk             (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos)       /*!< 0x00000001 */
11375 #define GTZC_MPCBB_CR_INVSECSTATE_Pos       (30U)
11376 #define GTZC_MPCBB_CR_INVSECSTATE_Msk       (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */
11377 #define GTZC_MPCBB_CR_SRWILADIS_Pos         (31U)
11378 #define GTZC_MPCBB_CR_SRWILADIS_Msk         (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos)   /*!< 0x80000000 */
11379 
11380 /*******************  Bits definition for GTZC_MPCBB_CFGLOCKR1 register  ************/
11381 #define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos      (0U)
11382 #define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */
11383 #define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos      (1U)
11384 #define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */
11385 #define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos      (2U)
11386 #define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */
11387 #define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos      (3U)
11388 #define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */
11389 #define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos      (4U)
11390 #define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */
11391 #define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos      (5U)
11392 #define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */
11393 #define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos      (6U)
11394 #define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */
11395 #define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos      (7U)
11396 #define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */
11397 #define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos      (8U)
11398 #define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */
11399 #define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos      (9U)
11400 #define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk      (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */
11401 #define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos     (10U)
11402 #define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */
11403 #define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos     (11U)
11404 #define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */
11405 #define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos     (12U)
11406 #define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */
11407 #define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos     (13U)
11408 #define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */
11409 #define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos     (14U)
11410 #define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */
11411 #define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos     (15U)
11412 #define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */
11413 #define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos     (16U)
11414 #define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */
11415 #define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos     (17U)
11416 #define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */
11417 #define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos     (18U)
11418 #define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */
11419 #define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos     (19U)
11420 #define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */
11421 #define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos     (20U)
11422 #define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */
11423 #define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos     (21U)
11424 #define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */
11425 #define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos     (22U)
11426 #define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */
11427 #define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos     (23U)
11428 #define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */
11429 #define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos     (24U)
11430 #define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */
11431 #define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos     (25U)
11432 #define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */
11433 #define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos     (26U)
11434 #define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */
11435 #define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos     (27U)
11436 #define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */
11437 #define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos     (28U)
11438 #define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */
11439 #define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos     (29U)
11440 #define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */
11441 #define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos     (30U)
11442 #define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */
11443 #define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos     (31U)
11444 #define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk     (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */
11445 
11446 
11447 
11448 /******************************************************************************/
11449 /*                                                                            */
11450 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
11451 /*                                                                            */
11452 /******************************************************************************/
11453 /******************  Bit definition for USART_CR1 register  *******************/
11454 #define USART_CR1_UE_Pos                    (0U)
11455 #define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)             /*!< 0x00000001 */
11456 #define USART_CR1_UE                        USART_CR1_UE_Msk                        /*!< USART Enable */
11457 #define USART_CR1_UESM_Pos                  (1U)
11458 #define USART_CR1_UESM_Msk                  (0x1UL << USART_CR1_UESM_Pos)           /*!< 0x00000002 */
11459 #define USART_CR1_UESM                      USART_CR1_UESM_Msk                      /*!< USART Enable in STOP Mode */
11460 #define USART_CR1_RE_Pos                    (2U)
11461 #define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)             /*!< 0x00000004 */
11462 #define USART_CR1_RE                        USART_CR1_RE_Msk                        /*!< Receiver Enable */
11463 #define USART_CR1_TE_Pos                    (3U)
11464 #define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)             /*!< 0x00000008 */
11465 #define USART_CR1_TE                        USART_CR1_TE_Msk                        /*!< Transmitter Enable */
11466 #define USART_CR1_IDLEIE_Pos                (4U)
11467 #define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)         /*!< 0x00000010 */
11468 #define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk                    /*!< IDLE Interrupt Enable */
11469 #define USART_CR1_RXNEIE_Pos                (5U)
11470 #define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)         /*!< 0x00000020 */
11471 #define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk                    /*!< RXNE Interrupt Enable */
11472 #define USART_CR1_RXNEIE_RXFNEIE_Pos        USART_CR1_RXNEIE_Pos
11473 #define USART_CR1_RXNEIE_RXFNEIE_Msk        USART_CR1_RXNEIE_Msk                    /*!< 0x00000020 */
11474 #define USART_CR1_RXNEIE_RXFNEIE            USART_CR1_RXNEIE_Msk                    /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
11475 #define USART_CR1_TCIE_Pos                  (6U)
11476 #define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)           /*!< 0x00000040 */
11477 #define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                      /*!< Transmission Complete Interrupt Enable */
11478 #define USART_CR1_TXEIE_Pos                 (7U)
11479 #define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
11480 #define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                     /*!< TXE Interrupt Enable */
11481 #define USART_CR1_TXEIE_TXFNFIE_Pos         (7U)
11482 #define USART_CR1_TXEIE_TXFNFIE_Msk         (0x1UL << USART_CR1_TXEIE_Pos)          /*!< 0x00000080 */
11483 #define USART_CR1_TXEIE_TXFNFIE             USART_CR1_TXEIE                         /*!< TXE and TX FIFO Not Full Interrupt Enable */
11484 #define USART_CR1_PEIE_Pos                  (8U)
11485 #define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)           /*!< 0x00000100 */
11486 #define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                      /*!< PE Interrupt Enable */
11487 #define USART_CR1_PS_Pos                    (9U)
11488 #define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)             /*!< 0x00000200 */
11489 #define USART_CR1_PS                        USART_CR1_PS_Msk                        /*!< Parity Selection */
11490 #define USART_CR1_PCE_Pos                   (10U)
11491 #define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)            /*!< 0x00000400 */
11492 #define USART_CR1_PCE                       USART_CR1_PCE_Msk                       /*!< Parity Control Enable */
11493 #define USART_CR1_WAKE_Pos                  (11U)
11494 #define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)           /*!< 0x00000800 */
11495 #define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                      /*!< Receiver Wakeup method */
11496 #define USART_CR1_M_Pos                     (12U)
11497 #define USART_CR1_M_Msk                     (0x10001UL << USART_CR1_M_Pos)          /*!< 0x10001000 */
11498 #define USART_CR1_M                         USART_CR1_M_Msk                         /*!< Word length */
11499 #define USART_CR1_M0_Pos                    (12U)
11500 #define USART_CR1_M0_Msk                    (0x1UL << USART_CR1_M0_Pos)             /*!< 0x00001000 */
11501 #define USART_CR1_M0                        USART_CR1_M0_Msk                        /*!< Word length - Bit 0 */
11502 #define USART_CR1_MME_Pos                   (13U)
11503 #define USART_CR1_MME_Msk                   (0x1UL << USART_CR1_MME_Pos)            /*!< 0x00002000 */
11504 #define USART_CR1_MME                       USART_CR1_MME_Msk                       /*!< Mute Mode Enable */
11505 #define USART_CR1_CMIE_Pos                  (14U)
11506 #define USART_CR1_CMIE_Msk                  (0x1UL << USART_CR1_CMIE_Pos)           /*!< 0x00004000 */
11507 #define USART_CR1_CMIE                      USART_CR1_CMIE_Msk                      /*!< Character match interrupt enable */
11508 #define USART_CR1_OVER8_Pos                 (15U)
11509 #define USART_CR1_OVER8_Msk                 (0x1UL << USART_CR1_OVER8_Pos)          /*!< 0x00008000 */
11510 #define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                     /*!< Oversampling by 8-bit or 16-bit mode */
11511 #define USART_CR1_DEDT_Pos                  (16U)
11512 #define USART_CR1_DEDT_Msk                  (0x1FUL << USART_CR1_DEDT_Pos)          /*!< 0x001F0000 */
11513 #define USART_CR1_DEDT                      USART_CR1_DEDT_Msk                      /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
11514 #define USART_CR1_DEDT_0                    (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
11515 #define USART_CR1_DEDT_1                    (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
11516 #define USART_CR1_DEDT_2                    (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
11517 #define USART_CR1_DEDT_3                    (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
11518 #define USART_CR1_DEDT_4                    (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
11519 #define USART_CR1_DEAT_Pos                  (21U)
11520 #define USART_CR1_DEAT_Msk                  (0x1FUL << USART_CR1_DEAT_Pos)          /*!< 0x03E00000 */
11521 #define USART_CR1_DEAT                      USART_CR1_DEAT_Msk                      /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
11522 #define USART_CR1_DEAT_0                    (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
11523 #define USART_CR1_DEAT_1                    (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
11524 #define USART_CR1_DEAT_2                    (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
11525 #define USART_CR1_DEAT_3                    (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
11526 #define USART_CR1_DEAT_4                    (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
11527 #define USART_CR1_RTOIE_Pos                 (26U)
11528 #define USART_CR1_RTOIE_Msk                 (0x1UL << USART_CR1_RTOIE_Pos)          /*!< 0x04000000 */
11529 #define USART_CR1_RTOIE                     USART_CR1_RTOIE_Msk                     /*!< Receive Time Out interrupt enable */
11530 #define USART_CR1_EOBIE_Pos                 (27U)
11531 #define USART_CR1_EOBIE_Msk                 (0x1UL << USART_CR1_EOBIE_Pos)          /*!< 0x08000000 */
11532 #define USART_CR1_EOBIE                     USART_CR1_EOBIE_Msk                     /*!< End of Block interrupt enable */
11533 #define USART_CR1_M1_Pos                    (28U)
11534 #define USART_CR1_M1_Msk                    (0x1UL << USART_CR1_M1_Pos)             /*!< 0x10000000 */
11535 #define USART_CR1_M1                        USART_CR1_M1_Msk                        /*!< Word length - Bit 1 */
11536 #define USART_CR1_FIFOEN_Pos                (29U)
11537 #define USART_CR1_FIFOEN_Msk                (0x1UL << USART_CR1_FIFOEN_Pos)         /*!< 0x20000000 */
11538 #define USART_CR1_FIFOEN                    USART_CR1_FIFOEN_Msk                    /*!< FIFO mode enable */
11539 #define USART_CR1_TXFEIE_Pos                (30U)
11540 #define USART_CR1_TXFEIE_Msk                (0x1UL << USART_CR1_TXFEIE_Pos)         /*!< 0x40000000 */
11541 #define USART_CR1_TXFEIE                    USART_CR1_TXFEIE_Msk                    /*!< TXFIFO empty interrupt enable */
11542 #define USART_CR1_RXFFIE_Pos                (31U)
11543 #define USART_CR1_RXFFIE_Msk                (0x1UL << USART_CR1_RXFFIE_Pos)         /*!< 0x80000000 */
11544 #define USART_CR1_RXFFIE                    USART_CR1_RXFFIE_Msk                    /*!< RXFIFO Full interrupt enable */
11545 
11546 /******************  Bit definition for USART_CR2 register  *******************/
11547 #define USART_CR2_SLVEN_Pos                 (0U)
11548 #define USART_CR2_SLVEN_Msk                 (0x1UL << USART_CR2_SLVEN_Pos)          /*!< 0x00000001 */
11549 #define USART_CR2_SLVEN                     USART_CR2_SLVEN_Msk                     /*!< Synchronous Slave mode enable */
11550 #define USART_CR2_DIS_NSS_Pos               (3U)
11551 #define USART_CR2_DIS_NSS_Msk               (0x1UL << USART_CR2_DIS_NSS_Pos)        /*!< 0x00000008 */
11552 #define USART_CR2_DIS_NSS                   USART_CR2_DIS_NSS_Msk                   /*!< Slave Select (NSS) pin management */
11553 #define USART_CR2_ADDM7_Pos                 (4U)
11554 #define USART_CR2_ADDM7_Msk                 (0x1UL << USART_CR2_ADDM7_Pos)          /*!< 0x00000010 */
11555 #define USART_CR2_ADDM7                     USART_CR2_ADDM7_Msk                     /*!< 7-bit or 4-bit Address Detection */
11556 #define USART_CR2_LBDL_Pos                  (5U)
11557 #define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)           /*!< 0x00000020 */
11558 #define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                      /*!< LIN Break Detection Length */
11559 #define USART_CR2_LBDIE_Pos                 (6U)
11560 #define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)          /*!< 0x00000040 */
11561 #define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                     /*!< LIN Break Detection Interrupt Enable */
11562 #define USART_CR2_LBCL_Pos                  (8U)
11563 #define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)           /*!< 0x00000100 */
11564 #define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                      /*!< Last Bit Clock pulse */
11565 #define USART_CR2_CPHA_Pos                  (9U)
11566 #define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)           /*!< 0x00000200 */
11567 #define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                      /*!< Clock Phase */
11568 #define USART_CR2_CPOL_Pos                  (10U)
11569 #define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)           /*!< 0x00000400 */
11570 #define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                      /*!< Clock Polarity */
11571 #define USART_CR2_CLKEN_Pos                 (11U)
11572 #define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)          /*!< 0x00000800 */
11573 #define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                     /*!< Clock Enable */
11574 #define USART_CR2_STOP_Pos                  (12U)
11575 #define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)           /*!< 0x00003000 */
11576 #define USART_CR2_STOP                      USART_CR2_STOP_Msk                      /*!< STOP[1:0] bits (STOP bits) */
11577 #define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
11578 #define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
11579 #define USART_CR2_LINEN_Pos                 (14U)
11580 #define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)          /*!< 0x00004000 */
11581 #define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                     /*!< LIN mode enable */
11582 #define USART_CR2_SWAP_Pos                  (15U)
11583 #define USART_CR2_SWAP_Msk                  (0x1UL << USART_CR2_SWAP_Pos)           /*!< 0x00008000 */
11584 #define USART_CR2_SWAP                      USART_CR2_SWAP_Msk                      /*!< SWAP TX/RX pins */
11585 #define USART_CR2_RXINV_Pos                 (16U)
11586 #define USART_CR2_RXINV_Msk                 (0x1UL << USART_CR2_RXINV_Pos)          /*!< 0x00010000 */
11587 #define USART_CR2_RXINV                     USART_CR2_RXINV_Msk                     /*!< RX pin active level inversion */
11588 #define USART_CR2_TXINV_Pos                 (17U)
11589 #define USART_CR2_TXINV_Msk                 (0x1UL << USART_CR2_TXINV_Pos)          /*!< 0x00020000 */
11590 #define USART_CR2_TXINV                     USART_CR2_TXINV_Msk                     /*!< TX pin active level inversion */
11591 #define USART_CR2_DATAINV_Pos               (18U)
11592 #define USART_CR2_DATAINV_Msk               (0x1UL << USART_CR2_DATAINV_Pos)        /*!< 0x00040000 */
11593 #define USART_CR2_DATAINV                   USART_CR2_DATAINV_Msk                   /*!< Binary data inversion */
11594 #define USART_CR2_MSBFIRST_Pos              (19U)
11595 #define USART_CR2_MSBFIRST_Msk              (0x1UL << USART_CR2_MSBFIRST_Pos)       /*!< 0x00080000 */
11596 #define USART_CR2_MSBFIRST                  USART_CR2_MSBFIRST_Msk                  /*!< Most Significant Bit First */
11597 #define USART_CR2_ABREN_Pos                 (20U)
11598 #define USART_CR2_ABREN_Msk                 (0x1UL << USART_CR2_ABREN_Pos)          /*!< 0x00100000 */
11599 #define USART_CR2_ABREN                     USART_CR2_ABREN_Msk                     /*!< Auto Baud-Rate Enable*/
11600 #define USART_CR2_ABRMODE_Pos               (21U)
11601 #define USART_CR2_ABRMODE_Msk               (0x3UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00600000 */
11602 #define USART_CR2_ABRMODE                   USART_CR2_ABRMODE_Msk                   /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
11603 #define USART_CR2_ABRMODE_0                 (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
11604 #define USART_CR2_ABRMODE_1                 (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
11605 #define USART_CR2_RTOEN_Pos                 (23U)
11606 #define USART_CR2_RTOEN_Msk                 (0x1UL << USART_CR2_RTOEN_Pos)          /*!< 0x00800000 */
11607 #define USART_CR2_RTOEN                     USART_CR2_RTOEN_Msk                     /*!< Receiver Time-Out enable */
11608 #define USART_CR2_ADD_Pos                   (24U)
11609 #define USART_CR2_ADD_Msk                   (0xFFUL << USART_CR2_ADD_Pos)           /*!< 0xFF000000 */
11610 #define USART_CR2_ADD                       USART_CR2_ADD_Msk                       /*!< Address of the USART node */
11611 
11612 /******************  Bit definition for USART_CR3 register  *******************/
11613 #define USART_CR3_EIE_Pos                   (0U)
11614 #define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)            /*!< 0x00000001 */
11615 #define USART_CR3_EIE                       USART_CR3_EIE_Msk                       /*!< Error Interrupt Enable */
11616 #define USART_CR3_IREN_Pos                  (1U)
11617 #define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)           /*!< 0x00000002 */
11618 #define USART_CR3_IREN                      USART_CR3_IREN_Msk                      /*!< IrDA mode Enable */
11619 #define USART_CR3_IRLP_Pos                  (2U)
11620 #define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)           /*!< 0x00000004 */
11621 #define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                      /*!< IrDA Low-Power */
11622 #define USART_CR3_HDSEL_Pos                 (3U)
11623 #define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)          /*!< 0x00000008 */
11624 #define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                     /*!< Half-Duplex Selection */
11625 #define USART_CR3_NACK_Pos                  (4U)
11626 #define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)           /*!< 0x00000010 */
11627 #define USART_CR3_NACK                      USART_CR3_NACK_Msk                      /*!< SmartCard NACK enable */
11628 #define USART_CR3_SCEN_Pos                  (5U)
11629 #define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)           /*!< 0x00000020 */
11630 #define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                      /*!< SmartCard mode enable */
11631 #define USART_CR3_DMAR_Pos                  (6U)
11632 #define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)           /*!< 0x00000040 */
11633 #define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                      /*!< DMA Enable Receiver */
11634 #define USART_CR3_DMAT_Pos                  (7U)
11635 #define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)           /*!< 0x00000080 */
11636 #define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                      /*!< DMA Enable Transmitter */
11637 #define USART_CR3_RTSE_Pos                  (8U)
11638 #define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)           /*!< 0x00000100 */
11639 #define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                      /*!< RTS Enable */
11640 #define USART_CR3_CTSE_Pos                  (9U)
11641 #define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)           /*!< 0x00000200 */
11642 #define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                      /*!< CTS Enable */
11643 #define USART_CR3_CTSIE_Pos                 (10U)
11644 #define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)          /*!< 0x00000400 */
11645 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                     /*!< CTS Interrupt Enable */
11646 #define USART_CR3_ONEBIT_Pos                (11U)
11647 #define USART_CR3_ONEBIT_Msk                (0x1UL << USART_CR3_ONEBIT_Pos)         /*!< 0x00000800 */
11648 #define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk                    /*!< One sample bit method enable */
11649 #define USART_CR3_OVRDIS_Pos                (12U)
11650 #define USART_CR3_OVRDIS_Msk                (0x1UL << USART_CR3_OVRDIS_Pos)         /*!< 0x00001000 */
11651 #define USART_CR3_OVRDIS                    USART_CR3_OVRDIS_Msk                    /*!< Overrun Disable */
11652 #define USART_CR3_DDRE_Pos                  (13U)
11653 #define USART_CR3_DDRE_Msk                  (0x1UL << USART_CR3_DDRE_Pos)           /*!< 0x00002000 */
11654 #define USART_CR3_DDRE                      USART_CR3_DDRE_Msk                      /*!< DMA Disable on Reception Error */
11655 #define USART_CR3_DEM_Pos                   (14U)
11656 #define USART_CR3_DEM_Msk                   (0x1UL << USART_CR3_DEM_Pos)            /*!< 0x00004000 */
11657 #define USART_CR3_DEM                       USART_CR3_DEM_Msk                       /*!< Driver Enable Mode */
11658 #define USART_CR3_DEP_Pos                   (15U)
11659 #define USART_CR3_DEP_Msk                   (0x1UL << USART_CR3_DEP_Pos)            /*!< 0x00008000 */
11660 #define USART_CR3_DEP                       USART_CR3_DEP_Msk                       /*!< Driver Enable Polarity Selection */
11661 #define USART_CR3_SCARCNT_Pos               (17U)
11662 #define USART_CR3_SCARCNT_Msk               (0x7UL << USART_CR3_SCARCNT_Pos)        /*!< 0x000E0000 */
11663 #define USART_CR3_SCARCNT                   USART_CR3_SCARCNT_Msk                   /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
11664 #define USART_CR3_SCARCNT_0                 (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
11665 #define USART_CR3_SCARCNT_1                 (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
11666 #define USART_CR3_SCARCNT_2                 (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
11667 #define USART_CR3_WUS_Pos                   (20U)
11668 #define USART_CR3_WUS_Msk                   (0x3UL << USART_CR3_WUS_Pos)            /*!< 0x00300000 */
11669 #define USART_CR3_WUS                       USART_CR3_WUS_Msk                       /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
11670 #define USART_CR3_WUS_0                     (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
11671 #define USART_CR3_WUS_1                     (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
11672 #define USART_CR3_WUFIE_Pos                 (22U)
11673 #define USART_CR3_WUFIE_Msk                 (0x1UL << USART_CR3_WUFIE_Pos)          /*!< 0x00400000 */
11674 #define USART_CR3_WUFIE                     USART_CR3_WUFIE_Msk                     /*!< Wake Up Interrupt Enable */
11675 #define USART_CR3_TXFTIE_Pos                (23U)
11676 #define USART_CR3_TXFTIE_Msk                (0x1UL << USART_CR3_TXFTIE_Pos)         /*!< 0x00800000 */
11677 #define USART_CR3_TXFTIE                    USART_CR3_TXFTIE_Msk                    /*!< TXFIFO threshold interrupt enable */
11678 #define USART_CR3_TCBGTIE_Pos               (24U)
11679 #define USART_CR3_TCBGTIE_Msk               (0x1UL << USART_CR3_TCBGTIE_Pos)        /*!< 0x01000000 */
11680 #define USART_CR3_TCBGTIE                   USART_CR3_TCBGTIE_Msk                   /*!< Transmission Complete Before Guard Time Interrupt Enable */
11681 #define USART_CR3_RXFTCFG_Pos               (25U)
11682 #define USART_CR3_RXFTCFG_Msk               (0x7UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x0E000000 */
11683 #define USART_CR3_RXFTCFG                   USART_CR3_RXFTCFG_Msk                   /*!< RXFIFO FIFO threshold configuration */
11684 #define USART_CR3_RXFTCFG_0                 (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
11685 #define USART_CR3_RXFTCFG_1                 (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
11686 #define USART_CR3_RXFTCFG_2                 (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
11687 #define USART_CR3_RXFTIE_Pos                (28U)
11688 #define USART_CR3_RXFTIE_Msk                (0x1UL << USART_CR3_RXFTIE_Pos)         /*!< 0x10000000 */
11689 #define USART_CR3_RXFTIE                    USART_CR3_RXFTIE_Msk                    /*!< RXFIFO threshold interrupt enable */
11690 #define USART_CR3_TXFTCFG_Pos               (29U)
11691 #define USART_CR3_TXFTCFG_Msk               (0x7UL << USART_CR3_TXFTCFG_Pos)        /*!< 0xE0000000 */
11692 #define USART_CR3_TXFTCFG                   USART_CR3_TXFTCFG_Msk                   /*!< TXFIFO threshold configuration */
11693 #define USART_CR3_TXFTCFG_0                 (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
11694 #define USART_CR3_TXFTCFG_1                 (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
11695 #define USART_CR3_TXFTCFG_2                 (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
11696 
11697 /******************  Bit definition for USART_BRR register  *******************/
11698 #define USART_BRR_LPUART_Pos                (0U)
11699 #define USART_BRR_LPUART_Msk                (0xFFFFFUL << USART_BRR_LPUART_Pos)     /*!< 0x000FFFFF */
11700 #define USART_BRR_LPUART                    USART_BRR_LPUART_Msk                    /*!< LPUART Baud rate register [19:0] */
11701 #define USART_BRR_BRR                       ((uint16_t)0xFFFF)                      /*!< USART  Baud rate register [15:0] */
11702 
11703 /******************  Bit definition for USART_GTPR register  ******************/
11704 #define USART_GTPR_PSC_Pos                  (0U)
11705 #define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)          /*!< 0x000000FF */
11706 #define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                      /*!< PSC[7:0] bits (Prescaler value) */
11707 #define USART_GTPR_GT_Pos                   (8U)
11708 #define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)           /*!< 0x0000FF00 */
11709 #define USART_GTPR_GT                       USART_GTPR_GT_Msk                       /*!< GT[7:0] bits (Guard time value) */
11710 
11711 /*******************  Bit definition for USART_RTOR register  *****************/
11712 #define USART_RTOR_RTO_Pos                  (0U)
11713 #define USART_RTOR_RTO_Msk                  (0xFFFFFFUL << USART_RTOR_RTO_Pos)      /*!< 0x00FFFFFF */
11714 #define USART_RTOR_RTO                      USART_RTOR_RTO_Msk                      /*!< Receiver Time Out Value */
11715 #define USART_RTOR_BLEN_Pos                 (24U)
11716 #define USART_RTOR_BLEN_Msk                 (0xFFUL << USART_RTOR_BLEN_Pos)         /*!< 0xFF000000 */
11717 #define USART_RTOR_BLEN                     USART_RTOR_BLEN_Msk                     /*!< Block Length */
11718 
11719 /*******************  Bit definition for USART_RQR register  ******************/
11720 #define USART_RQR_ABRRQ                     ((uint16_t)0x0001)                      /*!< Auto-Baud Rate Request */
11721 #define USART_RQR_SBKRQ                     ((uint16_t)0x0002)                      /*!< Send Break Request */
11722 #define USART_RQR_MMRQ                      ((uint16_t)0x0004)                      /*!< Mute Mode Request */
11723 #define USART_RQR_RXFRQ                     ((uint16_t)0x0008)                      /*!< Receive Data flush Request */
11724 #define USART_RQR_TXFRQ                     ((uint16_t)0x0010)                      /*!< Transmit data flush Request */
11725 
11726 /*******************  Bit definition for USART_ISR register  ******************/
11727 #define USART_ISR_PE_Pos                    (0U)
11728 #define USART_ISR_PE_Msk                    (0x1UL << USART_ISR_PE_Pos)             /*!< 0x00000001 */
11729 #define USART_ISR_PE                        USART_ISR_PE_Msk                        /*!< Parity Error */
11730 #define USART_ISR_FE_Pos                    (1U)
11731 #define USART_ISR_FE_Msk                    (0x1UL << USART_ISR_FE_Pos)             /*!< 0x00000002 */
11732 #define USART_ISR_FE                        USART_ISR_FE_Msk                        /*!< Framing Error */
11733 #define USART_ISR_NE_Pos                    (2U)
11734 #define USART_ISR_NE_Msk                    (0x1UL << USART_ISR_NE_Pos)             /*!< 0x00000004 */
11735 #define USART_ISR_NE                        USART_ISR_NE_Msk                        /*!< Noise detected Flag */
11736 #define USART_ISR_ORE_Pos                   (3U)
11737 #define USART_ISR_ORE_Msk                   (0x1UL << USART_ISR_ORE_Pos)            /*!< 0x00000008 */
11738 #define USART_ISR_ORE                       USART_ISR_ORE_Msk                       /*!< OverRun Error */
11739 #define USART_ISR_IDLE_Pos                  (4U)
11740 #define USART_ISR_IDLE_Msk                  (0x1UL << USART_ISR_IDLE_Pos)           /*!< 0x00000010 */
11741 #define USART_ISR_IDLE                      USART_ISR_IDLE_Msk                      /*!< IDLE line detected */
11742 #define USART_ISR_RXNE_Pos                  (5U)
11743 #define USART_ISR_RXNE_Msk                  (0x1UL << USART_ISR_RXNE_Pos)           /*!< 0x00000020 */
11744 #define USART_ISR_RXNE                      USART_ISR_RXNE_Msk                      /*!< Read Data Register Not Empty */
11745 #define USART_ISR_RXNE_RXFNE_Pos            USART_ISR_RXNE_Pos
11746 #define USART_ISR_RXNE_RXFNE_Msk            USART_ISR_RXNE_Msk                      /*!< 0x00000020 */
11747 #define USART_ISR_RXNE_RXFNE                USART_ISR_RXNE_Msk                      /*!< Read Data Register or RX FIFO Not Empty */
11748 #define USART_ISR_TC_Pos                    (6U)
11749 #define USART_ISR_TC_Msk                    (0x1UL << USART_ISR_TC_Pos)             /*!< 0x00000040 */
11750 #define USART_ISR_TC                        USART_ISR_TC_Msk                        /*!< Transmission Complete */
11751 #define USART_ISR_TXE_Pos                   (7U)
11752 #define USART_ISR_TXE_Msk                   (0x1UL << USART_ISR_TXE_Pos)            /*!< 0x00000080 */
11753 #define USART_ISR_TXE                       USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty */
11754 #define USART_ISR_TXE_TXFNF_Pos             USART_ISR_TXE_Pos
11755 #define USART_ISR_TXE_TXFNF_Msk             USART_ISR_TXE_Msk                       /*!< 0x00000080 */
11756 #define USART_ISR_TXE_TXFNF                 USART_ISR_TXE_Msk                       /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
11757 #define USART_ISR_LBDF_Pos                  (8U)
11758 #define USART_ISR_LBDF_Msk                  (0x1UL << USART_ISR_LBDF_Pos)           /*!< 0x00000100 */
11759 #define USART_ISR_LBDF                      USART_ISR_LBDF_Msk                      /*!< LIN Break Detection Flag */
11760 #define USART_ISR_CTSIF_Pos                 (9U)
11761 #define USART_ISR_CTSIF_Msk                 (0x1UL << USART_ISR_CTSIF_Pos)          /*!< 0x00000200 */
11762 #define USART_ISR_CTSIF                     USART_ISR_CTSIF_Msk                     /*!< CTS interrupt flag */
11763 #define USART_ISR_CTS_Pos                   (10U)
11764 #define USART_ISR_CTS_Msk                   (0x1UL << USART_ISR_CTS_Pos)            /*!< 0x00000400 */
11765 #define USART_ISR_CTS                       USART_ISR_CTS_Msk                       /*!< CTS flag */
11766 #define USART_ISR_RTOF_Pos                  (11U)
11767 #define USART_ISR_RTOF_Msk                  (0x1UL << USART_ISR_RTOF_Pos)           /*!< 0x00000800 */
11768 #define USART_ISR_RTOF                      USART_ISR_RTOF_Msk                      /*!< Receiver Time Out */
11769 #define USART_ISR_EOBF_Pos                  (12U)
11770 #define USART_ISR_EOBF_Msk                  (0x1UL << USART_ISR_EOBF_Pos)           /*!< 0x00001000 */
11771 #define USART_ISR_EOBF                      USART_ISR_EOBF_Msk                      /*!< End Of Block Flag */
11772 #define USART_ISR_UDR_Pos                   (13U)
11773 #define USART_ISR_UDR_Msk                   (0x1UL << USART_ISR_UDR_Pos)            /*!< 0x00002000 */
11774 #define USART_ISR_UDR                       USART_ISR_UDR_Msk                       /*!< SPI slave underrun error flag */
11775 #define USART_ISR_ABRE_Pos                  (14U)
11776 #define USART_ISR_ABRE_Msk                  (0x1UL << USART_ISR_ABRE_Pos)           /*!< 0x00004000 */
11777 #define USART_ISR_ABRE                      USART_ISR_ABRE_Msk                      /*!< Auto-Baud Rate Error */
11778 #define USART_ISR_ABRF_Pos                  (15U)
11779 #define USART_ISR_ABRF_Msk                  (0x1UL << USART_ISR_ABRF_Pos)           /*!< 0x00008000 */
11780 #define USART_ISR_ABRF                      USART_ISR_ABRF_Msk                      /*!< Auto-Baud Rate Flag */
11781 #define USART_ISR_BUSY_Pos                  (16U)
11782 #define USART_ISR_BUSY_Msk                  (0x1UL << USART_ISR_BUSY_Pos)           /*!< 0x00010000 */
11783 #define USART_ISR_BUSY                      USART_ISR_BUSY_Msk                      /*!< Busy Flag */
11784 #define USART_ISR_CMF_Pos                   (17U)
11785 #define USART_ISR_CMF_Msk                   (0x1UL << USART_ISR_CMF_Pos)            /*!< 0x00020000 */
11786 #define USART_ISR_CMF                       USART_ISR_CMF_Msk                       /*!< Character Match Flag */
11787 #define USART_ISR_SBKF_Pos                  (18U)
11788 #define USART_ISR_SBKF_Msk                  (0x1UL << USART_ISR_SBKF_Pos)           /*!< 0x00040000 */
11789 #define USART_ISR_SBKF                      USART_ISR_SBKF_Msk                      /*!< Send Break Flag */
11790 #define USART_ISR_RWU_Pos                   (19U)
11791 #define USART_ISR_RWU_Msk                   (0x1UL << USART_ISR_RWU_Pos)            /*!< 0x00080000 */
11792 #define USART_ISR_RWU                       USART_ISR_RWU_Msk                       /*!< Receive Wake Up from mute mode Flag */
11793 #define USART_ISR_WUF_Pos                   (20U)
11794 #define USART_ISR_WUF_Msk                   (0x1UL << USART_ISR_WUF_Pos)            /*!< 0x00100000 */
11795 #define USART_ISR_WUF                       USART_ISR_WUF_Msk                       /*!< Wake Up from low power mode Flag */
11796 #define USART_ISR_TEACK_Pos                 (21U)
11797 #define USART_ISR_TEACK_Msk                 (0x1UL << USART_ISR_TEACK_Pos)          /*!< 0x00200000 */
11798 #define USART_ISR_TEACK                     USART_ISR_TEACK_Msk                     /*!< Transmit Enable Acknowledge Flag */
11799 #define USART_ISR_REACK_Pos                 (22U)
11800 #define USART_ISR_REACK_Msk                 (0x1UL << USART_ISR_REACK_Pos)          /*!< 0x00400000 */
11801 #define USART_ISR_REACK                     USART_ISR_REACK_Msk                     /*!< Receive Enable Acknowledge Flag */
11802 #define USART_ISR_TXFE_Pos                  (23U)
11803 #define USART_ISR_TXFE_Msk                  (0x1UL << USART_ISR_TXFE_Pos)           /*!< 0x00800000 */
11804 #define USART_ISR_TXFE                      USART_ISR_TXFE_Msk                      /*!< TXFIFO Empty */
11805 #define USART_ISR_RXFF_Pos                  (24U)
11806 #define USART_ISR_RXFF_Msk                  (0x1UL << USART_ISR_RXFF_Pos)           /*!< 0x01000000 */
11807 #define USART_ISR_RXFF                      USART_ISR_RXFF_Msk                      /*!< RXFIFO Full */
11808 #define USART_ISR_TCBGT_Pos                 (25U)
11809 #define USART_ISR_TCBGT_Msk                 (0x1UL << USART_ISR_TCBGT_Pos)          /*!< 0x02000000 */
11810 #define USART_ISR_TCBGT                     USART_ISR_TCBGT_Msk                     /*!< Transmission Complete Before Guard Time completion */
11811 #define USART_ISR_RXFT_Pos                  (26U)
11812 #define USART_ISR_RXFT_Msk                  (0x1UL << USART_ISR_RXFT_Pos)           /*!< 0x04000000 */
11813 #define USART_ISR_RXFT                      USART_ISR_RXFT_Msk                      /*!< RXFIFO threshold flag */
11814 #define USART_ISR_TXFT_Pos                  (27U)
11815 #define USART_ISR_TXFT_Msk                  (0x1UL << USART_ISR_TXFT_Pos)           /*!< 0x08000000 */
11816 #define USART_ISR_TXFT                      USART_ISR_TXFT_Msk                      /*!< TXFIFO threshold flag */
11817 
11818 /*******************  Bit definition for USART_ICR register  ******************/
11819 #define USART_ICR_PECF_Pos                  (0U)
11820 #define USART_ICR_PECF_Msk                  (0x1UL << USART_ICR_PECF_Pos)           /*!< 0x00000001 */
11821 #define USART_ICR_PECF                      USART_ICR_PECF_Msk                      /*!< Parity Error Clear Flag */
11822 #define USART_ICR_FECF_Pos                  (1U)
11823 #define USART_ICR_FECF_Msk                  (0x1UL << USART_ICR_FECF_Pos)           /*!< 0x00000002 */
11824 #define USART_ICR_FECF                      USART_ICR_FECF_Msk                      /*!< Framing Error Clear Flag */
11825 #define USART_ICR_NECF_Pos                  (2U)
11826 #define USART_ICR_NECF_Msk                  (0x1UL << USART_ICR_NECF_Pos)           /*!< 0x00000004 */
11827 #define USART_ICR_NECF                      USART_ICR_NECF_Msk                      /*!< Noise detected Clear Flag */
11828 #define USART_ICR_ORECF_Pos                 (3U)
11829 #define USART_ICR_ORECF_Msk                 (0x1UL << USART_ICR_ORECF_Pos)          /*!< 0x00000008 */
11830 #define USART_ICR_ORECF                     USART_ICR_ORECF_Msk                     /*!< OverRun Error Clear Flag */
11831 #define USART_ICR_IDLECF_Pos                (4U)
11832 #define USART_ICR_IDLECF_Msk                (0x1UL << USART_ICR_IDLECF_Pos)         /*!< 0x00000010 */
11833 #define USART_ICR_IDLECF                    USART_ICR_IDLECF_Msk                    /*!< IDLE line detected Clear Flag */
11834 #define USART_ICR_TXFECF_Pos                (5U)
11835 #define USART_ICR_TXFECF_Msk                (0x1UL << USART_ICR_TXFECF_Pos)         /*!< 0x00000020 */
11836 #define USART_ICR_TXFECF                    USART_ICR_TXFECF_Msk                    /*!< TXFIFO empty Clear flag */
11837 #define USART_ICR_TCCF_Pos                  (6U)
11838 #define USART_ICR_TCCF_Msk                  (0x1UL << USART_ICR_TCCF_Pos)           /*!< 0x00000040 */
11839 #define USART_ICR_TCCF                      USART_ICR_TCCF_Msk                      /*!< Transmission Complete Clear Flag */
11840 #define USART_ICR_TCBGTCF_Pos               (7U)
11841 #define USART_ICR_TCBGTCF_Msk               (0x1UL << USART_ICR_TCBGTCF_Pos)        /*!< 0x00000080 */
11842 #define USART_ICR_TCBGTCF                   USART_ICR_TCBGTCF_Msk                   /*!< Transmission Complete Before Guard Time Clear Flag */
11843 #define USART_ICR_LBDCF_Pos                 (8U)
11844 #define USART_ICR_LBDCF_Msk                 (0x1UL << USART_ICR_LBDCF_Pos)          /*!< 0x00000100 */
11845 #define USART_ICR_LBDCF                     USART_ICR_LBDCF_Msk                     /*!< LIN Break Detection Clear Flag */
11846 #define USART_ICR_CTSCF_Pos                 (9U)
11847 #define USART_ICR_CTSCF_Msk                 (0x1UL << USART_ICR_CTSCF_Pos)          /*!< 0x00000200 */
11848 #define USART_ICR_CTSCF                     USART_ICR_CTSCF_Msk                     /*!< CTS Interrupt Clear Flag */
11849 #define USART_ICR_RTOCF_Pos                 (11U)
11850 #define USART_ICR_RTOCF_Msk                 (0x1UL << USART_ICR_RTOCF_Pos)          /*!< 0x00000800 */
11851 #define USART_ICR_RTOCF                     USART_ICR_RTOCF_Msk                     /*!< Receiver Time Out Clear Flag */
11852 #define USART_ICR_EOBCF_Pos                 (12U)
11853 #define USART_ICR_EOBCF_Msk                 (0x1UL << USART_ICR_EOBCF_Pos)          /*!< 0x00001000 */
11854 #define USART_ICR_EOBCF                     USART_ICR_EOBCF_Msk                     /*!< End Of Block Clear Flag */
11855 #define USART_ICR_UDRCF_Pos                 (13U)
11856 #define USART_ICR_UDRCF_Msk                 (0x1UL << USART_ICR_UDRCF_Pos)          /*!< 0x00002000 */
11857 #define USART_ICR_UDRCF                     USART_ICR_UDRCF_Msk                     /*!< SPI Slave Underrun Clear Flag */
11858 #define USART_ICR_CMCF_Pos                  (17U)
11859 #define USART_ICR_CMCF_Msk                  (0x1UL << USART_ICR_CMCF_Pos)           /*!< 0x00020000 */
11860 #define USART_ICR_CMCF                      USART_ICR_CMCF_Msk                      /*!< Character Match Clear Flag */
11861 #define USART_ICR_WUCF_Pos                  (20U)
11862 #define USART_ICR_WUCF_Msk                  (0x1UL << USART_ICR_WUCF_Pos)           /*!< 0x00100000 */
11863 #define USART_ICR_WUCF                      USART_ICR_WUCF_Msk                      /*!< Wake Up from stop mode Clear Flag */
11864 
11865 /*******************  Bit definition for USART_RDR register  ******************/
11866 #define USART_RDR_RDR                       ((uint16_t)0x01FF)                      /*!< RDR[8:0] bits (Receive Data value) */
11867 
11868 /*******************  Bit definition for USART_TDR register  ******************/
11869 #define USART_TDR_TDR                       ((uint16_t)0x01FF)                      /*!< TDR[8:0] bits (Transmit Data value) */
11870 
11871 /*******************  Bit definition for USART_PRESC register  ****************/
11872 #define USART_PRESC_PRESCALER_Pos           (0U)
11873 #define USART_PRESC_PRESCALER_Msk           (0xFUL << USART_PRESC_PRESCALER_Pos)    /*!< 0x0000000F */
11874 #define USART_PRESC_PRESCALER               USART_PRESC_PRESCALER_Msk               /*!< PRESCALER[3:0] bits (Clock prescaler) */
11875 #define USART_PRESC_PRESCALER_0             (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
11876 #define USART_PRESC_PRESCALER_1             (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
11877 #define USART_PRESC_PRESCALER_2             (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
11878 #define USART_PRESC_PRESCALER_3             (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
11879 
11880 /*******************  Bit definition for USART_HWCFGR2 register  **************/
11881 #define USART_HWCFGR2_CFG1_Pos              (0U)
11882 #define USART_HWCFGR2_CFG1_Msk              (0xFUL << USART_HWCFGR2_CFG1_Pos)       /*!< 0x0000000F */
11883 #define USART_HWCFGR2_CFG1                  USART_HWCFGR2_CFG1_Msk                  /*!< CFG1[3:0] bits (USART hardware configuration 1) */
11884 #define USART_HWCFGR2_CFG2_Pos              (4U)
11885 #define USART_HWCFGR2_CFG2_Msk              (0xFUL << USART_HWCFGR2_CFG2_Pos)       /*!< 0x000000F0 */
11886 #define USART_HWCFGR2_CFG2                  USART_HWCFGR2_CFG2_Msk                  /*!< CFG2[7:4] bits (USART hardware configuration 2) */
11887 
11888 /*******************  Bit definition for USART_HWCFGR1 register  **************/
11889 #define USART_HWCFGR1_CFG1_Pos              (0U)
11890 #define USART_HWCFGR1_CFG1_Msk              (0xFUL << USART_HWCFGR1_CFG1_Pos)       /*!< 0x0000000F */
11891 #define USART_HWCFGR1_CFG1                  USART_HWCFGR1_CFG1_Msk                  /*!< CFG1[3:0] bits (USART hardware configuration 1) */
11892 #define USART_HWCFGR1_CFG2_Pos              (4U)
11893 #define USART_HWCFGR1_CFG2_Msk              (0xFUL << USART_HWCFGR1_CFG2_Pos)       /*!< 0x000000F0 */
11894 #define USART_HWCFGR1_CFG2                  USART_HWCFGR1_CFG2_Msk                  /*!< CFG2[7:4] bits (USART hardware configuration 2) */
11895 #define USART_HWCFGR1_CFG3_Pos              (8U)
11896 #define USART_HWCFGR1_CFG3_Msk              (0xFUL << USART_HWCFGR1_CFG3_Pos)       /*!< 0x00000F00 */
11897 #define USART_HWCFGR1_CFG3                  USART_HWCFGR1_CFG3_Msk                  /*!< CFG3[11:8] bits (USART hardware configuration 3) */
11898 #define USART_HWCFGR1_CFG4_Pos              (12U)
11899 #define USART_HWCFGR1_CFG4_Msk              (0xFUL << USART_HWCFGR1_CFG4_Pos)       /*!< 0x0000F000 */
11900 #define USART_HWCFGR1_CFG4                  USART_HWCFGR1_CFG4_Msk                  /*!< CFG4[15:12] bits (USART hardware configuration 4) */
11901 #define USART_HWCFGR1_CFG5_Pos              (16U)
11902 #define USART_HWCFGR1_CFG5_Msk              (0xFUL << USART_HWCFGR1_CFG5_Pos)       /*!< 0x000F0000 */
11903 #define USART_HWCFGR1_CFG5                  USART_HWCFGR1_CFG5_Msk                  /*!< CFG5[19:16] bits (USART hardware configuration 5) */
11904 #define USART_HWCFGR1_CFG6_Pos              (20U)
11905 #define USART_HWCFGR1_CFG6_Msk              (0xFUL << USART_HWCFGR1_CFG6_Pos)       /*!< 0x00F00000 */
11906 #define USART_HWCFGR1_CFG6                  USART_HWCFGR1_CFG6_Msk                  /*!< CFG6[23:20] bits (USART hardware configuration 6) */
11907 #define USART_HWCFGR1_CFG7_Pos              (24U)
11908 #define USART_HWCFGR1_CFG7_Msk              (0xFUL << USART_HWCFGR1_CFG7_Pos)       /*!< 0x0F000000 */
11909 #define USART_HWCFGR1_CFG7                  USART_HWCFGR1_CFG7_Msk                  /*!< CFG7[27:24] bits (USART hardware configuration 7) */
11910 #define USART_HWCFGR1_CFG8_Pos              (28U)
11911 #define USART_HWCFGR1_CFG8_Msk              (0xFUL << USART_HWCFGR1_CFG8_Pos)       /*!< 0xF0000000 */
11912 #define USART_HWCFGR1_CFG8                  USART_HWCFGR1_CFG8_Msk                  /*!< CFG8[31:28] bits (USART hardware configuration 8) */
11913 
11914 /*******************  Bit definition for USART_VERR register  *****************/
11915 #define USART_VERR_MINREV_Pos               (0U)
11916 #define USART_VERR_MINREV_Msk               (0xFUL << USART_VERR_MINREV_Pos)        /*!< 0x0000000F */
11917 #define USART_VERR_MINREV                   USART_VERR_MINREV_Msk                   /*!< MAJREV[3:0] bits (Minor revision) */
11918 #define USART_VERR_MAJREV_Pos               (4U)
11919 #define USART_VERR_MAJREV_Msk               (0xFUL << USART_VERR_MAJREV_Pos)        /*!< 0x000000F0 */
11920 #define USART_VERR_MAJREV                   USART_VERR_MAJREV_Msk                   /*!< MINREV[3:0] bits (Major revision) */
11921 
11922 /*******************  Bit definition for USART_IPIDR register  ****************/
11923 #define USART_IPIDR_ID_Pos                  (0U)
11924 #define USART_IPIDR_ID_Msk                  (0xFFFFFFFFUL << USART_IPIDR_ID_Pos)    /*!< 0xFFFFFFFF */
11925 #define USART_IPIDR_ID                      USART_IPIDR_ID_Msk                      /*!< ID[31:0] bits (Peripheral identifier) */
11926 
11927 /*******************  Bit definition for USART_SIDR register  ****************/
11928 #define USART_SIDR_ID_Pos                   (0U)
11929 #define USART_SIDR_ID_Msk                   (0xFFFFFFFFUL << USART_SIDR_ID_Pos)     /*!< 0xFFFFFFFF */
11930 #define USART_SIDR_ID                       USART_SIDR_ID_Msk                       /*!< SID[31:0] bits (Size identification) */
11931 
11932 
11933 /******************************************************************************/
11934 /*                                                                            */
11935 /*                      Inter-integrated Circuit Interface (I2C)              */
11936 /*                                                                            */
11937 /******************************************************************************/
11938 /*******************  Bit definition for I2C_CR1 register  *******************/
11939 #define I2C_CR1_PE_Pos                      (0U)
11940 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)               /*!< 0x00000001 */
11941 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                          /*!< Peripheral enable */
11942 #define I2C_CR1_TXIE_Pos                    (1U)
11943 #define I2C_CR1_TXIE_Msk                    (0x1UL << I2C_CR1_TXIE_Pos)             /*!< 0x00000002 */
11944 #define I2C_CR1_TXIE                        I2C_CR1_TXIE_Msk                        /*!< TX interrupt enable */
11945 #define I2C_CR1_RXIE_Pos                    (2U)
11946 #define I2C_CR1_RXIE_Msk                    (0x1UL << I2C_CR1_RXIE_Pos)             /*!< 0x00000004 */
11947 #define I2C_CR1_RXIE                        I2C_CR1_RXIE_Msk                        /*!< RX interrupt enable */
11948 #define I2C_CR1_ADDRIE_Pos                  (3U)
11949 #define I2C_CR1_ADDRIE_Msk                  (0x1UL << I2C_CR1_ADDRIE_Pos)           /*!< 0x00000008 */
11950 #define I2C_CR1_ADDRIE                      I2C_CR1_ADDRIE_Msk                      /*!< Address match interrupt enable */
11951 #define I2C_CR1_NACKIE_Pos                  (4U)
11952 #define I2C_CR1_NACKIE_Msk                  (0x1UL << I2C_CR1_NACKIE_Pos)           /*!< 0x00000010 */
11953 #define I2C_CR1_NACKIE                      I2C_CR1_NACKIE_Msk                      /*!< NACK received interrupt enable */
11954 #define I2C_CR1_STOPIE_Pos                  (5U)
11955 #define I2C_CR1_STOPIE_Msk                  (0x1UL << I2C_CR1_STOPIE_Pos)           /*!< 0x00000020 */
11956 #define I2C_CR1_STOPIE                      I2C_CR1_STOPIE_Msk                      /*!< STOP detection interrupt enable */
11957 #define I2C_CR1_TCIE_Pos                    (6U)
11958 #define I2C_CR1_TCIE_Msk                    (0x1UL << I2C_CR1_TCIE_Pos)             /*!< 0x00000040 */
11959 #define I2C_CR1_TCIE                        I2C_CR1_TCIE_Msk                        /*!< Transfer complete interrupt enable */
11960 #define I2C_CR1_ERRIE_Pos                   (7U)
11961 #define I2C_CR1_ERRIE_Msk                   (0x1UL << I2C_CR1_ERRIE_Pos)            /*!< 0x00000080 */
11962 #define I2C_CR1_ERRIE                       I2C_CR1_ERRIE_Msk                       /*!< Errors interrupt enable */
11963 #define I2C_CR1_DNF_Pos                     (8U)
11964 #define I2C_CR1_DNF_Msk                     (0xFUL << I2C_CR1_DNF_Pos)              /*!< 0x00000F00 */
11965 #define I2C_CR1_DNF                         I2C_CR1_DNF_Msk                         /*!< Digital noise filter */
11966 #define I2C_CR1_ANFOFF_Pos                  (12U)
11967 #define I2C_CR1_ANFOFF_Msk                  (0x1UL << I2C_CR1_ANFOFF_Pos)           /*!< 0x00001000 */
11968 #define I2C_CR1_ANFOFF                      I2C_CR1_ANFOFF_Msk                      /*!< Analog noise filter OFF */
11969 #define I2C_CR1_SWRST_Pos                   (13U)
11970 #define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)            /*!< 0x00002000 */
11971 #define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                       /*!< Software reset */
11972 #define I2C_CR1_TXDMAEN_Pos                 (14U)
11973 #define I2C_CR1_TXDMAEN_Msk                 (0x1UL << I2C_CR1_TXDMAEN_Pos)          /*!< 0x00004000 */
11974 #define I2C_CR1_TXDMAEN                     I2C_CR1_TXDMAEN_Msk                     /*!< DMA transmission requests enable */
11975 #define I2C_CR1_RXDMAEN_Pos                 (15U)
11976 #define I2C_CR1_RXDMAEN_Msk                 (0x1UL << I2C_CR1_RXDMAEN_Pos)          /*!< 0x00008000 */
11977 #define I2C_CR1_RXDMAEN                     I2C_CR1_RXDMAEN_Msk                     /*!< DMA reception requests enable */
11978 #define I2C_CR1_SBC_Pos                     (16U)
11979 #define I2C_CR1_SBC_Msk                     (0x1UL << I2C_CR1_SBC_Pos)              /*!< 0x00010000 */
11980 #define I2C_CR1_SBC                         I2C_CR1_SBC_Msk                         /*!< Slave byte control */
11981 #define I2C_CR1_NOSTRETCH_Pos               (17U)
11982 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)        /*!< 0x00020000 */
11983 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk                   /*!< Clock stretching disable */
11984 #define I2C_CR1_WUPEN_Pos                   (18U)
11985 #define I2C_CR1_WUPEN_Msk                   (0x1UL << I2C_CR1_WUPEN_Pos)            /*!< 0x00040000 */
11986 #define I2C_CR1_WUPEN                       I2C_CR1_WUPEN_Msk                       /*!< Wakeup from STOP enable */
11987 #define I2C_CR1_GCEN_Pos                    (19U)
11988 #define I2C_CR1_GCEN_Msk                    (0x1UL << I2C_CR1_GCEN_Pos)             /*!< 0x00080000 */
11989 #define I2C_CR1_GCEN                        I2C_CR1_GCEN_Msk                        /*!< General call enable */
11990 #define I2C_CR1_SMBHEN_Pos                  (20U)
11991 #define I2C_CR1_SMBHEN_Msk                  (0x1UL << I2C_CR1_SMBHEN_Pos)           /*!< 0x00100000 */
11992 #define I2C_CR1_SMBHEN                      I2C_CR1_SMBHEN_Msk                      /*!< SMBus host address enable */
11993 #define I2C_CR1_SMBDEN_Pos                  (21U)
11994 #define I2C_CR1_SMBDEN_Msk                  (0x1UL << I2C_CR1_SMBDEN_Pos)           /*!< 0x00200000 */
11995 #define I2C_CR1_SMBDEN                      I2C_CR1_SMBDEN_Msk                      /*!< SMBus device default address enable */
11996 #define I2C_CR1_ALERTEN_Pos                 (22U)
11997 #define I2C_CR1_ALERTEN_Msk                 (0x1UL << I2C_CR1_ALERTEN_Pos)          /*!< 0x00400000 */
11998 #define I2C_CR1_ALERTEN                     I2C_CR1_ALERTEN_Msk                     /*!< SMBus alert enable */
11999 #define I2C_CR1_PECEN_Pos                   (23U)
12000 #define I2C_CR1_PECEN_Msk                   (0x1UL << I2C_CR1_PECEN_Pos)            /*!< 0x00800000 */
12001 #define I2C_CR1_PECEN                       I2C_CR1_PECEN_Msk                       /*!< PEC enable */
12002 #define I2C_CR1_FMP_Pos                     (24U)
12003 #define I2C_CR1_FMP_Msk                     (0x1UL << I2C_CR1_FMP_Pos)            /*!< 0x01000000 */
12004 #define I2C_CR1_FMP                         I2C_CR1_FMP_Msk                       /*!< Fast-mode Plus 20 mA drive enable */
12005 #define I2C_CR1_ADDRACLR_Pos                (30U)
12006 #define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
12007 #define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
12008 #define I2C_CR1_STOPFACLR_Pos               (31U)
12009 #define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
12010 #define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
12011 
12012 /******************  Bit definition for I2C_CR2 register  ********************/
12013 #define I2C_CR2_SADD_Pos                    (0U)
12014 #define I2C_CR2_SADD_Msk                    (0x3FFUL << I2C_CR2_SADD_Pos)           /*!< 0x000003FF */
12015 #define I2C_CR2_SADD                        I2C_CR2_SADD_Msk                        /*!< Slave address (master mode) */
12016 #define I2C_CR2_RD_WRN_Pos                  (10U)
12017 #define I2C_CR2_RD_WRN_Msk                  (0x1UL << I2C_CR2_RD_WRN_Pos)           /*!< 0x00000400 */
12018 #define I2C_CR2_RD_WRN                      I2C_CR2_RD_WRN_Msk                      /*!< Transfer direction (master mode) */
12019 #define I2C_CR2_ADD10_Pos                   (11U)
12020 #define I2C_CR2_ADD10_Msk                   (0x1UL << I2C_CR2_ADD10_Pos)            /*!< 0x00000800 */
12021 #define I2C_CR2_ADD10                       I2C_CR2_ADD10_Msk                       /*!< 10-bit addressing mode (master mode) */
12022 #define I2C_CR2_HEAD10R_Pos                 (12U)
12023 #define I2C_CR2_HEAD10R_Msk                 (0x1UL << I2C_CR2_HEAD10R_Pos)          /*!< 0x00001000 */
12024 #define I2C_CR2_HEAD10R                     I2C_CR2_HEAD10R_Msk                     /*!< 10-bit address header only read direction (master mode) */
12025 #define I2C_CR2_START_Pos                   (13U)
12026 #define I2C_CR2_START_Msk                   (0x1UL << I2C_CR2_START_Pos)            /*!< 0x00002000 */
12027 #define I2C_CR2_START                       I2C_CR2_START_Msk                       /*!< START generation */
12028 #define I2C_CR2_STOP_Pos                    (14U)
12029 #define I2C_CR2_STOP_Msk                    (0x1UL << I2C_CR2_STOP_Pos)             /*!< 0x00004000 */
12030 #define I2C_CR2_STOP                        I2C_CR2_STOP_Msk                        /*!< STOP generation (master mode) */
12031 #define I2C_CR2_NACK_Pos                    (15U)
12032 #define I2C_CR2_NACK_Msk                    (0x1UL << I2C_CR2_NACK_Pos)             /*!< 0x00008000 */
12033 #define I2C_CR2_NACK                        I2C_CR2_NACK_Msk                        /*!< NACK generation (slave mode) */
12034 #define I2C_CR2_NBYTES_Pos                  (16U)
12035 #define I2C_CR2_NBYTES_Msk                  (0xFFUL << I2C_CR2_NBYTES_Pos)          /*!< 0x00FF0000 */
12036 #define I2C_CR2_NBYTES                      I2C_CR2_NBYTES_Msk                      /*!< Number of bytes */
12037 #define I2C_CR2_RELOAD_Pos                  (24U)
12038 #define I2C_CR2_RELOAD_Msk                  (0x1UL << I2C_CR2_RELOAD_Pos)           /*!< 0x01000000 */
12039 #define I2C_CR2_RELOAD                      I2C_CR2_RELOAD_Msk                      /*!< NBYTES reload mode */
12040 #define I2C_CR2_AUTOEND_Pos                 (25U)
12041 #define I2C_CR2_AUTOEND_Msk                 (0x1UL << I2C_CR2_AUTOEND_Pos)          /*!< 0x02000000 */
12042 #define I2C_CR2_AUTOEND                     I2C_CR2_AUTOEND_Msk                     /*!< Automatic end mode (master mode) */
12043 #define I2C_CR2_PECBYTE_Pos                 (26U)
12044 #define I2C_CR2_PECBYTE_Msk                 (0x1UL << I2C_CR2_PECBYTE_Pos)          /*!< 0x04000000 */
12045 #define I2C_CR2_PECBYTE                     I2C_CR2_PECBYTE_Msk                     /*!< Packet error checking byte */
12046 
12047 /*******************  Bit definition for I2C_OAR1 register  ******************/
12048 #define I2C_OAR1_OA1_Pos                    (0U)
12049 #define I2C_OAR1_OA1_Msk                    (0x3FFUL << I2C_OAR1_OA1_Pos)           /*!< 0x000003FF */
12050 #define I2C_OAR1_OA1                        I2C_OAR1_OA1_Msk                        /*!< Interface own address 1 */
12051 #define I2C_OAR1_OA1MODE_Pos                (10U)
12052 #define I2C_OAR1_OA1MODE_Msk                (0x1UL << I2C_OAR1_OA1MODE_Pos)         /*!< 0x00000400 */
12053 #define I2C_OAR1_OA1MODE                    I2C_OAR1_OA1MODE_Msk                    /*!< Own address 1 10-bit mode */
12054 #define I2C_OAR1_OA1EN_Pos                  (15U)
12055 #define I2C_OAR1_OA1EN_Msk                  (0x1UL << I2C_OAR1_OA1EN_Pos)           /*!< 0x00008000 */
12056 #define I2C_OAR1_OA1EN                      I2C_OAR1_OA1EN_Msk                      /*!< Own address 1 enable */
12057 
12058 /*******************  Bit definition for I2C_OAR2 register  ******************/
12059 #define I2C_OAR2_OA2_Pos                    (1U)
12060 #define I2C_OAR2_OA2_Msk                    (0x7FUL << I2C_OAR2_OA2_Pos)            /*!< 0x000000FE */
12061 #define I2C_OAR2_OA2                        I2C_OAR2_OA2_Msk                        /*!< Interface own address 2 */
12062 #define I2C_OAR2_OA2MSK_Pos                 (8U)
12063 #define I2C_OAR2_OA2MSK_Msk                 (0x7UL << I2C_OAR2_OA2MSK_Pos)          /*!< 0x00000700 */
12064 #define I2C_OAR2_OA2MSK                     I2C_OAR2_OA2MSK_Msk                     /*!< Own address 2 masks */
12065 #define I2C_OAR2_OA2NOMASK                  (0x00000000UL)                          /*!< No mask                                        */
12066 #define I2C_OAR2_OA2MASK01_Pos              (8U)
12067 #define I2C_OAR2_OA2MASK01_Msk              (0x1UL << I2C_OAR2_OA2MASK01_Pos)       /*!< 0x00000100 */
12068 #define I2C_OAR2_OA2MASK01                  I2C_OAR2_OA2MASK01_Msk                  /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
12069 #define I2C_OAR2_OA2MASK02_Pos              (9U)
12070 #define I2C_OAR2_OA2MASK02_Msk              (0x1UL << I2C_OAR2_OA2MASK02_Pos)       /*!< 0x00000200 */
12071 #define I2C_OAR2_OA2MASK02                  I2C_OAR2_OA2MASK02_Msk                  /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
12072 #define I2C_OAR2_OA2MASK03_Pos              (8U)
12073 #define I2C_OAR2_OA2MASK03_Msk              (0x3UL << I2C_OAR2_OA2MASK03_Pos)       /*!< 0x00000300 */
12074 #define I2C_OAR2_OA2MASK03                  I2C_OAR2_OA2MASK03_Msk                  /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
12075 #define I2C_OAR2_OA2MASK04_Pos              (10U)
12076 #define I2C_OAR2_OA2MASK04_Msk              (0x1UL << I2C_OAR2_OA2MASK04_Pos)       /*!< 0x00000400 */
12077 #define I2C_OAR2_OA2MASK04                  I2C_OAR2_OA2MASK04_Msk                  /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
12078 #define I2C_OAR2_OA2MASK05_Pos              (8U)
12079 #define I2C_OAR2_OA2MASK05_Msk              (0x5UL << I2C_OAR2_OA2MASK05_Pos)       /*!< 0x00000500 */
12080 #define I2C_OAR2_OA2MASK05                  I2C_OAR2_OA2MASK05_Msk                  /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
12081 #define I2C_OAR2_OA2MASK06_Pos              (9U)
12082 #define I2C_OAR2_OA2MASK06_Msk              (0x3UL << I2C_OAR2_OA2MASK06_Pos)       /*!< 0x00000600 */
12083 #define I2C_OAR2_OA2MASK06                  I2C_OAR2_OA2MASK06_Msk                  /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
12084 #define I2C_OAR2_OA2MASK07_Pos              (8U)
12085 #define I2C_OAR2_OA2MASK07_Msk              (0x7UL << I2C_OAR2_OA2MASK07_Pos)       /*!< 0x00000700 */
12086 #define I2C_OAR2_OA2MASK07                  I2C_OAR2_OA2MASK07_Msk                  /*!< OA2[7:1] is masked, No comparison is done      */
12087 #define I2C_OAR2_OA2EN_Pos                  (15U)
12088 #define I2C_OAR2_OA2EN_Msk                  (0x1UL << I2C_OAR2_OA2EN_Pos)           /*!< 0x00008000 */
12089 #define I2C_OAR2_OA2EN                      I2C_OAR2_OA2EN_Msk                      /*!< Own address 2 enable */
12090 
12091 /*******************  Bit definition for I2C_TIMINGR register *******************/
12092 #define I2C_TIMINGR_SCLL_Pos                (0U)
12093 #define I2C_TIMINGR_SCLL_Msk                (0xFFUL << I2C_TIMINGR_SCLL_Pos)        /*!< 0x000000FF */
12094 #define I2C_TIMINGR_SCLL                    I2C_TIMINGR_SCLL_Msk                    /*!< SCL low period (master mode) */
12095 #define I2C_TIMINGR_SCLH_Pos                (8U)
12096 #define I2C_TIMINGR_SCLH_Msk                (0xFFUL << I2C_TIMINGR_SCLH_Pos)        /*!< 0x0000FF00 */
12097 #define I2C_TIMINGR_SCLH                    I2C_TIMINGR_SCLH_Msk                    /*!< SCL high period (master mode) */
12098 #define I2C_TIMINGR_SDADEL_Pos              (16U)
12099 #define I2C_TIMINGR_SDADEL_Msk              (0xFUL << I2C_TIMINGR_SDADEL_Pos)       /*!< 0x000F0000 */
12100 #define I2C_TIMINGR_SDADEL                  I2C_TIMINGR_SDADEL_Msk                  /*!< Data hold time */
12101 #define I2C_TIMINGR_SCLDEL_Pos              (20U)
12102 #define I2C_TIMINGR_SCLDEL_Msk              (0xFUL << I2C_TIMINGR_SCLDEL_Pos)       /*!< 0x00F00000 */
12103 #define I2C_TIMINGR_SCLDEL                  I2C_TIMINGR_SCLDEL_Msk                  /*!< Data setup time */
12104 #define I2C_TIMINGR_PRESC_Pos               (28U)
12105 #define I2C_TIMINGR_PRESC_Msk               (0xFUL << I2C_TIMINGR_PRESC_Pos)        /*!< 0xF0000000 */
12106 #define I2C_TIMINGR_PRESC                   I2C_TIMINGR_PRESC_Msk                   /*!< Timings prescaler */
12107 
12108 /******************* Bit definition for I2C_TIMEOUTR register *******************/
12109 #define I2C_TIMEOUTR_TIMEOUTA_Pos           (0U)
12110 #define I2C_TIMEOUTR_TIMEOUTA_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)  /*!< 0x00000FFF */
12111 #define I2C_TIMEOUTR_TIMEOUTA               I2C_TIMEOUTR_TIMEOUTA_Msk               /*!< Bus timeout A */
12112 #define I2C_TIMEOUTR_TIDLE_Pos              (12U)
12113 #define I2C_TIMEOUTR_TIDLE_Msk              (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)       /*!< 0x00001000 */
12114 #define I2C_TIMEOUTR_TIDLE                  I2C_TIMEOUTR_TIDLE_Msk                  /*!< Idle clock timeout detection */
12115 #define I2C_TIMEOUTR_TIMOUTEN_Pos           (15U)
12116 #define I2C_TIMEOUTR_TIMOUTEN_Msk           (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)    /*!< 0x00008000 */
12117 #define I2C_TIMEOUTR_TIMOUTEN               I2C_TIMEOUTR_TIMOUTEN_Msk               /*!< Clock timeout enable */
12118 #define I2C_TIMEOUTR_TIMEOUTB_Pos           (16U)
12119 #define I2C_TIMEOUTR_TIMEOUTB_Msk           (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)  /*!< 0x0FFF0000 */
12120 #define I2C_TIMEOUTR_TIMEOUTB               I2C_TIMEOUTR_TIMEOUTB_Msk               /*!< Bus timeout B*/
12121 #define I2C_TIMEOUTR_TEXTEN_Pos             (31U)
12122 #define I2C_TIMEOUTR_TEXTEN_Msk             (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)      /*!< 0x80000000 */
12123 #define I2C_TIMEOUTR_TEXTEN                 I2C_TIMEOUTR_TEXTEN_Msk                 /*!< Extended clock timeout enable */
12124 
12125 /******************  Bit definition for I2C_ISR register  *********************/
12126 #define I2C_ISR_TXE_Pos                     (0U)
12127 #define I2C_ISR_TXE_Msk                     (0x1UL << I2C_ISR_TXE_Pos)              /*!< 0x00000001 */
12128 #define I2C_ISR_TXE                         I2C_ISR_TXE_Msk                         /*!< Transmit data register empty */
12129 #define I2C_ISR_TXIS_Pos                    (1U)
12130 #define I2C_ISR_TXIS_Msk                    (0x1UL << I2C_ISR_TXIS_Pos)             /*!< 0x00000002 */
12131 #define I2C_ISR_TXIS                        I2C_ISR_TXIS_Msk                        /*!< Transmit interrupt status */
12132 #define I2C_ISR_RXNE_Pos                    (2U)
12133 #define I2C_ISR_RXNE_Msk                    (0x1UL << I2C_ISR_RXNE_Pos)             /*!< 0x00000004 */
12134 #define I2C_ISR_RXNE                        I2C_ISR_RXNE_Msk                        /*!< Receive data register not empty */
12135 #define I2C_ISR_ADDR_Pos                    (3U)
12136 #define I2C_ISR_ADDR_Msk                    (0x1UL << I2C_ISR_ADDR_Pos)             /*!< 0x00000008 */
12137 #define I2C_ISR_ADDR                        I2C_ISR_ADDR_Msk                        /*!< Address matched (slave mode)*/
12138 #define I2C_ISR_NACKF_Pos                   (4U)
12139 #define I2C_ISR_NACKF_Msk                   (0x1UL << I2C_ISR_NACKF_Pos)            /*!< 0x00000010 */
12140 #define I2C_ISR_NACKF                       I2C_ISR_NACKF_Msk                       /*!< NACK received flag */
12141 #define I2C_ISR_STOPF_Pos                   (5U)
12142 #define I2C_ISR_STOPF_Msk                   (0x1UL << I2C_ISR_STOPF_Pos)            /*!< 0x00000020 */
12143 #define I2C_ISR_STOPF                       I2C_ISR_STOPF_Msk                       /*!< STOP detection flag */
12144 #define I2C_ISR_TC_Pos                      (6U)
12145 #define I2C_ISR_TC_Msk                      (0x1UL << I2C_ISR_TC_Pos)               /*!< 0x00000040 */
12146 #define I2C_ISR_TC                          I2C_ISR_TC_Msk                          /*!< Transfer complete (master mode) */
12147 #define I2C_ISR_TCR_Pos                     (7U)
12148 #define I2C_ISR_TCR_Msk                     (0x1UL << I2C_ISR_TCR_Pos)              /*!< 0x00000080 */
12149 #define I2C_ISR_TCR                         I2C_ISR_TCR_Msk                         /*!< Transfer complete reload */
12150 #define I2C_ISR_BERR_Pos                    (8U)
12151 #define I2C_ISR_BERR_Msk                    (0x1UL << I2C_ISR_BERR_Pos)             /*!< 0x00000100 */
12152 #define I2C_ISR_BERR                        I2C_ISR_BERR_Msk                        /*!< Bus error */
12153 #define I2C_ISR_ARLO_Pos                    (9U)
12154 #define I2C_ISR_ARLO_Msk                    (0x1UL << I2C_ISR_ARLO_Pos)             /*!< 0x00000200 */
12155 #define I2C_ISR_ARLO                        I2C_ISR_ARLO_Msk                        /*!< Arbitration lost */
12156 #define I2C_ISR_OVR_Pos                     (10U)
12157 #define I2C_ISR_OVR_Msk                     (0x1UL << I2C_ISR_OVR_Pos)              /*!< 0x00000400 */
12158 #define I2C_ISR_OVR                         I2C_ISR_OVR_Msk                         /*!< Overrun/Underrun */
12159 #define I2C_ISR_PECERR_Pos                  (11U)
12160 #define I2C_ISR_PECERR_Msk                  (0x1UL << I2C_ISR_PECERR_Pos)           /*!< 0x00000800 */
12161 #define I2C_ISR_PECERR                      I2C_ISR_PECERR_Msk                      /*!< PEC error in reception */
12162 #define I2C_ISR_TIMEOUT_Pos                 (12U)
12163 #define I2C_ISR_TIMEOUT_Msk                 (0x1UL << I2C_ISR_TIMEOUT_Pos)          /*!< 0x00001000 */
12164 #define I2C_ISR_TIMEOUT                     I2C_ISR_TIMEOUT_Msk                     /*!< Timeout or Tlow detection flag */
12165 #define I2C_ISR_ALERT_Pos                   (13U)
12166 #define I2C_ISR_ALERT_Msk                   (0x1UL << I2C_ISR_ALERT_Pos)            /*!< 0x00002000 */
12167 #define I2C_ISR_ALERT                       I2C_ISR_ALERT_Msk                       /*!< SMBus alert */
12168 #define I2C_ISR_BUSY_Pos                    (15U)
12169 #define I2C_ISR_BUSY_Msk                    (0x1UL << I2C_ISR_BUSY_Pos)             /*!< 0x00008000 */
12170 #define I2C_ISR_BUSY                        I2C_ISR_BUSY_Msk                        /*!< Bus busy */
12171 #define I2C_ISR_DIR_Pos                     (16U)
12172 #define I2C_ISR_DIR_Msk                     (0x1UL << I2C_ISR_DIR_Pos)              /*!< 0x00010000 */
12173 #define I2C_ISR_DIR                         I2C_ISR_DIR_Msk                         /*!< Transfer direction (slave mode) */
12174 #define I2C_ISR_ADDCODE_Pos                 (17U)
12175 #define I2C_ISR_ADDCODE_Msk                 (0x7FUL << I2C_ISR_ADDCODE_Pos)         /*!< 0x00FE0000 */
12176 #define I2C_ISR_ADDCODE                     I2C_ISR_ADDCODE_Msk                     /*!< Address match code (slave mode) */
12177 
12178 /******************  Bit definition for I2C_ICR register  *********************/
12179 #define I2C_ICR_ADDRCF_Pos                  (3U)
12180 #define I2C_ICR_ADDRCF_Msk                  (0x1UL << I2C_ICR_ADDRCF_Pos)           /*!< 0x00000008 */
12181 #define I2C_ICR_ADDRCF                      I2C_ICR_ADDRCF_Msk                      /*!< Address matched clear flag */
12182 #define I2C_ICR_NACKCF_Pos                  (4U)
12183 #define I2C_ICR_NACKCF_Msk                  (0x1UL << I2C_ICR_NACKCF_Pos)           /*!< 0x00000010 */
12184 #define I2C_ICR_NACKCF                      I2C_ICR_NACKCF_Msk                      /*!< NACK clear flag */
12185 #define I2C_ICR_STOPCF_Pos                  (5U)
12186 #define I2C_ICR_STOPCF_Msk                  (0x1UL << I2C_ICR_STOPCF_Pos)           /*!< 0x00000020 */
12187 #define I2C_ICR_STOPCF                      I2C_ICR_STOPCF_Msk                      /*!< STOP detection clear flag */
12188 #define I2C_ICR_BERRCF_Pos                  (8U)
12189 #define I2C_ICR_BERRCF_Msk                  (0x1UL << I2C_ICR_BERRCF_Pos)           /*!< 0x00000100 */
12190 #define I2C_ICR_BERRCF                      I2C_ICR_BERRCF_Msk                      /*!< Bus error clear flag */
12191 #define I2C_ICR_ARLOCF_Pos                  (9U)
12192 #define I2C_ICR_ARLOCF_Msk                  (0x1UL << I2C_ICR_ARLOCF_Pos)           /*!< 0x00000200 */
12193 #define I2C_ICR_ARLOCF                      I2C_ICR_ARLOCF_Msk                      /*!< Arbitration lost clear flag */
12194 #define I2C_ICR_OVRCF_Pos                   (10U)
12195 #define I2C_ICR_OVRCF_Msk                   (0x1UL << I2C_ICR_OVRCF_Pos)            /*!< 0x00000400 */
12196 #define I2C_ICR_OVRCF                       I2C_ICR_OVRCF_Msk                       /*!< Overrun/Underrun clear flag */
12197 #define I2C_ICR_PECCF_Pos                   (11U)
12198 #define I2C_ICR_PECCF_Msk                   (0x1UL << I2C_ICR_PECCF_Pos)            /*!< 0x00000800 */
12199 #define I2C_ICR_PECCF                       I2C_ICR_PECCF_Msk                       /*!< PAC error clear flag */
12200 #define I2C_ICR_TIMOUTCF_Pos                (12U)
12201 #define I2C_ICR_TIMOUTCF_Msk                (0x1UL << I2C_ICR_TIMOUTCF_Pos)         /*!< 0x00001000 */
12202 #define I2C_ICR_TIMOUTCF                    I2C_ICR_TIMOUTCF_Msk                    /*!< Timeout clear flag */
12203 #define I2C_ICR_ALERTCF_Pos                 (13U)
12204 #define I2C_ICR_ALERTCF_Msk                 (0x1UL << I2C_ICR_ALERTCF_Pos)          /*!< 0x00002000 */
12205 #define I2C_ICR_ALERTCF                     I2C_ICR_ALERTCF_Msk                     /*!< Alert clear flag */
12206 
12207 /******************  Bit definition for I2C_PECR register  *********************/
12208 #define I2C_PECR_PEC_Pos                    (0U)
12209 #define I2C_PECR_PEC_Msk                    (0xFFUL << I2C_PECR_PEC_Pos)            /*!< 0x000000FF */
12210 #define I2C_PECR_PEC                        I2C_PECR_PEC_Msk                        /*!< PEC register */
12211 
12212 /******************  Bit definition for I2C_RXDR register  *********************/
12213 #define I2C_RXDR_RXDATA_Pos                 (0U)
12214 #define I2C_RXDR_RXDATA_Msk                 (0xFFUL << I2C_RXDR_RXDATA_Pos)         /*!< 0x000000FF */
12215 #define I2C_RXDR_RXDATA                     I2C_RXDR_RXDATA_Msk                     /*!< 8-bit receive data */
12216 
12217 /******************  Bit definition for I2C_TXDR register  *********************/
12218 #define I2C_TXDR_TXDATA_Pos                 (0U)
12219 #define I2C_TXDR_TXDATA_Msk                 (0xFFUL << I2C_TXDR_TXDATA_Pos)         /*!< 0x000000FF */
12220 #define I2C_TXDR_TXDATA                     I2C_TXDR_TXDATA_Msk                     /*!< 8-bit transmit data */
12221 
12222 
12223 /******************************************************************************/
12224 /*                                                                            */
12225 /*             Improved Inter-integrated Circuit Interface (I3C)              */
12226 /*                                                                            */
12227 /******************************************************************************/
12228 /*******************  Bit definition for I3C_CR register  *********************/
12229 #define I3C_CR_DCNT_Pos                     (0U)
12230 #define I3C_CR_DCNT_Msk                     (0xFFFFUL << I3C_CR_DCNT_Pos)           /*!< 0x0000FFFF */
12231 #define I3C_CR_DCNT                         I3C_CR_DCNT_Msk                         /*!< Data Byte Count */
12232 #define I3C_CR_RNW_Pos                      (16U)
12233 #define I3C_CR_RNW_Msk                      (0x1UL << I3C_CR_RNW_Pos)               /*!< 0x00010000 */
12234 #define I3C_CR_RNW                          I3C_CR_RNW_Msk                          /*!< Read Not Write */
12235 #define I3C_CR_CCC_Pos                      (16U)
12236 #define I3C_CR_CCC_Msk                      (0xFFUL << I3C_CR_CCC_Pos)              /*!< 0x00FF0000 */
12237 #define I3C_CR_CCC                          I3C_CR_CCC_Msk                          /*!< 8-Bit CCC code */
12238 #define I3C_CR_ADD_Pos                      (17U)
12239 #define I3C_CR_ADD_Msk                      (0x7FUL << I3C_CR_ADD_Pos)              /*!< 0x00FE0000 */
12240 #define I3C_CR_ADD                          I3C_CR_ADD_Msk                          /*!< Target Address */
12241 #define I3C_CR_MTYPE_Pos                    (27U)
12242 #define I3C_CR_MTYPE_Msk                    (0xFUL << I3C_CR_MTYPE_Pos)             /*!< 0xF8000000 */
12243 #define I3C_CR_MTYPE                        I3C_CR_MTYPE_Msk                        /*!< Message Type */
12244 #define I3C_CR_MTYPE_0                      (0x1UL << I3C_CR_MTYPE_Pos)             /*!< 0x08000000 */
12245 #define I3C_CR_MTYPE_1                      (0x2UL << I3C_CR_MTYPE_Pos)             /*!< 0x10000000 */
12246 #define I3C_CR_MTYPE_2                      (0x4UL << I3C_CR_MTYPE_Pos)             /*!< 0x20000000 */
12247 #define I3C_CR_MTYPE_3                      (0x8UL << I3C_CR_MTYPE_Pos)             /*!< 0x40000000 */
12248 #define I3C_CR_MEND_Pos                     (31U)
12249 #define I3C_CR_MEND_Msk                     (0x1UL << I3C_CR_MEND_Pos)              /*!< 0x80000000 */
12250 #define I3C_CR_MEND                         I3C_CR_MEND_Msk                         /*!< Message End */
12251 
12252 /*******************  Bit definition for I3C_CFGR register  *******************/
12253 #define I3C_CFGR_EN_Pos                     (0U)
12254 #define I3C_CFGR_EN_Msk                     (0x1UL << I3C_CFGR_EN_Pos)              /*!< 0x00000001 */
12255 #define I3C_CFGR_EN                         I3C_CFGR_EN_Msk                         /*!< Peripheral Enable */
12256 #define I3C_CFGR_CRINIT_Pos                 (1U)
12257 #define I3C_CFGR_CRINIT_Msk                 (0x1UL << I3C_CFGR_CRINIT_Pos)          /*!< 0x00000002 */
12258 #define I3C_CFGR_CRINIT                     I3C_CFGR_CRINIT_Msk                     /*!< Peripheral Init mode (Target/Controller) */
12259 #define I3C_CFGR_NOARBH_Pos                 (2U)
12260 #define I3C_CFGR_NOARBH_Msk                 (0x1UL << I3C_CFGR_NOARBH_Pos)          /*!< 0x00000004 */
12261 #define I3C_CFGR_NOARBH                     I3C_CFGR_NOARBH_Msk                     /*!< No Arbitration Header (7'h7E)*/
12262 #define I3C_CFGR_RSTPTRN_Pos                (3U)
12263 #define I3C_CFGR_RSTPTRN_Msk                (0x1UL << I3C_CFGR_RSTPTRN_Pos)         /*!< 0x00000008 */
12264 #define I3C_CFGR_RSTPTRN                    I3C_CFGR_RSTPTRN_Msk                    /*!< Reset Pattern enable */
12265 #define I3C_CFGR_EXITPTRN_Pos               (4U)
12266 #define I3C_CFGR_EXITPTRN_Msk               (0x1UL << I3C_CFGR_EXITPTRN_Pos)        /*!< 0x00000010 */
12267 #define I3C_CFGR_EXITPTRN                   I3C_CFGR_EXITPTRN_Msk                   /*!< Exit Pattern enable */
12268 #define I3C_CFGR_HKSDAEN_Pos                (5U)
12269 #define I3C_CFGR_HKSDAEN_Msk                (0x1UL << I3C_CFGR_HKSDAEN_Pos)         /*!< 0x00000020 */
12270 #define I3C_CFGR_HKSDAEN                    I3C_CFGR_HKSDAEN_Msk                    /*!< High-Keeper on SDA Enable */
12271 #define I3C_CFGR_HJACK_Pos                  (7U)
12272 #define I3C_CFGR_HJACK_Msk                  (0x1UL << I3C_CFGR_HJACK_Pos)           /*!< 0x00000080 */
12273 #define I3C_CFGR_HJACK                      I3C_CFGR_HJACK_Msk                      /*!< Hot Join Acknowledgment */
12274 #define I3C_CFGR_RXDMAEN_Pos                (8U)
12275 #define I3C_CFGR_RXDMAEN_Msk                (0x1UL << I3C_CFGR_RXDMAEN_Pos)         /*!< 0x00000100 */
12276 #define I3C_CFGR_RXDMAEN                    I3C_CFGR_RXDMAEN_Msk                    /*!< RX FIFO DMA mode Enable */
12277 #define I3C_CFGR_RXFLUSH_Pos                (9U)
12278 #define I3C_CFGR_RXFLUSH_Msk                (0x1UL << I3C_CFGR_RXFLUSH_Pos)         /*!< 0x00000200 */
12279 #define I3C_CFGR_RXFLUSH                    I3C_CFGR_RXFLUSH_Msk                    /*!< RX FIFO Flush */
12280 #define I3C_CFGR_RXTHRES_Pos                (10U)
12281 #define I3C_CFGR_RXTHRES_Msk                (0x1UL << I3C_CFGR_RXTHRES_Pos)         /*!< 0x00000400 */
12282 #define I3C_CFGR_RXTHRES                    I3C_CFGR_RXTHRES_Msk                    /*!< RX FIFO Threshold */
12283 #define I3C_CFGR_TXDMAEN_Pos                (12U)
12284 #define I3C_CFGR_TXDMAEN_Msk                (0x1UL << I3C_CFGR_TXDMAEN_Pos)         /*!< 0x00001000 */
12285 #define I3C_CFGR_TXDMAEN                    I3C_CFGR_TXDMAEN_Msk                    /*!< TX FIFO DMA mode Enable */
12286 #define I3C_CFGR_TXFLUSH_Pos                (13U)
12287 #define I3C_CFGR_TXFLUSH_Msk                (0x1UL << I3C_CFGR_TXFLUSH_Pos)         /*!< 0x00002000 */
12288 #define I3C_CFGR_TXFLUSH                    I3C_CFGR_TXFLUSH_Msk                    /*!< TX FIFO Flush */
12289 #define I3C_CFGR_TXTHRES_Pos                (14U)
12290 #define I3C_CFGR_TXTHRES_Msk                (0x1UL << I3C_CFGR_TXTHRES_Pos)         /*!< 0x00004000 */
12291 #define I3C_CFGR_TXTHRES                    I3C_CFGR_TXTHRES_Msk                    /*!< TX FIFO Threshold */
12292 #define I3C_CFGR_SDMAEN_Pos                 (16U)
12293 #define I3C_CFGR_SDMAEN_Msk                 (0x1UL << I3C_CFGR_SDMAEN_Pos)          /*!< 0x00010000 */
12294 #define I3C_CFGR_SDMAEN                     I3C_CFGR_SDMAEN_Msk                     /*!< Status FIFO DMA mode Enable */
12295 #define I3C_CFGR_SFLUSH_Pos                 (17U)
12296 #define I3C_CFGR_SFLUSH_Msk                 (0x1UL << I3C_CFGR_SFLUSH_Pos)          /*!< 0x00020000 */
12297 #define I3C_CFGR_SFLUSH                     I3C_CFGR_SFLUSH_Msk                     /*!< Status FIFO Flush */
12298 #define I3C_CFGR_SMODE_Pos                  (18U)
12299 #define I3C_CFGR_SMODE_Msk                  (0x1UL << I3C_CFGR_SMODE_Pos)           /*!< 0x00040000 */
12300 #define I3C_CFGR_SMODE                      I3C_CFGR_SMODE_Msk                      /*!< Status FIFO mode Enable */
12301 #define I3C_CFGR_TMODE_Pos                  (19U)
12302 #define I3C_CFGR_TMODE_Msk                  (0x1UL << I3C_CFGR_TMODE_Pos)           /*!< 0x00080000 */
12303 #define I3C_CFGR_TMODE                      I3C_CFGR_TMODE_Msk                      /*!< Control FIFO mode Enable */
12304 #define I3C_CFGR_CDMAEN_Pos                 (20U)
12305 #define I3C_CFGR_CDMAEN_Msk                 (0x1UL << I3C_CFGR_CDMAEN_Pos)          /*!< 0x00100000 */
12306 #define I3C_CFGR_CDMAEN                     I3C_CFGR_CDMAEN_Msk                     /*!< Control FIFO DMA mode Enable */
12307 #define I3C_CFGR_CFLUSH_Pos                 (21U)
12308 #define I3C_CFGR_CFLUSH_Msk                 (0x1UL << I3C_CFGR_CFLUSH_Pos)          /*!< 0x00200000 */
12309 #define I3C_CFGR_CFLUSH                     I3C_CFGR_CFLUSH_Msk                     /*!< Control FIFO Flush */
12310 #define I3C_CFGR_TSFSET_Pos                 (30U)
12311 #define I3C_CFGR_TSFSET_Msk                 (0x1UL << I3C_CFGR_TSFSET_Pos)          /*!< 0x40000000 */
12312 #define I3C_CFGR_TSFSET                     I3C_CFGR_TSFSET_Msk                     /*!< Transfer Set */
12313 
12314 /*******************  Bit definition for I3C_RDR register  ********************/
12315 #define I3C_RDR_RDB0_Pos                    (0U)
12316 #define I3C_RDR_RDB0_Msk                    (0xFFUL << I3C_RDR_RDB0_Pos)            /*!< 0x000000FF */
12317 #define I3C_RDR_RDB0                        I3C_RDR_RDB0_Msk                        /*!< Receive Data Byte */
12318 
12319 /******************  Bit definition for I3C_RDWR register  ********************/
12320 #define I3C_RDWR_RDBx_Pos                   (0U)
12321 #define I3C_RDWR_RDBx_Msk                   (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos)     /*!< 0xFFFFFFFF */
12322 #define I3C_RDWR_RDBx                       I3C_RDWR_RDBx_Msk                       /*!< Receive Data Byte, full double word */
12323 #define I3C_RDWR_RDB0_Pos                   (0U)
12324 #define I3C_RDWR_RDB0_Msk                   (0xFFUL << I3C_RDWR_RDB0_Pos)           /*!< 0x000000FF */
12325 #define I3C_RDWR_RDB0                       I3C_RDWR_RDB0_Msk                       /*!< Receive Data Byte 0 */
12326 #define I3C_RDWR_RDB1_Pos                   (8U)
12327 #define I3C_RDWR_RDB1_Msk                   (0xFFUL << I3C_RDWR_RDB1_Pos)           /*!< 0x0000FF00 */
12328 #define I3C_RDWR_RDB1                       I3C_RDWR_RDB1_Msk                       /*!< Receive Data Byte 1 */
12329 #define I3C_RDWR_RDB2_Pos                   (16U)
12330 #define I3C_RDWR_RDB2_Msk                   (0xFFUL << I3C_RDWR_RDB2_Pos)           /*!< 0x00FF0000 */
12331 #define I3C_RDWR_RDB2                       I3C_RDWR_RDB2_Msk                       /*!< Receive Data Byte 2 */
12332 #define I3C_RDWR_RDB3_Pos                   (24U)
12333 #define I3C_RDWR_RDB3_Msk                   (0xFFUL << I3C_RDWR_RDB3_Pos)           /*!< 0xFF000000 */
12334 #define I3C_RDWR_RDB3                       I3C_RDWR_RDB3_Msk                       /*!< Receive Data Byte 3 */
12335 
12336 /*******************  Bit definition for I3C_TDR register  ********************/
12337 #define I3C_TDR_TDB0_Pos                    (0U)
12338 #define I3C_TDR_TDB0_Msk                    (0xFFUL << I3C_TDR_TDB0_Pos)            /*!< 0x000000FF */
12339 #define I3C_TDR_TDB0                        I3C_TDR_TDB0_Msk                        /*!< Transmit Data Byte */
12340 
12341 /******************  Bit definition for I3C_TDWR register  ********************/
12342 #define I3C_TDWR_TDBx_Pos                   (0U)
12343 #define I3C_TDWR_TDBx_Msk                   (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos)     /*!< 0xFFFFFFFF */
12344 #define I3C_TDWR_TDBx                       I3C_TDWR_TDBx_Msk                       /*!< Transmit Data Byte, full double word */
12345 #define I3C_TDWR_TDB0_Pos                   (0U)
12346 #define I3C_TDWR_TDB0_Msk                   (0xFFUL << I3C_TDWR_TDB0_Pos)           /*!< 0x000000FF */
12347 #define I3C_TDWR_TDB0                       I3C_TDWR_TDB0_Msk                       /*!< Transmit Data Byte 0 */
12348 #define I3C_TDWR_TDB1_Pos                   (8U)
12349 #define I3C_TDWR_TDB1_Msk                   (0xFFUL << I3C_TDWR_TDB1_Pos)           /*!< 0x0000FF00 */
12350 #define I3C_TDWR_TDB1                       I3C_TDWR_TDB1_Msk                       /*!< Transmit Data Byte 1 */
12351 #define I3C_TDWR_TDB2_Pos                   (16U)
12352 #define I3C_TDWR_TDB2_Msk                   (0xFFUL << I3C_TDWR_TDB2_Pos)           /*!< 0x00FF0000 */
12353 #define I3C_TDWR_TDB2                       I3C_TDWR_TDB2_Msk                       /*!< Transmit Data Byte 2 */
12354 #define I3C_TDWR_TDB3_Pos                   (24U)
12355 #define I3C_TDWR_TDB3_Msk                   (0xFFUL << I3C_TDWR_TDB3_Pos)           /*!< 0xFF000000 */
12356 #define I3C_TDWR_TDB3                       I3C_TDWR_TDB3_Msk                       /*!< Transmit Data Byte 3 */
12357 
12358 /*******************  Bit definition for I3C_IBIDR register  ******************/
12359 #define I3C_IBIDR_IBIDBx_Pos                (0U)
12360 #define I3C_IBIDR_IBIDBx_Msk                (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos)  /*!< 0xFFFFFFFF */
12361 #define I3C_IBIDR_IBIDBx                    I3C_IBIDR_IBIDBx_Msk                    /*!< IBI Data Byte, full double word */
12362 #define I3C_IBIDR_IBIDB0_Pos                (0U)
12363 #define I3C_IBIDR_IBIDB0_Msk                (0xFFUL << I3C_IBIDR_IBIDB0_Pos)        /*!< 0x000000FF */
12364 #define I3C_IBIDR_IBIDB0                    I3C_IBIDR_IBIDB0_Msk                    /*!< IBI Data Byte 0 */
12365 #define I3C_IBIDR_IBIDB1_Pos                (8U)
12366 #define I3C_IBIDR_IBIDB1_Msk                (0xFFUL << I3C_IBIDR_IBIDB1_Pos)        /*!< 0x0000FF00 */
12367 #define I3C_IBIDR_IBIDB1                    I3C_IBIDR_IBIDB1_Msk                    /*!< IBI Data Byte 1 */
12368 #define I3C_IBIDR_IBIDB2_Pos                (16U)
12369 #define I3C_IBIDR_IBIDB2_Msk                (0xFFUL << I3C_IBIDR_IBIDB2_Pos)        /*!< 0x00FF0000 */
12370 #define I3C_IBIDR_IBIDB2                    I3C_IBIDR_IBIDB2_Msk                    /*!< IBI Data Byte 2 */
12371 #define I3C_IBIDR_IBIDB3_Pos                (24U)
12372 #define I3C_IBIDR_IBIDB3_Msk                (0xFFUL << I3C_IBIDR_IBIDB3_Pos)        /*!< 0xFF000000 */
12373 #define I3C_IBIDR_IBIDB3                    I3C_IBIDR_IBIDB3_Msk                    /*!< IBI Data Byte 3 */
12374 
12375 /******************  Bit definition for I3C_TGTTDR register  ******************/
12376 #define I3C_TGTTDR_TGTTDCNT_Pos             (0U)
12377 #define I3C_TGTTDR_TGTTDCNT_Msk             (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos)   /*!< 0x0000FFFF */
12378 #define I3C_TGTTDR_TGTTDCNT                 I3C_TGTTDR_TGTTDCNT_Msk                 /*!< Target Transmit Data Counter */
12379 #define I3C_TGTTDR_PRELOAD_Pos              (16U)
12380 #define I3C_TGTTDR_PRELOAD_Msk              (0x1UL << I3C_TGTTDR_PRELOAD_Pos)       /*!< 0x00010000 */
12381 #define I3C_TGTTDR_PRELOAD                  I3C_TGTTDR_PRELOAD_Msk                  /*!< Transmit FIFO Preload Enable/Status */
12382 
12383 /*******************  Bit definition for I3C_SR register  *********************/
12384 #define I3C_SR_XDCNT_Pos                    (0U)
12385 #define I3C_SR_XDCNT_Msk                    (0xFFFFUL << I3C_SR_XDCNT_Pos)          /*!< 0x0000FFFF */
12386 #define I3C_SR_XDCNT                        I3C_SR_XDCNT_Msk                        /*!< Transfer Data Byte Count status */
12387 #define I3C_SR_ABT_Pos                      (17U)
12388 #define I3C_SR_ABT_Msk                      (0x1UL << I3C_SR_ABT_Pos)               /*!< 0x00020000 */
12389 #define I3C_SR_ABT                          I3C_SR_ABT_Msk                          /*!< Target Abort Indication */
12390 #define I3C_SR_DIR_Pos                      (18U)
12391 #define I3C_SR_DIR_Msk                      (0x1UL << I3C_SR_DIR_Pos)               /*!< 0x00040000 */
12392 #define I3C_SR_DIR                          I3C_SR_DIR_Msk                          /*!< Message Direction */
12393 #define I3C_SR_MID_Pos                      (24U)
12394 #define I3C_SR_MID_Msk                      (0xFFUL << I3C_SR_MID_Pos)              /*!< 0xFF000000 */
12395 #define I3C_SR_MID                          I3C_SR_MID_Msk                          /*!< Message Identifier */
12396 
12397 /*******************  Bit definition for I3C_SER register  ********************/
12398 #define I3C_SER_CODERR_Pos                  (0U)
12399 #define I3C_SER_CODERR_Msk                  (0xFUL << I3C_SER_CODERR_Pos)           /*!< 0x0000000F */
12400 #define I3C_SER_CODERR                      I3C_SER_CODERR_Msk                      /*!< Protocol Error Code */
12401 #define I3C_SER_CODERR_0                    (0x1UL << I3C_SER_CODERR_Pos)           /*!< 0x00000001 */
12402 #define I3C_SER_CODERR_1                    (0x2UL << I3C_SER_CODERR_Pos)           /*!< 0x00000002 */
12403 #define I3C_SER_CODERR_2                    (0x4UL << I3C_SER_CODERR_Pos)           /*!< 0x00000004 */
12404 #define I3C_SER_CODERR_3                    (0x8UL << I3C_SER_CODERR_Pos)           /*!< 0x00000008 */
12405 #define I3C_SER_PERR_Pos                    (4U)
12406 #define I3C_SER_PERR_Msk                    (0x1UL << I3C_SER_PERR_Pos)             /*!< 0x00000010 */
12407 #define I3C_SER_PERR                        I3C_SER_PERR_Msk                        /*!< Protocol Error */
12408 #define I3C_SER_STALL_Pos                   (5U)
12409 #define I3C_SER_STALL_Msk                   (0x1UL << I3C_SER_STALL_Pos)            /*!< 0x00000020 */
12410 #define I3C_SER_STALL                       I3C_SER_STALL_Msk                       /*!< SCL Stall Error */
12411 #define I3C_SER_DOVR_Pos                    (6U)
12412 #define I3C_SER_DOVR_Msk                    (0x1UL << I3C_SER_DOVR_Pos)             /*!< 0x00000040 */
12413 #define I3C_SER_DOVR                        I3C_SER_DOVR_Msk                        /*!< RX/TX FIFO Overrun */
12414 #define I3C_SER_COVR_Pos                    (7U)
12415 #define I3C_SER_COVR_Msk                    (0x1UL << I3C_SER_COVR_Pos)             /*!< 0x00000080 */
12416 #define I3C_SER_COVR                        I3C_SER_COVR_Msk                        /*!< Status/Control FIFO Overrun */
12417 #define I3C_SER_ANACK_Pos                   (8U)
12418 #define I3C_SER_ANACK_Msk                   (0x1UL << I3C_SER_ANACK_Pos)            /*!< 0x00000100 */
12419 #define I3C_SER_ANACK                       I3C_SER_ANACK_Msk                       /*!< Address Not Acknowledged */
12420 #define I3C_SER_DNACK_Pos                   (9U)
12421 #define I3C_SER_DNACK_Msk                   (0x1UL << I3C_SER_DNACK_Pos)            /*!< 0x00000200 */
12422 #define I3C_SER_DNACK                       I3C_SER_DNACK_Msk                       /*!< Data Not Acknowledged */
12423 #define I3C_SER_DERR_Pos                    (10U)
12424 #define I3C_SER_DERR_Msk                    (0x1UL << I3C_SER_DERR_Pos)             /*!< 0x00000400 */
12425 #define I3C_SER_DERR                        I3C_SER_DERR_Msk                        /*!< Data Error during the controller-role hand-off procedure */
12426 
12427 /*******************  Bit definition for I3C_RMR register  ********************/
12428 #define I3C_RMR_IBIRDCNT_Pos                (0U)
12429 #define I3C_RMR_IBIRDCNT_Msk                (0x7UL << I3C_RMR_IBIRDCNT_Pos)         /*!< 0x00000007 */
12430 #define I3C_RMR_IBIRDCNT                    I3C_RMR_IBIRDCNT_Msk                    /*!< Data Count when reading IBI data */
12431 #define I3C_RMR_RCODE_Pos                   (8U)
12432 #define I3C_RMR_RCODE_Msk                   (0xFFUL << I3C_RMR_RCODE_Pos)           /*!< 0x0000FF00 */
12433 #define I3C_RMR_RCODE                       I3C_RMR_RCODE_Msk                       /*!< CCC code of received command */
12434 #define I3C_RMR_RADD_Pos                    (17U)
12435 #define I3C_RMR_RADD_Msk                    (0x7FUL << I3C_RMR_RADD_Pos)            /*!< 0x00FE0000 */
12436 #define I3C_RMR_RADD                        I3C_RMR_RADD_Msk                        /*!< Target Address Received during accepted IBI or Controller-role request */
12437 
12438 /*******************  Bit definition for I3C_EVR register  ********************/
12439 #define I3C_EVR_CFEF_Pos                    (0U)
12440 #define I3C_EVR_CFEF_Msk                    (0x1UL << I3C_EVR_CFEF_Pos)             /*!< 0x00000001 */
12441 #define I3C_EVR_CFEF                        I3C_EVR_CFEF_Msk                        /*!< Control FIFO Empty Flag */
12442 #define I3C_EVR_TXFEF_Pos                   (1U)
12443 #define I3C_EVR_TXFEF_Msk                   (0x1UL << I3C_EVR_TXFEF_Pos)            /*!< 0x00000002 */
12444 #define I3C_EVR_TXFEF                       I3C_EVR_TXFEF_Msk                       /*!< TX FIFO Empty Flag */
12445 #define I3C_EVR_CFNFF_Pos                   (2U)
12446 #define I3C_EVR_CFNFF_Msk                   (0x1UL << I3C_EVR_CFNFF_Pos)            /*!< 0x00000004 */
12447 #define I3C_EVR_CFNFF                       I3C_EVR_CFNFF_Msk                       /*!< Control FIFO Not Full Flag */
12448 #define I3C_EVR_SFNEF_Pos                   (3U)
12449 #define I3C_EVR_SFNEF_Msk                   (0x1UL << I3C_EVR_SFNEF_Pos)            /*!< 0x00000008 */
12450 #define I3C_EVR_SFNEF                       I3C_EVR_SFNEF_Msk                       /*!< Status FIFO Not Empty Flag */
12451 #define I3C_EVR_TXFNFF_Pos                  (4U)
12452 #define I3C_EVR_TXFNFF_Msk                  (0x1UL << I3C_EVR_TXFNFF_Pos)           /*!< 0x00000010 */
12453 #define I3C_EVR_TXFNFF                      I3C_EVR_TXFNFF_Msk                      /*!< TX FIFO Not Full Flag */
12454 #define I3C_EVR_RXFNEF_Pos                  (5U)
12455 #define I3C_EVR_RXFNEF_Msk                  (0x1UL << I3C_EVR_RXFNEF_Pos)           /*!< 0x00000020 */
12456 #define I3C_EVR_RXFNEF                      I3C_EVR_RXFNEF_Msk                      /*!< RX FIFO Not Empty Flag */
12457 #define I3C_EVR_TXLASTF_Pos                 (6U)
12458 #define I3C_EVR_TXLASTF_Msk                 (0x1UL << I3C_EVR_TXLASTF_Pos)          /*!< 0x00000040 */
12459 #define I3C_EVR_TXLASTF                     I3C_EVR_TXLASTF_Msk                     /*!< Last TX byte available in FIFO */
12460 #define I3C_EVR_RXLASTF_Pos                 (7U)
12461 #define I3C_EVR_RXLASTF_Msk                 (0x1UL << I3C_EVR_RXLASTF_Pos)          /*!< 0x00000080 */
12462 #define I3C_EVR_RXLASTF                     I3C_EVR_RXLASTF_Msk                     /*!< Last RX byte read from FIFO */
12463 #define I3C_EVR_FCF_Pos                     (9U)
12464 #define I3C_EVR_FCF_Msk                     (0x1UL << I3C_EVR_FCF_Pos)              /*!< 0x00000200 */
12465 #define I3C_EVR_FCF                         I3C_EVR_FCF_Msk                         /*!< Frame Complete Flag */
12466 #define I3C_EVR_RXTGTENDF_Pos               (10U)
12467 #define I3C_EVR_RXTGTENDF_Msk               (0x1UL << I3C_EVR_RXTGTENDF_Pos)        /*!< 0x00000400 */
12468 #define I3C_EVR_RXTGTENDF                   I3C_EVR_RXTGTENDF_Msk                   /*!< Reception Target End Flag */
12469 #define I3C_EVR_ERRF_Pos                    (11U)
12470 #define I3C_EVR_ERRF_Msk                    (0x1UL << I3C_EVR_ERRF_Pos)             /*!< 0x00000800 */
12471 #define I3C_EVR_ERRF                        I3C_EVR_ERRF_Msk                        /*!< Error Flag */
12472 #define I3C_EVR_IBIF_Pos                    (15U)
12473 #define I3C_EVR_IBIF_Msk                    (0x1UL << I3C_EVR_IBIF_Pos)             /*!< 0x00008000 */
12474 #define I3C_EVR_IBIF                        I3C_EVR_IBIF_Msk                        /*!< IBI Flag */
12475 #define I3C_EVR_IBIENDF_Pos                 (16U)
12476 #define I3C_EVR_IBIENDF_Msk                 (0x1UL << I3C_EVR_IBIENDF_Pos)          /*!< 0x00010000 */
12477 #define I3C_EVR_IBIENDF                     I3C_EVR_IBIENDF_Msk                     /*!< IBI End Flag */
12478 #define I3C_EVR_CRF_Pos                     (17U)
12479 #define I3C_EVR_CRF_Msk                     (0x1UL << I3C_EVR_CRF_Pos)              /*!< 0x00020000 */
12480 #define I3C_EVR_CRF                         I3C_EVR_CRF_Msk                         /*!< Controller-role Request Flag */
12481 #define I3C_EVR_CRUPDF_Pos                  (18U)
12482 #define I3C_EVR_CRUPDF_Msk                  (0x1UL << I3C_EVR_CRUPDF_Pos)           /*!< 0x00040000 */
12483 #define I3C_EVR_CRUPDF                      I3C_EVR_CRUPDF_Msk                      /*!< Controller-role Update Flag */
12484 #define I3C_EVR_HJF_Pos                     (19U)
12485 #define I3C_EVR_HJF_Msk                     (0x1UL << I3C_EVR_HJF_Pos)              /*!< 0x00080000 */
12486 #define I3C_EVR_HJF                         I3C_EVR_HJF_Msk                         /*!< Hot Join Flag */
12487 #define I3C_EVR_WKPF_Pos                    (21U)
12488 #define I3C_EVR_WKPF_Msk                    (0x1UL << I3C_EVR_WKPF_Pos)             /*!< 0x00200000 */
12489 #define I3C_EVR_WKPF                        I3C_EVR_WKPF_Msk                        /*!< Wake Up Flag */
12490 #define I3C_EVR_GETF_Pos                    (22U)
12491 #define I3C_EVR_GETF_Msk                    (0x1UL << I3C_EVR_GETF_Pos)             /*!< 0x00400000 */
12492 #define I3C_EVR_GETF                        I3C_EVR_GETF_Msk                        /*!< Get type CCC received Flag */
12493 #define I3C_EVR_STAF_Pos                    (23U)
12494 #define I3C_EVR_STAF_Msk                    (0x1UL << I3C_EVR_STAF_Pos)             /*!< 0x00800000 */
12495 #define I3C_EVR_STAF                        I3C_EVR_STAF_Msk                        /*!< Get Status Flag */
12496 #define I3C_EVR_DAUPDF_Pos                  (24U)
12497 #define I3C_EVR_DAUPDF_Msk                  (0x1UL << I3C_EVR_DAUPDF_Pos)           /*!< 0x01000000 */
12498 #define I3C_EVR_DAUPDF                      I3C_EVR_DAUPDF_Msk                      /*!< Dynamic Address Update Flag */
12499 #define I3C_EVR_MWLUPDF_Pos                 (25U)
12500 #define I3C_EVR_MWLUPDF_Msk                 (0x1UL << I3C_EVR_MWLUPDF_Pos)          /*!< 0x02000000 */
12501 #define I3C_EVR_MWLUPDF                     I3C_EVR_MWLUPDF_Msk                     /*!< Max Write Length Update Flag */
12502 #define I3C_EVR_MRLUPDF_Pos                 (26U)
12503 #define I3C_EVR_MRLUPDF_Msk                 (0x1UL << I3C_EVR_MRLUPDF_Pos)          /*!< 0x04000000 */
12504 #define I3C_EVR_MRLUPDF                     I3C_EVR_MRLUPDF_Msk                     /*!< Max Read Length Update Flag */
12505 #define I3C_EVR_RSTF_Pos                    (27U)
12506 #define I3C_EVR_RSTF_Msk                    (0x1UL << I3C_EVR_RSTF_Pos)             /*!< 0x08000000 */
12507 #define I3C_EVR_RSTF                        I3C_EVR_RSTF_Msk                        /*!< Reset Flag, due to Reset pattern received */
12508 #define I3C_EVR_ASUPDF_Pos                  (28U)
12509 #define I3C_EVR_ASUPDF_Msk                  (0x1UL << I3C_EVR_ASUPDF_Pos)           /*!< 0x10000000 */
12510 #define I3C_EVR_ASUPDF                      I3C_EVR_ASUPDF_Msk                      /*!< Activity State Flag */
12511 #define I3C_EVR_INTUPDF_Pos                 (29U)
12512 #define I3C_EVR_INTUPDF_Msk                 (0x1UL << I3C_EVR_INTUPDF_Pos)          /*!< 0x20000000 */
12513 #define I3C_EVR_INTUPDF                     I3C_EVR_INTUPDF_Msk                     /*!< Interrupt Update Flag */
12514 #define I3C_EVR_DEFF_Pos                    (30U)
12515 #define I3C_EVR_DEFF_Msk                    (0x1UL << I3C_EVR_DEFF_Pos)             /*!< 0x40000000 */
12516 #define I3C_EVR_DEFF                        I3C_EVR_DEFF_Msk                        /*!< List of Targets Command Received Flag */
12517 #define I3C_EVR_GRPF_Pos                    (31U)
12518 #define I3C_EVR_GRPF_Msk                    (0x1UL << I3C_EVR_GRPF_Pos)             /*!< 0x80000000 */
12519 #define I3C_EVR_GRPF                        I3C_EVR_GRPF_Msk                        /*!< List of Group Addresses Command Received Flag */
12520 
12521 /*******************  Bit definition for I3C_IER register  ********************/
12522 #define I3C_IER_CFNFIE_Pos                  (2U)
12523 #define I3C_IER_CFNFIE_Msk                  (0x1UL << I3C_IER_CFNFIE_Pos)           /*!< 0x00000004 */
12524 #define I3C_IER_CFNFIE                      I3C_IER_CFNFIE_Msk                      /*!< Control FIFO Not Full Interrupt Enable */
12525 #define I3C_IER_SFNEIE_Pos                  (3U)
12526 #define I3C_IER_SFNEIE_Msk                  (0x1UL << I3C_IER_SFNEIE_Pos)           /*!< 0x00000008 */
12527 #define I3C_IER_SFNEIE                      I3C_IER_SFNEIE_Msk                      /*!< Status FIFO Not Empty Interrupt Enable */
12528 #define I3C_IER_TXFNFIE_Pos                 (4U)
12529 #define I3C_IER_TXFNFIE_Msk                 (0x1UL << I3C_IER_TXFNFIE_Pos)          /*!< 0x00000010 */
12530 #define I3C_IER_TXFNFIE                     I3C_IER_TXFNFIE_Msk                     /*!< TX FIFO Not Full Interrupt Enable */
12531 #define I3C_IER_RXFNEIE_Pos                 (5U)
12532 #define I3C_IER_RXFNEIE_Msk                 (0x1UL << I3C_IER_RXFNEIE_Pos)          /*!< 0x00000020 */
12533 #define I3C_IER_RXFNEIE                     I3C_IER_RXFNEIE_Msk                     /*!< RX FIFO Not Empty Interrupt Enable */
12534 #define I3C_IER_FCIE_Pos                    (9U)
12535 #define I3C_IER_FCIE_Msk                    (0x1UL << I3C_IER_FCIE_Pos)             /*!< 0x00000200 */
12536 #define I3C_IER_FCIE                        I3C_IER_FCIE_Msk                        /*!< Frame Complete Interrupt Enable */
12537 #define I3C_IER_RXTGTENDIE_Pos              (10U)
12538 #define I3C_IER_RXTGTENDIE_Msk              (0x1UL << I3C_IER_RXTGTENDIE_Pos)       /*!< 0x00000400 */
12539 #define I3C_IER_RXTGTENDIE                  I3C_IER_RXTGTENDIE_Msk                  /*!< Reception Target End Interrupt Enable */
12540 #define I3C_IER_ERRIE_Pos                   (11U)
12541 #define I3C_IER_ERRIE_Msk                   (0x1UL << I3C_IER_ERRIE_Pos)            /*!< 0x00000800 */
12542 #define I3C_IER_ERRIE                       I3C_IER_ERRIE_Msk                       /*!< Error Interrupt Enable */
12543 #define I3C_IER_IBIIE_Pos                   (15U)
12544 #define I3C_IER_IBIIE_Msk                   (0x1UL << I3C_IER_IBIIE_Pos)            /*!< 0x00008000 */
12545 #define I3C_IER_IBIIE                       I3C_IER_IBIIE_Msk                       /*!< IBI Interrupt Enable */
12546 #define I3C_IER_IBIENDIE_Pos                (16U)
12547 #define I3C_IER_IBIENDIE_Msk                (0x1UL << I3C_IER_IBIENDIE_Pos)         /*!< 0x00010000 */
12548 #define I3C_IER_IBIENDIE                    I3C_IER_IBIENDIE_Msk                    /*!< IBI End Interrupt Enable */
12549 #define I3C_IER_CRIE_Pos                    (17U)
12550 #define I3C_IER_CRIE_Msk                    (0x1UL << I3C_IER_CRIE_Pos)             /*!< 0x00020000 */
12551 #define I3C_IER_CRIE                        I3C_IER_CRIE_Msk                        /*!< Controller-role Interrupt Enable */
12552 #define I3C_IER_CRUPDIE_Pos                 (18U)
12553 #define I3C_IER_CRUPDIE_Msk                 (0x1UL << I3C_IER_CRUPDIE_Pos)          /*!< 0x00040000 */
12554 #define I3C_IER_CRUPDIE                     I3C_IER_CRUPDIE_Msk                     /*!< Controller-role Update Interrupt Enable */
12555 #define I3C_IER_HJIE_Pos                    (19U)
12556 #define I3C_IER_HJIE_Msk                    (0x1UL << I3C_IER_HJIE_Pos)             /*!< 0x00080000 */
12557 #define I3C_IER_HJIE                        I3C_IER_HJIE_Msk                        /*!< Hot Join Interrupt Enable */
12558 #define I3C_IER_WKPIE_Pos                   (21U)
12559 #define I3C_IER_WKPIE_Msk                   (0x1UL << I3C_IER_WKPIE_Pos)            /*!< 0x00200000 */
12560 #define I3C_IER_WKPIE                       I3C_IER_WKPIE_Msk                       /*!< Wake Up Interrupt Enable */
12561 #define I3C_IER_GETIE_Pos                   (22U)
12562 #define I3C_IER_GETIE_Msk                   (0x1UL << I3C_IER_GETIE_Pos)            /*!< 0x00400000 */
12563 #define I3C_IER_GETIE                       I3C_IER_GETIE_Msk                       /*!< Get type CCC received Interrupt Enable */
12564 #define I3C_IER_STAIE_Pos                   (23U)
12565 #define I3C_IER_STAIE_Msk                   (0x1UL << I3C_IER_STAIE_Pos)            /*!< 0x00800000 */
12566 #define I3C_IER_STAIE                       I3C_IER_STAIE_Msk                       /*!< Get Status Interrupt Enable */
12567 #define I3C_IER_DAUPDIE_Pos                 (24U)
12568 #define I3C_IER_DAUPDIE_Msk                 (0x1UL << I3C_IER_DAUPDIE_Pos)          /*!< 0x01000000 */
12569 #define I3C_IER_DAUPDIE                     I3C_IER_DAUPDIE_Msk                     /*!< Dynamic Address Update Interrupt Enable */
12570 #define I3C_IER_MWLUPDIE_Pos                (25U)
12571 #define I3C_IER_MWLUPDIE_Msk                (0x1UL << I3C_IER_MWLUPDIE_Pos)         /*!< 0x02000000 */
12572 #define I3C_IER_MWLUPDIE                    I3C_IER_MWLUPDIE_Msk                    /*!< Max Write Length Update Interrupt Enable */
12573 #define I3C_IER_MRLUPDIE_Pos                (26U)
12574 #define I3C_IER_MRLUPDIE_Msk                (0x1UL << I3C_IER_MRLUPDIE_Pos)         /*!< 0x04000000 */
12575 #define I3C_IER_MRLUPDIE                    I3C_IER_MRLUPDIE_Msk                    /*!< Max Read Length Update Interrupt Enable */
12576 #define I3C_IER_RSTIE_Pos                   (27U)
12577 #define I3C_IER_RSTIE_Msk                   (0x1UL << I3C_IER_RSTIE_Pos)            /*!< 0x08000000 */
12578 #define I3C_IER_RSTIE                       I3C_IER_RSTIE_Msk                       /*!< Reset Interrupt Enabled, due to Reset pattern received */
12579 #define I3C_IER_ASUPDIE_Pos                 (28U)
12580 #define I3C_IER_ASUPDIE_Msk                 (0x1UL << I3C_IER_ASUPDIE_Pos)          /*!< 0x10000000 */
12581 #define I3C_IER_ASUPDIE                     I3C_IER_ASUPDIE_Msk                     /*!< Activity State Interrupt Enable */
12582 #define I3C_IER_INTUPDIE_Pos                (29U)
12583 #define I3C_IER_INTUPDIE_Msk                (0x1UL << I3C_IER_INTUPDIE_Pos)         /*!< 0x20000000 */
12584 #define I3C_IER_INTUPDIE                    I3C_IER_INTUPDIE_Msk                    /*!< Interrupt Update Interrupt Enable */
12585 #define I3C_IER_DEFIE_Pos                   (30U)
12586 #define I3C_IER_DEFIE_Msk                   (0x1UL << I3C_IER_DEFIE_Pos)            /*!< 0x40000000 */
12587 #define I3C_IER_DEFIE                       I3C_IER_DEFIE_Msk                       /*!< List of Targets Command Received Interrupt Enable */
12588 #define I3C_IER_GRPIE_Pos                   (31U)
12589 #define I3C_IER_GRPIE_Msk                   (0x1UL << I3C_IER_GRPIE_Pos)            /*!< 0x80000000 */
12590 #define I3C_IER_GRPIE                       I3C_IER_GRPIE_Msk                       /*!< List of Group Addresses Command Received Interrupt Enable */
12591 
12592 /*******************  Bit definition for I3C_CEVR register  *******************/
12593 #define I3C_CEVR_CFCF_Pos                   (9U)
12594 #define I3C_CEVR_CFCF_Msk                   (0x1UL << I3C_CEVR_CFCF_Pos)            /*!< 0x00000200 */
12595 #define I3C_CEVR_CFCF                       I3C_CEVR_CFCF_Msk                       /*!< Frame Complete Clear Flag */
12596 #define I3C_CEVR_CRXTGTENDF_Pos             (10U)
12597 #define I3C_CEVR_CRXTGTENDF_Msk             (0x1UL << I3C_CEVR_CRXTGTENDF_Pos)      /*!< 0x00000400 */
12598 #define I3C_CEVR_CRXTGTENDF                 I3C_CEVR_CRXTGTENDF_Msk                 /*!< Reception Target End Clear Flag */
12599 #define I3C_CEVR_CERRF_Pos                  (11U)
12600 #define I3C_CEVR_CERRF_Msk                  (0x1UL << I3C_CEVR_CERRF_Pos)           /*!< 0x00000800 */
12601 #define I3C_CEVR_CERRF                      I3C_CEVR_CERRF_Msk                      /*!< Error Clear Flag */
12602 #define I3C_CEVR_CIBIF_Pos                  (15U)
12603 #define I3C_CEVR_CIBIF_Msk                  (0x1UL << I3C_CEVR_CIBIF_Pos)           /*!< 0x00008000 */
12604 #define I3C_CEVR_CIBIF                      I3C_CEVR_CIBIF_Msk                      /*!< IBI Clear Flag */
12605 #define I3C_CEVR_CIBIENDF_Pos               (16U)
12606 #define I3C_CEVR_CIBIENDF_Msk               (0x1UL << I3C_CEVR_CIBIENDF_Pos)        /*!< 0x00010000 */
12607 #define I3C_CEVR_CIBIENDF                   I3C_CEVR_CIBIENDF_Msk                   /*!< IBI End Clear Flag */
12608 #define I3C_CEVR_CCRF_Pos                   (17U)
12609 #define I3C_CEVR_CCRF_Msk                   (0x1UL << I3C_CEVR_CCRF_Pos)            /*!< 0x00020000 */
12610 #define I3C_CEVR_CCRF                       I3C_CEVR_CCRF_Msk                       /*!< Controller-role Clear Flag */
12611 #define I3C_CEVR_CCRUPDF_Pos                (18U)
12612 #define I3C_CEVR_CCRUPDF_Msk                (0x1UL << I3C_CEVR_CCRUPDF_Pos)         /*!< 0x00040000 */
12613 #define I3C_CEVR_CCRUPDF                    I3C_CEVR_CCRUPDF_Msk                    /*!< Controller-role Update Clear Flag */
12614 #define I3C_CEVR_CHJF_Pos                   (19U)
12615 #define I3C_CEVR_CHJF_Msk                   (0x1UL << I3C_CEVR_CHJF_Pos)            /*!< 0x00080000 */
12616 #define I3C_CEVR_CHJF                       I3C_CEVR_CHJF_Msk                       /*!< Hot Join Clear Flag */
12617 #define I3C_CEVR_CWKPF_Pos                  (21U)
12618 #define I3C_CEVR_CWKPF_Msk                  (0x1UL << I3C_CEVR_CWKPF_Pos)           /*!< 0x00200000 */
12619 #define I3C_CEVR_CWKPF                      I3C_CEVR_CWKPF_Msk                      /*!< Wake Up Clear Flag */
12620 #define I3C_CEVR_CGETF_Pos                  (22U)
12621 #define I3C_CEVR_CGETF_Msk                  (0x1UL << I3C_CEVR_CGETF_Pos)           /*!< 0x00400000 */
12622 #define I3C_CEVR_CGETF                      I3C_CEVR_CGETF_Msk                      /*!< Get type CCC received Clear Flag */
12623 #define I3C_CEVR_CSTAF_Pos                  (23U)
12624 #define I3C_CEVR_CSTAF_Msk                  (0x1UL << I3C_CEVR_CSTAF_Pos)           /*!< 0x00800000 */
12625 #define I3C_CEVR_CSTAF                      I3C_CEVR_CSTAF_Msk                      /*!< Get Status Clear Flag */
12626 #define I3C_CEVR_CDAUPDF_Pos                (24U)
12627 #define I3C_CEVR_CDAUPDF_Msk                (0x1UL << I3C_CEVR_CDAUPDF_Pos)         /*!< 0x01000000 */
12628 #define I3C_CEVR_CDAUPDF                    I3C_CEVR_CDAUPDF_Msk                    /*!< Dynamic Address Update Clear Flag */
12629 #define I3C_CEVR_CMWLUPDF_Pos               (25U)
12630 #define I3C_CEVR_CMWLUPDF_Msk               (0x1UL << I3C_CEVR_CMWLUPDF_Pos)        /*!< 0x02000000 */
12631 #define I3C_CEVR_CMWLUPDF                   I3C_CEVR_CMWLUPDF_Msk                   /*!< Max Write Length Update Clear Flag */
12632 #define I3C_CEVR_CMRLUPDF_Pos               (26U)
12633 #define I3C_CEVR_CMRLUPDF_Msk               (0x1UL << I3C_CEVR_CMRLUPDF_Pos)        /*!< 0x04000000 */
12634 #define I3C_CEVR_CMRLUPDF                   I3C_CEVR_CMRLUPDF_Msk                   /*!< Max Read Length Update Clear Flag */
12635 #define I3C_CEVR_CRSTF_Pos                  (27U)
12636 #define I3C_CEVR_CRSTF_Msk                  (0x1UL << I3C_CEVR_CRSTF_Pos)           /*!< 0x08000000 */
12637 #define I3C_CEVR_CRSTF                      I3C_CEVR_CRSTF_Msk                      /*!< Reset Flag, due to Reset pattern received */
12638 #define I3C_CEVR_CASUPDF_Pos                (28U)
12639 #define I3C_CEVR_CASUPDF_Msk                (0x1UL << I3C_CEVR_CASUPDF_Pos)         /*!< 0x10000000 */
12640 #define I3C_CEVR_CASUPDF                    I3C_CEVR_CASUPDF_Msk                    /*!< Activity State Clear Flag */
12641 #define I3C_CEVR_CINTUPDF_Pos               (29U)
12642 #define I3C_CEVR_CINTUPDF_Msk               (0x1UL << I3C_CEVR_CINTUPDF_Pos)        /*!< 0x20000000 */
12643 #define I3C_CEVR_CINTUPDF                   I3C_CEVR_CINTUPDF_Msk                   /*!< Interrupt Update Clear Flag */
12644 #define I3C_CEVR_CDEFF_Pos                  (30U)
12645 #define I3C_CEVR_CDEFF_Msk                  (0x1UL << I3C_CEVR_CDEFF_Pos)           /*!< 0x40000000 */
12646 #define I3C_CEVR_CDEFF                      I3C_CEVR_CDEFF_Msk                      /*!< List of Targets Command Received Clear Flag */
12647 #define I3C_CEVR_CGRPF_Pos                  (31U)
12648 #define I3C_CEVR_CGRPF_Msk                  (0x1UL << I3C_CEVR_CGRPF_Pos)           /*!< 0x80000000 */
12649 #define I3C_CEVR_CGRPF                      I3C_CEVR_CGRPF_Msk                      /*!< List of Group Addresses Command Received Clear Flag */
12650 
12651 /******************  Bit definition for I3C_DEVR0 register  *******************/
12652 #define I3C_DEVR0_DAVAL_Pos                 (0U)
12653 #define I3C_DEVR0_DAVAL_Msk                 (0x1UL << I3C_DEVR0_DAVAL_Pos)          /*!< 0x00000001 */
12654 #define I3C_DEVR0_DAVAL                     I3C_DEVR0_DAVAL_Msk                     /*!< Dynamic Address Validity */
12655 #define I3C_DEVR0_DA_Pos                    (1U)
12656 #define I3C_DEVR0_DA_Msk                    (0x7FUL << I3C_DEVR0_DA_Pos)            /*!< 0x000000FE */
12657 #define I3C_DEVR0_DA                        I3C_DEVR0_DA_Msk                        /*!< Own Target Device Address */
12658 #define I3C_DEVR0_IBIEN_Pos                 (16U)
12659 #define I3C_DEVR0_IBIEN_Msk                 (0x1UL << I3C_DEVR0_IBIEN_Pos)          /*!< 0x00010000 */
12660 #define I3C_DEVR0_IBIEN                     I3C_DEVR0_IBIEN_Msk                     /*!< IBI Enable */
12661 #define I3C_DEVR0_CREN_Pos                  (17U)
12662 #define I3C_DEVR0_CREN_Msk                  (0x1UL << I3C_DEVR0_CREN_Pos)           /*!< 0x00020000 */
12663 #define I3C_DEVR0_CREN                      I3C_DEVR0_CREN_Msk                      /*!< Controller-role Enable */
12664 #define I3C_DEVR0_HJEN_Pos                  (19U)
12665 #define I3C_DEVR0_HJEN_Msk                  (0x1UL << I3C_DEVR0_HJEN_Pos)           /*!< 0x00080000 */
12666 #define I3C_DEVR0_HJEN                      I3C_DEVR0_HJEN_Msk                      /*!< Hot Join Enable */
12667 #define I3C_DEVR0_AS_Pos                    (20U)
12668 #define I3C_DEVR0_AS_Msk                    (0x3UL << I3C_DEVR0_AS_Pos)             /*!< 0x00300000 */
12669 #define I3C_DEVR0_AS                        I3C_DEVR0_AS_Msk                        /*!< Activity State value update after ENTAx received */
12670 #define I3C_DEVR0_AS_0                      (0x1UL << I3C_DEVR0_AS_Pos)             /*!< 0x00100000 */
12671 #define I3C_DEVR0_AS_1                      (0x2UL << I3C_DEVR0_AS_Pos)             /*!< 0x00200000 */
12672 #define I3C_DEVR0_RSTACT_Pos                (22U)
12673 #define I3C_DEVR0_RSTACT_Msk                (0x3UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00C000000 */
12674 #define I3C_DEVR0_RSTACT                    I3C_DEVR0_RSTACT_Msk                    /*!< Reset Action value update after RSTACT received */
12675 #define I3C_DEVR0_RSTACT_0                  (0x1UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00400000 */
12676 #define I3C_DEVR0_RSTACT_1                  (0x2UL << I3C_DEVR0_RSTACT_Pos)         /*!< 0x00800000 */
12677 #define I3C_DEVR0_RSTVAL_Pos                (24U)
12678 #define I3C_DEVR0_RSTVAL_Msk                (0x1UL << I3C_DEVR0_RSTVAL_Pos)         /*!< 0x01000000 */
12679 #define I3C_DEVR0_RSTVAL                    I3C_DEVR0_RSTVAL_Msk                    /*!< Reset Action Valid */
12680 
12681 /******************  Bit definition for I3C_DEVRX register  *******************/
12682 #define I3C_DEVRX_DA_Pos                    (1U)
12683 #define I3C_DEVRX_DA_Msk                    (0x7FUL << I3C_DEVRX_DA_Pos)            /*!< 0x000000FE */
12684 #define I3C_DEVRX_DA                        I3C_DEVRX_DA_Msk                        /*!< Dynamic Address Target x */
12685 #define I3C_DEVRX_IBIACK_Pos                (16U)
12686 #define I3C_DEVRX_IBIACK_Msk                (0x1UL << I3C_DEVRX_IBIACK_Pos)         /*!< 0x00010000 */
12687 #define I3C_DEVRX_IBIACK                    I3C_DEVRX_IBIACK_Msk                    /*!< IBI Acknowledge from Target x */
12688 #define I3C_DEVRX_CRACK_Pos                 (17U)
12689 #define I3C_DEVRX_CRACK_Msk                 (0x1UL << I3C_DEVRX_CRACK_Pos)          /*!< 0x00020000 */
12690 #define I3C_DEVRX_CRACK                     I3C_DEVRX_CRACK_Msk                     /*!< Controller-role Acknowledge from Target x */
12691 #define I3C_DEVRX_IBIDEN_Pos                (18U)
12692 #define I3C_DEVRX_IBIDEN_Msk                (0x1UL << I3C_DEVRX_IBIDEN_Pos)         /*!< 0x00040000 */
12693 #define I3C_DEVRX_IBIDEN                    I3C_DEVRX_IBIDEN_Msk                    /*!< IBI Additional Data Enable */
12694 #define I3C_DEVRX_SUSP_Pos                  (19U)
12695 #define I3C_DEVRX_SUSP_Msk                  (0x1UL << I3C_DEVRX_SUSP_Pos)           /*!< 0x00080000 */
12696 #define I3C_DEVRX_SUSP                      I3C_DEVRX_SUSP_Msk                      /*!< Suspended Transfer */
12697 #define I3C_DEVRX_DIS_Pos                   (31U)
12698 #define I3C_DEVRX_DIS_Msk                   (0x1UL << I3C_DEVRX_DIS_Pos)            /*!< 0x80000000 */
12699 #define I3C_DEVRX_DIS                       I3C_DEVRX_DIS_Msk                       /*!< Disable Register access */
12700 
12701 /******************  Bit definition for I3C_MAXRLR register  ******************/
12702 #define I3C_MAXRLR_MRL_Pos                  (0U)
12703 #define I3C_MAXRLR_MRL_Msk                  (0xFFFFUL << I3C_MAXRLR_MRL_Pos)        /*!< 0x0000FFFF */
12704 #define I3C_MAXRLR_MRL                      I3C_MAXRLR_MRL_Msk                      /*!< Maximum Read Length */
12705 #define I3C_MAXRLR_IBIP_Pos                 (16U)
12706 #define I3C_MAXRLR_IBIP_Msk                 (0x7UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00070000 */
12707 #define I3C_MAXRLR_IBIP                     I3C_MAXRLR_IBIP_Msk                     /*!< IBI Payload size */
12708 #define I3C_MAXRLR_IBIP_0                   (0x1UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00010000 */
12709 #define I3C_MAXRLR_IBIP_1                   (0x2UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00020000 */
12710 #define I3C_MAXRLR_IBIP_2                   (0x4UL << I3C_MAXRLR_IBIP_Pos)          /*!< 0x00040000 */
12711 
12712 /******************  Bit definition for I3C_MAXWLR register  ******************/
12713 #define I3C_MAXWLR_MWL_Pos                  (0U)
12714 #define I3C_MAXWLR_MWL_Msk                  (0xFFFFUL << I3C_MAXWLR_MWL_Pos)        /*!< 0x0000FFFF */
12715 #define I3C_MAXWLR_MWL                      I3C_MAXWLR_MWL_Msk                      /*!< Maximum Write Length */
12716 
12717 /****************  Bit definition for I3C_TIMINGR0 register  ******************/
12718 #define I3C_TIMINGR0_SCLL_PP_Pos            (0U)
12719 #define I3C_TIMINGR0_SCLL_PP_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos)    /*!< 0x000000FF */
12720 #define I3C_TIMINGR0_SCLL_PP                I3C_TIMINGR0_SCLL_PP_Msk                /*!< SCL Low duration during I3C Push-Pull phases */
12721 #define I3C_TIMINGR0_SCLH_I3C_Pos           (8U)
12722 #define I3C_TIMINGR0_SCLH_I3C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos)   /*!< 0x0000FF00 */
12723 #define I3C_TIMINGR0_SCLH_I3C               I3C_TIMINGR0_SCLH_I3C_Msk               /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
12724 #define I3C_TIMINGR0_SCLL_OD_Pos            (16U)
12725 #define I3C_TIMINGR0_SCLL_OD_Msk            (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos)    /*!< 0x00FF0000 */
12726 #define I3C_TIMINGR0_SCLL_OD                I3C_TIMINGR0_SCLL_OD_Msk                /*!< SCL Low duration during  I3C Open-drain phases and I2C transfer */
12727 #define I3C_TIMINGR0_SCLH_I2C_Pos           (24U)
12728 #define I3C_TIMINGR0_SCLH_I2C_Msk           (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos)   /*!< 0xFF000000 */
12729 #define I3C_TIMINGR0_SCLH_I2C               I3C_TIMINGR0_SCLH_I2C_Msk               /*!< SCL High duration during I2C transfer */
12730 
12731 /****************  Bit definition for I3C_TIMINGR1 register  ******************/
12732 #define I3C_TIMINGR1_AVAL_Pos               (0U)
12733 #define I3C_TIMINGR1_AVAL_Msk               (0xFFUL << I3C_TIMINGR1_AVAL_Pos)       /*!< 0x000000FF */
12734 #define I3C_TIMINGR1_AVAL                   I3C_TIMINGR1_AVAL_Msk                   /*!< Timing for I3C Bus Idle or Available condition */
12735 #define I3C_TIMINGR1_ASNCR_Pos              (8U)
12736 #define I3C_TIMINGR1_ASNCR_Msk              (0x3UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000300 */
12737 #define I3C_TIMINGR1_ASNCR                  I3C_TIMINGR1_ASNCR_Msk                  /*!< Activity State of the New Controller */
12738 #define I3C_TIMINGR1_ASNCR_0                (0x1UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000100 */
12739 #define I3C_TIMINGR1_ASNCR_1                (0x2UL << I3C_TIMINGR1_ASNCR_Pos)       /*!< 0x00000200 */
12740 #define I3C_TIMINGR1_FREE_Pos               (16U)
12741 #define I3C_TIMINGR1_FREE_Msk               (0x7FUL << I3C_TIMINGR1_FREE_Pos)       /*!< 0x007F0000 */
12742 #define I3C_TIMINGR1_FREE                   I3C_TIMINGR1_FREE_Msk                   /*!< Timing for I3C Bus Free condition */
12743 #define I3C_TIMINGR1_SDA_HD_Pos             (28U)
12744 #define I3C_TIMINGR1_SDA_HD_Msk             (0x1UL << I3C_TIMINGR1_SDA_HD_Pos)      /*!< 0x00010000 */
12745 #define I3C_TIMINGR1_SDA_HD                 I3C_TIMINGR1_SDA_HD_Msk                 /*!< SDA Hold Duration */
12746 
12747 /****************  Bit definition for I3C_TIMINGR2 register  ******************/
12748 #define I3C_TIMINGR2_STALLT_Pos             (0U)
12749 #define I3C_TIMINGR2_STALLT_Msk             (0x1UL << I3C_TIMINGR2_STALLT_Pos)      /*!< 0x00000001 */
12750 #define I3C_TIMINGR2_STALLT                 I3C_TIMINGR2_STALLT_Msk                 /*!< Stall on T bit */
12751 #define I3C_TIMINGR2_STALLD_Pos             (1U)
12752 #define I3C_TIMINGR2_STALLD_Msk             (0x1UL << I3C_TIMINGR2_STALLD_Pos)      /*!< 0x00000002 */
12753 #define I3C_TIMINGR2_STALLD                 I3C_TIMINGR2_STALLD_Msk                 /*!< Stall on PAR bit of data bytes */
12754 #define I3C_TIMINGR2_STALLC_Pos             (2U)
12755 #define I3C_TIMINGR2_STALLC_Msk             (0x1UL << I3C_TIMINGR2_STALLC_Pos)      /*!< 0x00000004 */
12756 #define I3C_TIMINGR2_STALLC                 I3C_TIMINGR2_STALLC_Msk                 /*!< Stall on PAR bit of CCC byte */
12757 #define I3C_TIMINGR2_STALLA_Pos             (3U)
12758 #define I3C_TIMINGR2_STALLA_Msk             (0x1UL << I3C_TIMINGR2_STALLA_Pos)      /*!< 0x00000008 */
12759 #define I3C_TIMINGR2_STALLA                 I3C_TIMINGR2_STALLA_Msk                 /*!< Stall on ACK bit */
12760 #define I3C_TIMINGR2_STALL_Pos              (8U)
12761 #define I3C_TIMINGR2_STALL_Msk              (0xFFUL << I3C_TIMINGR2_STALL_Pos)      /*!< 0x0000FF00 */
12762 #define I3C_TIMINGR2_STALL                  I3C_TIMINGR2_STALL_Msk                  /*!< Controller Stall duration */
12763 
12764 /*******************  Bit definition for I3C_BCR register  ********************/
12765 #define I3C_BCR_BCR_Pos                     (0U)
12766 #define I3C_BCR_BCR_Msk                     (0xFFUL << I3C_BCR_BCR_Pos)             /*!< 0x000000FF */
12767 #define I3C_BCR_BCR                         I3C_BCR_BCR_Msk                         /*!< Bus Characteristics */
12768 #define I3C_BCR_BCR0_Pos                    (0U)
12769 #define I3C_BCR_BCR0_Msk                    (0x1UL << I3C_BCR_BCR0_Pos)             /*!< 0x00000001 */
12770 #define I3C_BCR_BCR0                        I3C_BCR_BCR0_Msk                        /*!< Max Data Speed Limitation */
12771 #define I3C_BCR_BCR1_Pos                    (1U)
12772 #define I3C_BCR_BCR1_Msk                    (0x1UL << I3C_BCR_BCR1_Pos)             /*!< 0x00000002 */
12773 #define I3C_BCR_BCR1                        I3C_BCR_BCR1_Msk                        /*!< IBI Request capable */
12774 #define I3C_BCR_BCR2_Pos                    (2U)
12775 #define I3C_BCR_BCR2_Msk                    (0x1UL << I3C_BCR_BCR2_Pos)             /*!< 0x00000004 */
12776 #define I3C_BCR_BCR2                        I3C_BCR_BCR2_Msk                        /*!< IBI Payload additional Mandatory Data Byte */
12777 #define I3C_BCR_BCR6_Pos                    (6U)
12778 #define I3C_BCR_BCR6_Msk                    (0x1UL << I3C_BCR_BCR6_Pos)             /*!< 0x00000040 */
12779 #define I3C_BCR_BCR6                        I3C_BCR_BCR6_Msk                        /*!< Device Role shared during Dynamic Address Assignment */
12780 
12781 /*******************  Bit definition for I3C_DCR register  ********************/
12782 #define I3C_DCR_DCR_Pos                     (0U)
12783 #define I3C_DCR_DCR_Msk                     (0xFFUL << I3C_DCR_DCR_Pos)             /*!< 0x000000FF */
12784 #define I3C_DCR_DCR                         I3C_DCR_DCR_Msk                         /*!< Devices Characteristics */
12785 
12786 /*****************  Bit definition for I3C_GETCAPR register  ******************/
12787 #define I3C_GETCAPR_CAPPEND_Pos             (14U)
12788 #define I3C_GETCAPR_CAPPEND_Msk             (0x1UL << I3C_GETCAPR_CAPPEND_Pos)      /*!< 0x00004000 */
12789 #define I3C_GETCAPR_CAPPEND                 I3C_GETCAPR_CAPPEND_Msk                 /*!< IBI Request with Mandatory Data Byte */
12790 
12791 /*****************  Bit definition for I3C_CRCAPR register  *******************/
12792 #define I3C_CRCAPR_CAPDHOFF_Pos             (3U)
12793 #define I3C_CRCAPR_CAPDHOFF_Msk             (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos)      /*!< 0x00000008 */
12794 #define I3C_CRCAPR_CAPDHOFF                 I3C_CRCAPR_CAPDHOFF_Msk                 /*!< Controller-role handoff needed */
12795 #define I3C_CRCAPR_CAPGRP_Pos               (9U)
12796 #define I3C_CRCAPR_CAPGRP_Msk               (0x1UL << I3C_CRCAPR_CAPGRP_Pos)        /*!< 0x00000200 */
12797 #define I3C_CRCAPR_CAPGRP                   I3C_CRCAPR_CAPGRP_Msk                   /*!< Group Address handoff supported */
12798 
12799 /****************  Bit definition for I3C_GETMXDSR register  ******************/
12800 #define I3C_GETMXDSR_HOFFAS_Pos             (0U)
12801 #define I3C_GETMXDSR_HOFFAS_Msk             (0x3UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000003 */
12802 #define I3C_GETMXDSR_HOFFAS                 I3C_GETMXDSR_HOFFAS_Msk                 /*!< Handoff Activity State */
12803 #define I3C_GETMXDSR_HOFFAS_0               (0x1UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000001 */
12804 #define I3C_GETMXDSR_HOFFAS_1               (0x2UL << I3C_GETMXDSR_HOFFAS_Pos)      /*!< 0x00000002 */
12805 #define I3C_GETMXDSR_FMT_Pos                (8U)
12806 #define I3C_GETMXDSR_FMT_Msk                (0x3UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000300 */
12807 #define I3C_GETMXDSR_FMT                    I3C_GETMXDSR_FMT_Msk                    /*!< Get Max Data Speed response in format 2 */
12808 #define I3C_GETMXDSR_FMT_0                  (0x1UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000100 */
12809 #define I3C_GETMXDSR_FMT_1                  (0x2UL << I3C_GETMXDSR_FMT_Pos)         /*!< 0x00000200 */
12810 #define I3C_GETMXDSR_RDTURN_Pos             (16U)
12811 #define I3C_GETMXDSR_RDTURN_Msk             (0xFFUL << I3C_GETMXDSR_RDTURN_Pos)     /*!< 0x00FF0000 */
12812 #define I3C_GETMXDSR_RDTURN                 I3C_GETMXDSR_RDTURN_Msk                 /*!< Max Read Turnaround Middle Byte  */
12813 #define I3C_GETMXDSR_TSCO_Pos               (24U)
12814 #define I3C_GETMXDSR_TSCO_Msk               (0x1UL << I3C_GETMXDSR_TSCO_Pos)        /*!< 0x01000000 */
12815 #define I3C_GETMXDSR_TSCO                   I3C_GETMXDSR_TSCO_Msk                   /*!< Clock-to-data Turnaround time */
12816 
12817 /******************  Bit definition for I3C_EPIDR register  *******************/
12818 #define I3C_EPIDR_MIPIID_Pos                (12U)
12819 #define I3C_EPIDR_MIPIID_Msk                (0xFUL << I3C_EPIDR_MIPIID_Pos)         /*!< 0x0000F000 */
12820 #define I3C_EPIDR_MIPIID                    I3C_EPIDR_MIPIID_Msk                    /*!< MIPI Instance ID */
12821 #define I3C_EPIDR_IDTSEL_Pos                (16U)
12822 #define I3C_EPIDR_IDTSEL_Msk                (0x1UL << I3C_EPIDR_IDTSEL_Pos)         /*!< 0x00010000 */
12823 #define I3C_EPIDR_IDTSEL                    I3C_EPIDR_IDTSEL_Msk                    /*!< ID Type Selector */
12824 #define I3C_EPIDR_MIPIMID_Pos               (17U)
12825 #define I3C_EPIDR_MIPIMID_Msk               (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos)     /*!< 0xFFFE0000 */
12826 #define I3C_EPIDR_MIPIMID                   I3C_EPIDR_MIPIMID_Msk                   /*!< MIPI Manufacturer ID */
12827 
12828 /******************************************************************************/
12829 /*                                                                            */
12830 /*                           Independent WATCHDOG                             */
12831 /*                                                                            */
12832 /******************************************************************************/
12833 /*******************  Bit definition for IWDG_KR register  ********************/
12834 #define IWDG_KR_KEY_Pos                     (0U)
12835 #define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)           /*!< 0x0000FFFF */
12836 #define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                         /*!<Key value (write only, read 0000h)  */
12837 
12838 /*******************  Bit definition for IWDG_PR register  ********************/
12839 #define IWDG_PR_PR_Pos                      (0U)
12840 #define IWDG_PR_PR_Msk                      (0xFUL << IWDG_PR_PR_Pos)               /*!< 0x0000000F */
12841 #define IWDG_PR_PR                          IWDG_PR_PR_Msk                          /*!<PR[3:0] (Prescaler divider)         */
12842 #define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)               /*!< 0x00000001 */
12843 #define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)               /*!< 0x00000002 */
12844 #define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)               /*!< 0x00000004 */
12845 #define IWDG_PR_PR_3                        (0x8UL << IWDG_PR_PR_Pos)               /*!< 0x00000008 */
12846 
12847 /*******************  Bit definition for IWDG_RLR register  *******************/
12848 #define IWDG_RLR_RL_Pos                     (0U)
12849 #define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)            /*!< 0x00000FFF */
12850 #define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                         /*!<Watchdog counter reload value        */
12851 
12852 /*******************  Bit definition for IWDG_SR register  ********************/
12853 #define IWDG_SR_PVU_Pos                     (0U)
12854 #define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)              /*!< 0x00000001 */
12855 #define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                         /*!< Watchdog prescaler value update */
12856 #define IWDG_SR_RVU_Pos                     (1U)
12857 #define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)              /*!< 0x00000002 */
12858 #define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                         /*!< Watchdog counter reload value update */
12859 #define IWDG_SR_WVU_Pos                     (2U)
12860 #define IWDG_SR_WVU_Msk                     (0x1UL << IWDG_SR_WVU_Pos)              /*!< 0x00000004 */
12861 #define IWDG_SR_WVU                         IWDG_SR_WVU_Msk                         /*!< Watchdog counter window value update */
12862 #define IWDG_SR_EWU_Pos                     (3U)
12863 #define IWDG_SR_EWU_Msk                     (0x1UL << IWDG_SR_EWU_Pos)              /*!< 0x00000008 */
12864 #define IWDG_SR_EWU                         IWDG_SR_EWU_Msk                         /*!< Watchdog interrupt comparator value update */
12865 #define IWDG_SR_ONF_Pos                     (8U)
12866 #define IWDG_SR_ONF_Msk                     (0x1UL << IWDG_SR_ONF_Pos)              /*!< 0x00000100 */
12867 #define IWDG_SR_ONF                         IWDG_SR_ONF_Msk                         /*!< Watchdog Enable status bit */
12868 #define IWDG_SR_EWIF_Pos                    (14U)
12869 #define IWDG_SR_EWIF_Msk                    (0x1UL << IWDG_SR_EWIF_Pos)             /*!< 0x00004000 */
12870 #define IWDG_SR_EWIF                        IWDG_SR_EWIF_Msk                        /*!< Watchdog early interrupt flag */
12871 
12872 /******************  Bit definition for IWDG_WINR register  *******************/
12873 #define IWDG_WINR_WIN_Pos                   (0U)
12874 #define IWDG_WINR_WIN_Msk                   (0xFFFUL << IWDG_WINR_WIN_Pos)          /*!< 0x00000FFF */
12875 #define IWDG_WINR_WIN                       IWDG_WINR_WIN_Msk                       /*!< Watchdog counter window value */
12876 
12877 /******************  Bit definition for IWDG_EWCR register  *******************/
12878 #define IWDG_EWCR_EWIT_Pos                  (0U)
12879 #define IWDG_EWCR_EWIT_Msk                  (0xFFFUL << IWDG_EWCR_EWIT_Pos)         /*!< 0x00000FFF */
12880 #define IWDG_EWCR_EWIT                      IWDG_EWCR_EWIT_Msk                      /*!< Watchdog early wakeup comparator value */
12881 #define IWDG_EWCR_EWIC_Pos                  (14U)
12882 #define IWDG_EWCR_EWIC_Msk                  (0x1UL << IWDG_EWCR_EWIC_Pos)           /*!< 0x00000FFF */
12883 #define IWDG_EWCR_EWIC                      IWDG_EWCR_EWIC_Msk                      /*!< Watchdog early wakeup comparator value */
12884 #define IWDG_EWCR_EWIE_Pos                  (15U)
12885 #define IWDG_EWCR_EWIE_Msk                  (0x1UL << IWDG_EWCR_EWIE_Pos)           /*!< 0x00000FFF */
12886 #define IWDG_EWCR_EWIE                      IWDG_EWCR_EWIE_Msk                      /*!< Watchdog early wakeup comparator value */
12887 
12888 
12889 /******************************************************************************/
12890 /*                                                                            */
12891 /*                   Serial Peripheral Interface (SPI/I2S)                    */
12892 /*                                                                            */
12893 /******************************************************************************/
12894 /*******************  Bit definition for SPI_CR1 register  ********************/
12895 #define SPI_CR1_SPE_Pos                     (0U)
12896 #define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)              /*!< 0x00000001 */
12897 #define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                         /*!<Serial Peripheral Enable */
12898 #define SPI_CR1_MASRX_Pos                   (8U)
12899 #define SPI_CR1_MASRX_Msk                   (0x1UL << SPI_CR1_MASRX_Pos)            /*!< 0x00000100 */
12900 #define SPI_CR1_MASRX                       SPI_CR1_MASRX_Msk                       /*!<Master automatic SUSP in Receive mode */
12901 #define SPI_CR1_CSTART_Pos                  (9U)
12902 #define SPI_CR1_CSTART_Msk                  (0x1UL << SPI_CR1_CSTART_Pos)           /*!< 0x00000200 */
12903 #define SPI_CR1_CSTART                      SPI_CR1_CSTART_Msk                      /*!<Master transfer start  */
12904 #define SPI_CR1_CSUSP_Pos                   (10U)
12905 #define SPI_CR1_CSUSP_Msk                   (0x1UL << SPI_CR1_CSUSP_Pos)            /*!< 0x00000400 */
12906 #define SPI_CR1_CSUSP                       SPI_CR1_CSUSP_Msk                       /*!<Master SUSPend request */
12907 #define SPI_CR1_HDDIR_Pos                   (11U)
12908 #define SPI_CR1_HDDIR_Msk                   (0x1UL << SPI_CR1_HDDIR_Pos)            /*!< 0x00000800 */
12909 #define SPI_CR1_HDDIR                       SPI_CR1_HDDIR_Msk                       /*!<Rx/Tx direction at Half-duplex mode */
12910 #define SPI_CR1_SSI_Pos                     (12U)
12911 #define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)              /*!< 0x00001000 */
12912 #define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                         /*!<Internal SS signal input level */
12913 #define SPI_CR1_CRC33_17_Pos                (13U)
12914 #define SPI_CR1_CRC33_17_Msk                (0x1UL << SPI_CR1_CRC33_17_Pos)         /*!< 0x00002000 */
12915 #define SPI_CR1_CRC33_17                    SPI_CR1_CRC33_17_Msk                    /*!<32-bit CRC polynomial configuration */
12916 #define SPI_CR1_RCRCINI_Pos                 (14U)
12917 #define SPI_CR1_RCRCINI_Msk                 (0x1UL << SPI_CR1_RCRCINI_Pos)          /*!< 0x00004000 */
12918 #define SPI_CR1_RCRCINI                     SPI_CR1_RCRCINI_Msk                     /*!<CRC init pattern control for receiver */
12919 #define SPI_CR1_TCRCINI_Pos                 (15U)
12920 #define SPI_CR1_TCRCINI_Msk                 (0x1UL << SPI_CR1_TCRCINI_Pos)          /*!< 0x00008000 */
12921 #define SPI_CR1_TCRCINI                     SPI_CR1_TCRCINI_Msk                     /*!<CRC init pattern control for transmitter */
12922 #define SPI_CR1_IOLOCK_Pos                  (16U)
12923 #define SPI_CR1_IOLOCK_Msk                  (0x1UL << SPI_CR1_IOLOCK_Pos)           /*!< 0x00010000 */
12924 #define SPI_CR1_IOLOCK                      SPI_CR1_IOLOCK_Msk                      /*!<Locking the AF configuration of associated IOs */
12925 
12926 /*******************  Bit definition for SPI_CR2 register  ********************/
12927 #define SPI_CR2_TSIZE_Pos                   (0U)
12928 #define SPI_CR2_TSIZE_Msk                   (0xFFFFUL << SPI_CR2_TSIZE_Pos)         /*!< 0x0000FFFF */
12929 #define SPI_CR2_TSIZE                       SPI_CR2_TSIZE_Msk                       /*!<Number of data at current transfer */
12930 
12931 /*******************  Bit definition for SPI_CFG1 register  ********************/
12932 #define SPI_CFG1_DSIZE_Pos                  (0U)
12933 #define SPI_CFG1_DSIZE_Msk                  (0x1FUL << SPI_CFG1_DSIZE_Pos)          /*!< 0x0000001F */
12934 #define SPI_CFG1_DSIZE                      SPI_CFG1_DSIZE_Msk                      /*!<DSIZE[4:0]: Bits number in single SPI data frame */
12935 #define SPI_CFG1_DSIZE_0                    (0x01UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000001 */
12936 #define SPI_CFG1_DSIZE_1                    (0x02UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000002 */
12937 #define SPI_CFG1_DSIZE_2                    (0x04UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000004 */
12938 #define SPI_CFG1_DSIZE_3                    (0x08UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000008 */
12939 #define SPI_CFG1_DSIZE_4                    (0x10UL << SPI_CFG1_DSIZE_Pos)          /*!< 0x00000010 */
12940 #define SPI_CFG1_FTHLV_Pos                  (5U)
12941 #define SPI_CFG1_FTHLV_Msk                  (0xFUL << SPI_CFG1_FTHLV_Pos)           /*!< 0x000001E0 */
12942 #define SPI_CFG1_FTHLV                      SPI_CFG1_FTHLV_Msk                      /*!<FTHVL [3:0]: FIFO threshold level*/
12943 #define SPI_CFG1_FTHLV_0                    (0x1UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000020 */
12944 #define SPI_CFG1_FTHLV_1                    (0x2UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000040 */
12945 #define SPI_CFG1_FTHLV_2                    (0x4UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000080 */
12946 #define SPI_CFG1_FTHLV_3                    (0x8UL << SPI_CFG1_FTHLV_Pos)           /*!< 0x00000100 */
12947 #define SPI_CFG1_UDRCFG_Pos                 (9U)
12948 #define SPI_CFG1_UDRCFG_Msk                 (0x1UL << SPI_CFG1_UDRCFG_Pos)          /*!< 0x00000600 */
12949 #define SPI_CFG1_UDRCFG                     SPI_CFG1_UDRCFG_Msk                     /*!<Behavior of Slave transmitter at underrun */
12950 #define SPI_CFG1_RXDMAEN_Pos                (14U)
12951 #define SPI_CFG1_RXDMAEN_Msk                (0x1UL << SPI_CFG1_RXDMAEN_Pos)         /*!< 0x00004000 */
12952 #define SPI_CFG1_RXDMAEN                    SPI_CFG1_RXDMAEN_Msk                    /*!<Rx DMA stream enable */
12953 #define SPI_CFG1_TXDMAEN_Pos                (15U)
12954 #define SPI_CFG1_TXDMAEN_Msk                (0x1UL << SPI_CFG1_TXDMAEN_Pos)         /*!< 0x00008000 */
12955 #define SPI_CFG1_TXDMAEN                    SPI_CFG1_TXDMAEN_Msk                    /*!<Tx DMA stream enable */
12956 #define SPI_CFG1_CRCSIZE_Pos                (16U)
12957 #define SPI_CFG1_CRCSIZE_Msk                (0x1FUL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x001F0000 */
12958 #define SPI_CFG1_CRCSIZE                    SPI_CFG1_CRCSIZE_Msk                    /*!<CRCSIZE [4:0]: Length of CRC frame */
12959 #define SPI_CFG1_CRCSIZE_0                  (0x01UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00010000 */
12960 #define SPI_CFG1_CRCSIZE_1                  (0x02UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00020000 */
12961 #define SPI_CFG1_CRCSIZE_2                  (0x04UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00040000 */
12962 #define SPI_CFG1_CRCSIZE_3                  (0x08UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00080000 */
12963 #define SPI_CFG1_CRCSIZE_4                  (0x10UL << SPI_CFG1_CRCSIZE_Pos)        /*!< 0x00100000 */
12964 #define SPI_CFG1_CRCEN_Pos                  (22U)
12965 #define SPI_CFG1_CRCEN_Msk                  (0x1UL << SPI_CFG1_CRCEN_Pos)           /*!< 0x00400000 */
12966 #define SPI_CFG1_CRCEN                      SPI_CFG1_CRCEN_Msk                      /*!<Hardware CRC computation enable */
12967 #define SPI_CFG1_MBR_Pos                    (28U)
12968 #define SPI_CFG1_MBR_Msk                    (0x7UL << SPI_CFG1_MBR_Pos)             /*!< 0x70000000 */
12969 #define SPI_CFG1_MBR                        SPI_CFG1_MBR_Msk                        /*!<Master baud rate */
12970 #define SPI_CFG1_MBR_0                      (0x1UL << SPI_CFG1_MBR_Pos)             /*!< 0x10000000 */
12971 #define SPI_CFG1_MBR_1                      (0x2UL << SPI_CFG1_MBR_Pos)             /*!< 0x20000000 */
12972 #define SPI_CFG1_MBR_2                      (0x4UL << SPI_CFG1_MBR_Pos)             /*!< 0x40000000 */
12973 #define SPI_CFG1_BPASS_Pos                  (31U)
12974 #define SPI_CFG1_BPASS_Msk                  (0x1UL << SPI_CFG1_BPASS_Pos)           /*!< 0x80000000 */
12975 #define SPI_CFG1_BPASS                      SPI_CFG1_BPASS_Msk                      /*!<Bypass of the prescaler */
12976 
12977 /*******************  Bit definition for SPI_CFG2 register  ********************/
12978 #define SPI_CFG2_MSSI_Pos                   (0U)
12979 #define SPI_CFG2_MSSI_Msk                   (0xFUL << SPI_CFG2_MSSI_Pos)            /*!< 0x0000000F */
12980 #define SPI_CFG2_MSSI                       SPI_CFG2_MSSI_Msk                       /*!<Master SS Idleness */
12981 #define SPI_CFG2_MSSI_0                     (0x1UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000001 */
12982 #define SPI_CFG2_MSSI_1                     (0x2UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000002 */
12983 #define SPI_CFG2_MSSI_2                     (0x4UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000004 */
12984 #define SPI_CFG2_MSSI_3                     (0x8UL << SPI_CFG2_MSSI_Pos)            /*!< 0x00000008 */
12985 #define SPI_CFG2_MIDI_Pos                   (4U)
12986 #define SPI_CFG2_MIDI_Msk                   (0xFUL << SPI_CFG2_MIDI_Pos)            /*!< 0x000000F0 */
12987 #define SPI_CFG2_MIDI                       SPI_CFG2_MIDI_Msk                       /*!<Master Inter-Data Idleness */
12988 #define SPI_CFG2_MIDI_0                     (0x1UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000010 */
12989 #define SPI_CFG2_MIDI_1                     (0x2UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000020 */
12990 #define SPI_CFG2_MIDI_2                     (0x4UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000040 */
12991 #define SPI_CFG2_MIDI_3                     (0x8UL << SPI_CFG2_MIDI_Pos)            /*!< 0x00000080 */
12992 #define SPI_CFG2_RDIOM_Pos                  (13U)
12993 #define SPI_CFG2_RDIOM_Msk                  (0x1UL << SPI_CFG2_RDIOM_Pos)           /*!< 0x00002000 */
12994 #define SPI_CFG2_RDIOM                      SPI_CFG2_RDIOM_Msk                      /*!<RDY signal input/output management */
12995 #define SPI_CFG2_RDIOP_Pos                  (14U)
12996 #define SPI_CFG2_RDIOP_Msk                  (0x1UL << SPI_CFG2_RDIOP_Pos)           /*!< 0x00004000 */
12997 #define SPI_CFG2_RDIOP                      SPI_CFG2_RDIOP_Msk                      /*!<RDY signal input/output polarity */
12998 #define SPI_CFG2_IOSWP_Pos                  (15U)
12999 #define SPI_CFG2_IOSWP_Msk                  (0x1UL << SPI_CFG2_IOSWP_Pos)           /*!< 0x00008000 */
13000 #define SPI_CFG2_IOSWP                      SPI_CFG2_IOSWP_Msk                      /*!<Swap functionality of MISO and MOSI pins */
13001 #define SPI_CFG2_COMM_Pos                   (17U)
13002 #define SPI_CFG2_COMM_Msk                   (0x3UL << SPI_CFG2_COMM_Pos)            /*!< 0x00060000 */
13003 #define SPI_CFG2_COMM                       SPI_CFG2_COMM_Msk                       /*!<COMM [1:0]: SPI Communication Mode*/
13004 #define SPI_CFG2_COMM_0                     (0x1UL << SPI_CFG2_COMM_Pos)            /*!< 0x00020000 */
13005 #define SPI_CFG2_COMM_1                     (0x2UL << SPI_CFG2_COMM_Pos)            /*!< 0x00040000 */
13006 #define SPI_CFG2_SP_Pos                     (19U)
13007 #define SPI_CFG2_SP_Msk                     (0x7UL << SPI_CFG2_SP_Pos)              /*!< 0x00380000 */
13008 #define SPI_CFG2_SP                         SPI_CFG2_SP_Msk                         /*!<SP[2:0]: Serial Protocol */
13009 #define SPI_CFG2_SP_0                       (0x1UL << SPI_CFG2_SP_Pos)              /*!< 0x00080000 */
13010 #define SPI_CFG2_SP_1                       (0x2UL << SPI_CFG2_SP_Pos)              /*!< 0x00100000 */
13011 #define SPI_CFG2_SP_2                       (0x4UL << SPI_CFG2_SP_Pos)              /*!< 0x00200000 */
13012 #define SPI_CFG2_MASTER_Pos                 (22U)
13013 #define SPI_CFG2_MASTER_Msk                 (0x1UL << SPI_CFG2_MASTER_Pos)          /*!< 0x00400000 */
13014 #define SPI_CFG2_MASTER                     SPI_CFG2_MASTER_Msk                     /*!<SPI Master */
13015 #define SPI_CFG2_LSBFRST_Pos                (23U)
13016 #define SPI_CFG2_LSBFRST_Msk                (0x1UL << SPI_CFG2_LSBFRST_Pos)         /*!< 0x00800000 */
13017 #define SPI_CFG2_LSBFRST                    SPI_CFG2_LSBFRST_Msk                    /*!<Data frame format */
13018 #define SPI_CFG2_CPHA_Pos                   (24U)
13019 #define SPI_CFG2_CPHA_Msk                   (0x1UL << SPI_CFG2_CPHA_Pos)            /*!< 0x01000000 */
13020 #define SPI_CFG2_CPHA                       SPI_CFG2_CPHA_Msk                       /*!<Clock Phase */
13021 #define SPI_CFG2_CPOL_Pos                   (25U)
13022 #define SPI_CFG2_CPOL_Msk                   (0x1UL << SPI_CFG2_CPOL_Pos)            /*!< 0x02000000 */
13023 #define SPI_CFG2_CPOL                       SPI_CFG2_CPOL_Msk                       /*!<Clock Polarity */
13024 #define SPI_CFG2_SSM_Pos                    (26U)
13025 #define SPI_CFG2_SSM_Msk                    (0x1UL << SPI_CFG2_SSM_Pos)             /*!< 0x04000000 */
13026 #define SPI_CFG2_SSM                        SPI_CFG2_SSM_Msk                        /*!<Software slave management */
13027 #define SPI_CFG2_SSIOP_Pos                  (28U)
13028 #define SPI_CFG2_SSIOP_Msk                  (0x1UL << SPI_CFG2_SSIOP_Pos)           /*!< 0x10000000 */
13029 #define SPI_CFG2_SSIOP                      SPI_CFG2_SSIOP_Msk                      /*!<SS input/output polarity */
13030 #define SPI_CFG2_SSOE_Pos                   (29U)
13031 #define SPI_CFG2_SSOE_Msk                   (0x1UL << SPI_CFG2_SSOE_Pos)            /*!< 0x20000000 */
13032 #define SPI_CFG2_SSOE                       SPI_CFG2_SSOE_Msk                       /*!<SS output enable */
13033 #define SPI_CFG2_SSOM_Pos                   (30U)
13034 #define SPI_CFG2_SSOM_Msk                   (0x1UL << SPI_CFG2_SSOM_Pos)            /*!< 0x40000000 */
13035 #define SPI_CFG2_SSOM                       SPI_CFG2_SSOM_Msk                       /*!<SS output management in master mode */
13036 #define SPI_CFG2_AFCNTR_Pos                 (31U)
13037 #define SPI_CFG2_AFCNTR_Msk                 (0x1UL << SPI_CFG2_AFCNTR_Pos)          /*!< 0x80000000 */
13038 #define SPI_CFG2_AFCNTR                     SPI_CFG2_AFCNTR_Msk                     /*!<Alternate function GPIOs control */
13039 
13040 /*******************  Bit definition for SPI_IER register  ********************/
13041 #define SPI_IER_RXPIE_Pos                   (0U)
13042 #define SPI_IER_RXPIE_Msk                   (0x1UL << SPI_IER_RXPIE_Pos)            /*!< 0x00000001 */
13043 #define SPI_IER_RXPIE                       SPI_IER_RXPIE_Msk                       /*!<RXP Interrupt Enable */
13044 #define SPI_IER_TXPIE_Pos                   (1U)
13045 #define SPI_IER_TXPIE_Msk                   (0x1UL << SPI_IER_TXPIE_Pos)            /*!< 0x00000002 */
13046 #define SPI_IER_TXPIE                       SPI_IER_TXPIE_Msk                       /*!<TXP interrupt enable */
13047 #define SPI_IER_DXPIE_Pos                   (2U)
13048 #define SPI_IER_DXPIE_Msk                   (0x1UL << SPI_IER_DXPIE_Pos)            /*!< 0x00000004 */
13049 #define SPI_IER_DXPIE                       SPI_IER_DXPIE_Msk                       /*!<DXP interrupt enable */
13050 #define SPI_IER_EOTIE_Pos                   (3U)
13051 #define SPI_IER_EOTIE_Msk                   (0x1UL << SPI_IER_EOTIE_Pos)            /*!< 0x00000008 */
13052 #define SPI_IER_EOTIE                       SPI_IER_EOTIE_Msk                       /*!<EOT/SUSP/TXC interrupt enable */
13053 #define SPI_IER_TXTFIE_Pos                  (4U)
13054 #define SPI_IER_TXTFIE_Msk                  (0x1UL << SPI_IER_TXTFIE_Pos)           /*!< 0x00000010 */
13055 #define SPI_IER_TXTFIE                      SPI_IER_TXTFIE_Msk                      /*!<TXTF interrupt enable */
13056 #define SPI_IER_UDRIE_Pos                   (5U)
13057 #define SPI_IER_UDRIE_Msk                   (0x1UL << SPI_IER_UDRIE_Pos)            /*!< 0x00000020 */
13058 #define SPI_IER_UDRIE                       SPI_IER_UDRIE_Msk                       /*!<UDR interrupt enable */
13059 #define SPI_IER_OVRIE_Pos                   (6U)
13060 #define SPI_IER_OVRIE_Msk                   (0x1UL << SPI_IER_OVRIE_Pos)            /*!< 0x00000040 */
13061 #define SPI_IER_OVRIE                       SPI_IER_OVRIE_Msk                       /*!<OVR interrupt enable */
13062 #define SPI_IER_CRCEIE_Pos                  (7U)
13063 #define SPI_IER_CRCEIE_Msk                  (0x1UL << SPI_IER_CRCEIE_Pos)           /*!< 0x00000080 */
13064 #define SPI_IER_CRCEIE                      SPI_IER_CRCEIE_Msk                      /*!<CRCE interrupt enable */
13065 #define SPI_IER_TIFREIE_Pos                 (8U)
13066 #define SPI_IER_TIFREIE_Msk                 (0x1UL << SPI_IER_TIFREIE_Pos)          /*!< 0x00000100 */
13067 #define SPI_IER_TIFREIE                     SPI_IER_TIFREIE_Msk                     /*!<TI Frame Error interrupt enable */
13068 #define SPI_IER_MODFIE_Pos                  (9U)
13069 #define SPI_IER_MODFIE_Msk                  (0x1UL << SPI_IER_MODFIE_Pos)           /*!< 0x00000200 */
13070 #define SPI_IER_MODFIE                      SPI_IER_MODFIE_Msk                      /*!<MODF interrupt enable */
13071 
13072 /*******************  Bit definition for SPI_SR register  ********************/
13073 #define SPI_SR_RXP_Pos                      (0U)
13074 #define SPI_SR_RXP_Msk                      (0x1UL << SPI_SR_RXP_Pos)               /*!< 0x00000001 */
13075 #define SPI_SR_RXP                          SPI_SR_RXP_Msk                          /*!<Rx-Packet available */
13076 #define SPI_SR_TXP_Pos                      (1U)
13077 #define SPI_SR_TXP_Msk                      (0x1UL << SPI_SR_TXP_Pos)               /*!< 0x00000002 */
13078 #define SPI_SR_TXP                          SPI_SR_TXP_Msk                          /*!<Tx-Packet space available */
13079 #define SPI_SR_DXP_Pos                      (2U)
13080 #define SPI_SR_DXP_Msk                      (0x1UL << SPI_SR_DXP_Pos)               /*!< 0x00000004 */
13081 #define SPI_SR_DXP                          SPI_SR_DXP_Msk                          /*!<Duplex Packet available */
13082 #define SPI_SR_EOT_Pos                      (3U)
13083 #define SPI_SR_EOT_Msk                      (0x1UL << SPI_SR_EOT_Pos)               /*!< 0x00000008 */
13084 #define SPI_SR_EOT                          SPI_SR_EOT_Msk                          /*!<Duplex Packet available */
13085 #define SPI_SR_TXTF_Pos                     (4U)
13086 #define SPI_SR_TXTF_Msk                     (0x1UL << SPI_SR_TXTF_Pos)              /*!< 0x00000010 */
13087 #define SPI_SR_TXTF                         SPI_SR_TXTF_Msk                         /*!<Transmission Transfer Filled */
13088 #define SPI_SR_UDR_Pos                      (5U)
13089 #define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)               /*!< 0x00000020 */
13090 #define SPI_SR_UDR                          SPI_SR_UDR_Msk                          /*!<UDR at Slave transmission */
13091 #define SPI_SR_OVR_Pos                      (6U)
13092 #define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)               /*!< 0x00000040 */
13093 #define SPI_SR_OVR                          SPI_SR_OVR_Msk                          /*!<Rx-Packet available */
13094 #define SPI_SR_CRCE_Pos                     (7U)
13095 #define SPI_SR_CRCE_Msk                     (0x1UL << SPI_SR_CRCE_Pos)              /*!< 0x00000080 */
13096 #define SPI_SR_CRCE                         SPI_SR_CRCE_Msk                         /*!<CRC Error Detected */
13097 #define SPI_SR_TIFRE_Pos                    (8U)
13098 #define SPI_SR_TIFRE_Msk                    (0x1UL << SPI_SR_TIFRE_Pos)             /*!< 0x00000100 */
13099 #define SPI_SR_TIFRE                        SPI_SR_TIFRE_Msk                        /*!<TI frame format error Detected */
13100 #define SPI_SR_MODF_Pos                     (9U)
13101 #define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)              /*!< 0x00000200 */
13102 #define SPI_SR_MODF                         SPI_SR_MODF_Msk                         /*!<Mode Fault Detected */
13103 #define SPI_SR_SUSP_Pos                     (11U)
13104 #define SPI_SR_SUSP_Msk                     (0x1UL << SPI_SR_SUSP_Pos)              /*!< 0x00000800 */
13105 #define SPI_SR_SUSP                         SPI_SR_SUSP_Msk                         /*!<SUSP is set by hardware */
13106 #define SPI_SR_TXC_Pos                      (12U)
13107 #define SPI_SR_TXC_Msk                      (0x1UL << SPI_SR_TXC_Pos)               /*!< 0x00001000 */
13108 #define SPI_SR_TXC                          SPI_SR_TXC_Msk                          /*!<TxFIFO transmission complete */
13109 #define SPI_SR_RXPLVL_Pos                   (13U)
13110 #define SPI_SR_RXPLVL_Msk                   (0x3UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00006000 */
13111 #define SPI_SR_RXPLVL                       SPI_SR_RXPLVL_Msk                       /*!<RxFIFO Packing Level */
13112 #define SPI_SR_RXPLVL_0                     (0x1UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00002000 */
13113 #define SPI_SR_RXPLVL_1                     (0x2UL << SPI_SR_RXPLVL_Pos)            /*!< 0x00004000 */
13114 #define SPI_SR_RXWNE_Pos                    (15U)
13115 #define SPI_SR_RXWNE_Msk                    (0x1UL << SPI_SR_RXWNE_Pos)             /*!< 0x00008000 */
13116 #define SPI_SR_RXWNE                        SPI_SR_RXWNE_Msk                        /*!<Rx FIFO Word Not Empty */
13117 #define SPI_SR_CTSIZE_Pos                   (16U)
13118 #define SPI_SR_CTSIZE_Msk                   (0xFFFFUL << SPI_SR_CTSIZE_Pos)         /*!< 0xFFFF0000 */
13119 #define SPI_SR_CTSIZE                       SPI_SR_CTSIZE_Msk                       /*!<Number of data frames remaining in TSIZE */
13120 
13121 /*******************  Bit definition for SPI_IFCR register  ********************/
13122 #define SPI_IFCR_EOTC_Pos                   (3U)
13123 #define SPI_IFCR_EOTC_Msk                   (0x1UL << SPI_IFCR_EOTC_Pos)            /*!< 0x00000008 */
13124 #define SPI_IFCR_EOTC                       SPI_IFCR_EOTC_Msk                       /*!<End Of Transfer flag clear */
13125 #define SPI_IFCR_TXTFC_Pos                  (4U)
13126 #define SPI_IFCR_TXTFC_Msk                  (0x1UL << SPI_IFCR_TXTFC_Pos)           /*!< 0x00000010 */
13127 #define SPI_IFCR_TXTFC                      SPI_IFCR_TXTFC_Msk                      /*!<Transmission Transfer Filled flag clear */
13128 #define SPI_IFCR_UDRC_Pos                   (5U)
13129 #define SPI_IFCR_UDRC_Msk                   (0x1UL << SPI_IFCR_UDRC_Pos)            /*!< 0x00000020 */
13130 #define SPI_IFCR_UDRC                       SPI_IFCR_UDRC_Msk                       /*!<Underrun flag clear */
13131 #define SPI_IFCR_OVRC_Pos                   (6U)
13132 #define SPI_IFCR_OVRC_Msk                   (0x1UL << SPI_IFCR_OVRC_Pos)            /*!< 0x00000040 */
13133 #define SPI_IFCR_OVRC                       SPI_IFCR_OVRC_Msk                       /*!<Overrun flag clear */
13134 #define SPI_IFCR_CRCEC_Pos                  (7U)
13135 #define SPI_IFCR_CRCEC_Msk                  (0x1UL << SPI_IFCR_CRCEC_Pos)           /*!< 0x00000080 */
13136 #define SPI_IFCR_CRCEC                      SPI_IFCR_CRCEC_Msk                      /*!<CRC Error flag clear */
13137 #define SPI_IFCR_TIFREC_Pos                 (8U)
13138 #define SPI_IFCR_TIFREC_Msk                 (0x1UL << SPI_IFCR_TIFREC_Pos)          /*!< 0x00000100 */
13139 #define SPI_IFCR_TIFREC                     SPI_IFCR_TIFREC_Msk                     /*!<TI frame format error flag clear */
13140 #define SPI_IFCR_MODFC_Pos                  (9U)
13141 #define SPI_IFCR_MODFC_Msk                  (0x1UL << SPI_IFCR_MODFC_Pos)           /*!< 0x00000200 */
13142 #define SPI_IFCR_MODFC                      SPI_IFCR_MODFC_Msk                      /*!<Mode Fault flag clear */
13143 #define SPI_IFCR_SUSPC_Pos                  (11U)
13144 #define SPI_IFCR_SUSPC_Msk                  (0x1UL << SPI_IFCR_SUSPC_Pos)           /*!< 0x00000800 */
13145 #define SPI_IFCR_SUSPC                      SPI_IFCR_SUSPC_Msk                      /*!<SUSPend flag clear */
13146 
13147 /*******************  Bit definition for SPI_TXDR register  ********************/
13148 #define SPI_TXDR_TXDR_Pos                   (0U)
13149 #define SPI_TXDR_TXDR_Msk                   (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)     /*!< 0xFFFFFFFF */
13150 #define SPI_TXDR_TXDR                       SPI_TXDR_TXDR_Msk                       /*!<Transmit Data Register */
13151 
13152 /*******************  Bit definition for SPI_RXDR register  ********************/
13153 #define SPI_RXDR_RXDR_Pos                   (0U)
13154 #define SPI_RXDR_RXDR_Msk                   (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)     /*!< 0xFFFFFFFF */
13155 #define SPI_RXDR_RXDR                       SPI_RXDR_RXDR_Msk                       /*!<Receive Data Register */
13156 
13157 /*******************  Bit definition for SPI_CRCPOLY register  ********************/
13158 #define SPI_CRCPOLY_CRCPOLY_Pos             (0U)
13159 #define SPI_CRCPOLY_CRCPOLY_Msk             (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
13160 #define SPI_CRCPOLY_CRCPOLY                 SPI_CRCPOLY_CRCPOLY_Msk                   /*!<CRC Polynomial register */
13161 
13162 /*******************  Bit definition for SPI_TXCRC register  ********************/
13163 #define SPI_TXCRC_TXCRC_Pos                 (0U)
13164 #define SPI_TXCRC_TXCRC_Msk                 (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)   /*!< 0xFFFFFFFF */
13165 #define SPI_TXCRC_TXCRC                     SPI_TXCRC_TXCRC_Msk                     /*!<CRCRegister for transmitter */
13166 
13167 /*******************  Bit definition for SPI_RXCRC register  ********************/
13168 #define SPI_RXCRC_RXCRC_Pos                 (0U)
13169 #define SPI_RXCRC_RXCRC_Msk                 (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)   /*!< 0xFFFFFFFF */
13170 #define SPI_RXCRC_RXCRC                     SPI_RXCRC_RXCRC_Msk                     /*!<CRCRegister for receiver */
13171 
13172 /*******************  Bit definition for SPI_UDRDR register  ********************/
13173 #define SPI_UDRDR_UDRDR_Pos                 (0U)
13174 #define SPI_UDRDR_UDRDR_Msk                 (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)   /*!< 0xFFFFFFFF */
13175 #define SPI_UDRDR_UDRDR                     SPI_UDRDR_UDRDR_Msk                     /*!<Data at slave underrun condition */
13176 
13177 /******************  Bit definition for SPI_I2SCFGR register  *****************/
13178 #define SPI_I2SCFGR_I2SMOD_Pos      (0U)
13179 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */
13180 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
13181 #define SPI_I2SCFGR_I2SCFG_Pos      (1U)
13182 #define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */
13183 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */
13184 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
13185 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
13186 #define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
13187 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
13188 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
13189 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
13190 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
13191 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
13192 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
13193 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
13194 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
13195 #define SPI_I2SCFGR_DATLEN_Pos      (8U)
13196 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */
13197 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
13198 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
13199 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
13200 #define SPI_I2SCFGR_CHLEN_Pos       (10U)
13201 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */
13202 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
13203 #define SPI_I2SCFGR_CKPOL_Pos       (11U)
13204 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */
13205 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
13206 #define SPI_I2SCFGR_FIXCH_Pos       (12U)
13207 #define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */
13208 #define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
13209 #define SPI_I2SCFGR_WSINV_Pos       (13U)
13210 #define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */
13211 #define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
13212 #define SPI_I2SCFGR_DATFMT_Pos      (14U)
13213 #define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */
13214 #define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
13215 #define SPI_I2SCFGR_I2SDIV_Pos      (16U)
13216 #define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */
13217 #define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
13218 #define SPI_I2SCFGR_ODD_Pos         (24U)
13219 #define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */
13220 #define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
13221 #define SPI_I2SCFGR_MCKOE_Pos       (25U)
13222 #define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */
13223 #define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
13224 
13225 
13226 /******************************************************************************/
13227 /*                                                                            */
13228 /*                            Window WATCHDOG                                 */
13229 /*                                                                            */
13230 /******************************************************************************/
13231 /*******************  Bit definition for WWDG_CR register  ********************/
13232 #define WWDG_CR_T_Pos                       (0U)
13233 #define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)               /*!< 0x0000007F */
13234 #define WWDG_CR_T                           WWDG_CR_T_Msk                           /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
13235 #define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)               /*!< 0x00000001 */
13236 #define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)               /*!< 0x00000002 */
13237 #define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)               /*!< 0x00000004 */
13238 #define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)               /*!< 0x00000008 */
13239 #define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)               /*!< 0x00000010 */
13240 #define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)               /*!< 0x00000020 */
13241 #define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)               /*!< 0x00000040 */
13242 #define WWDG_CR_WDGA_Pos                    (7U)
13243 #define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)             /*!< 0x00000080 */
13244 #define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                        /*!<Activation bit */
13245 
13246 /*******************  Bit definition for WWDG_CFR register  *******************/
13247 #define WWDG_CFR_W_Pos                      (0U)
13248 #define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)              /*!< 0x0000007F */
13249 #define WWDG_CFR_W                          WWDG_CFR_W_Msk                          /*!<W[6:0] bits (7-bit window value) */
13250 #define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)              /*!< 0x00000001 */
13251 #define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)              /*!< 0x00000002 */
13252 #define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)              /*!< 0x00000004 */
13253 #define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)              /*!< 0x00000008 */
13254 #define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)              /*!< 0x00000010 */
13255 #define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)              /*!< 0x00000020 */
13256 #define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)              /*!< 0x00000040 */
13257 #define WWDG_CFR_EWI_Pos                    (9U)
13258 #define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)             /*!< 0x00000200 */
13259 #define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                        /*!<Early Wakeup Interrupt */
13260 #define WWDG_CFR_WDGTB_Pos                  (11U)
13261 #define WWDG_CFR_WDGTB_Msk                  (0x7UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00003800 */
13262 #define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                      /*!<WDGTB[2:0] bits (Timer Base) */
13263 #define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00000800 */
13264 #define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00001000 */
13265 #define WWDG_CFR_WDGTB_2                    (0x4UL << WWDG_CFR_WDGTB_Pos)           /*!< 0x00002000 */
13266 
13267 /*******************  Bit definition for WWDG_SR register  ********************/
13268 #define WWDG_SR_EWIF_Pos                    (0U)
13269 #define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)             /*!< 0x00000001 */
13270 #define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                        /*!<Early Wakeup Interrupt Flag */
13271 
13272 
13273 /******************************************************************************/
13274 /*                                                                            */
13275 /*                         USB Dual Role Device FS Endpoint registers         */
13276 /*                                                                            */
13277 /******************************************************************************/
13278 
13279 /******************  Bits definition for USB_DRD_CNTR register  *******************/
13280 #define USB_CNTR_HOST_Pos               (31U)
13281 #define USB_CNTR_HOST_Msk               (0x1UL << USB_CNTR_HOST_Pos)    /*!< 0x80000000 */
13282 #define USB_CNTR_HOST                   USB_CNTR_HOST_Msk               /*!< Host Mode  */
13283 #define USB_CNTR_THR512M_Pos            (16U)
13284 #define USB_CNTR_THR512M_Msk            (0x1UL << USB_CNTR_THR512M_Pos)  /*!< 0x00010000 */
13285 #define USB_CNTR_THR512M                USB_CNTR_THR512M_Msk             /*!< 512byte Threshold interrupt mask */
13286 #define USB_CNTR_CTRM_Pos               (15U)
13287 #define USB_CNTR_CTRM_Msk               (0x1UL << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */
13288 #define USB_CNTR_CTRM                   USB_CNTR_CTRM_Msk               /*!< Correct Transfer Mask */
13289 #define USB_CNTR_PMAOVRM_Pos            (14U)
13290 #define USB_CNTR_PMAOVRM_Msk            (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
13291 #define USB_CNTR_PMAOVRM                USB_CNTR_PMAOVRM_Msk            /*!< DMA OVeR/underrun Mask */
13292 #define USB_CNTR_ERRM_Pos               (13U)
13293 #define USB_CNTR_ERRM_Msk               (0x1UL << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */
13294 #define USB_CNTR_ERRM                   USB_CNTR_ERRM_Msk               /*!< ERRor Mask */
13295 #define USB_CNTR_WKUPM_Pos              (12U)
13296 #define USB_CNTR_WKUPM_Msk              (0x1UL << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */
13297 #define USB_CNTR_WKUPM                  USB_CNTR_WKUPM_Msk              /*!< WaKe UP Mask */
13298 #define USB_CNTR_SUSPM_Pos              (11U)
13299 #define USB_CNTR_SUSPM_Msk              (0x1UL << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */
13300 #define USB_CNTR_SUSPM                  USB_CNTR_SUSPM_Msk              /*!< SUSPend Mask */
13301 #define USB_CNTR_RESETM_Pos             (10U)
13302 #define USB_CNTR_RESETM_Msk             (0x1UL << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */
13303 #define USB_CNTR_RESETM                 USB_CNTR_RESETM_Msk             /*!< RESET Mask */
13304 #define USB_CNTR_DCON                   USB_CNTR_RESETM_Msk             /*!< Disconnection Connection Mask */
13305 #define USB_CNTR_SOFM_Pos               (9U)
13306 #define USB_CNTR_SOFM_Msk               (0x1UL << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */
13307 #define USB_CNTR_SOFM                   USB_CNTR_SOFM_Msk               /*!< Start Of Frame Mask */
13308 #define USB_CNTR_ESOFM_Pos              (8U)
13309 #define USB_CNTR_ESOFM_Msk              (0x1UL << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */
13310 #define USB_CNTR_ESOFM                  USB_CNTR_ESOFM_Msk              /*!< Expected Start Of Frame Mask */
13311 #define USB_CNTR_L1REQM_Pos             (7U)
13312 #define USB_CNTR_L1REQM_Msk             (0x1UL << USB_CNTR_L1REQM_Pos)  /*!< 0x00000080 */
13313 #define USB_CNTR_L1REQM                 USB_CNTR_L1REQM_Msk             /*!< LPM L1 state request interrupt Mask */
13314 #define USB_CNTR_L1XACT_Pos             (6U)
13315 #define USB_CNTR_L1XACT_Msk             (0x1UL << USB_CNTR_L1XACT_Pos)  /*!< 0x00000040 */
13316 #define USB_CNTR_L1XACT                 USB_CNTR_L1XACT_Msk             /*!< Host LPM L1 transaction request Mask */
13317 #define USB_CNTR_L1RES_Pos              (5U)
13318 #define USB_CNTR_L1RES_Msk              (0x1UL << USB_CNTR_L1RES_Pos)   /*!< 0x00000020 */
13319 #define USB_CNTR_L1RES                  USB_CNTR_L1RES_Msk              /*!< LPM L1 Resume request/ Remote Wakeup Mask */
13320 #define USB_CNTR_L2RES_Pos              (4U)
13321 #define USB_CNTR_L2RES_Msk              (0x1UL << USB_CNTR_L2RES_Pos)   /*!< 0x00000010 */
13322 #define USB_CNTR_L2RES                  USB_CNTR_L2RES_Msk              /*!< L2 Remote Wakeup / Resume driver Mask */
13323 #define USB_CNTR_SUSPEN_Pos             (3U)
13324 #define USB_CNTR_SUSPEN_Msk             (0x1UL << USB_CNTR_SUSPEN_Pos)  /*!< 0x00000008 */
13325 #define USB_CNTR_SUSPEN                 USB_CNTR_SUSPEN_Msk             /*!< Suspend state enable Mask */
13326 #define USB_CNTR_SUSPRDY_Pos            (2U)
13327 #define USB_CNTR_SUSPRDY_Msk            (0x1UL << USB_CNTR_SUSPRDY_Pos) /*!< 0x00000004 */
13328 #define USB_CNTR_SUSPRDY                USB_CNTR_SUSPRDY_Msk            /*!< Suspend state effective Mask */
13329 #define USB_CNTR_PDWN_Pos               (1U)
13330 #define USB_CNTR_PDWN_Msk               (0x1UL << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */
13331 #define USB_CNTR_PDWN                   USB_CNTR_PDWN_Msk               /*!< Power DoWN Mask */
13332 #define USB_CNTR_USBRST_Pos             (0U)
13333 #define USB_CNTR_USBRST_Msk             (0x1UL << USB_CNTR_USBRST_Pos)  /*!< 0x00000001 */
13334 #define USB_CNTR_USBRST                 USB_CNTR_USBRST_Msk             /*!< USB Reset Mask */
13335 
13336 /******************  Bits definition for USB_DRD_ISTR register  *******************/
13337 #define USB_ISTR_IDN_Pos                (0U)
13338 #define USB_ISTR_IDN_Msk                (0xFUL << USB_ISTR_IDN_Pos)     /*!< 0x0000000F */
13339 #define USB_ISTR_IDN                    USB_ISTR_IDN_Msk                /*!< EndPoint IDentifier (read-only bit) Mask */
13340 #define USB_ISTR_DIR_Pos                (4U)
13341 #define USB_ISTR_DIR_Msk                (0x1UL << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */
13342 #define USB_ISTR_DIR                    USB_ISTR_DIR_Msk                /*!< DIRection of transaction (read-only bit) Mask */
13343 #define USB_ISTR_L1REQ_Pos              (7U)
13344 #define USB_ISTR_L1REQ_Msk              (0x1UL << USB_ISTR_L1REQ_Pos)   /*!< 0x00000080 */
13345 #define USB_ISTR_L1REQ                  USB_ISTR_L1REQ_Msk              /*!< LPM L1 state request Mask */
13346 #define USB_ISTR_ESOF_Pos               (8U)
13347 #define USB_ISTR_ESOF_Msk               (0x1UL << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */
13348 #define USB_ISTR_ESOF                   USB_ISTR_ESOF_Msk               /*!< Expected Start Of Frame (clear-only bit) Mask */
13349 #define USB_ISTR_SOF_Pos                (9U)
13350 #define USB_ISTR_SOF_Msk                (0x1UL << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */
13351 #define USB_ISTR_SOF                    USB_ISTR_SOF_Msk                /*!< Start Of Frame (clear-only bit) Mask */
13352 #define USB_ISTR_RESET_Pos              (10U)
13353 #define USB_ISTR_RESET_Msk              (0x1UL << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */
13354 #define USB_ISTR_RESET                  USB_ISTR_RESET_Msk              /*!< RESET Mask */
13355 #define USB_ISTR_DCON_Pos               (10U)
13356 #define USB_ISTR_DCON_Msk               (0x1UL << USB_ISTR_DCON_Pos)    /*!< 0x00000400 */
13357 #define USB_ISTR_DCON                   USB_ISTR_DCON_Msk               /*!< HOST MODE-Device Connection or disconnection Mask */
13358 #define USB_ISTR_SUSP_Pos               (11U)
13359 #define USB_ISTR_SUSP_Msk               (0x1UL << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */
13360 #define USB_ISTR_SUSP                   USB_ISTR_SUSP_Msk               /*!< SUSPend (clear-only bit) Mask */
13361 #define USB_ISTR_WKUP_Pos               (12U)
13362 #define USB_ISTR_WKUP_Msk               (0x1UL << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */
13363 #define USB_ISTR_WKUP                   USB_ISTR_WKUP_Msk               /*!< WaKe UP (clear-only bit) Mask */
13364 #define USB_ISTR_ERR_Pos                (13U)
13365 #define USB_ISTR_ERR_Msk                (0x1UL << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */
13366 #define USB_ISTR_ERR                    USB_ISTR_ERR_Msk                /*!< ERRor (clear-only bit) Mask */
13367 #define USB_ISTR_PMAOVR_Pos             (14U)
13368 #define USB_ISTR_PMAOVR_Msk             (0x1UL << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */
13369 #define USB_ISTR_PMAOVR                 USB_ISTR_PMAOVR_Msk             /*!< PMA OVeR/underrun (clear-only bit) Mask */
13370 #define USB_ISTR_CTR_Pos                (15U)
13371 #define USB_ISTR_CTR_Msk                (0x1UL << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */
13372 #define USB_ISTR_CTR                    USB_ISTR_CTR_Msk                /*!< Correct TRansfer (clear-only bit) Mask */
13373 #define USB_ISTR_THR512_Pos             (16U)
13374 #define USB_ISTR_THR512_Msk             (0x1UL << USB_ISTR_THR512_Pos)  /*!< 0x00010000 */
13375 #define USB_ISTR_THR512                 USB_ISTR_THR512_Msk             /*!< 512byte threshold interrupt (used with isochrnous single buffer ) */
13376 #define USB_ISTR_DCON_STAT_Pos          (29U)
13377 #define USB_ISTR_DCON_STAT_Msk          (0x1UL << USB_ISTR_DCON_STAT_Pos)/*!< 0x20000000 */
13378 #define USB_ISTR_DCON_STAT              USB_ISTR_DCON_STAT_Msk           /*!< Device Connection status (connected/Disconnected) don't cause an interrupt */
13379 #define USB_ISTR_LS_DCONN_Pos           (30U)
13380 #define USB_ISTR_LS_DCONN_Msk           (0x1UL << USB_ISTR_LS_DCONN_Pos)/*!< 0x40000000 */
13381 #define USB_ISTR_LS_DCONN               USB_ISTR_LS_DCONN_Msk           /*!< LS_DCONN Mask */
13382 
13383 /******************  Bits definition for USB_DRD_FNR register  ********************/
13384 #define USB_FNR_FN_Pos                  (0U)
13385 #define USB_FNR_FN_Msk                  (0x7FFUL << USB_FNR_FN_Pos)     /*!< 0x000007FF */
13386 #define USB_FNR_FN                      USB_FNR_FN_Msk                  /*!< Frame Number Mask */
13387 #define USB_FNR_LSOF_Pos                (11U)
13388 #define USB_FNR_LSOF_Msk                (0x3UL << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */
13389 #define USB_FNR_LSOF                    USB_FNR_LSOF_Msk                /*!< Lost SOF  Mask */
13390 #define USB_FNR_LCK_Pos                 (13U)
13391 #define USB_FNR_LCK_Msk                 (0x1UL << USB_FNR_LCK_Pos)      /*!< 0x00002000 */
13392 #define USB_FNR_LCK                     USB_FNR_LCK_Msk                 /*!< LoCKed Mask */
13393 #define USB_FNR_RXDM_Pos                (14U)
13394 #define USB_FNR_RXDM_Msk                (0x1UL << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */
13395 #define USB_FNR_RXDM                    USB_FNR_RXDM_Msk                /*!< status of D- data line Mask */
13396 #define USB_FNR_RXDP_Pos                (15U)
13397 #define USB_FNR_RXDP_Msk                (0x1UL << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */
13398 #define USB_FNR_RXDP                    USB_FNR_RXDP_Msk                /*!< status of D+ data line Mask */
13399 
13400 /******************  Bits definition for USB_DRD_DADDR register    ****************/
13401 #define USB_DADDR_ADD_Pos               (0U)
13402 #define USB_DADDR_ADD_Msk               (0x7FUL << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */
13403 #define USB_DADDR_ADD                   USB_DADDR_ADD_Msk               /*!<  ADD[6:0] bits (Device Address)Mask */
13404 #define USB_DADDR_ADD0_Pos              (0U)
13405 #define USB_DADDR_ADD0_Msk              (0x1UL << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */
13406 #define USB_DADDR_ADD0                  USB_DADDR_ADD0_Msk              /*!< Bit 0 Mask */
13407 #define USB_DADDR_ADD1_Pos              (1U)
13408 #define USB_DADDR_ADD1_Msk              (0x1UL << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */
13409 #define USB_DADDR_ADD1                  USB_DADDR_ADD1_Msk              /*!< Bit 1 Mask */
13410 #define USB_DADDR_ADD2_Pos              (2U)
13411 #define USB_DADDR_ADD2_Msk              (0x1UL << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */
13412 #define USB_DADDR_ADD2                  USB_DADDR_ADD2_Msk              /*!< Bit 2 Mask */
13413 #define USB_DADDR_ADD3_Pos              (3U)
13414 #define USB_DADDR_ADD3_Msk              (0x1UL << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */
13415 #define USB_DADDR_ADD3                  USB_DADDR_ADD3_Msk              /*!< Bit 3 Mask */
13416 #define USB_DADDR_ADD4_Pos              (4U)
13417 #define USB_DADDR_ADD4_Msk              (0x1UL << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */
13418 #define USB_DADDR_ADD4                  USB_DADDR_ADD4_Msk              /*!< Bit 4 Mask */
13419 #define USB_DADDR_ADD5_Pos              (5U)
13420 #define USB_DADDR_ADD5_Msk              (0x1UL << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */
13421 #define USB_DADDR_ADD5                  USB_DADDR_ADD5_Msk              /*!< Bit 5 Mask */
13422 #define USB_DADDR_ADD6_Pos              (6U)
13423 #define USB_DADDR_ADD6_Msk              (0x1UL << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */
13424 #define USB_DADDR_ADD6                  USB_DADDR_ADD6_Msk              /*!< Bit 6 Mask */
13425 #define USB_DADDR_EF_Pos                (7U)
13426 #define USB_DADDR_EF_Msk                (0x1UL << USB_DADDR_EF_Pos)     /*!< 0x00000080 */
13427 #define USB_DADDR_EF                    USB_DADDR_EF_Msk                /*!< Enable Function Mask */
13428 
13429 /******************  Bit definition for USB_DRD_BTABLE register  ******************/
13430 #define USB_BTABLE_BTABLE_Pos          (3U)
13431 #define USB_BTABLE_BTABLE_Msk          (0xFFF8UL << USB_BTABLE_BTABLE_Pos)/*!< 0x00000000 */
13432 #define USB_BTABLE_BTABLE              USB_BTABLE_BTABLE_Msk              /*!< Buffer Table Mask */
13433 
13434 /*******************  Bit definition for LPMCSR register  *********************/
13435 #define USB_LPMCSR_LMPEN_Pos           (0U)
13436 #define USB_LPMCSR_LMPEN_Msk           (0x1UL << USB_LPMCSR_LMPEN_Pos)  /*!< 0x00000001 */
13437 #define USB_LPMCSR_LMPEN               USB_LPMCSR_LMPEN_Msk             /*!< LPM support enable Mask */
13438 #define USB_LPMCSR_LPMACK_Pos          (1U)
13439 #define USB_LPMCSR_LPMACK_Msk          (0x1UL << USB_LPMCSR_LPMACK_Pos) /*!< 0x00000002 */
13440 #define USB_LPMCSR_LPMACK              USB_LPMCSR_LPMACK_Msk            /*!< LPM Token acknowledge enable Mask */
13441 #define USB_LPMCSR_REMWAKE_Pos         (3U)
13442 #define USB_LPMCSR_REMWAKE_Msk         (0x1UL << USB_LPMCSR_REMWAKE_Pos)/*!< 0x00000008 */
13443 #define USB_LPMCSR_REMWAKE             USB_LPMCSR_REMWAKE_Msk           /*!< bRemoteWake value received with last ACKed LPM Token Mask */
13444 #define USB_LPMCSR_BESL_Pos            (4U)
13445 #define USB_LPMCSR_BESL_Msk            (0xFUL << USB_LPMCSR_BESL_Pos)   /*!< 0x000000F0 */
13446 #define USB_LPMCSR_BESL                USB_LPMCSR_BESL_Msk              /*!< BESL value received with last ACKed LPM Token Mask */
13447 
13448 /******************  Bits definition for USB_DRD_BCDR register  *******************/
13449 #define USB_BCDR_BCDEN_Pos             (0U)
13450 #define USB_BCDR_BCDEN_Msk             (0x1UL << USB_BCDR_BCDEN_Pos)    /*!< 0x00000001 */
13451 #define USB_BCDR_BCDEN                 USB_BCDR_BCDEN_Msk               /*!< Battery charging detector (BCD) enable Mask */
13452 #define USB_BCDR_DCDEN_Pos             (1U)
13453 #define USB_BCDR_DCDEN_Msk             (0x1UL << USB_BCDR_DCDEN_Pos)    /*!< 0x00000002 */
13454 #define USB_BCDR_DCDEN                 USB_BCDR_DCDEN_Msk               /*!< Data contact detection (DCD) mode enable Mask */
13455 #define USB_BCDR_PDEN_Pos              (2U)
13456 #define USB_BCDR_PDEN_Msk              (0x1UL << USB_BCDR_PDEN_Pos)     /*!< 0x00000004 */
13457 #define USB_BCDR_PDEN                  USB_BCDR_PDEN_Msk                /*!< Primary detection (PD) mode enable Mask */
13458 #define USB_BCDR_SDEN_Pos              (3U)
13459 #define USB_BCDR_SDEN_Msk              (0x1UL << USB_BCDR_SDEN_Pos)     /*!< 0x00000008 */
13460 #define USB_BCDR_SDEN                  USB_BCDR_SDEN_Msk                /*!< Secondary detection (SD) mode enable Mask */
13461 #define USB_BCDR_DCDET_Pos             (4U)
13462 #define USB_BCDR_DCDET_Msk             (0x1UL << USB_BCDR_DCDET_Pos)    /*!< 0x00000010 */
13463 #define USB_BCDR_DCDET                 USB_BCDR_DCDET_Msk               /*!< Data contact detection (DCD) status Mask */
13464 #define USB_BCDR_PDET_Pos              (5U)
13465 #define USB_BCDR_PDET_Msk              (0x1UL << USB_BCDR_PDET_Pos)     /*!< 0x00000020 */
13466 #define USB_BCDR_PDET                  USB_BCDR_PDET_Msk                /*!< Primary detection (PD) status Mask */
13467 #define USB_BCDR_SDET_Pos              (6U)
13468 #define USB_BCDR_SDET_Msk              (0x1UL << USB_BCDR_SDET_Pos)     /*!< 0x00000040 */
13469 #define USB_BCDR_SDET                  USB_BCDR_SDET_Msk                /*!< Secondary detection (SD) status Mask */
13470 #define USB_BCDR_PS2DET_Pos            (7U)
13471 #define USB_BCDR_PS2DET_Msk            (0x1UL << USB_BCDR_PS2DET_Pos)   /*!< 0x00000080 */
13472 #define USB_BCDR_PS2DET                USB_BCDR_PS2DET_Msk              /*!< PS2 port or proprietary charger detected Mask */
13473 #define USB_BCDR_DPPU_Pos              (15U)
13474 #define USB_BCDR_DPPU_Msk              (0x1UL << USB_BCDR_DPPU_Pos)     /*!< 0x00008000 */
13475 #define USB_BCDR_DPPU                  USB_BCDR_DPPU_Msk                /*!< DP Pull-up Enable Mask */
13476 #define USB_BCDR_DPPD_Pos              (15U)
13477 #define USB_BCDR_DPPD_Msk              (0x1UL << USB_BCDR_DPPD_Pos)     /*!< 0x00008000 */
13478 #define USB_BCDR_DPPD                  USB_BCDR_DPPD_Msk                /*!< DP Pull-Down Enable Mask */
13479 
13480 /******************  Bits definition for USB_DRD_CHEP register  *******************/
13481 #define USB_CHEP_ERRRX_Pos             (26U)
13482 #define USB_CHEP_ERRRX_Msk             (0x01UL << USB_CHEP_ERRRX_Pos)   /*!< 0x04000000 */
13483 #define USB_CHEP_ERRRX                 USB_CHEP_ERRRX_Msk               /*!< Receive error */
13484 #define USB_EP_ERRRX                   USB_CHEP_ERRRX_Msk               /*!< EP Receive error */
13485 #define USB_CH_ERRRX                   USB_CHEP_ERRRX_Msk               /*!< CH Receive error */
13486 #define USB_CHEP_ERRTX_Pos             (25U)
13487 #define USB_CHEP_ERRTX_Msk             (0x01UL << USB_CHEP_ERRTX_Pos)   /*!< 0x02000000 */
13488 #define USB_CHEP_ERRTX                 USB_CHEP_ERRTX_Msk               /*!< Transmit error */
13489 #define USB_EP_ERRTX                   USB_CHEP_ERRTX_Msk               /*!< EP Transmit error */
13490 #define USB_CH_ERRTX                   USB_CHEP_ERRTX_Msk               /*!< CH Transmit error */
13491 #define USB_CHEP_LSEP_Pos              (24U)
13492 #define USB_CHEP_LSEP_Msk              (0x01UL << USB_CHEP_LSEP_Pos)    /*!< 0x01000000 */
13493 #define USB_CHEP_LSEP                  USB_CHEP_LSEP_Msk                /*!< Low Speed Endpoint (host with Hub Only) */
13494 #define USB_CHEP_NAK_Pos               (23U)
13495 #define USB_CHEP_NAK_Msk               (0x01UL << USB_CHEP_NAK_Pos)     /*!< 0x00800000 */
13496 #define USB_CHEP_NAK                   USB_CHEP_NAK_Msk                 /*!< Previous NAK detected */
13497 #define USB_CHEP_DEVADDR_Pos           (16U)
13498 #define USB_CHEP_DEVADDR_Msk           (0x7FU << USB_CHEP_DEVADDR_Pos)  /*!< 0x7F000000 */
13499 #define USB_CHEP_DEVADDR               USB_CHEP_DEVADDR_Msk             /* Target Endpoint address*/
13500 #define USB_CHEP_VTRX_Pos              (15U)
13501 #define USB_CHEP_VTRX_Msk              (0x1UL << USB_CHEP_VTRX_Pos)     /*!< 0x00008000 */
13502 #define USB_CHEP_VTRX                  USB_CHEP_VTRX_Msk                /*!< USB valid transaction received Mask */
13503 #define USB_EP_VTRX                    USB_CHEP_VTRX_Msk                /*!< USB Endpoint valid transaction received Mask */
13504 #define USB_CH_VTRX                    USB_CHEP_VTRX_Msk                /*!< USB valid Channel transaction received Mask */
13505 #define USB_CHEP_DTOG_RX_Pos           (14U)
13506 #define USB_CHEP_DTOG_RX_Msk           (0x1UL << USB_CHEP_DTOG_RX_Pos)  /*!< 0x00004000 */
13507 #define USB_CHEP_DTOG_RX               USB_CHEP_DTOG_RX_Msk             /*!< Data Toggle, for reception transfers Mask */
13508 #define USB_EP_DTOG_RX                 USB_CHEP_DTOG_RX_Msk             /*!< EP Data Toggle, for reception transfers Mask */
13509 #define USB_CH_DTOG_RX                 USB_CHEP_DTOG_RX_Msk             /*!< CH Data Toggle, for reception transfers Mask */
13510 #define USB_CHEP_RX_STRX_Pos           (12U)
13511 #define USB_CHEP_RX_STRX_Msk           (0x3UL << USB_CHEP_RX_STRX_Pos)  /*!< 0x00003000 */
13512 #define USB_CHEP_RX_STRX               USB_CHEP_RX_STRX_Msk             /*!< Status bits, for reception transfers Mask */
13513 #define USB_EP_RX_STRX                 USB_CHEP_RX_STRX_Msk             /*!< Status bits, for EP reception transfers Mask */
13514 #define USB_CH_RX_STRX                 USB_CHEP_RX_STRX_Msk             /*!< Status bits, for CH reception transfers Mask */
13515 #define USB_CHEP_SETUP_Pos             (11U)
13516 #define USB_CHEP_SETUP_Msk             (0x1UL << USB_CHEP_SETUP_Pos)    /*!< 0x00000800 */
13517 #define USB_CHEP_SETUP                 USB_CHEP_SETUP_Msk               /*!< Setup transaction completed Mask */
13518 #define USB_EP_SETUP                   USB_CHEP_SETUP_Msk               /*!< EP Setup transaction completed Mask */
13519 #define USB_CH_SETUP                   USB_CHEP_SETUP_Msk               /*!< CH Setup transaction completed Mask */
13520 #define USB_CHEP_UTYPE_Pos             (9U)
13521 #define USB_CHEP_UTYPE_Msk             (0x3UL << USB_CHEP_UTYPE_Pos)    /*!< 0x00000600 */
13522 #define USB_CHEP_UTYPE                 USB_CHEP_UTYPE_Msk               /*!< USB type of transaction Mask */
13523 #define USB_EP_UTYPE                   USB_CHEP_UTYPE_Msk               /*!< USB type of EP transaction Mask */
13524 #define USB_CH_UTYPE                   USB_CHEP_UTYPE_Msk               /*!< USB type of CH transaction Mask */
13525 #define USB_CHEP_KIND_Pos              (8U)
13526 #define USB_CHEP_KIND_Msk              (0x1UL << USB_CHEP_KIND_Pos)     /*!< 0x00000100 */
13527 #define USB_CHEP_KIND                  USB_CHEP_KIND_Msk                /*!< EndPoint KIND Mask */
13528 #define USB_EP_KIND                    USB_CHEP_KIND_Msk                /*!< EndPoint KIND Mask */
13529 #define USB_CH_KIND                    USB_CHEP_KIND_Msk                /*!< Channel KIND Mask */
13530 #define USB_CHEP_VTTX_Pos              (7U)
13531 #define USB_CHEP_VTTX_Msk              (0x1UL << USB_CHEP_VTTX_Pos)     /*!< 0x00000080 */
13532 #define USB_CHEP_VTTX                  USB_CHEP_VTTX_Msk                /*!< Valid USB transaction transmitted Mask */
13533 #define USB_EP_VTTX                    USB_CHEP_VTTX_Msk                /*!< USB Endpoint valid transaction transmitted Mask */
13534 #define USB_CH_VTTX                    USB_CHEP_VTTX_Msk                /*!< USB valid Channel transaction transmitted Mask */
13535 #define USB_CHEP_DTOG_TX_Pos           (6U)
13536 #define USB_CHEP_DTOG_TX_Msk           (0x1UL << USB_CHEP_DTOG_TX_Pos)  /*!< 0x00000040 */
13537 #define USB_CHEP_DTOG_TX               USB_CHEP_DTOG_TX_Msk             /*!< Data Toggle, for transmission transfers Mask */
13538 #define USB_EP_DTOG_TX                 USB_CHEP_DTOG_TX_Msk             /*!< EP Data Toggle, for transmission transfers Mask */
13539 #define USB_CH_DTOG_TX                 USB_CHEP_DTOG_TX_Msk             /*!< CH Data Toggle, for transmission transfers Mask */
13540 #define USB_CHEP_TX_STTX_Pos           (4U)
13541 #define USB_CHEP_TX_STTX_Msk           (0x3UL << USB_CHEP_TX_STTX_Pos)  /*!< 0x00000030 */
13542 #define USB_CHEP_TX_STTX               USB_CHEP_TX_STTX_Msk             /*!< Status bits, for transmission transfers Mask */
13543 #define USB_EP_TX_STTX                 USB_CHEP_TX_STTX_Msk             /*!< Status bits, for EP transmission transfers Mask */
13544 #define USB_CH_TX_STTX                 USB_CHEP_TX_STTX_Msk             /*!< Status bits, for CH transmission transfers Mask */
13545 #define USB_CHEP_ADDR_Pos              (0U)
13546 #define USB_CHEP_ADDR_Msk              (0xFUL << USB_CHEP_ADDR_Pos)     /*!< 0x0000000F */
13547 #define USB_CHEP_ADDR                  USB_CHEP_ADDR_Msk                /*!< Endpoint address Mask */
13548 
13549 
13550 /* EndPoint Register MASK (no toggle fields) */
13551 #define USB_CHEP_REG_MASK                          (USB_CHEP_ERRRX | USB_CHEP_ERRTX | USB_CHEP_LSEP | \
13552                                                     USB_CHEP_DEVADDR | USB_CHEP_VTRX | USB_CHEP_SETUP | \
13553                                                     USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR | \
13554                                                     USB_CHEP_NAK) /* 0x07FF8F8F */
13555 
13556 #define USB_CHEP_TX_DTOGMASK                       (USB_CHEP_TX_STTX | USB_CHEP_REG_MASK)
13557 #define USB_CHEP_RX_DTOGMASK                       (USB_CHEP_RX_STRX | USB_CHEP_REG_MASK)
13558 
13559 #define USB_CHEP_TX_DTOG1                          (0x00000010UL)           /*!< Channel/EndPoint TX Data Toggle bit1 */
13560 #define USB_CHEP_TX_DTOG2                          (0x00000020UL)           /*!< Channel/EndPoint TX Data Toggle bit2 */
13561 #define USB_CHEP_RX_DTOG1                          (0x00001000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */
13562 #define USB_CHEP_RX_DTOG2                          (0x00002000UL)           /*!< Channel/EndPoint RX Data Toggle bit1 */
13563 
13564 /*!< EP_TYPE[1:0] Channel/EndPoint TYPE */
13565 #define USB_EP_TYPE_MASK                           (0x00000600UL)           /*!< Channel/EndPoint TYPE Mask */
13566 #define USB_EP_BULK                                (0x00000000UL)           /*!< Channel/EndPoint BULK */
13567 #define USB_EP_CONTROL                             (0x00000200UL)           /*!< Channel/EndPoint CONTROL */
13568 #define USB_EP_ISOCHRONOUS                         (0x00000400UL)           /*!< Channel/EndPoint ISOCHRONOUS */
13569 #define USB_EP_INTERRUPT                           (0x00000600UL)           /*!< Channel/EndPoint INTERRUPT */
13570 
13571 #define USB_EP_T_MASK                              ((~USB_EP_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */
13572 #define USB_CH_T_MASK                              ((~USB_CH_UTYPE) & USB_CHEP_REG_MASK) /* =0x898F */
13573 
13574 #define USB_EP_KIND_MASK                           ((~USB_EP_KIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */
13575 #define USB_CH_KIND_MASK                           ((~USB_CH_KIND) & USB_CHEP_REG_MASK) /*!< EP_KIND EndPoint KIND */
13576 
13577 /*!< STAT_TX[1:0] STATus for TX transfer */
13578 #define USB_EP_TX_DIS                              (0x00000000UL)           /*!< EndPoint TX Disabled */
13579 #define USB_EP_TX_STALL                            (0x00000010UL)           /*!< EndPoint TX STALLed */
13580 #define USB_EP_TX_NAK                              (0x00000020UL)           /*!< EndPoint TX NAKed */
13581 #define USB_EP_TX_VALID                            (0x00000030UL)           /*!< EndPoint TX VALID */
13582 
13583 #define USB_CH_TX_DIS                              (0x00000000UL)           /*!< Channel TX Disabled */
13584 #define USB_CH_TX_STALL                            (0x00000010UL)           /*!< Channel TX STALLed */
13585 #define USB_CH_TX_NAK                              (0x00000020UL)           /*!< Channel TX NAKed */
13586 #define USB_CH_TX_VALID                            (0x00000030UL)           /*!< Channel TX VALID */
13587 
13588 #define USB_EP_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
13589 #define USB_EP_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */
13590 
13591 #define USB_CH_TX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
13592 #define USB_CH_TX_ACK_DBUF                         (0x00000030UL)           /*!< ACK Double buffer mode */
13593 
13594 /*!< STAT_RX[1:0] STATus for RX transfer */
13595 #define USB_EP_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
13596 #define USB_EP_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
13597 #define USB_EP_RX_NAK                              (0x00002000UL)           /*!< EndPoint RX NAKed */
13598 #define USB_EP_RX_VALID                            (0x00003000UL)           /*!< EndPoint RX VALID */
13599 
13600 #define USB_EP_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
13601 #define USB_EP_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */
13602 
13603 
13604 
13605 #define USB_CH_RX_DIS                              (0x00000000UL)           /*!< EndPoint RX Disabled */
13606 #define USB_CH_RX_STALL                            (0x00001000UL)           /*!< EndPoint RX STALLed */
13607 #define USB_CH_RX_NAK                              (0x00002000UL)           /*!< Channel RX NAKed */
13608 #define USB_CH_RX_VALID                            (0x00003000UL)           /*!< Channel RX VALID */
13609 
13610 #define USB_CH_RX_ACK_SBUF                         (0x00000000UL)           /*!< ACK single buffer mode */
13611 #define USB_CH_RX_ACK_DBUF                         (0x00003000UL)           /*!< ACK Double buffer mode */
13612 
13613 /*! <used For Double Buffer Enable Disable */
13614 #define USB_CHEP_DB_MSK                            (0xFFFF0F0FUL)
13615 
13616 /*Buffer Descriptor Mask*/
13617 #define USB_PMA_TXBD_ADDMSK                        (0xFFFF0000UL)
13618 #define USB_PMA_TXBD_COUNTMSK                      (0x0000FFFFUL)
13619 #define USB_PMA_RXBD_ADDMSK                        (0xFFFF0000UL)
13620 #define USB_PMA_RXBD_COUNTMSK                      (0x03FFFFFFUL)
13621 
13622 
13623 /** @addtogroup STM32H5xx_Peripheral_Exported_macros
13624   * @{
13625   */
13626 
13627 /******************************* ADC Instances ********************************/
13628 
13629 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS))
13630 
13631 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS))
13632 
13633 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS))
13634 
13635 /******************************* CRC Instances ********************************/
13636 #define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS))
13637 
13638 /******************************* DAC Instances ********************************/
13639 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS))
13640 
13641 /******************************** DMA Instances *******************************/
13642 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS)  || \
13643                                        ((INSTANCE) == GPDMA1_Channel1_NS)  || \
13644                                        ((INSTANCE) == GPDMA1_Channel2_NS)  || \
13645                                        ((INSTANCE) == GPDMA1_Channel3_NS)  || \
13646                                        ((INSTANCE) == GPDMA1_Channel4_NS)  || \
13647                                        ((INSTANCE) == GPDMA1_Channel5_NS)  || \
13648                                        ((INSTANCE) == GPDMA1_Channel6_NS)  || \
13649                                        ((INSTANCE) == GPDMA1_Channel7_NS)  || \
13650                                        ((INSTANCE) == GPDMA2_Channel0_NS)  || \
13651                                        ((INSTANCE) == GPDMA2_Channel1_NS)  || \
13652                                        ((INSTANCE) == GPDMA2_Channel2_NS)  || \
13653                                        ((INSTANCE) == GPDMA2_Channel3_NS)  || \
13654                                        ((INSTANCE) == GPDMA2_Channel4_NS)  || \
13655                                        ((INSTANCE) == GPDMA2_Channel5_NS)  || \
13656                                        ((INSTANCE) == GPDMA2_Channel6_NS)  || \
13657                                        ((INSTANCE) == GPDMA2_Channel7_NS))
13658 
13659 #define IS_GPDMA_INSTANCE(INSTANCE)   IS_DMA_ALL_INSTANCE(INSTANCE)
13660 
13661 #define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS)  || \
13662                                                  ((INSTANCE) == GPDMA1_Channel7_NS)  || \
13663                                                  ((INSTANCE) == GPDMA2_Channel6_NS)  || \
13664                                                  ((INSTANCE) == GPDMA2_Channel7_NS))
13665 
13666 /****************************** RAMCFG Instances ********************************/
13667 #define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \
13668                                           ((INSTANCE) == RAMCFG_SRAM2_NS) || \
13669                                           ((INSTANCE) == RAMCFG_BKPRAM_NS))
13670 
13671 /***************************** RAMCFG ECC Instances *****************************/
13672 #define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || \
13673                                           ((INSTANCE) == RAMCFG_BKPRAM_NS))
13674 
13675 /************************ RAMCFG Write Protection Instances *********************/
13676 #define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS))
13677 
13678 /******************************* GPIO Instances *******************************/
13679 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \
13680                                         ((INSTANCE) == GPIOB_NS) || \
13681                                         ((INSTANCE) == GPIOC_NS) || \
13682                                         ((INSTANCE) == GPIOD_NS) || \
13683                                         ((INSTANCE) == GPIOH_NS))
13684 
13685 /******************************* DTS Instances *******************************/
13686 #define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS))
13687 
13688 /******************************* GPIO AF Instances ****************************/
13689 /* On H5, all GPIO Bank support AF */
13690 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
13691 
13692 /**************************** GPIO Lock Instances *****************************/
13693 /* On H5, all GPIO Bank support the Lock mechanism */
13694 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
13695 
13696 /******************************** I2C Instances *******************************/
13697 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C2_NS))
13698 
13699 /****************** I2C Instances : wakeup capability from stop modes *********/
13700 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
13701 
13702 /******************************** I3C Instances *******************************/
13703 #define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C2_NS))
13704 
13705 /******************************* RNG Instances ********************************/
13706 #define IS_RNG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == RNG_NS))
13707 
13708 /****************************** RTC Instances *********************************/
13709 #define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS))
13710 
13711 /****************************** FDCAN Instances *******************************/
13712 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS))
13713 
13714 /****************************** SMBUS Instances *******************************/
13715 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C2_NS))
13716 
13717 
13718 /******************************** SPI Instances *******************************/
13719 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS))
13720 
13721 #define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == NULL)
13722 
13723 #define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI3_NS))
13724 
13725 /****************** LPTIM Instances : All supported instances *****************/
13726 #define IS_LPTIM_INSTANCE(INSTANCE)  (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13727 
13728 /****************** LPTIM Instances : DMA supported instances *****************/
13729 #define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13730 
13731 /************* LPTIM Instances : at least 1 capture/compare channel ***********/
13732 #define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13733 
13734 /************* LPTIM Instances : at least 2 capture/compare channel ***********/
13735 #define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13736 
13737 /****************** LPTIM Instances : supporting encoder interface **************/
13738 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13739 
13740 /****************** LPTIM Instances : supporting Input Capture **************/
13741 #define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS))
13742 
13743 /****************** TIM Instances : All supported instances *******************/
13744 #define IS_TIM_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
13745                                     ((INSTANCE) == TIM2_NS)  || \
13746                                     ((INSTANCE) == TIM3_NS)  || \
13747                                     ((INSTANCE) == TIM6_NS)  || \
13748                                     ((INSTANCE) == TIM7_NS))
13749 
13750 /****************** TIM Instances : supporting 32 bits counter ****************/
13751 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS))
13752 
13753 /****************** TIM Instances : supporting the break function *************/
13754 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS))
13755 
13756 /************** TIM Instances : supporting Break source selection *************/
13757 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS))
13758 
13759 /****************** TIM Instances : supporting 2 break inputs *****************/
13760 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS))
13761 
13762 /************* TIM Instances : at least 1 capture/compare channel *************/
13763 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13764                                          ((INSTANCE) == TIM2_NS)  || \
13765                                          ((INSTANCE) == TIM3_NS))
13766 /************ TIM Instances : at least 2 capture/compare channels *************/
13767 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13768                                          ((INSTANCE) == TIM2_NS)  || \
13769                                          ((INSTANCE) == TIM3_NS))
13770 
13771 /************ TIM Instances : at least 3 capture/compare channels *************/
13772 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13773                                          ((INSTANCE) == TIM2_NS)  || \
13774                                          ((INSTANCE) == TIM3_NS))
13775 
13776 /************ TIM Instances : at least 4 capture/compare channels *************/
13777 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13778                                          ((INSTANCE) == TIM2_NS)  || \
13779                                          ((INSTANCE) == TIM3_NS))
13780 
13781 /****************** TIM Instances : at least 5 capture/compare channels *******/
13782 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS))
13783 
13784 /****************** TIM Instances : at least 6 capture/compare channels *******/
13785 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS))
13786 
13787 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
13788 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS)  || \
13789                                             ((INSTANCE) == TIM2_NS)  || \
13790                                             ((INSTANCE) == TIM3_NS)  || \
13791                                             ((INSTANCE) == TIM6_NS)  || \
13792                                             ((INSTANCE) == TIM7_NS))
13793 
13794 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
13795 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13796                                             ((INSTANCE) == TIM2_NS)  || \
13797                                             ((INSTANCE) == TIM3_NS))
13798 
13799 /******************** TIM Instances : DMA burst feature ***********************/
13800 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS)  || \
13801                                             ((INSTANCE) == TIM2_NS)  || \
13802                                             ((INSTANCE) == TIM3_NS))
13803 
13804 /******************* TIM Instances : output(s) available **********************/
13805 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
13806     ((((INSTANCE) == TIM1_NS)  && \
13807      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13808       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13809       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13810       ((CHANNEL) == TIM_CHANNEL_4) ||          \
13811       ((CHANNEL) == TIM_CHANNEL_5) ||          \
13812       ((CHANNEL) == TIM_CHANNEL_6)))           \
13813      ||                                        \
13814      (((INSTANCE) == TIM2_NS)  && \
13815      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13816       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13817       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13818       ((CHANNEL) == TIM_CHANNEL_4)))           \
13819      ||                                        \
13820      (((INSTANCE) == TIM3_NS)  && \
13821      (((CHANNEL) == TIM_CHANNEL_1) ||          \
13822       ((CHANNEL) == TIM_CHANNEL_2) ||          \
13823       ((CHANNEL) == TIM_CHANNEL_3) ||          \
13824       ((CHANNEL) == TIM_CHANNEL_4))))
13825 
13826 /****************** TIM Instances : supporting complementary output(s) ********/
13827 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
13828     ((((INSTANCE) == TIM1_NS)  && \
13829      (((CHANNEL) == TIM_CHANNEL_1) ||           \
13830       ((CHANNEL) == TIM_CHANNEL_2) ||           \
13831       ((CHANNEL) == TIM_CHANNEL_3) ||           \
13832       ((CHANNEL) == TIM_CHANNEL_4))))
13833 
13834 /****************** TIM Instances : supporting clock division *****************/
13835 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS) || \
13836                                                     ((INSTANCE) == TIM2_NS) || \
13837                                                     ((INSTANCE) == TIM3_NS))
13838 
13839 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
13840 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
13841                                                         ((INSTANCE) == TIM2_NS) || \
13842                                                         ((INSTANCE) == TIM3_NS))
13843 
13844 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
13845 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
13846                                                         ((INSTANCE) == TIM2_NS) || \
13847                                                         ((INSTANCE) == TIM3_NS))
13848 
13849 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
13850 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS) || \
13851                                                         ((INSTANCE) == TIM2_NS) || \
13852                                                         ((INSTANCE) == TIM3_NS))
13853 
13854 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
13855 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1_NS) || \
13856                                                         ((INSTANCE) == TIM2_NS) || \
13857                                                         ((INSTANCE) == TIM3_NS))
13858 
13859 
13860 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
13861 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS))
13862 
13863 /****************** TIM Instances : supporting commutation event generation ***/
13864 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS))
13865 
13866 /****************** TIM Instances : supporting counting mode selection ********/
13867 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS) || \
13868                                                         ((INSTANCE) == TIM2_NS) || \
13869                                                         ((INSTANCE) == TIM3_NS))
13870 
13871 /****************** TIM Instances : supporting encoder interface **************/
13872 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS) || \
13873                                                         ((INSTANCE) == TIM2_NS) || \
13874                                                         ((INSTANCE) == TIM3_NS))
13875 
13876 /****************** TIM Instances : supporting Hall sensor interface **********/
13877 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
13878                                                         ((INSTANCE) == TIM2_NS) || \
13879                                                         ((INSTANCE) == TIM3_NS))
13880 
13881 /**************** TIM Instances : external trigger input available ************/
13882 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS) || \
13883                                                         ((INSTANCE) == TIM2_NS) || \
13884                                                         ((INSTANCE) == TIM3_NS))
13885 
13886 /************* TIM Instances : supporting ETR source selection ***************/
13887 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS) || \
13888                                              ((INSTANCE) == TIM2_NS) || \
13889                                              ((INSTANCE) == TIM3_NS))
13890 
13891 
13892 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
13893 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1_NS)  || \
13894                                             ((INSTANCE) == TIM2_NS)  || \
13895                                             ((INSTANCE) == TIM3_NS)  || \
13896                                             ((INSTANCE) == TIM6_NS)  || \
13897                                             ((INSTANCE) == TIM7_NS))
13898 
13899 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
13900 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS) || \
13901                                              ((INSTANCE) == TIM2_NS) || \
13902                                              ((INSTANCE) == TIM3_NS))
13903 
13904 /****************** TIM Instances : supporting OCxREF clear *******************/
13905 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS) || \
13906                                                    ((INSTANCE) == TIM2_NS) || \
13907                                                    ((INSTANCE) == TIM3_NS))
13908 
13909 /****************** TIM Instances : remapping capability **********************/
13910 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS) || \
13911                                             ((INSTANCE) == TIM2_NS) || \
13912                                             ((INSTANCE) == TIM3_NS))
13913 
13914 /****************** TIM Instances : supporting repetition counter *************/
13915 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS))
13916 
13917 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
13918 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS))
13919 
13920 /******************* TIM Instances : Timer input XOR function *****************/
13921 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1_NS) || \
13922                                             ((INSTANCE) == TIM2_NS) || \
13923                                             ((INSTANCE) == TIM3_NS))
13924 
13925 /******************* TIM Instances : Timer input selection ********************/
13926 #define IS_TIM_TISEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1_NS) || \
13927                                             ((INSTANCE) == TIM2_NS) || \
13928                                             ((INSTANCE) == TIM3_NS))
13929 
13930 /****************** TIM Instances : Advanced timer instances *******************/
13931 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS))
13932 
13933 /****************** TIM Instances : supporting synchronization ****************/
13934 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)  (((INSTANCE) == TIM1_NS)  || \
13935                                                 ((INSTANCE) == TIM2_NS)  || \
13936                                                 ((INSTANCE) == TIM3_NS)  || \
13937                                                 ((INSTANCE) == TIM6_NS)  || \
13938                                                 ((INSTANCE) == TIM7_NS))
13939 
13940 /******************** USART Instances : Synchronous mode **********************/
13941 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13942                                      ((INSTANCE) == USART2_NS)  || \
13943                                      ((INSTANCE) == USART3_NS))
13944 
13945 /******************** UART Instances : Asynchronous mode **********************/
13946 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13947                                      ((INSTANCE) == USART2_NS) || \
13948                                      ((INSTANCE) == USART3_NS))
13949 
13950 /*********************** UART Instances : FIFO mode ***************************/
13951 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13952                                          ((INSTANCE) == USART2_NS)  || \
13953                                          ((INSTANCE) == USART3_NS)  || \
13954                                          ((INSTANCE) == LPUART1_NS))
13955 
13956 /*********************** UART Instances : SPI Slave mode **********************/
13957 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13958                                               ((INSTANCE) == USART2_NS) || \
13959                                               ((INSTANCE) == USART3_NS))
13960 
13961 /******************************** I2S Instances *******************************/
13962 #define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
13963                                          ((INSTANCE) == SPI2) || \
13964                                          ((INSTANCE) == SPI3))
13965 
13966 /****************** UART Instances : Auto Baud Rate detection ****************/
13967 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13968                                                             ((INSTANCE) == USART2_NS) || \
13969                                                             ((INSTANCE) == USART3_NS))
13970 
13971 /****************** UART Instances : Driver Enable *****************/
13972 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1_NS)  || \
13973                                                       ((INSTANCE) == USART2_NS)  || \
13974                                                       ((INSTANCE) == USART3_NS)  || \
13975                                                       ((INSTANCE) == LPUART1_NS))
13976 
13977 /******************** UART Instances : Half-Duplex mode **********************/
13978 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || \
13979                                                  ((INSTANCE) == USART2_NS)  || \
13980                                                  ((INSTANCE) == USART3_NS)  || \
13981                                                  ((INSTANCE) == LPUART1_NS))
13982 
13983 /****************** UART Instances : Hardware Flow control ********************/
13984 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
13985                                            ((INSTANCE) == USART2_NS)  || \
13986                                            ((INSTANCE) == USART3_NS)  || \
13987                                            ((INSTANCE) == LPUART1_NS))
13988 /******************** UART Instances : LIN mode **********************/
13989 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || \
13990                                           ((INSTANCE) == USART2_NS) || \
13991                                           ((INSTANCE) == USART3_NS))
13992 
13993 /******************** UART Instances : Wake-up from Stop mode **********************/
13994 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1_NS)  || \
13995                                                       ((INSTANCE) == USART2_NS)  || \
13996                                                       ((INSTANCE) == USART3_NS)  || \
13997                                                       ((INSTANCE) == LPUART1_NS))
13998 
13999 /*********************** UART Instances : IRDA mode ***************************/
14000 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
14001                                     ((INSTANCE) == USART2_NS) || \
14002                                     ((INSTANCE) == USART3_NS))
14003 
14004 /********************* USART Instances : Smard card mode ***********************/
14005 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS)  || \
14006                                          ((INSTANCE) == USART2_NS) || \
14007                                          ((INSTANCE) == USART3_NS))
14008 
14009 /******************** LPUART Instance *****************************************/
14010 #define IS_LPUART_INSTANCE(INSTANCE)    (((INSTANCE) == LPUART1_NS))
14011 
14012 /****************************** IWDG Instances ********************************/
14013 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG_NS))
14014 
14015 /****************************** WWDG Instances ********************************/
14016 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG_NS))
14017 
14018 /******************************* USB DRD FS HCD Instances *************************/
14019 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS_NS)
14020 
14021 /******************************* USB DRD FS PCD Instances *************************/
14022 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_DRD_FS_NS)
14023 
14024 /******************************** COMP Instances ******************************/
14025 #define IS_COMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
14026 
14027 /******************************** OPAMP Instances *****************************/
14028 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
14029 
14030 /** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */
14031 
14032 /** @} */ /* End of group STM32H503xx */
14033 
14034 /** @} */ /* End of group ST */
14035 
14036 #ifdef __cplusplus
14037 }
14038 #endif
14039 
14040 #endif  /* STM32H503xx_H */
14041